MPC9600 [MOTOROLA]
LOW VOLTAGE 2.5 V AND 3.3 V CMOS PLL CLOCK DRIVER; 低电压2.5 V和3.3 V CMOS PLL时钟驱动器
| 型号： | MPC9600 |
| 厂家： | 
MOTOROLA |
| 描述： | LOW VOLTAGE 2.5 V AND 3.3 V CMOS PLL CLOCK DRIVER |
| 文件： | 总16页 (文件大小：323K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
Order Number: MPC9600/D
Rev. 2, 11/2001
SEMICONDUCTOR TECHNICAL DATA
The MPC9600 is a low voltage 2.5 V or 3.3 V compatible, 1:21 PLL
based clock driver and fanout buffer. With output frequencies up to 200
MHz and output skews of 150 ps, the device meets the needs of the most
demanding clock tree applications.
Features:
•
Multiplication of input frequency by 2, 3, 4 and 6
•
Distribution of output frequency to 21 outputs organized in three output
banks: QA0-QA6, QB0-QB6, QC0-QC6, each fully selectable
3.3 V OR 2.5 V
LOW VOLTAGE CMOS
PLL CLOCK DRIVER
•
•
•
•
•
•
•
•
•
•
Fully integrated PLL
Selectable output frequency range is 50 to 100 MHz and 100 to 200 MHz
Selectable input frequency range is 16.67 to 33 MHz and 25 to 50 MHz
LVCMOS outputs
Outputs disable to high impedance (except QFB)
LVCMOS or LVPECL reference clock options
48 lead QFP packaging
±50 ps cycle-to-cycle jitter
150 ps maximum output-to-output skew
200 ps maximum static phase offset window
FA SUFFIX
48–LEAD LQFP PACKAGE
CASE 932–03
The MPC9600 is a fully LVCMOS 2.5 V or 3.3 V compatible PLL clock
driver. The MPC9600 has the capability to generate clock signals of 50 to
200 MHz from clock sources of 16.67 to 50 MHz. The internal PLL is
optimized for this frequency range and does not require external loop filter
components. QFB provides an output for the external feedback path to
the feedback input FB_IN. The QFB divider ratio is configurable and
determines the PLL frequency multiplication factor when QFB is directly
connected to FB_IN. The MPC9600 is optimized for minimizing the
propagation delay between the clock input and FB_IN.
Three output banks of 7 outputs each bank can be individually configured to divide the VCO frequency by 2 or by 4. Combining
the feedback and output divider ratios, the MPC9600 is capable to multiply the input frequency by 2, 3, 4 and 6.
The reference clock is selectable either LVPECL or LVCMOS. The LVPECL reference clock feature allows the designer to use
LVPECL fanout buffers for the inner branches of the clock distribution tree. All control inputs accept LVCMOS compatible levels.
The outputs provide low impedance LVCMOS outputs capable of driving parallel terminated 50 Ω transmission to V =V /2.
TT CC
For series terminated lines the MPC9600 can drive two lines per output giving the device an effective total fanout of 1:42. With
guaranteed maximum output-to-output skew of 150 ps, the MPC9600 PLL clock driver meets the synchronization requirements
of the most demanding systems.
The V
analog power pin doubles as a PLL bypass select line for test purpose. When the V
is driven to GND the
CCA
CCA
reference clock will bypass the PLL.
The device is packaged in a 48-lead LQFP package to provide optimum combination of board density and performance.
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VCCA
VCC
7
(pulldown)
(pulldn)
0
1
0
1
CCLK
QA0
QA1
Bank A
/2
0
1
PLL
Ref
FB
PCLK
PCLK
D
Q
/4
/8
QA2
QA3
Vcc/2
(pullup)
200 - 400 MHz
REF_SEL
FB_IN
/12
(pulldown)
(pullup)
QA4
QA5
FSELA
QA6
Bank B
0
1
D
Q
QB0–6
7
7
(pullup)
(pullup)
FSELB
FSELC
Bank C
0
1
D
Q
QC0–6
QFB
Feedback
0
1
D
Q
(pullup)
FSEL_FB
OE
(pulldown)
8
GND
Figure 1. MPC9600 Logic Diagram
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PIN CONFIGURATION
Pin
PCLK, PCLK
CCLK
FB_IN
QAn
I/O
Type
PECL
Description
Input
Input
Input
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Differential reference clock frequency input
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Power supply
Power supply
Ground
Reference clock input
PLL feedback clock input
Bank A outputs
QBn
Bank B outputs
QCn
Bank C outputs
QFB
Differential feedback output
REF_SEL
FSELA
FSELB
FSELC
FSEL_FB
OE
Reference clock input select
Selection of bank A output frequency
Selection of bank B output frequency
Selection of bank C output frequency
Selection of feedback frequency
Output enable
VCCA
VCC
Analog power supply and PLL bypass. An external VCC filter is recommended for VCCA
Core power supply
GND
Ground
36 35 34 33 32 31 30 29 28 27 26 25
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
GND
QC0
QC1
QC2
VCC
QC3
QC4
GND
QC5
QC6
OE
VCC
QA6
QA5
QA4
GND
QA3
QA2
VCC
MPC9600
QA1
QA0
FB_IN
GND
VCC
1
2
3
4
5
6
7
8
9
10 11 12
Figure 2. 48 Lead Package Pinout (Top View)
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FUNCTION TABLE (CONTROLS)
Control Pin
REF_SEL
VCCA
0
1
CCLK
PCLK
1
PLL Bypass
PLL Power
OE
Outputs Enabled
Outputs Disabled (except QFB)
Output Bank A at VCO/4
Output Bank B at VCO/4
Output Bank C at VCO/4
Feedback Output at VCO/12
FSELA
Output Bank A at VCO/2
Output Bank B at VCO/2
Output Bank C at VCO/2
Feedback Output at VCO/8
FSELB
FSELC
FSEL_FB
1..V
CCA
= GND, PLL off and bypassed for static test and diagnosis
Table 1: ABSOLUTE MAXIMUM RATINGS*
Symbol
Parameter
Min
Max
Unit
V
V
V
V
Supply Voltage
–0.3
–0.3
–0.3
4.6
CC
DC Input Voltage
V
V
+ 0.3
V
IN
CC
DC Output Voltage
DC Input Current
+ 0.3
V
OUT
CC
I
I
±20
mA
mA
°C
IN
DC Output Current
Storage Temperature Range
±50
OUT
T
–40
125
Stor
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is
not implied.
Table 2: GENERAL SPECIFICATIONS
Symbol
Characteristics
Output Termination Voltage
Min
Typ
Max
Unit
V
Condition
V
TT
V
2
CC
MM
HBM
CDM
LU
ESD Protection (Machine Model)
ESD Protection (Human Body Model)
ESD Protection (Charged Device Model)
Latch–Up Immunity
400
4000
1500
200
V
V
V
mA
pF
pF
C
Power Dissipation Capacitance
Input Capacitance
10
Per output
Inputs
PD
C
4.0
IN
Table 3: DC CHARACTERISTICS (V
CC
= 3.3 V ±5%, T = –40° to +85°C)
A
Symbol
Characteristics
Input High Voltage
Min
Typ
Max
+ 0.3
Unit
V
Condition
V
V
V
V
V
V
2.0
V
LVCMOS
IH
CC
Input Low Voltage
0.8
V
LVCMOS
LVPECL
LVPECL
IL
Peak-to-peak Input Voltage (DC)
Common Mode Range (DC)
Output High Voltage
PCLK, PCLK
PCLK, PCLK
250
1.0
2.4
mV
V
PP
CMR
OH
OL
a
V
-0.6
CC
b
V
I
=-24 mA
OH
Output Low Voltage
0.55
0.30
V
V
I
I
= 24mA
= 12mA
OL
OL
Z
Output Impedance
14 – 17
2.0
OUT
I
I
I
Input Leakage Current
±150
5.0
µA
mA
mA
V
V
= V
or GND
IN
IN
CC
Pin
Pins
Maximum PLL Supply Current
Maximum Quiescent Supply Current
CCA
CCQ
CCA
1.0
All V
CC
a. V
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V range
CMR
CMR
and the input swing lies within the V
PP
b. The MPC9600 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated
(DC) specification.
transmission line to a termination voltage of V . Alternatively, the device drives up to two 50Ω series terminated transmission lines.
TT
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Table 4: DC CHARACTERISTICS (V
CC
= 2.5 V ±5%, T = –40° to +85°C)
A
Symbol
Characteristics
Input High Voltage
Min
Typ
Max
+ 0.3
Unit
V
Condition
LVCMOS
V
V
V
V
V
V
1.7
V
IH
CC
Input Low Voltage
0.7
V
LVCMOS
LVPECL
LVPECL
IL
Peak-to-peak input voltage (DC)
Common Mode Range (DC)
Output High Voltage
PCLK, PCLK
PCLK, PCLK
250
1.0
1.8
mV
V
PP
a
V
-0.6
CMR
OH
OL
CC
b
V
I
=-15 mA
OH
Output Low Voltage
0.6
V
I = 15 mA
OL
Z
Output Impedance
17 – 20
3.0
OUT
I
I
I
Input Leakage Current
±150
5.0
µA
mA
mA
V
V
= V
or GND
IN
IN
CC
Pin
Pins
Maximum PLL Supply Current
Maximum Quiescent Supply Current
CCA
CCQ
CCA
1.0
All V
CC
a. V
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V range
CMR
CMR
and the input swing lies within the V
PP
b. The MPC9600 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated
(DC) specification.
transmission line to a termination voltage of V . Alternatively, the device drives up to two 50 Ω series terminated transmission lines per
TT
output.
a
Table 5: AC CHARACTERISTICS (V
CC
= 3.3 V ±5% or V = 2.5 V ±5%, T = –40° to +85°C)
CC A
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
f
Input Frequency
ref
8 feedback (FSEL_FB=0)
12 feedback (FSEL_FB=1)
25
16.67
50
33
MHz
MHz
PLL locked
PLL locked
Static test mode (VCCA = GND)
0
500
400
MHz
MHz
VCCA = GND
f
f
VCO Frequency
200
VCO
Maximum Output Frequency
MAX
2 outputs (FSELx=0)
4 outputs (FSELx=1)
100
50
200
100
MHz
MHz
PLL locked
PLL locked
f
Reference Input Duty Cycle
Peak-to-peak Input Voltage
Common Mode Range
25
75
%
refDC
V
PCLK, PCLK
500
1000
mV
LVPECL
PP
V
b
CMR
PCLK, PCLK (VCC = 3.3 V ±5%)
PCLK, PCLK (VCC = 2.5 V ±5%)
1.2
1.2
V
V
-0.8
-0.6
V
V
LVPECL
LVPECL
CC
CC
t , t
r f
CCLK Input Rise/Fall Time
Propagation Delay (static phase offset)
1.0
ns
see Figure 12
t
(
)
CCLK to FB_IN
PECL_CLK to FB_IN
–60
+30
+40
+130
+140
+230
ps
ps
PLL locked
PLL locked
t
Output-to-output Skew
sk(o)
all outputs, single frequency
all outputs, multiple frequency
70
70
150
150
ps
ps
Measured at
coincident
rising edge
within QAx output bank
within QBx outputs
within QCx outputs
30
40
30
75
125
75
ps
ps
ps
DC
t , t
Output Duty Cycle
Output Rise/Fall Time
Output Disable Time
Output Enable Time
45
50
55
1.0
10
10
%
ns
ns
ns
0.1
see Figure 12
r f
t
PLZ, HZ
PZL, ZH
t
BW
PLL Closed Loop Bandwidth
8 feedback (FSEL_FB=0)
12 feedback (FSEL_FB=1)
–3 dB point of
PLL transfer
characteristic
1.0 – 10
0.6 – 4.0
MHz
MHz
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a
Table 5: AC CHARACTERISTICS (V
CC
= 3.3 V ±5% or V = 2.5 V ±5%, T = –40° to +85°C)
CC A
Symbol
Characteristics
c
Min
Typ
Max
Unit
Condition
t
Cycle-to-cycle Jitter
See application
section for
other
JIT(CC)
All outputs in 2 configuration
All outputs in 4 configuration
40
40
130
180
ps
ps
configurations
c
t
Period Jitter
See application
section for
other
JIT(PER)
All outputs in 2 configuration
All outputs in 4 configuration
25
20
70
100
ps
ps
configurations
d
c
t
t
I/O Phase Jitter (1
)
V
CC
V
CC
= 3.3V
= 2.5V
17
15
ps
ps
RMS value at
JIT(
)
f
=400MHz
VCO
Maximum PLL Lock Time
5.0
ms
LOCK
a. AC characteristics are applicable over the entire ambient temperature and supply voltage range and are production tested. AC
characteristics apply for parallel output termination of 50 Ω to V
.
TT
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
b. V
range
CMR
CMR
and the input swing lies within the V
(AC) specification. Violation of V
or V
impacts static phase offset t
PP (
PP
CMR
).
c. Cycle–to–cycle and period jitter depends on output divider configuration.
d. See applications section for max I/O phase jitter versus frequency.
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configurations, the table describes the outputs using the
input clock frequency CLK as a reference.
APPLICATIONS INFORMATION
Programming the MPC9600
The feedback divider division settings establish the output
relationship, in addition, it must be ensured that the VCO will
be stable given the frequency of the outputs desired. The
feedback frequency should be used to situate the VCO into a
frequency range in which the PLL will be stable. The design
of the PLL supports output frequencies from 50 MHz to 200
MHz while the VCO frequency range is specified from 200
MHz to 400 MHz and should not be exceeded for stable
The MPC9600 clock driver outputs can be configured into
several divider modes. Additionally the external feedback of
the device allows for flexibility in establishing various input to
output frequency relationships. The selectable feedback
divider of the three output groups allows the user to configure
the device for 1:2, 1:3, 1:4 and 1:6 input:output frequency
ratios. The use of even dividers ensure that the output duty
cycle is always 50%. Table 6 illustrates the various output
operation.
a
Table 6: Output Frequency Relationship for QFB connected to FB_IN
Input
Frequency
Range CLK
[MHz]
Configuration Inputs
Output Frequency Ratio and Range
FSEL_FB
FSELA
FSELB
FSELC
Ratio, QAx [MHz]
Ratio, QBx [MHz]
Ratio, QCx [MHz]
4 CLK (100–200)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
4 CLK (100–200)
4 CLK (100–200)
4 CLK (100–200)
4 CLK (100–200) 2 CLK (50.0–100)
4 CLK (100–200) 2 CLK (50.0–100) 4 CLK (100–200)
4 CLK (100–200) 2 CLK (50.0–100) 2 CLK (50.0–100)
25.0–50.0
2 CLK (50.0–100)
4 CLK (100–200)
4 CLK (100–200)
2 CLK (50.0–100) 4 CLK (100–200) 2 CLK (50.0–100)
2 CLK (50.0–100) 2 CLK (50.0–100) 4 CLK (100–200)
2 CLK (50.0–100) 2 CLK (50.0–100) 2 CLK (50.0–100)
6 CLK (100–200)
6 CLK (100–200)
6 CLK (100–200)
6 CLK (100–200)
6 CLK (100–200) 3 CLK (50.0–100)
6 CLK (100–200) 3 CLK (50.0–100) 6 CLK (100–200)
6 CLK (100–200) 3 CLK (50.0–100) 3 CLK (50.0–100)
16.67–33.33
3 CLK (50.0–100) 6 CLK (100–200)
6 CLK (100–200)
3 CLK (50.0–100) 6 CLK (100–200) 3 CLK (50.0–100)
3 CLK (50.0–100) 3 CLK (50.0–100) 6 CLK (100–200)
3 CLK (50.0–100) 3 CLK (50.0–100) 3 CLK (50.0–100)
a. Output frequency relationship with respect to input reference frequency CLK. The VCO frequency range is always 200–400.
Typical and Maximum Period Jitter Specification
QA0 to QA6
QB0 to QB6
QC0 to QC6
Device Configuration
Typ
Max
Typ
Max
Typ
Max
a
All output banks in 2 or 4 divider configuration
2 (FSELA=0 and FESLB=0 and FSELC=0)
4 (FSELA=1 and FESLB=1 and FSELC=1)
25
20
50
70
50
50
70
100
25
20
50
70
b
Mixed 2/ 4 divider configurations
for output banks in 2 divider configurations
for output banks in 4 divider configurations
80
25
130
70
100
60
150
100
80
25
130
70
a. In this configuration, all MPC9600 outputs generate the same clock frequency. See Figure 1 for an example configuration.
b. Multiple frequency generation. Jitter data are specified for each output divider sepeerately. See Figure 2 for an example.
Typical and Maximum Cycle–to–cycle Jitter Specification
QA0 to QA6
QB0 to QB6
QC0 to QC6
Device Configuration
Typ
Max
Typ
Max
Typ
Max
a
All output banks in 2 or 4 divider configuration
2 (FSELA=0 and FESLB=0 and FSELC=0)
4 (FSELA=1 and FESLB=1 and FSELC=1)
40
40
90
110
80
120
130
180
40
40
90
110
b
Mixed 2/ 4 divider configurations
for output banks in 2 divider configurations
for output banks in 4 divider configurations
150
30
250
110
200
120
280
180
150
30
250
110
a. In this configuration, all MPC9600 outputs generate the same clock frequency.
b. Multiple frequency generation. Jitter data are specified for each output divider sepeerately.
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Figure 3. Configuration for 125 MHz clocks
Figure 4. Configuration for 133.3/66.67 MHz clocks
fref = 20.833 MHz
fref = 33.33 MHz
CCLK
QA0–6
QB0–6
QC0–6
125 MHz
125 MHz
125 MHz
CCLK
QA0–6
QB0–6
QC0–6
133.3 MHz
66.67 MHz
66.67 MHz
7
7
7
7
FB_IN
FB_IN
FSEL_FB
FSEL_FB
1
0
7
7
0
0
0
FSELA
FSELB
FSELC
0
1
1
FSELA
FSELB
FSELC
QFB
QFB
MPC9600
20.833 MHz (Feedback)
MPC9600
33.33 MHz (Feedback)
Frequency range
Input
Min
Max
Frequency range
Input
Min
Max
16.67 MHz
100 MHz
100 MHz
100 MHz
33.33 MHz
200 MHz
200 MHz
200 MHz
25 MHz
100 MHz
100 MHz
100 MHz
50 MHz
200 MHz
200 MHz
200 MHz
QA outputs
QB outputs
QC outputs
QA outputs
QB outputs
QC outputs
R = 9–10 Ω for V = 2.5 V or V = 3.3 V
F CC CC
Power Supply Filtering
The MPC9600 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Random noise
C = 22 µF for V = 2.5 V or V = 3.3 V
CC CC
F
R
F
VCCA
VCC
on the V
(PLL) power supply impacts the device
CCA
characteristics, for instance I/O jitter. The MPC9600 provides
separate power supplies for the output buffers (V ) and the
C
F
10 nF
MPC9600
CC
) of the device.The purpose of this
phase-locked loop (V
CCA
VCC
design technique is to isolate the high switching noise digital
outputs from the relatively sensitive internal analog
phase-locked loop. In a digital system environment where it
is more difficult to minimize noise on the power supplies a
second level of isolation may be required. The simple but
33...100 nF
Figure 5. V
Power Supply Filter
CCA
effective form of isolation is a power supply filter on the V
CCA
pin for the MPC9600. Figure 5. illustrates a typical power
supply filter scheme. The MPC9600 frequency and phase
stability is most susceptible to noise with spectral content in
the 100kHz to 20MHz range. Therefore the filter should be
designed to target this range. The key parameter that needs
to be met in the final filter design is the DC voltage drop
As the noise frequency crosses the series resonant point
of an individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Although the MPC9600 has
several design features to minimize the susceptibility to
power supply noise (isolated power and grounds and fully
differential PLL) there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter schemes discussed in
this section should be adequate to eliminate power supply
noise related problems in most designs.
across the series filter resistor R . From the data sheet the
F
I
current (the current sourced through the V
pin) is
CCA
CCA
typically 3 mA (5 mA maximum), assuming that a minimum of
2.325 V (V =3.3 V or V =2.5 V) must be maintained on
pin. The resistor R shown in Figure 5. “V
F CCA
Power Supply Filter” must have a resistance of 9-10
CC
CC
the V
CCA
(V =2.5 V) to meet the voltage drop criteria.
CC
The minimum values for R and the filter capacitor C are
F
F
defined by the required filter characteristics: the RC filter
should provide an attenuation greater than 40 dB for noise
whose spectral content is above 100 kHz. In the example RC
filter shown in Figure 5. “V
cut-off frequency is around 3-5 kHz and the noise attenuation
at 100 kHz is better than 42 dB.
Power Supply Filter”, the filter
CCA
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Using the MPC9600 in zero–delay applications
Table 8: Confidence Facter CF
Nested clock trees are typical applications for the
MPC9600. For these applications the MPC9600 offers a
differential LVPECL clock input pair as a PLL reference. This
allows for the use of differential LVPECL primary clock
distribution devices such as the Motorola MC100ES6111 or
MC100ES6226, taking advantage of its superior low-skew
performance. Clock trees using LVPECL for clock distribution
and the MPC9600 as LVCMOS PLL fanout buffer with zero
insertion delay will show significantly lower clock skew than
clock distributions developed from CMOS fanout buffers.
CF
Probability of clock edge within the distribution
± 1
± 2
± 3
± 4
± 5
± 6
0.68268948
0.95449988
0.99730007
0.99993663
0.99999943
0.99999999
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device. In the following example calculation a
I/O jitter confidence factor of 99.7% (± 3 ) is assumed,
resulting in a worst case timing uncertainty from input to any
The external feedback option of the MPC9600 PLL allows
for its use as a zero delay buffer. The PLL aligns the feedback
clock output edge with the clock input reference edge and
virtually eliminates the propagation delay through the device.
output of -261 ps to 341 ps relative to CCLK (V =3.3V and
CC
The remaining insertion delay (skew error) of the
MPC9600 in zero-delay applications is measured between
the reference clock input and any output. This effective delay
f
= 200 MHz):
VCO
t
=
=
[–60ps...140ps] + [–150ps...150ps] +
SK(PP)
consists of the static phase offset (SPO or t ), I/O jitter
( )
[(17ps –3)...(17ps 3)] + t
PD, LINE(FB)
(t
, phase or long-term jitter), feedback path delay and
JIT( )
t
[–261ps...341ps] + t
the output-to-output skew (t
output.
relative to the feedback
SK(PP)
PD, LINE(FB)
SK(O)
Above equation uses the maximum I/O jitter number
shown in the AC characteristic table for V =3.3V (17 ps
CC
Calculation of part-to-part skew
RMS). I/O jitter is frequency dependant with a maximum at
the lowest VCO frequency (200 MHz for the MPC9600).
Applications using a higher VCO frequency exhibit less I/O
jitter than the AC characteristic limit. The I/O jitter
characteristics in Figure 7. can be used to derive a smaller
I/O jitter number at the specific VCO frequency, resulting in
tighter timing limits in zero-delay mode and for part-to-part
The MPC9600 zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs (CCLK or
PCLK) of two or more MPC9600 are connected together, the
maximum overall timing uncertainty from the common CCLK
input to any output is:
skew t
.
SK(PP)
t
= t
+ t
+ t
+ t
CF
This maximum timing uncertainty consist of 4
SK(PP)
( )
SK(O)
PD, LINE(FB)
JIT( )
components: static phase offset, output skew, feedback
board trace delay and I/O (phase) jitter:
TCLK
Common
t
PD,LINE(FB)
–t
(
)
QFB
Device 1
t
JIT(
)
Any Q
Device 1
+t
SK(O)
Figure 7. Max. I/O Jitter versus VCO frequency for
=2.5V and V =3.3V
+t
(
)
V
CC
CC
Driving Transmission Lines
QFB
Device2
t
JIT(
)
The MPC9600 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20 Ω the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to Motorola application note
AN1091. In most high performance clock networks
point-to-point distribution of signals is the method of choice.
In a point-to-point scheme either series terminated or parallel
Any Q
Device 2
+t
SK(O)
Max. skew
t
SK(PP)
Figure 6. MPC9600 max. device-to-device skew
Due to the statistical nature of I/O jitter a RMS value (1 )
is specified. I/O jitter numbers for other confidence factors
(CF) can be derived from Table 8.
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terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
Z
R
R
= 50 Ω || 50 Ω
= 36 Ω || 36 Ω
= 14 Ω
= 3.0 ( 25 ÷ (18+17+25)
= 1.31 V
0
S
0
50Ω resistance to V ÷2.
CC
V
L
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC9600 clock driver. For the series
terminated case however there is no DC current draw, thus
the outputs can drive multiple series terminated lines.
Figure 8. “Single versus Dual Transmission Lines” illustrates
an output driving a single series terminated line versus two
series terminated lines in parallel. When taken to its extreme
the fanout of the MPC9600 clock driver is effectively doubled
due to its capability to drive multiple lines.
At the load end the voltage will double due to the near unity
reflection coefficient, to 2.6 V. It will then increment towards
the quiescent 3.0 V in steps separated by one round trip
delay (in this case 4.0 ns).
3.0
OutA
= 3.8956
OutB
t
D
2.5
2.0
1.5
1.0
0.5
0
t
D
= 3.9386
MPC9600
OUTPUT
BUFFER
In
Z
O
= 50 Ω
R = 36 Ω
S
14Ω
IN
IN
OutA
MPC9600
OUTPUT
BUFFER
Z
= 50 Ω
= 50 Ω
O
R = 36 Ω
S
OutB0
OutB1
14Ω
2
4
6
8
10
12
14
Z
O
R = 36 Ω
S
TIME (nS)
Figure 9. Single versus Dual Waveforms
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To
better match the impedances when driving multiple lines the
situation in Figure 10. “Optimized Dual Line Termination”
should be used. In this case the series terminating resistors
are reduced such that when the parallel combination is added
to the output buffer impedance the line impedance is
perfectly matched.
Figure 8. Single versus Dual Transmission Lines
The waveform plots in Figure 9. “Single versus Dual Line
Termination Waveforms” show the simulation results of an
output driving a single line versus two lines. In both cases the
drive capability of the MPC9600 output buffer is more than
sufficient to drive 50 Ω transmission lines on the incident
edge. Note from the delay measurements in the simulations a
delta of only 43 ps exists between the two differently loaded
outputs. This suggests that the dual line driving need not be
used exclusively to maintain the tight output-to-output skew
of the MPC9600. The output waveform in Figure 9. “Single
versus Dual Line Termination Waveforms” shows a step in
the waveform, this step is caused by the impedance
mismatch seen looking into the driver. The parallel
combination of the 36Ω series resistor plus the output
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
MPC9600
OUTPUT
BUFFER
Z
= 50 Ω
= 50 Ω
O
R = 22 Ω
S
14Ω
Z
O
R = 22 Ω
S
14 Ω + 22 Ω 22 Ω = 50 Ω 50 Ω
25 Ω = 25 Ω
Figure 10. Optimized Dual Line Termination
V
= V ( Z ÷ (R +R +Z ))
S 0 S 0 0
L
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The Following Figures Illustrate the Measurement Reference for the MPC9600 Clock Driver Circuit
MPC9600 DUT
Pulse
Generator
Z = 50
Z
O
= 50 Ω
Z = 50 Ω
O
R = 50 Ω
T
R = 50 Ω
T
V
TT
V
TT
Figure 11. CCLK MPC9600 AC test reference
MPC9600 DUT
Z
O
= 50 Ω
Differential
Pulse Generator
Z = 50
Z
O
= 50 Ω
R = 50 Ω
T
R = 50 Ω
T
V
TT
V
TT
Figure 12. PCLK MPC9600 AC test reference
V
PCLK
PCLK
CC
CCLK
FB_IN
V
CC
GND
2
2
V
CMR
V
PP
V
CC
V
CC
V
CC
V
2
CC
GND
FB_IN
GND
t
(
)
t
(
)
Figure 13. Propagation delay t , static phase
(
)
Figure 14. Propagation delay t
test reference
)
(
offset) test reference
V
V
CC
CC
V
CC
GND
2
V
CC
GND
2
2
t
P
V
CC
V
CC
GND
T
0
DC = t /T x 100%
P 0
t
SK(O)
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
The pin–to–pin skew is defined as the worst case difference in
propagation delay between any similar delay path within a
single device
Figure 15. Output Duty Cycle (DC)
Figure 16. Output–to–output Skew t
SK(O)
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T
= |T –T
N+1
|
T
= |T –1/f |
JIT(CC)
N
JIT(P) N 0
T
N
T
N+1
T
0
The variation in cycle time of a signal between adjacent cycles, over a
random sample of adjacent cycle pairs
The deviation in cycle time of a signal with respect to the ideal period over
a random sample of cycles
Figure 17. Cycle–to–cycle Jitter
Figure 18. Period Jitter
CCLK
(PCLK)
V =3.3V
CC
V =2.5 V
CC
2.4
0.55
1.8 V
0.6 V
FB_IN
T
JIT(
= |T –T mean|
0 1
)
t
F
t
R
The deviation in t for a controlled edge with respect to a t mean in a
0
0
random sample of cycles
Figure 19. I/O Jitter
Figure 20. Output Transition Time Test Reference
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OUTLINE DIMENSIONS
FA SUFFIX
LQFP PACKAGE
CASE 932–03
4X
ISSUE F
NOTES:
0.200 AB T–U Z
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3.DATUM PLANE AB IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4.DATUMS T, U, AND Z TO BE DETERMINED AT
DATUM PLANE AB.
DETAIL Y
9
A
P
A1
48
37
5.DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE AC.
1
36
6.DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE AB.
7.DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.350.
T
U
B
V
AE
AE
B1
V1
8.MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076.
12
25
9.EXACT SHAPE OF EACH CORNER IS OPTIONAL.
MILLIMETERS
13
24
DIM MIN
MAX
7.000 BSC
3.500 BSC
Z
A
A1
B
B1
C
D
E
F
G
H
J
K
L
M
N
P
S1
7.000 BSC
3.500 BSC
T, U, Z
1.400
1.600
0.270
1.450
0.230
S
0.170
1.350
0.170
DETAIL Y
4X
0.200 AC T–U Z
0.500 BSC
0.050
0.090
0.500
0
0.150
0.200
0.700
7
0.080 AC
12 REF
G
AB
AC
0.090
0.150
0.160
0.250 BSC
R
0.250
S
9.000 BSC
S1
V
V1
W
AA
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
AD
M
BASE METAL
TOP & BOTTOM
R
N
J
E
C
H
F
D
M
0.080
AC T–U Z
SECTION AE–AE
W
L
K
DETAIL AD
AA
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NOTES
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NOTES
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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
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MOTOROLA and the
logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners.
Motorola, Inc. 2001.
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◊
MPC9600/D
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