MPC9653_技术文档

Freescale Semiconductor, Inc.

SEMICONDUCTOR TECHNICAL DATA

Order Number: MPC9653/D

Rev 3, 02/2003

The MPC9653 is a 3.3V compatible, 1:8 PLL based clock generator

and zero-delay buffer targeted for high performance low-skew clock

distribution in mid-range to high-performance telecom, networking and

computing applications. With output frequencies up to 125 MHz and

output skews less than 150 ps the device meets the needs of the most

demanding clock applications.

LOW VOLTAGE

3.3V LVCMOS 1:8

PLL CLOCK GENERATOR

Features

• 1:8 PLL based low-voltage clock generator

• Supports zero-delay operation

• 3.3V power supply

• Generates clock signals up to 125 MHz

• Maximum output skew of 150 ps

• Differential LVPECL reference clock input

• External PLL feedback

• Drives up to 16 clock lines

• 32 lead LQFP packaging

• Ambient temperature range 0°C to +70°C

• Pin and function compatible to the MPC953

FA SUFFIX

32 LEAD LQFP PACKAGE

CASE 873A

Functional Description

The MPC9653 utilizes PLL technology to frequency lock its outputs

onto an input reference clock. Normal operation of the MPC9653 requires

the connection of the QFB output to the feedback input to close the PLL

feedback path (external feedback). With the PLL locked, the output

frequency is equal to the reference frequency of the device and

VCO_SEL selects the operating frequency range of 25 to 62.5 MHz or 50

to 125 MHz. The two available post-PLL dividers selected by VCO_SEL

(divide-by-4 or divide-by-8) and the reference clock frequency determine

the VCO frequency. Both must be selected to match the VCO frequency

range. The internal VCO of the MPC9653 is running at either 4x or 8x of

the reference clock frequency.

The MPC9653 has a differential LVPECL reference input along with an external feedback input. The device is ideal for use as a

zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance.

The PLL_EN and BYPASS controls select the PLL bypass configuration for test and diagnosis. In this configuration, the

selected input reference clock is bypassing the PLL and routed either to the output dividers or directly to the outputs. The PLL

bypass configurations are fully static and the minimum clock frequency specification and all other PLL characteristics do not

apply. The outputs can be disabled (high-impedance) and the device reset by asserting the MR/OE pin. Asserting MR/OE also

causes the PLL to loose lock due to missing feedback signal presence at FB_IN. Deasserting MR/OE will enable the outputs and

close the phase locked loop, enabling the PLL to recover to normal operation.

The MPC9653 is fully 3.3V compatible and requires no external loop filter components. The inputs (except PCLK) accept

LVCMOS except signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50

transmission lines. For series terminated transmission lines, each of the MPC9653 outputs can drive one or two traces giving the

2

devices an effective fanout of 1:16. The device is packaged in a 7x7 mm 32-lead LQFP package.

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MPC9653

V

CC

Q0

Q1

Q2

Q3

Q4

0

2 25k

0

1

0

1

÷1

÷2

PCLK

1

÷4

&

Ref

VCO

PLL

200–500 MHz

V

CC

25k

Q5

FB_IN

FB

Q6

V

CC

3 25k

Q7

PLL_EN

QFB

VCO_SEL

BYPASS

MR/OE

25k

Figure 1. MPC9653 Logic Diagram

24 23 22 21 20 19 18 17

MPC9653

25

26

27

28

29

30

31

32

16

Q5

GND

15

14

13

12

11

10

9

VCC

Q6

Q0

VCC

GND

Q7

QFB

GND

VCC

MR/OE

PCLK

PLL_EN

BYPASS

VCO_SEL

1

2

3

4

5

6

7

8

Figure 2. MPC9653 32–Lead Package Pinout (Top View)

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Table 1: PIN CONFIGURATION

I/O

Input

Type

Function

PCLK, PCLK

FB_IN

LVPECL

LVCMOS

PECL reference clock signal

Input

PLL feedback signal input, connect to QFB

Operating frequency range select

VCO_SEL

BYPASS

PLL_EN

Input

LVCMOS

PLL and output divider bypass select

PLL enable/disable

MR/OE

Q0-7

Input

LVCMOS

Ground

VCC

Output enable/disable (high-impedance tristate) and device reset

Clock outputs

Output

Supply

QFB

Clock output for PLL feedback, connect to FB_IN

Negative power supply (GND)

GND

VCC_PLL

PLL positive power supply (analog power supply). It is recommended to use an external RC filter

for the analog power supply pin V . Please see applications section for details.

CC_PLL

VCC

Supply

VCC

Positive power supply for I/O and core. All VCC pins must be connected to the positive power

supply for correct operation

Table 2: FUNCTION TABLE

Control

Default

0

1

a

PLL_EN

1

Test mode with PLL bypassed. The reference clock (PCLK) Selects the VCO output

is substituted for the internal VCO output. MPC9653 is fully

static and no minimum frequency limit applies. All PLL

related AC characteristics are not applicable.

BYPASS

1

Test mode with PLL and output dividers bypassed. The

reference clock (PCLK) is directly routed to the outputs.

MPC9653 is fully static and no minimum frequency limit

applies. All PLL related AC characteristics are not

applicable.

Selects the output dividers.

VCO_SEL

MR/OE

1

0

VCO ÷ 1 (High frequency range). f

= f

= 4

f

VCO ÷ 2 (Low output range). f = 8 f

= f

REF Q0-7

VCO

REF Q0-7 VCO

Outputs enabled (active)

Outputs disabled (high-impedance state) and reset of

the device. During reset the PLL feedback loop is open.

The VCO is tied to its lowest frequency. The length of

the reset pulse should be greater than one reference

clock cycle (PCLK).

a. PLL operation requires BYPASS=1 and PLL_EN=1.

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Table 3: GENERAL SPECIFICATIONS

Symbol

Characteristics

Output Termination Voltage

Min

Typ

Max

Unit

V

Condition

V

TT

V

2

CC

MM

HBM

LU

ESD Protection (Machine Model)

ESD Protection (Human Body Model)

Latch–Up Immunity

200

2000

200

V

mA

pF

C

Power Dissipation Capacitance

Input Capacitance

10

Per output

Inputs

PD

C

4.0

IN

a

Table 4: ABSOLUTE MAXIMUM RATINGS

Symbol

Characteristics

Min

-0.3

Max

3.9

Unit

V

Condition

V

CC

Supply Voltage

V

IN

DC Input Voltage

V

+0.3

V

CC

V

OUT

DC Output Voltage

DC Input Current

+0.3

V

CC

I

IN

±20

mA

°C

I

DC Output Current

Storage Temperature

±50

OUT

T

S

-65

125

a. Absolutemaximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions

or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not

implied.

Table 5: DC CHARACTERISTICS (V

CC

= 3.3V ± 5%, T = 0°C to 70°C)

A

Symbol

Characteristics

Min

Typ

Max

+ 0.3

Unit

V

Condition

LVCMOS

V

IH

Input high voltage

2.0

V

CC

0.8

V

IL

Input low voltage

V

LVCMOS

LVPECL

V

PP

Peak-to-peak input voltage

Common Mode Range

Output High Voltage

Output Low Voltage

(PCLK)

300

1.0

2.4

mV

V

a

V

CMR

V

-0.6

CC

b

I =-24 mA

OH

V

OH

V

OL

0.55

0.30

V

I = 24 mA

OL

I = 12 mA

OL

Z

Output impedance

14 - 17

5.0

OUT

c

I

IN

Input Current

Maximum PLL Supply Current

Maximum Quiescent Supply Current

±200

10

µA

mA

V

=V

or GND

IN CC

I

CC_PLL

d

I

10

All V

Pins

CC

CCQ

a

b

V

(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V range and

CMR

the input swing lies within the V

(DC) specification.

PP

The MPC9653 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission

line to a termination voltage of V . Alternatively, the device drives up to two 50Ω series terminated transmission lines. The MPC9653 meets

TT

specification of the MPC953 (V

the V

and V

> V –0.6V at I

=–20mA and V > 0.6V at I =20mA).

OH

OL

OH

CC

OH

OL OL

c

d

Inputs have pull-down or pull–up resistors affecting the input current.

OE/MR=1 (outputs in high–impedance state).

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a

Table 6: AC CHARACTERISTICS (V

CC

= 3.3V ± 5%, T = 0°C to 70°C)

A

Symbol

Characteristics

Input reference frequency

PLL mode, external feedback

Min

Typ

Max

Unit

Condition

b

c

f

÷4 feedback

÷8 feedback

50

25

125

62.5

MHz

PLL locked

REF

d

Input reference frequency in PLL bypass mode

0

200

500

MHz

e

f

VCO lock frequency range

200

VCO

b

c

Output Frequency

÷4 feedback

÷8 feedback

50

25

125

62.5

MHz

PLL locked

MAX

V

Peak-to-peak input voltage

Common Mode Range

PCLK

450

1.2

2

1000

mV

V

LVPECL

PP

V

CMR

f

V

-0.75

CC

g

t

Input Reference Pulse Width

ns

ps

PW,MIN

h

t

(

Propagation Delay (static phase offset)

PCLK to FB_IN

–75

125

PLL locked

)

t

Propagation Delay

PD

PLL and divider bypass (BYPASS=0), PCLK to Q0-7

PLL disable (BYPASS=1 and PLL_EN=0), PCLK to Q0-7

1.2

3.0

3.3

7.0

ns

i

t

Output-to-output Skew

150

ps

sk(O)

j

t

Device-to-device Skew in PLL and divider bypass

1.5

55

ns

%

BYPASS=0

PLL locked

0.55 to 2.4V

sk(PP)

DC

Output duty cycle

45

50

t , t

R

Output Rise/Fall Time

Output Disable Time

0.1

1.0

ns

ps

F

t

7.0

PLZ, HZ

t

Output Enable Time

6.0

PZL, LZ

t

Cycle-to-cycle jitter

100

25

JIT(CC)

t

Period Jitter

JIT(PER)

k

t

I/O Phase Jitter

RMS (1 σ)

JIT(

BW

)

l

b

c

PLL closed loop bandwidth

÷ 4 feedback

÷ 8 feedback

0.8 – 4

0.5 – 1.3

MHz

PLL mode, external feedback

Maximum PLL Lock Time

t

10

ms

LOCK

a

b

c

d

e

f

AC characteristics apply for parallel output termination of 50Ω to V

.

TT

÷4 PLL feedback (high frequency range) requires VCO_SEL=0, PLL_EN=1, BYPASS=1 and MR/OE=0.

÷8 PLL feedback (low frequency range) requires VCO_SEL=1, PLL_EN=1, BYPASS=1 and MR/OE=0.

In bypass mode, the MPC9653 divides the input reference clock.

The input frequency f

must match the VCO frequency range divided by the feedback divider ratio FB: f

= f

÷ FB.

CMR

REF

REF VCO

V

(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V

range and

CMR

the input swing lies within the V

(AC) specification. Violation of V

or V

impacts static phase offset t

.

)

PP

CMR

f

PP

100% and DC

(

g

Calculation of reference duty cycle limits: DC

= t

= 100% – DC .

REF,MIN PW,MIN REF

=100 MHz the input duty cycle range is 20% < DC < 80%.

REF,MAX

REF,MIN

E.g. at f

REF

Valid for f

h

i

j

k

l

=50 MHz and FB=÷8 (VCO_SEL=1). For other reference frequencies: t

REF

[ps] = 50 ps ± (1÷(120

)

f

)).

(

REF

See application section for part-to-part skew calculation in PLL zero-delay mode.

For a specified temperature and voltage, includes output skew.

I/O phase jitter is reference frequency dependent. See application section for details.

-3 dB point of PLL transfer characteristics.

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APPLICATIONS INFORMATION

Programming the MPC9653

500 MHz for stable and optimal operation. Two operating

frequency ranges are supported: 25 to 62.5 MHz and 50 to

125 MHz. Table 9 illustrates the configurations supported by

the MPC9653. PLL zero-delay is supported if BYPASS=1,

PLL_EN=1 and the input frequency is within the specified

The MPC9653 supports output clock frequencies from 25

to 125 MHz. Two different feedback divider configurations

can be used to achieve the desired frequency operation

range. The feedback divider (VCO_SEL) should be used to

situate the VCO in the frequency lock range between 200 and

PLL reference frequency range.

Table 9: MPC9653 Configurations (QFB connected to FB_IN)

Frequency

BYPASS PLL_EN VCO_SEL

Operation

Ratio

= f

Output range (f

)

VCO

n/a

Q0-7

0

1

X

0

1

X

0

1

0

1

Test mode: PLL and divider bypass

Test mode: PLL bypass

f

0-200 MHz

Q0-7 REF

f

= f

Q0-7 REF

÷ 4

÷ 8

0-50 MHz

n/a

Test mode: PLL bypass

f

= f

Q0-7 REF

0-25 MHz

n/a

PLL mode (high frequency range)

PLL mode (low frequency range)

f

= f

Q0-7 REF

50 to 125 MHz

25 to 62.5 MHz

f

= f

VCO REF

4

8

f

= f

Q0-7 REF

f

= f

VCO REF

Power Supply Filtering

The minimum values for R and the filter capacitor C are

F F

defined by the required filter characteristics: the RC filter

should provide an attenuation greater than 40 dB for noise

whose spectral content is above 100 kHz. In the example RC

The MPC9653 is a mixed analog/digital product. Its analog

circuitry is naturally susceptible to random noise, especially if

this noise is seen on the power supply pins. Random noise

filter shown in Figure 3. “V

filter cut-off frequency is around 4 kHz and the noise

attenuation at 100 kHz is better than 42 dB.

Power Supply Filter”, the

CC_PLL

on the V

power supply impacts the device

CCA_PLL

characteristics, for instance I/O jitter. The MPC9653 provides

separate power supplies for the output buffers (V ) and the

CC

) of the device. The purpose of

As the noise frequency crosses the series resonant point

of an individual capacitor its overall impedance begins to look

inductive and thus increases with increasing frequency. The

parallel capacitor combination shown ensures that a low

impedance path to ground exists for frequencies well above

the bandwidth of the PLL. Although the MPC9653 has

several design features to minimize the susceptibility to

power supply noise (isolated power and grounds and fully

differential PLL) there still may be applications in which

overall performance is being degraded due to system power

supply noise. The power supply filter schemes discussed in

this section should be adequate to eliminate power supply

noise related problems in most designs.

phase-locked loop (V

CCA_PLL

this design technique is to isolate the high switching noise

digital outputs from the relatively sensitive internal analog

phase-locked loop. In a digital system environment where it is

more difficult to minimize noise on the power supplies a

second level of isolation may be required. The simple but

effective form of isolation is a power supply filter on the

V

pin for the MPC9653. Figure 3. illustrates a typical

CC_PLL

power supply filter scheme. The MPC9653 frequency and

phase stability is most susceptible to noise with spectral

content in the 100kHz to 20MHz range. Therefore the filter

should be designed to target this range. The key parameter

that needs to be met in the final filter design is the DC voltage

drop across the series filter resistor R . From the data sheet

F

Using the MPC9653 in zero–delay applications

the I

current (the current sourced through the V

CCA

CC_PLL

Nested clock trees are typical applications for the

MPC9653. Designs using the MPC9653 as LVCMOS PLL

fanout buffer with zero insertion delay will show significantly

lower clock skew than clock distributions developed from

CMOS fanout buffers. The external feedback option of the

MPC9653 clock driver allows for its use as a zero delay

buffer. The PLL aligns the feedback clock output edge with

the clock input reference edge resulting a near zero delay

through the device (the propagation delay through the device

is virtually eliminated). The maximum insertion delay of the

device in zero-delay applications is measured between the

reference clock input and any output. This effective delay

consists of the static phase offset, I/O jitter (phase or

long-term jitter), feedback path delay and the output-to-output

skew error relative to the feedback output.

pin) is typically 5 mA (10 mA maximum), assuming that a

minimum of 2.985V must be maintained on the V pin.

CC_PLL

R = 5–15Ω

F

C = 22 µF

F

R

F

VCC_PLL

VCC

C

F

10 nF

MPC9653

VCC

33...100 nF

Figure 3. V

CC_PLL

Power Supply Filter

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Calculation of part-to-part skew

I/O jitter confidence factor of 99.7% (± 3 ) is assumed,

resulting in a worst case timing uncertainty from input to any

output of -197 ps to 297 ps (at 125 MHz reference frequency)

relative to PCLK:

The MPC9653 zero delay buffer supports applications

where critical clock signal timing can be maintained across

several devices. If the reference clock inputs of two or more

MPC9653 are connected together, the maximum overall

timing uncertainty from the common PCLK input to any output

is:

t

=

[–17ps...117ps] + [–150ps...150ps] +

[(10ps –3)...(10ps 3)] + t

SK(PP)

PD, LINE(FB)

[–197ps...297ps] + t

PD, LINE(FB)

t

SK(PP)

t

= t

( )

+ t

SK(O)

+ t

PD, LINE(FB)

+ t

JIT( )

CF

SK(PP)

Due to the frequency dependence of the I/O jitter,

Figure 5. “Max. I/O Jitter versus frequency” can be used for a

more precise timing performance analysis.

This maximum timing uncertainty consist of 4

components: static phase offset, output skew, feedback

board trace delay and I/O (phase) jitter:

PCLK

Common

t

PD,LINE(FB)

–t

(

)

QFB

Device 1

t

JIT(

)

Any Q

Device 1

+t

SK(O)

+t

(

)

Figure 5. Max. I/O Jitter versus frequency

Driving Transmission Lines

QFB

Device2

t

JIT(

)

Any Q

Device 2

The MPC9653 clock driver was designed to drive high

speed signals in a terminated transmission line environment.

To provide the optimum flexibility to the user the output

drivers were designed to exhibit the lowest impedance

possible. With an output impedance of less than 20Ω the

drivers can drive either parallel or series terminated

transmission lines. For more information on transmission

lines the reader is referred to Motorola application note

AN1091. In most high performance clock networks

point-to-point distribution of signals is the method of choice.

In a point-to-point scheme either series terminated or parallel

terminated transmission lines can be used. The parallel

technique terminates the signal at the end of the line with a

+t

SK(O)

Max. skew

t

SK(PP)

Figure 4. MPC9653 max. device-to-device skew

Due to the statistical nature of I/O jitter a RMS value (1 ) is

specified. I/O jitter numbers for other confidence factors (CF)

can be derived from Table 10.

Table 10: Confidence Factor CF

CF

± 1

± 2

± 3

± 4

± 5

± 6

Probability of clock edge within the distribution

0.68268948

0.95449988

0.99730007

0.99993663

0.99999943

0.99999999

50Ω resistance to V ÷2.

CC

This technique draws a fairly high level of DC current and

thus only a single terminated line can be driven by each

output of the MPC9653 clock driver. For the series terminated

case however there is no DC current draw, thus the outputs

can drive multiple series terminated lines. Figure 6. “Single

versus Dual Transmission Lines” illustrates an output driving

a single series terminated line versus two series terminated

lines in parallel. When taken to its extreme the fanout of the

MPC9653 clock driver is effectively doubled due to its

capability to drive multiple lines.

The feedback trace delay is determined by the board

layout and can be used to fine-tune the effective delay

through each device. In the following example calculation a

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MPC9653

3.0

MPC9653

OUTPUT

BUFFER

OutA

= 3.8956

OutB

t = 3.9386

t

D

2.5

2.0

1.5

1.0

0.5

0

Z

= 50Ω

D

O

R = 36Ω

S

14Ω

IN

OutA

In

MPC9653

OUTPUT

BUFFER

Z

O

= 50Ω

R = 36Ω

S

OutB0

OutB1

14Ω

Z

O

R = 36Ω

S

2

4

6

8

10

12

14

Figure 6. Single versus Dual Transmission Lines

TIME (nS)

Figure 7. Single versus Dual Waveforms

The waveform plots in Figure 7. “Single versus Dual Line

Termination Waveforms” show the simulation results of an

output driving a single line versus two lines. In both cases the

drive capability of the MPC9653 output buffer is more than

sufficient to drive 50Ω transmission lines on the incident

edge. Note from the delay measurements in the simulations a

delta of only 43ps exists between the two differently loaded

outputs. This suggests that the dual line driving need not be

used exclusively to maintain the tight output-to-output skew

of the MPC9653. The output waveform in Figure 7. “Single

versus Dual Line Termination Waveforms” shows a step in

the waveform, this step is caused by the impedance

mismatch seen looking into the driver. The parallel

combination of the 36Ω series resistor plus the output

impedance does not match the parallel combination of the

line impedances. The voltage wave launched down the two

lines will equal:

Since this step is well above the threshold region it will not

cause any false clock triggering, however designers may be

uncomfortable with unwanted reflections on the line. To better

match the impedances when driving multiple lines the

situation in Figure 8. “Optimized Dual Line Termination”

should be used. In this case the series terminating resistors

are reduced such that when the parallel combination is added

to the output buffer impedance the line impedance is perfectly

matched.

MPC9653

OUTPUT

BUFFER

Z

= 50Ω

O

R = 22Ω

S

14Ω

Z

O

R = 22Ω

S

V

Z

R

V

= V ( Z ÷ (R +R +Z ))

S 0 S 0 0

L

0

S

0

= 50Ω || 50Ω

= 36Ω || 36Ω

= 14Ω

14Ω + 22Ω 22Ω = 50Ω 50Ω

25Ω = 25Ω

= 3.0 ( 25 ÷ (18+14+25)

= 1.31V

L

Figure 8. Optimized Dual Line Termination

At the load end the voltage will double, due to the near

unity reflection coefficient, to 2.6V. It will then increment

towards the quiescent 3.0V in steps separated by one round

trip delay (in this case 4.0ns).

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MPC9653 DUT

Z

O

= 50 Ω

Differential

Pulse Generator

Z = 50

Z

O

= 50 Ω

R = 50 Ω

T

R = 50 Ω

T

V

TT

V

TT

Figure 9. PCLK MPC9653 AC test reference

V

CC

V

2

CC

GND

PCLK

FB_IN

V

PP

= 0.8V

V

CC

=

CMR

–1.3V

V

CC

V

CC

GND

V

CC

2

CC

t

SK(O)

GND

The pin–to–pin skew is defined as the worst case difference

in propagation delay between any similar delay path within a

single device

t

(PD)

Figure 10. Output–to–output Skew t

SK(O)

Figure 11. Propagation delay (t

, static phase

(PD)

offset) test reference

V

CC

PCLK

FB_IN

V

CC

GND

2

t

P

T

0

DC = t /T x 100%

P 0

T

JIT(

= |T –T mean|

)

0 1

The time from the PLL controlled edge to the non controlled

edge, divided by the time between PLL controlled edges,

expressed as a percentage

The deviation in t for a controlled edge with respect to a t mean in a

random sample of cycles

0

Figure 12. Output Duty Cycle (DC)

Figure 13. I/O Jitter

T

= |T –T

N+1

|

T

= |T –1/f |

JIT(CC)

N

JIT(PER) N 0

T

N

T

N+1

T

0

The variation in cycle time of a signal between adjacent cycles, over a

random sample of adjacent cycle pairs

The deviation in cycle time of a signal with respect to the ideal period over

a random sample of cycles

Figure 14. Cycle–to–cycle Jitter

Figure 15. Period Jitter

V =3.3V

CC

2.4

0.55

t

F

t

R

Figure 16. Output Transition Time Test Reference

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MPC9653

OUTLINE DIMENSIONS

FA SUFFIX

LQFP PACKAGE

CASE 873A-03

ISSUE B

4X

0.20

H

A–B D

6

D1

3

A, B, D

e/2

D1/2

32

PIN 1 INDEX

25

1

F

A

B

E1/2

6

E1

E

4

DETAIL G

E/2

DETAIL G

17

8

NOTES:

9

7

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES PER

ASME Y14.5M, 1994.

3. DATUMS A, B, AND D TO BE DETERMINED AT

DATUM PLANE H.

D

4

D/2

4X

D

4. DIMENSIONS D AND E TO BE DETERMINED AT

SEATING PLANE C.

0.20

C A–B D

5. DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION

SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED

THE MAXIMUM b DIMENSION BY MORE THAN

0.08–mm. DAMBAR CANNOT BE LOCATED ON THE

LOWER RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSION AND ADJACENT LEAD OR

PROTRUSION: 0.07–mm.

H

_28Xe

32X

0.1 C

SEATING

PLANE

6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD

PROTRUSION. ALLOWABLE PROTRUSION IS

0.25–mm PER SIDE. D1 AND E1 ARE MAXIMUM

PLASTIC BODY SIZE DIMENSIONS INCLUDING

MOLD MISMATCH.

7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.

8. THESE DIMENSIONS APPLY TO THE FLAT

SECTION OF THE LEAD BETWEEN 0.1–mm AND

0.25–mm FROM THE LEAD TIP.

C

DETAIL AD

BASE

PLATING

METAL

b1

c

c1

MILLIMETERS

DIM MIN

MAX

1.60

0.15

1.45

0.45

0.40

0.20

0.16

A

A1

A2

b

b1

c

1.40

0.05

1.35

0.30

0.09

b

5

8

8X ( 1 )

M

0.20

C A–B D

R R2

SECTION F–F

R R1

0.25

c1

D

9.00 BSC

D1

e

E

E1

L

7.00 BSC

0.80 BSC

9.00 BSC

7.00 BSC

A2

A

GAUGE PLANE

0.50

0.70

L1

θ

θ1

R1

R2

S

1.00 REF

0

12 REF

(S)

7

A1

L

0.08

0.20

–––

(L1)

0.20 REF

DETAIL AD

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MPC9653

NOTES

For More Information On This Product,

TIMING SOLUTIONS

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MPC9653

Informationin this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright

licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document.

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and

specificallydisclaims any and all liability, includingwithoutlimitationconsequentialorincidentaldamages. “Typical”parameterswhichmaybeprovidedinMotorola

datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime.Alloperatingparameters,including“Typicals”

must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of

others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other

applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury

ordeathmayoccur.ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola

and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees

arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that

Motorola was negligent regarding the design or manufacture of the part.

MOTOROLA and the Stylized M Logo are registered in the US Patent and TrademarkOffice. All other product or service names are the property of their respective

owners.

Motorola Inc. 2003

HOW TO REACH US:

USA/EUROPE/LOCATIONS NOT LISTED:

ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre,

2, Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.

852–26668334

TECHNICAL INFORMATION CENTER:

1–800–521–6274 or 480–768–2130

HOME PAGE:http://motorola.com/semiconductors

JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center,

3–20–1, Minami–Azabu, Minato–ku, Tokyo 106–8573 Japan

81–3–3440–3569

◊

MPC9653/D

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型号：	MPC9653
厂家：	MOTOROLA
描述：	3.3V 1:8 LVCMOS PLL CLOCK GENERATOR 3.3V 1 ： 8 LVCMOS PLL时钟发生器时钟发生器
文件：	总12页 (文件大小：293K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MPC9653 [MOTOROLA]

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