MTD1P40E [MOTOROLA]
1A, 400V, 8ohm, P-CHANNEL, Si, POWER, MOSFET, DPAK-3;
| 型号： | MTD1P40E |
| 厂家： | 
MOTOROLA |
| 描述： | 1A, 400V, 8ohm, P-CHANNEL, Si, POWER, MOSFET, DPAK-3 开关 脉冲 晶体管 |
| 文件： | 总10页 (文件大小：182K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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by MTD1P40E/D
SEMICONDUCTOR TECHNICAL DATA
Motorola Preferred Device
TMOS POWER FET
1.0 AMPERES
400 VOLTS
P–Channel Enhancement–Mode Silicon Gate
This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltage–blocking capability without
degrading performance over time. In addition, this advanced TMOS
E–FET is designed to withstand high energy in the avalanche and
commutation mode. The new energy efficient design also offers a
drain–to–soure diode with fast recovery time. Designed for high
converters and PWM motor controls, these devices are particularly
well suited for low power flourescent lighting applications where
R
= 8.0 OHM
DS(on)
D
V
andR
havebeenoptimizedforusewithcomplimentary
DSS
N–Channel devices.
DS(on)
G
CASE 369A–13, Style 2
DPAK
•
•
•
Robust High Voltage Termination
Avalanche Energy Specified
Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
S
•
Diode is Characterized for Use in Bridge Circuits
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
C
Rating
Symbol
Value
Unit
Drain–Source Voltage
V
400
Vdc
Vdc
DSS
Drain–Gate Voltage (R
= 1.0 MΩ)
Gate–Source Voltage — Continuous
V
DGR
400
GS
V
± 20
± 25
Vdc
Vpk
GS
Gate–Source Voltage — Single Pulse (t ≤ 50 µs)
V
GSM
p
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (t ≤ 10 µs)
I
I
1.0
0.8
3.5
Adc
Apk
D
D
I
p
DM
Total Power Dissipation
Derate above 25°C
P
D
65
0.53
1.75
Watts
W/°C
Watts
Total Power Dissipation @ T = 25°C, when mounted with the minimum recommended pad size
C
Operating and Storage Temperature Range
T , T
J stg
–55 to 150
°C
UNCLAMPED DRAIN–TO–SOURCE AVALANCHE CHARACTERISTICS (T <150°C)
J
Single Pulse Drain–to–Source Avalanche Energy — Starting T = 25°C
E
AS
45
mJ
J
(V
DD
= 100 Vdc, V
= 10 Vdc, I = 3.0 Apk, L = 10 mH, R = 25 Ω)
GS L G
THERMAL CHARACTERISTICS
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient
R
R
R
1.91
100
71.4
°C/W
°C
θJC
θJA
θJA
(1)
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 5 seconds
T
260
L
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
Motorola, Inc. 1998
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
V
Vdc
(BR)DSS
(V
= 0 Vdc, I = 0.25 mAdc)
400
—
—
453
—
—
GS
D
Temperature Coefficient (Positive)
mV/°C
µAdc
Zero Gate Voltage Drain Current
I
DSS
(V
DS
(V
DS
= 400 Vdc, V
= 400 Vdc, V
= 0 Vdc)
= 0 Vdc, T = 125°C)
—
—
—
—
10
100
GS
GS
J
Gate–Body Leakage Current (V
GS
= ±20 Vdc, V
= 0)
I
—
—
100
nAdc
Vdc
DS
GSS
(1)
ON CHARACTERISTICS
Gate Threshold Voltage
V
GS(th)
(V
= V , I = 0.25 mA)
2.0
—
2.6
4.0
4.0
—
DS
GS
D
Threshold Temperature Coefficient (Negative)
mV/°C
Ohm
Vdc
Static Drain–Source On–Resistance (V = 10 Vdc, I = 0.5 Adc)
R
V
—
6.0
8.0
GS
= 10 Vdc)
D
DS(on)
Drain–Source On–Voltage (V
GS
DS(on)
(I = 1.0 Adc)
—
—
—
—
9.6
8.4
D
(I = 0.5 Adc, T = 125°C)
D
J
Forward Transconductance (V
= 15 Vdc, I = 0.5 Adc)
g
FS
0.5
1.2
—
mhos
pF
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
C
—
—
—
355
56
500
110
20
iss
(V
DS
= 25 Vdc, V
GS
f = 1.0 MHz)
= 0 Vdc,
Output Capacitance
C
oss
Reverse Transfer Capacitance
C
16
rss
(1)
SWITCHING CHARACTERISTICS
Turn–On Delay Time
t
—
—
—
—
—
—
—
—
15.4
12
30
20
50
40
20
—
—
—
ns
d(on)
(V
(V
= 200 Vdc, I = 1.0 Adc,
D
Rise Time
DD
t
r
V
= 10 Vdc,
GS
G
Turn–Off Delay Time
Fall Time
t
24
d(off)
R
= 9.1 Ω)
t
f
20
Gate Charge
Q
T
Q
1
Q
2
Q
3
12
nC
2.0
6.0
4.0
= 320 Vdc, I = 1.0 Adc,
DS
D
V
GS
= 10 Vdc)
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
V
Vdc
ns
SD
(I = 1.0 Adc, V
(I = 1.0 Adc, V
GS
= 0 Vdc)
= 0 Vdc, T = 125°C)
S
GS
—
—
2.5
4.5
4.0
—
S
J
Reverse Recovery Time
t
—
—
—
—
175
125
52
—
—
—
—
rr
t
a
(I = 1.0 Adc, V
= 0 Vdc,
dI /dt = 100 A/µs)
S
GS
S
t
b
Reverse Recovery Stored Charge
Q
1.2
µC
RR
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
2
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
1.8
1.6
1.4
2
V
= 10 V
V
≥ 10 V
T
= –55°C
GS
DS
J
T
= 25°C
J
6 V
8 V
100
°
C
25°C
1.5
1
5.5 V
1.2
1.0
0.8
0.6
0.4
5 V
4.5 V
4 V
0.5
0
0.2
0
0
2
4
6
8
0
1
2
3
4
5
6
7
8
9
10
V
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
V , GATE–TO–SOURCE VOLTAGE (VOLTS)
GS
DS
Figure 1. On–Region Characteristics
Figure 2. Transfer Characteristics
6.0
5.8
5.6
12
10
8
T
J
= 25°C
V
= 10 V
GS
T
= 100°C
J
5.4
5.2
5.0
4.8
V
= 10 V
GS
15 V
25°C
6
4
4.6
4.4
4.2
4.0
–55°C
2
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
I
, DRAIN CURRENT (AMPS)
I
, DRAIN CURRENT (AMPS)
D
D
Figure 3. On–Resistance versus Drain Current
and Temperature
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
2
1000
100
10
V
= 10 V
GS
= 0.5 A
V
= 0 V
GS
1.75
I
D
1.5
1.25
1
T
= 125°C
J
0.75
0.5
0.25
0
–50
–25
0
25
50
75
100
C)
125
150
0
100
V , DRAIN–TO–SOURCE VOLTAGE (VOLTS)
DS
200
300
400
500
T , JUNCTION TEMPERATURE (
°
J
Figure 5. On–Resistance Variation with
Temperature
Figure 6. Drain–To–Source Leakage
Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
3
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The capacitance (C ) is read from the capacitance curve at
iss
a voltage corresponding to the off–state condition when cal-
culating t
and is read at a voltage corresponding to the
d(on)
on–state when calculating t
.
d(off)
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (I
) can be made from a rudimentary analysis of
G(AV)
the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a resis-
tive load, V remains virtually constant at a level known as
GS
the plateau voltage, V
. Therefore, rise and fall times may
SGP
be approximated by the following:
t = Q x R /(V
– V )
GSP
r
2
G
GG
t = Q x R /V
f
2
G
GSP
where
V
= the gate drive voltage, which varies from zero to V
GG
GG
R
= the gate drive resistance
G
and Q and V
are read from the gate charge curve.
GSP
2
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
t
= R
= R
C
C
In [V
/(V
GG GG
– V
)]
GSP
d(on)
G
iss
In (V
/V
GG GSP
)
d(off)
G
iss
1000
800
600
400
V
= 0 V
V = 0 V
GS
DS
T
= 25°C
J
C
iss
C
rss
C
iss
C
oss
200
0
C
rss
–10
–5
0
5
10
15
20
25
V
V
DS
GS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
4
Motorola TMOS Power MOSFET Transistor Device Data
100
12
600
500
400
300
200
T
I
V
= 25°C
= 1.0 A
J
D
Q
T
10
8
t
= 200 V
= 10 V
f
DD
GS
V
V
t
GS
t
t
r
d(off)
d(on)
6
4
10
Q
Q
2
1
T
I
= 25°C
= 1.0 A
J
D
V
DS
100
0
2
0
Q
3
1
0
3
6
9
12
15
1
10
, GATE RESISTANCE (OHMS)
100
R
G
Q , TOTAL GATE CHARGE (nC)
g
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
1.0
0.9
V
T
= 0 V
GS
= 25
°C
0.8
0.7
0.6
0.5
0.4
0.3
0.2
J
0.1
0
0
0.4
0.8
1.2
1.6
2.0
2.4
V
, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
SD
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define the
maximum simultaneous drain–to–source voltage and drain
current that a transistor can handle safely when it is forward
biased. Curves are based upon maximum peak junction
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction
temperature.
temperature and a case temperature (T ) of 25°C. Peak
C
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–General
Data and Its Use.”
Although many E–FETs can withstand the stress of
drain–to–source avalanche at currents up to rated pulsed
Switching between the off–state and the on–state may
traverse any load line provided neither rated peak current
current (I
), the energy rating is specified at rated
DM
(I
) nor rated voltage (V ) is exceeded and the transition
DM DSS
continuous current (I ), in accordance with industry custom.
D
time (t ,t ) do not exceed 10 µs. In addition the total power av-
eraged over a complete switching cycle must not exceed
r f
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
(T
– T )/(R ).
J(MAX)
C
θJC
currents below rated continuous I can safely be assumed to
A Power MOSFET designated E–FET can be safely used
D
in switching circuits with unclamped inductive loads. For
Motorola TMOS Power MOSFET Transistor Device Data
equal the values indicated.
5
SAFE OPERATING AREA
10
48
44
40
36
V
= 20 V
GS
SINGLE PULSE
I
= 1.0 A
D
T
= 25
°C
10 µs
C
100 µs
32
28
24
20
16
12
8
1
1 ms
R
10 ms
dc
LIMIT
THERMAL LIMIT
PACKAGE LIMIT
DS(on)
4
0
0.1
0.1
1
10
100
1000
25
50
75
100
125
150
T , STARTING JUNCTION TEMPERATURE (
°C)
V
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
J
DS
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1
D = 0.5
0.2
0.1
0.1
0.05
0.02
SINGLE PULSE
0.01
0.01
1.0E–05
1.0E–04
1.0E–03
1.0E–02
1.0E–01
1.0E+00
1.0E+01
t, TIME (SECONDS)
Figure 13. Thermal Response
di/dt
I
S
t
rr
t
t
a
b
TIME
0.25 I
t
S
p
I
S
Figure 14. Diode Reverse Recovery Waveform
6
Motorola TMOS Power MOSFET Transistor Device Data
INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must be
the correct size to ensure proper solder connection interface
between the board and the package. With the correct pad
geometry, the packages will self align when subjected to a
solder reflow process.
0.165
4.191
0.118
3.0
0.100
2.54
0.063
1.6
0.190
4.826
0.243
6.172
inches
mm
POWER DISSIPATION FOR A SURFACE MOUNT DEVICE
The power dissipation for a surface mount device is a
dissipation can be increased. Although one can almost double
the power dissipation with this method, one will be giving up
area on the printed circuit board which can defeat the purpose
of using surface mount technology. For example, a graph of
function of the drain pad size. These can vary from the
minimum pad size for soldering to a pad size given for
maximum power dissipation. Power dissipation for a surface
mount device is determined by T
junction temperature of the die, R
, the maximum rated
, the thermal resistance
R
versus drain pad area is shown in Figure 15.
J(max)
θJA
θJA
100
from the device junction to ambient, and the operating
temperature, T . Using the values provided on the data sheet,
Board Material = 0.0625
″
A
G–10/FR–4, 2 oz Copper
P
can be calculated as follows:
D
1.75 Watts
80
60
40
20
T
= 25°C
A
T
– T
A
J(max)
P
=
D
R
θJA
3.0 Watts
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature T of 25°C, one can
calculate the power dissipation of the device. For a DPAK
5.0 Watts
6
A
device, P is calculated as follows.
D
0
2
4
8
10
A, AREA (SQUARE INCHES)
150°C – 25°C
= 1.75 Watts
P
=
D
71.4°C/W
Figure 15. Thermal Resistance versus Drain Pad
Area for the DPAK Package (Typical)
The 71.4°C/W for the DPAK package assumes the use of
the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 1.75 Watts. There are
other alternatives to achieving higher power dissipation from
thesurfacemountpackages. Oneistoincreasetheareaofthe
drain pad. By increasing the area of the drain pad, the power
Another alternative would be to use a ceramic substrate or
an aluminum core board such as Thermal Clad . Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
Motorola TMOS Power MOSFET Transistor Device Data
7
SOLDER STENCIL GUIDELINES
Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads. Solder
stencils are used to screen the optimum amount. These
stencils are typically 0.008 inches thick and may be made of
brass or stainless steel. For packages such as the SC–59,
SC–70/SOT–323, SOD–123, SOT–23, SOT–143, SOT–223,
SO–8, SO–14, SO–16, and SMB/SMC diode packages, the
stencil opening should be the same as the pad size or a 1:1
SOLDER PASTE
OPENINGS
STENCIL
2
registration. This is not the case with the DPAK and D PAK
packages. If one uses a 1:1 opening to screen solder onto the
drain pad, misalignment and/or “tombstoning” may occur due
to an excess of solder. For these two packages, the opening
in the stencil for the paste should be approximately 50% of the
tab area. The opening for the leads is still a 1:1 registration.
Figure 16. Typical Stencil for DPAK and
2
D PAK Packages
2
Figure 16 shows a typical stencil for the DPAK and D PAK
packages. The pattern of the opening in the stencil for the
drain pad is not critical as long as it allows approximately 50%
of the pad to be covered with paste.
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• When shifting from preheating to soldering, the maximum
temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should be
allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.
• Always preheat the device.
• The delta temperature between the preheat and soldering
should be 100°C or less.*
• Mechanical stress or shock should not be applied during
cooling.
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C.
* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.
* Due to shadowing and the inability to set the wave height to
2
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
incorporate other surface mount components, the D PAK is
not recommended for wave soldering.
8
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL SOLDER HEATING PROFILE
For any given circuit board, there will be a group of control
line on the graph shows the actual temperature that might be
experienced on the surface of a test board at or near a central
solder joint. The two profiles are based on a high density and
a low density board. The Vitronics SMD310 convection/in-
frared reflow soldering system was used to generate this
profile. The type of solder used was 62/36/2 Tin Lead Silver
with a melting point between 177–189°C. When this type of
furnace is used for solder reflow work, the circuit boards and
solder joints tend to heat first. The components on the board
are then heated by conduction. The circuit board, because it
has a large surface area, absorbs the thermal energy more
efficiently, then distributes this energy to the components.
Because of this effect, the main body of a component may be
up to 30 degrees cooler than the adjacent solder joints.
settings that will give the desired heat pattern. The operator
must set temperatures for several heating zones, and a figure
for belt speed. Taken together, these control settings make up
a heating “profile” for that particular circuit board. On
machines controlled by a computer, the computer remembers
these profiles from one operating session to the next. Figure
17 shows a typical heating profile for use when soldering a
surface mount device to a printed circuit board. This profile will
vary among soldering systems but it is a good starting point.
Factors that can affect the profile include the type of soldering
system in use, density and types of components on the board,
typeofsolderused, andthetypeofboardorsubstratematerial
being used. This profile shows temperature versus time. The
STEP 1
PREHEAT
ZONE 1
“RAMP”
STEP 2
VENT
“SOAK” ZONES 2 & 5
“RAMP”
STEP 3
HEATING
STEP 4
HEATING
ZONES 3 & 6 ZONES 4 & 7
“SOAK”
STEP 5
HEATING
STEP 6
VENT
STEP 7
COOLING
205
PEAK AT
SOLDER JOINT
° TO 219°C
“SPIKE”
170°C
200
150
100
50
°C
°C
°C
°C
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
160°
C
150°C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
100°C
140°C
MASS OF ASSEMBLY)
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
TIME (3 TO 7 MINUTES TOTAL)
T
MAX
Figure 17. Typical Solder Heating Profile
Motorola TMOS Power MOSFET Transistor Device Data
9
PACKAGE DIMENSIONS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
SEATING
PLANE
–T–
2. CONTROLLING DIMENSION: INCH.
C
B
R
INCHES
MILLIMETERS
E
V
DIM
A
B
C
D
E
MIN
MAX
0.250
0.265
0.094
0.035
0.040
0.047
MIN
5.97
6.35
2.19
0.69
0.84
0.94
MAX
6.35
6.73
2.38
0.88
1.01
1.19
0.235
0.250
0.086
0.027
0.033
0.037
4
2
Z
A
K
S
F
1
3
G
H
J
K
L
0.180 BSC
4.58 BSC
U
0.034
0.018
0.102
0.040
0.023
0.114
0.87
0.46
2.60
1.01
0.58
2.89
0.090 BSC
2.29 BSC
F
J
R
S
U
V
0.175
0.020
0.020
0.030
0.138
0.215
0.050
–––
0.050
–––
4.45
0.51
0.51
0.77
3.51
5.46
1.27
–––
1.27
–––
L
H
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
D 2 PL
0.13 (0.005)
Z
M
G
T
CASE 369A–13
ISSUE Y
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
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MTD1P40E/D
◊
相关型号：
MTD1P50ET4
Power Field-Effect Transistor, 1A I(D), 500V, 15ohm, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET
MOTOROLA
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