PPC7457RX1267LB [MOTOROLA]

32-BIT, 1267MHz, RISC PROCESSOR, CBGA483, 29 X 29 MM, 1.27 MM PITCH, CERAMIC, BGA-483;


型号：	PPC7457RX1267LB
厂家：	MOTOROLA
描述：	32-BIT, 1267MHz, RISC PROCESSOR, CBGA483, 29 X 29 MM, 1.27 MM PITCH, CERAMIC, BGA-483 时钟外围集成电路
文件：	总87页 (文件大小：1586K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Advance Information

MPC7457EC

Rev. 4, 11/2003

MPC7457

RISC Microprocessor

Hardware Specifications

This hardware specification is primarily concerned with the PowerPC™ MPC7457; however,

unless otherwise noted, all information here also applies to the MPC7447. The MPC7457 and

MPC7447 are implementations of the PowerPC microprocessor family of reduced instruction

set computer (RISC) microprocessors. This hardware specification describes pertinent

electrical and physical characteristics of the MPC7457. For functional characteristics of the

processor, refer to the MPC7450 RISC Microprocessor Family User’s Manual.

This hardware specification contains the following topics:

Topic

Page

Section 1.1, “Overview”

Section 1.2, “Features”

Section 1.3, “Comparison with the MPC7455, MPC7445, MPC7450, MPC7451,

and MPC7441”

Section 1.4, “General Parameters”

Section 1.5, “Electrical and Thermal Characteristics”

Section 1.6, “Pin Assignments”

Section 1.7, “Pinout Listings”

Section 1.8, “Package Description”

Section 1.9, “System Design Information”

Section 1.10, “Document Revision History”

Section 1.11, “Ordering Information”

To locate any published updates for this hardware specification, refer to the website at

http://www.motorola.com/semiconductors.

1.1 Overview

The MPC7457 is the fourth implementation of the fourth generation (G4) microprocessors

from Motorola. The MPC7457 implements the full PowerPC 32-bit architecture and is

targeted at networking and computing systems applications. The MPC7457 consists of a

processor core, a 512-Kbyte L2, and an internal L3 tag and controller that support a glueless

backside L3 cache through a dedicated high-bandwidth interface. The MPC7447 is identical

to the MPC7457 except that it does not support the L3 cache interface.

Features

Figure 1 shows a block diagram of the MPC7457. The core is a high-performance superscalar design

supporting a double-precision floating-point unit and a SIMD multimedia unit. The memory storage

subsystem supports the MPX bus protocol and a subset of the 60x bus protocol to main memory and other

system resources. The L3 interface supports 1, 2, or 4 Mbytes of external SRAM for L3 cache and/or private

memory data. For systems implementing 4 Mbytes of SRAM, a maximum of 2 Mbytes may be used as

cache; the remaining 2 Mbytes must be private memory.

Note that the MPC7457 is a footprint-compatible, drop-in replacement in a MPC7455 application if the core

power supply is 1.3 V.

1.2 Features

This section summarizes features of the MPC7457 implementation of the PowerPC architecture.

Major features of the MPC7457 are as follows:

•

High-performance, superscalar microprocessor

— As many as four instructions can be fetched from the instruction cache at a time.

— As many as three instructions can be dispatched to the issue queues at a time.

— As many as 12 instructions can be in the instruction queue (IQ).

— As many as 16 instructions can be at some stage of execution simultaneously.

— Single-cycle execution for most instructions

— One instruction per clock cycle throughput for most instructions

— Seven-stage pipeline control

•

Eleven independent execution units and three register files

— Branch processing unit (BPU) features static and dynamic branch prediction

– 128-entry (32-set, four-way set-associative) branch target instruction cache (BTIC), a cache

of branch instructions that have been encountered in branch/loop code sequences. If a target

instruction is in the BTIC, it is fetched into the instruction queue a cycle sooner than it can

be made available from the instruction cache. Typically, a fetch that hits the BTIC provides

the first four instructions in the target stream.

– 2048-entry branch history (BHT) with two bits per entry for four levels of

prediction—not-taken, strongly not-taken, taken, and strongly taken

– Up to three outstanding speculative branches

– Branch instructions that do not update the count register (CTR) or link register (LR) are

often removed from the instruction stream.

– Eight-entry link register stack to predict the target address of Branch Conditional to Link

— Four integer units (IUs) that share 32 GPRs for integer operands

– Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer instructions except

multiply, divide, and move to/from special-purpose register instructions

– IU2 executes miscellaneous instructions including the CR logical operations, integer

multiplication and division instructions, and move to/from special-purpose register

instructions

MPC7457 RISC Microprocessor Hardware Specifications

MOTOROLA

Features

Figure 1. MPC7457 Block Diagram

MOTOROLA

MPC7457 RISC Microprocessor Hardware Specifications

Features

— Five-stage FPU and a 32-entry FPR file

– Fully IEEE 754-1985-compliant FPU for both single- and double-precision operations

– Supports non-IEEE mode for time-critical operations

– Hardware support for denormalized numbers

– Thirty-two 64-bit FPRs for single- or double-precision operands

— Four vector units and 32-entry vector register file (VRs)

– Vector permute unit (VPU)

– Vector integer unit 1 (VIU1) handles short-latency AltiVec™ integer instructions, such as

vector add instructions (for example, vaddsbs, vaddshs, and vaddsws)

– Vector integer unit 2 (VIU2) handles longer-latency AltiVec integer instructions, such as

vector multiply add instructions (for example, vmhaddshs, vmhraddshs, and

vmladduhm)

– Vector floating-point unit (VFPU)

— Three-stage load/store unit (LSU)

– Supports integer, floating-point, and vector instruction load/store traffic

– Four-entry vector touch queue (VTQ) supports all four architected AltiVec data stream

operations

– Three-cycle GPR and AltiVec load latency (byte, half-word, word, vector) with one-cycle

throughput

– Four-cycle FPR load latency (single, double) with one-cycle throughput

– No additional delay for misaligned access within double-word boundary

– Dedicated adder calculates effective addresses (EAs)

– Supports store gathering

– Performs alignment, normalization, and precision conversion for floating-point data

– Executes cache control and TLB instructions

– Performs alignment, zero padding, and sign extension for integer data

– Supports hits under misses (multiple outstanding misses)

– Supports both big- and little-endian modes, including misaligned little-endian accesses

•

Three issue queues FIQ, VIQ, and GIQ can accept as many as one, two, and three instructions,

respectively, in a cycle. Instruction dispatch requires the following:

— Instructions can be dispatched only from the three lowest IQ entries—IQ0, IQ1, and IQ2

— A maximum of three instructions can be dispatched to the issue queues per clock cycle

— Space must be available in the CQ for an instruction to dispatch (this includes instructions that

are assigned a space in the CQ but not in an issue queue)

•

Rename buffers

— 16 GPR rename buffers

— 16 FPR rename buffers

— 16 VR rename buffers

Dispatch unit

— Decode/dispatch stage fully decodes each instruction

MPC7457 RISC Microprocessor Hardware Specifications

MOTOROLA

Features

•

Completion unit

— The completion unit retires an instruction from the 16-entry completion queue (CQ) when all

instructions ahead of it have been completed, the instruction has finished execution, and no

exceptions are pending.

— Guarantees sequential programming model (precise exception model)

— Monitors all dispatched instructions and retires them in order

— Tracks unresolved branches and flushes instructions after a mispredicted branch

— Retires as many as three instructions per clock cycle

•

Separate on-chip L1 instruction and data caches (Harvard architecture)

— 32-Kbyte, eight-way set-associative instruction and data caches

— Pseudo least-recently-used (PLRU) replacement algorithm

— 32-byte (eight-word) L1 cache block

— Physically indexed/physical tags

— Cache write-back or write-through operation programmable on a per-page or per-block basis

— Instruction cache can provide four instructions per clock cycle; data cache can provide four

words per clock cycle

— Caches can be disabled in software.

— Caches can be locked in software.

— MESI data cache coherency maintained in hardware

— Separate copy of data cache tags for efficient snooping

— Parity support on cache and tags

— No snooping of instruction cache except for icbi instruction

— Data cache supports AltiVec LRU and transient instructions

— Critical double- and/or quad-word forwarding is performed as needed. Critical quad-word

forwarding is used for AltiVec loads and instruction fetches. Other accesses use critical

double-word forwarding.

•

Level 2 (L2) cache interface

— On-chip, 512-Kbyte, eight-way set-associative unified instruction and data cache

— Fully pipelined to provide 32 bytes per clock cycle to the L1 caches

— A total nine-cycle load latency for an L1 data cache miss that hits in L2

— PLRU replacement algorithm

— Cache write-back or write-through operation programmable on a per-page or per-block basis

— 64-byte, two-sectored line size

— Parity support on cache

•

Level 3 (L3) cache interface (not implemented on MPC7447)

— Provides critical double-word forwarding to the requesting unit

— Internal L3 cache controller and tags

— External data SRAMs

— Support for 1-, 2-, and 4-Mbyte (MB) total SRAM space

— Support for 1- or 2-MB of cache space

— Cache write-back or write-through operation programmable on a per-page or per-block basis

MOTOROLA

MPC7457 RISC Microprocessor Hardware Specifications

Features

— 64-byte (1-MB) or 128-byte (2-MB) sectored line size

— Private memory capability for half (1 MB minimum) or all of the L3 SRAM space for a total of

1-, 2-, or 4-MB of private memory

— Supports MSUG2 dual data rate (DDR) synchronous burst SRAMs, PB2 pipelined

synchronous burst SRAMs, and pipelined (register-register) late write synchronous burst

SRAMs

— Supports parity on cache and tags

— Configurable core-to-L3 frequency divisors

— 64-bit external L3 data bus sustains 64 bits per L3 clock cycle

Separate memory management units (MMUs) for instructions and data

— 52-bit virtual address; 32- or 36-bit physical address

— Address translation for 4-Kbyte pages, variable-sized blocks, and 256-Mbyte segments

•

— Memory programmable as write-back/write-through, caching-inhibited/caching-allowed, and

memory coherency enforced/memory coherency not enforced on a page or block basis

— Separate IBATs and DBATs (eight each) also defined as SPRs

— Separate instruction and data translation lookaside buffers (TLBs)

– Both TLBs are 128-entry, two-way set-associative, and use LRU replacement algorithm

– TLBs are hardware- or software-reloadable (that is, on a TLB miss a page table search is

performed in hardware or by system software)

•

Efficient data flow

— Although the VR/LSU interface is 128 bits, the L1/L2/L3 bus interface allows up to 256 bits

— The L1 data cache is fully pipelined to provide 128 bits/cycle to or from the VRs

— L2 cache is fully pipelined to provide 256 bits per processor clock cycle to the L1 cache

— As many as eight outstanding, out-of-order, cache misses are allowed between the L1 data

cache and L2/L3 bus

— As many as 16 out-of-order transactions can be present on the MPX bus

— Store merging for multiple store misses to the same line. Only coherency action taken

(address-only) for store misses merged to all 32 bytes of a cache block (no data tenure needed).

— Three-entry finished store queue and five-entry completed store queue between the LSU and the

L1 data cache

— Separate additional queues for efficient buffering of outbound data (such as castouts and

write-through stores) from the L1 data cache and L2 cache

•

Multiprocessing support features include the following:

— Hardware-enforced, MESI cache coherency protocols for data cache

— Load/store with reservation instruction pair for atomic memory references, semaphores, and

other multiprocessor operations

Power and thermal management

— 1.3-V processor core

— The following three power-saving modes are available to the system:

– Nap—Instruction fetching is halted. Only those clocks for the time base, decrementer, and

JTAG logic remain running. The part goes into the doze state to snoop memory operations

on the bus and back to nap using a QREQ/QACK processor-system handshake protocol.

MPC7457 RISC Microprocessor Hardware Specifications

MOTOROLA

Comparison with the MPC7455, MPC7445, MPC7450, MPC7451, and MPC7441

– Sleep—Power consumption is further reduced by disabling bus snooping, leaving only the

PLL in a locked and running state. All internal functional units are disabled.

– Deep sleep—When the part is in the sleep state, the system can disable the PLL. The system

can then disable the SYSCLK source for greater system power savings. Power-on reset

procedures for restarting and relocking the PLL must be followed on exiting the deep sleep

state.

— Thermal management facility provides software-controllable thermal management. Thermal

management is performed through the use of three supervisor-level registers and an

MPC7457-specific thermal management exception.

— Instruction cache throttling provides control of instruction fetching to limit power consumption

Performance monitor can be used to help debug system designs and improve software efficiency

In-system testability and debugging features through JTAG boundary-scan capability

Testability

•

— LSSD scan design

— IEEE 1149.1 JTAG interface

— Array built-in self test (ABIST)—factory test only

Reliability and serviceability

•

— Parity checking on system bus and L3 cache bus

— Parity checking on the L2 and L3 cache tag arrays

1.3 Comparison with the MPC7455, MPC7445,

MPC7450, MPC7451, and MPC7441

Table 1 compares the key features of the MPC7457 with the key features of the earlier MPC7455,

MPC7445, MPC7450, MPC7451, and MPC7441. To achieve a higher frequency, the number of logic levels

per cycle is reduced. Also, to achieve this higher frequency, the pipeline of the MPC7457 is extended

(compared to the MPC7400), while maintaining the same level of performance as measured by the number

of instructions executed per cycle (IPC).

Table 1. Microarchitecture Comparison

MPC7450/MPC7451/

Microarchitectural Specs

MPC7457/MPC7447

MPC7455/MPC7445

MPC7441

Basic Pipeline Functions

Logic inversions per cycle

Pipeline stages up to execute

Total pipeline stages (minimum)

Pipeline maximum instruction

throughput

3 + Branch

Pipeline Resources

Instruction buffer size

Completion buffer size

Renames (integer, float, vector)

16, 16, 16

MOTOROLA

MPC7457 RISC Microprocessor Hardware Specifications

Comparison with the MPC7455, MPC7445, MPC7450, MPC7451, and MPC7441

Table 1. Microarchitecture Comparison (continued)

MPC7450/MPC7451/

MPC7441

Microarchitectural Specs

MPC7457/MPC7447

MPC7455/MPC7445

Maximum Execution Throughput

SFX

Vector

2 (any 2 of 4 units)

Scalar floating-point

Out-of-Order Window Size in Execution Queues

SFX integer units

Vector units

1 entry × 3 queues

In order, 4 queues

In order

1 entry × 3 queues

In order, 4 queues

In order

1 entry × 3 queues

In order, 4 queues

In order

Scalar floating-point unit

Branch Processing Resources

Prediction structures

BTIC, BHT, link stack

BTIC size, associativity

BHT size

128-entry, 4-way

2K-entry

Link stack depth

Unresolved branches supported

Branch taken penalty (BTIC hit)

Minimum misprediction penalty

Execution Unit Timings (Latency-Throughput)

Aligned load (integer, float, vector)

Misaligned load (integer, float, vector)

L1 miss, L2 hit latency

3-1, 4-1, 3-1

4-2, 5-2, 4-2

9 data/13 instruction

SFX (aDd Sub, Shift, Rot, Cmp, logicals)

Integer multiply (32 × 8, 32 × 16, 32 × 32)

Scalar float

1-1

3-1, 3-1, 4-2

5-1

1-1

3-1, 3-1, 4-2

5-1

1-1

3-1, 3-1, 4-2

5-1

VSFX (vector simple)

1-1

VCFX (vector complex)

4-1

VFPU (vector float)

4-1

VPER (vector permute)

2-1

MMUs

TLBs (instruction and data)

Tablewalk mechanism

128-entry, 2-way

Hardware + software

8/8

128-entry, 2-way

Hardware + software

8/8

128-entry, 2-way

Hardware + software

4/4

Instruction BATs/data BATs

MPC7457 RISC Microprocessor Hardware Specifications

MOTOROLA

Comparison with the MPC7455, MPC7445, MPC7450, MPC7451, and MPC7441

Table 1. Microarchitecture Comparison (continued)

MPC7450/MPC7451/

Microarchitectural Specs

MPC7457/MPC7447

MPC7455/MPC7445

MPC7441

L1 I Cache/D Cache Features

Size

32K/32K

8-way

Way

32K/32K

8-way

Way

32K/32K

8-way

Way

Associativity

Locking granularity

Parity on I cache

Word

Parity on D cache

Byte

Number of D cache misses (load/store)

Data stream touch engines

5/1

4 streams

On-Chip Cache Features

Cache level

Size/associativity

Access width

512-Kbyte/8-way

256-Kbyte/8-way

256 bits

Number of 32-byte sectors/line

Parity

Byte

Off-Chip Cache Support ¹

Cache level

1 MB, 2MB, 4 MB ²

1MB, 2MB

8-way

1 MB, 2 MB

1MB, 2MB

8-way

1 MB, 2 MB

1MB, 2MB

8-way

Total SRAM space supported

On-chip tag logical size (cache space)

Associativity

Number of 32-byte sectors/line

Off-Chip data SRAM support

Data path width

2, 4

MSUG2 DDR, LW, PB2 MSUG2 DDR, LW, PB2 MSUG2 DDR, LW, PB2

1 MB, 2 MB, 4MB

Byte

1 MB, 2 MB

Byte

1 MB, 2 MB

Byte

Direct mapped SRAM sizes

Parity

Notes:

1. Not implemented on MPC7447, MPC7445, or MPC7441

2. The MPC7457 supports up to 4 MB of SRAM, of which a maximum of 2 MB can be configured as cache memory;

the remaining 2 MB may be unused or configured as private memory.

MOTOROLA

MPC7457 RISC Microprocessor Hardware Specifications

General Parameters

1.4 General Parameters

The following list provides a summary of the general parameters of the MPC7457:

Technology

Die size

0.13 µm CMOS, nine-layer metal

9.1 mm × 10.8 mm

Transistor count

Logic design

Packages

58 million

Fully-static

MPC7447: Surface mount 360 ceramic ball grid array (CBGA)

MPC7457: Surface mount 483 ceramic ball grid array (CBGA)

1.3 V ± 50 mV DC nominal

Core power supply

I/O power supply

1.8 V ± 5% DC, or

2.5 V ± 5% DC, or

1.5 V ± 5% DC (L3 interface only, not implemented on MPC7447)

1.5 Electrical and Thermal Characteristics

This section provides the AC and DC electrical specifications and thermal characteristics for the MPC7457.

1.5.1 DC Electrical Characteristics

The tables in this section describe the MPC7457 DC electrical characteristics.Table 2 provides the absolute

maximum ratings.

Table 2. Absolute Maximum Ratings ¹

Characteristic

Symbol

Maximum Value

Unit

Notes

Core supply voltage

PLL supply voltage

V_DD

AV_DD

OV_DD

GV_DD

V_in

–0.3 to 1.60

Processor bus supply voltage BVSEL = 0

BVSEL = HRESET or OV_DD

–0.3 to 1.95

3, 4

3, 5

3, 6

3, 7

3, 8

9, 10

–0.3 to 2.7

L3 bus supply voltage

Input voltage

L3VSEL = ¬HRESET

L3VSEL = 0

–0.3 to 1.65

–0.3 to 1.95

L3VSEL = HRESET or GV_DD

Processor bus

–0.3 to 2.7

–0.3 to OV_DD+ 0.3

–0.3 to GV_DD+ 0.3

–0.3 to OV_DD+ 0.3

L3 bus

V_in

JTAG signals

V_in

MPC7457 RISC Microprocessor Hardware Specifications

MOTOROLA

Electrical and Thermal Characteristics

Table 2. Absolute Maximum Ratings ¹(continued)

Characteristic

Symbol

Maximum Value

Unit

Notes

Storage temperature range

Notes:

T_stg

–55 to 150

°C

1. Functional and tested operating conditions are given in Table 4. Absolute maximum ratings are stress ratings only,

and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device

reliability or cause permanent damage to the device.

2. Caution: V_DD/AV_DDmust not exceed OV_DD/GV_DDby more than 1.0 V during normal operation; this limit may be

exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

3. Caution: OV_DD/GV_DDmust not exceed V_DD/AV_DDby more than 2.0 V during normal operation; this limit may be

exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

4. BVSEL must be set to 0, such that the bus is in 1.8-V mode.

5. BVSEL must be set to HRESET or 1, such that the bus is in 2.5-V mode.

6. L3VSEL must be set to ¬HRESET (inverse of HRESET), such that the bus is in 1.5-V mode.

7. L3VSEL must be set to 0, such that the bus is in 1.8-V mode.

8. L3VSEL must be set to HRESET or 1, such that the bus is in 2.5-V mode.

9. Caution: V must not exceed OV_DDor GV_DDby more than 0.3 V at any time including during power-on reset.

10.V_inmay overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.

Figure 2 shows the undershoot and overshoot voltage on the MPC7457.

OV_DD/GV_DD+ 20%

OV_DD/GV_DD+ 5%

OV_DD/GV_DD

V_IH

V_IL

GND

GND – 0.3 V

GND – 0.7 V

Not to exceed 10%

of t_SYSCLK

Figure 2. Overshoot/Undershoot Voltage

The MPC7457 provides several I/O voltages to support both compatibility with existing systems and

migration to future systems. The MPC7457 core voltage must always be provided at nominal 1.3 V (see

Table 4 for actual recommended core voltage). Voltage to the L3 I/Os and processor interface I/Os are

provided through separate sets of supply pins and may be provided at the voltages shown in Table 3. The

input voltage threshold for each bus is selected by sampling the state of the voltage select pins at the

negation of the signal HRESET. The output voltage will swing from GND to the maximum voltage applied

to the OV or GV power pins.

MOTOROLA

MPC7457 RISC Microprocessor Hardware Specifications

Electrical and Thermal Characteristics

Table 3. Input Threshold Voltage Setting

Processor Bus Input

Threshold is Relative to:

L3 Bus Input Threshold is

Relative to:

BVSEL Signal

L3VSEL Signal ¹

Notes

1.8 V

Not Available

2.5 V

1.8 V

1.5 V

2.5 V

2, 3

2, 4

¬HRESET

HRESET

¬HRESET

HRESET

2.5 V

Notes:

1. Not implemented on MPC7447

2. Caution: The input threshold selection must agree with the OV_DD/GV_DDvoltages supplied. See notes in Table 2.

3. If used, pull-down resistors should be less than 250 Ω.

4. Applicable to L3 bus interface only. ¬HRESET is the inverse of HRESET.

Table 4 provides the recommended operating conditions for the MPC7457.

Table 4. Recommended Operating Conditions ¹

Recommended Value

Characteristic

Symbol

Unit

Notes

Min

Max

Core supply voltage

PLL supply voltage

V_DD

1.3 V ± 50 mV

°C

AV_DD

OV_DD

GV_DD

1.3 V ± 50 mV

1.8 V ± 5%

2.5 V ± 5%

1.8 V ± 5%

2.5 V ± 5%

1.5 V ± 5%

Processor bus supply voltage BVSEL = 0

BVSEL = HRESET or OV_DD

L3VSEL = 0

L3 bus supply voltage

L3VSEL = HRESET or GV_DDGV_DD

L3VSEL = ¬HRESET

Processor bus

L3 bus

GV_DD

V_in

Input voltage

GND

OV_DD

GV_DD

OV_DD

105

V_in

GND

JTAG signals

V_in

Die-junction temperature

T_j

Notes:

1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions

is not guaranteed.

2. This voltage is the input to the filter discussed in Section 1.9.2, “PLL Power Supply Filtering,” and not necessarily

the voltage at the AV_DDpin, which may be reduced from V_DDby the filter.

3. ¬HRESET is the inverse of HRESET.

MPC7457 RISC Microprocessor Hardware Specifications

MOTOROLA

Electrical and Thermal Characteristics

Table 5 provides the package thermal characteristics for the MPC7457.

Table 5. Package Thermal Characteristics ¹

Value

Characteristic

Symbol

Unit

Notes

MPC7447

MPC7457

Junction-to-ambient thermal resistance, natural

convection

°C/W

2, 3

2, 4

Junction-to-ambient thermal resistance, natural

convection, four-layer (2s2p) board

JMA

Junction-to-ambient thermal resistance, 200 ft/min

airflow, single-layer (1s) board

Junction-to-ambient thermal resistance, 200 ft/min

airflow, four-layer (2s2p) board

Junction-to-board thermal resistance

Junction-to-case thermal resistance

Notes:

°C/W

<0.1

1. Refer to Section 1.9.8, “Thermal Management Information,” for more details about thermal management.

2. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal

resistance.

3. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal

4. Per JEDEC JESD51-6 with the board horizontal

5. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is

measured on the top surface of the board near the package.

6. Thermal resistance between the die and the case top surface as measured by the cold plate method

(MIL SPEC-883 Method 1012.1) with the calculated case temperature. The actual value of R_θJCfor the part is less

than 0.1°C/W.

Table 6 provides the DC electrical characteristics for the MPC7457.

Table 6. DC Electrical Specifications

At recommended operating conditions. See Table 4.

Nominal

Characteristic

Bus

Symbol

Min

Max

Unit Notes

Voltage ¹

Input high voltage

(all inputs including SYSCLK)

1.5

1.8

2.5

1.5

1.8

2.5

—

V_IH

GV_DD× 0.65

GV_DD+ 0.3

OV_DD/GV_DD× 0.65 OV_DD/GV_DD+ 0.3

1.7

–0.3

—

OV_DD/GV_DD+ 0.3

GV_DD× 0.35

OV_DD/GV_DD× 0.35

0.7

Input low voltage

(all inputs including SYSCLK)

V_IL

2, 6

2, 3

Input leakage current,

V_in= GV_DD/OV_DD

I_in

µA

MOTOROLA

MPC7457 RISC Microprocessor Hardware Specifications

Electrical and Thermal Characteristics

Table 6. DC Electrical Specifications (continued)

At recommended operating conditions. See Table 4.

Nominal

Characteristic

Bus

Symbol

Min

Max

Unit Notes

Voltage ¹

High-impedance (off-state)

leakage current, V_in= GV_DD/OV_DD

—

I_TSI

—

µA

2, 3, 4

Output high voltage, I_OH= –5 mA

1.5

1.8

2.5

1.5

1.8

2.5

—

V_OH

OV_DD/GV_DD– 0.45

—

OV_DD/GV_DD– 0.45

1.8

—

Output low voltage, I_OL= 5 mA

V_OL

0.45

0.6

9.5

8.0

Capacitance,

V_in= 0 V,

f = 1 MHz

L3 interface

C_in

All other inputs

Notes:

1. Nominal voltages; see Table 4 for recommended operating conditions.

2. For processor bus signals, the reference is OV_DDwhile GV_DDis the reference for the L3 bus signals.

3. Excludes test signals and IEEE 1149.1 boundary scan (JTAG) signals

4. The leakage is measured for nominal OV_DD/GV_DDand V_DD, or both OV_DD/GV_DDand V_DDmust vary in the same

direction (for example, both OV_DDand V_DDvary by either +5% or –5%).

5. Capacitance is periodically sampled rather than 100% tested.

6. Applicable to L3 bus interface only

Table 7 provides the power consumption for the MPC7457.

Table 7. Power Consumption for MPC7457

Processor (CPU) Frequency

Unit

Notes

867 MHz

1000 MHz

1200 MHz

1267 MHz

Full-Power Mode

Typical

14.8

21.0

15.8

22.0

17.5

24.2

18.3

25.6

1, 2

1, 3

Maximum

Nap Mode

Typical

5.2

5.1

5.2

5.1

1, 2

Sleep Mode

5.1

Deep Sleep Mode (PLL Disabled)

MPC7457 RISC Microprocessor Hardware Specifications

MOTOROLA

Electrical and Thermal Characteristics

Table 7. Power Consumption for MPC7457 (continued)

Processor (CPU) Frequency

Unit

Notes

867 MHz

1000 MHz

1200 MHz

1267 MHz

Typical

5.0

1, 2

Notes:

1. These values apply for all valid processor bus and L3 bus ratios. The values do not include I/O supply power (OV_DD

and GV_DD) or PLL supply power (AV_DD). OV_DDand GV_DDpower is system dependent, but is typically <5% of V_DD

power. Worst case power consumption for AV_DD< 3 mW.

2. Typical power is an average value measured at the nominal recommended V_DD(see Table 4) and 65°C while

running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz.

3. Maximum power is the average measured at nominal V_DDand maximum operating junction temperature (see

Table 4) while running an entirely cache-resident, contrived sequence of instructions which keep all the execution

units maximally busy.

4. Doze mode is not a user-definable state; it is an intermediate state between full-power and either nap or sleep

mode. As a result, power consumption for this mode is not tested.

1.5.2 AC Electrical Characteristics

This section provides the AC electrical characteristics for the MPC7457. After fabrication, functional parts

are sorted by maximum processor core frequency as shown in Section 1.5.2.1, “Clock AC Specifications,”

and tested for conformance to the AC specifications for that frequency. The processor core frequency is

determined by the bus (SYSCLK) frequency and the settings of the PLL_CFG[0:4] signals. Parts are sold

by maximum processor core frequency; see Section 1.11, “Ordering Information.”

1.5.2.1 Clock AC Specifications

Table 8 provides the clock AC timing specifications as defined in Figure 6and represents the tested

operating frequencies of the devices. The maximum system bus frequency, f

, given in Table 8 is

SYSCLK

considered a practical maximum in a typical single-processor system. The actual maximum SYSCLK

frequency for any application of the MPC7457 will be a function of the AC timings of the MPC7457, the

AC timings for the system controller, bus loading, printed-circuit board topology, trace lengths, and so forth,

and may be less than the value given in Table 8.

Table 8. Clock AC Timing Specifications

At recommended operating conditions. See Table 4.

Maximum Processor Core Frequency

Characteristic

Symbol

Unit Notes

867 MHz

1000 MHz

1200 MHz

1267 MHz

Min

600

Max

Min

Max

Min

Max

Min

Max

1267 MHz

Processor frequency

VCO frequency

f_core

867

600

1000

600

1200

600

f_VCO

1200 1733 1200 2000 1200 2400 1200 2534 MHz

SYSCLK frequency

SYSCLK cycle time

SYSCLK rise and fall time

f_SYSCLK

t_SYSCLK

t_KR, t_KF

6.0

—

167

6.0

—

167

6.0

—

167

6.0

—

167 MHz 1, 2

1.0

MOTOROLA

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Electrical and Thermal Characteristics

Table 8. Clock AC Timing Specifications (continued)

At recommended operating conditions. See Table 4.

Maximum Processor Core Frequency

Characteristic

Symbol

Unit Notes

867 MHz

1000 MHz

1200 MHz

1267 MHz

Min

Max

Min

Max

Min

Max

Min

Max

SYSCLK duty cycle

measured at OV_DD/2

t_KHKL

t_SYSCLK

SYSCLK jitter

Internal PLL relock time

Notes:

—

± 150

100

—

± 150

100

—

± 150

100

—

± 150

100

5, 6

µs

1. Caution: The SYSCLK frequency and PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK

(bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or

minimum operating frequencies. Refer to the PLL_CFG[0:4] signal description in Section 1.9.1, “PLL Configuration,”

for valid PLL_CFG[0:4] settings.

2. Assumes lightly-loaded, single-processor system

3. Rise and fall times for the SYSCLK input measured from 0.4 to 1.4 V

4. Timing is guaranteed by design and characterization.

5. This represents total input jitter—short term and long term combined—and is guaranteed by design.

6. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low

to allow cascade connected PLL-based devices to track SYSCLK drivers with the specified jitter.

7. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time

required for PLL lock after a stable V_DDand SYSCLK are reached during the power-on reset sequence. This

specification also applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also

note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the

power-on reset sequence.

Figure 3 provides the SYSCLK input timing diagram.

CV_IH

SYSCLK

CV_IL

t_KHKL

t_SYSCLK

t_KR

t_KF

VM = Midpoint Voltage (OV_DD/2)

Figure 3. SYSCLK Input Timing Diagram

MPC7457 RISC Microprocessor Hardware Specifications

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Electrical and Thermal Characteristics

1.5.2.2 Processor Bus AC Specifications

Table 9 provides the processor bus AC timing specifications for the MPC7457 as defined in Figure 4 and

Figure 5. Timing specifications for the L3 bus are provided in Section 1.5.2.3, “L3 Clock AC

Specifications.”

Table 9. Processor Bus AC Timing Specifications ¹

At recommended operating conditions. See Table 4.

All Speed Grades

Parameter

Symbol ²

Unit

Notes

Min

Max

Input setup times:

A[0:35], AP[0:4]

D[0:63], DP[0:7]

AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL,

TT[0:3], QACK, TA, TBEN, TEA, TS,

t_AVKH

t_DVKH

t_IVKH

1.8

—

EXT_QUAL, PMON_IN, SHD[0:1], BMODE[0:1],

BMODE[0:1], BVSEL, L3VSEL

t_MVKH

1.8

—

Input hold times:

A[0:35], AP[0:4]

D[0:63], DP[0:7]

AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL,

TT[0:3], QACK, TA, TBEN, TEA, TS, EXT_QUAL,

PMON_IN, SHD[0:1]

t_AXKH

t_DXKH

t_IXKH

—

BMODE[0:1], BVSEL, L3VSEL

t_MXKH

—

Output valid times:

A[0:35], AP[0:4]

D[0:63], DP[0:7]

AACK, ARTRY, BR, CI, CKSTP_IN, DRDY, DTI[0:3],

GBL, HIT, PMON_OUT, QREQ, TBST, TSIZ[0:2], TT[0:3],

TS, SHD[0:1], WT

t_KHAV

t_KHDV

t_KHOV

—

2.0

Output hold times:

A[0:35], AP[0:4]

D[0:63], DP[0:7]

AACK, ARTRY, BR, CI, CKSTP_IN, DRDY, DTI[0:3],

GBL, HIT, PMON_OUT, QREQ, TBST, TSIZ[0:2], TT[0:3],

TS, SHD[0:1], WT

t_KHAX

t_KHDX

t_KHOX

0.5

—

SYSCLK to output enable

t_KHOE

t_KHOZ

0.5

—

SYSCLK to output high impedance (all except TS, ARTRY,

SHD0, SHD1)

3.5

SYSCLK to TS high impedance after precharge

Maximum delay to ARTRY/SHD0/SHD1 precharge

t_KHTSPZ

t_KHARP

—

t_SYSCLK

3, 4, 5

3, 5

6, 7

MOTOROLA

MPC7457 RISC Microprocessor Hardware Specifications

Electrical and Thermal Characteristics

Table 9. Processor Bus AC Timing Specifications ¹(continued)

At recommended operating conditions. See Table 4.

All Speed Grades

Parameter

Symbol ²

Unit

Notes

Min

Max

SYSCLK to ARTRY/SHD0/SHD1 high impedance after

precharge

t_KHARPZ

—

t_SYSCLK

3, 5

6, 7

Notes:

1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge

of the input SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to the

midpoint of the signal in question. All output timings assume a purely resistive 50-Ω load (see Figure 4). Input and

output timings are measured at the pin; time-of-flight delays must be added for trace lengths, vias, and connectors

in the system.

2. The symbology used for timing specifications herein follows the pattern of t_{(signal)(state)(reference)(state)}for inputs and

_{(reference)(state)(signal)(state)}for outputs. For example, t_IVKHsymbolizes the time input signals (I) reach the valid state

(V) relative to the SYSCLK reference (K) going to the high (H) state or input setup time. And t_KHOVsymbolizes the

time from SYSCLK(K) going high (H) until outputs (O) are valid (V) or output valid time. Input hold time can be read

as the time that the input signal (I) went invalid (X) with respect to the rising clock edge (KH) (note the position of

the reference and its state for inputs) and output hold time can be read as the time from the rising edge (KH) until

the output went invalid (OX).

3. t_sysclkis the period of the external clock (SYSCLK) in ns. The numbers given in the table must be multiplied by the

period of SYSCLK to compute the actual time duration (in ns) of the parameter in question.

4. According to the bus protocol, TS is driven only by the currently active bus master. It is asserted low then precharged

high before returning to high impedance as shown in Figure 6. The nominal precharge width for TS is 0.5 × t_SYSCLK

that is, less than the minimum t_SYSCLKperiod, to ensure that another master asserting TS on the following clock will

not contend with the precharge. Output valid and output hold timing is tested for the signal asserted. Output valid

time is tested for precharge.The high-impedance behavior is guaranteed by design.

5. Guaranteed by design and not tested.

6. According to the bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately

following AACK. Bus contention is not an issue because any master asserting ARTRY will be driving it low. Any

master asserting it low in the first clock following AACK will then go to high impedance for one clock before

precharging it high during the second cycle after the assertion of AACK. The nominal precharge width for ARTRY

is 1.0 t_SYSCLK; that is, it should be high impedance as shown in Figure 6 before the first opportunity for another

master to assert ARTRY. Output valid and output hold timing is tested for the signal asserted.The high-impedance

behavior is guaranteed by design.

7. According to the MPX bus protocol, SHD0 and SHD1 can be driven by multiple bus masters beginning the cycle of

TS. Timing is the same as ARTRY, that is, the signal is high impedance for a fraction of a cycle, then negated for up

to an entire cycle (crossing a bus cycle boundary) before being three-stated again. The nominal precharge width for

SHD0 and SHD1 is 1.0 t_SYSCLK. The edges of the precharge vary depending on the programmed ratio of core to

bus (PLL configurations).

8. BMODE[0:1] and BVSEL are mode select inputs and are sampled before and after HRESET negation. These

parameters represent the input setup and hold times for each sample. These values are guaranteed by design and

not tested. These inputs must remain stable after the second sample. See Figure 5 for sample timing.

Figure 4 provides the AC test load for the MPC7457.

Output

OV_DD/2

Z₀= 50 Ω

R_L= 50 Ω

Figure 4. AC Test Load

MPC7457 RISC Microprocessor Hardware Specifications

MOTOROLA

Electrical and Thermal Characteristics

Figure 5 provides the mode select input timing diagram for the MPC7457.

SYSCLK

HRESET

Mode Signals

2nd sample

1st sample

VM = Midpoint Voltage (OV /2)

Figure 5. Mode Input Timing Diagram

Figure 6 provides the input/output timing diagram for the MPC7457.

SYSCLK

t_AXKH

t_IXKH

t_MXKH

t_AVKH

t_IVKH

t_MVKH

All Inputs

t_KHAV

t_KHAX

t_KHDX

t_KHOX

t_KHDV

t_KHOV

All Outputs

(Except TS,

ARTRY, SHD0, SHD1)

KHOE

t_KHOZ

All Outputs

(Except TS,

ARTRY, SHD0, SHD1)

t_KHTSPZ

t_KHTSV

t_KHTSX

t_KHTSV

t_KHARPZ

t_KHARV

t_KHARP

t_KHARX

ARTRY,

SHD0,

SHD1

VM = Midpoint Voltage (OV_DD/2)

Figure 6. Input/Output Timing Diagram

MOTOROLA

MPC7457 RISC Microprocessor Hardware Specifications

Electrical and Thermal Characteristics

1.5.2.3 L3 Clock AC Specifications

The L3_CLK frequency is programmed by the L3 configuration register core-to-L3 divisor ratio. See

Table 18 for example core and L3 frequencies at various divisors. Table 10 provides the potential range of

L3_CLK output AC timing specifications as defined in Figure 7.

The maximum L3_CLK frequency is the core frequency divided by two. Given the high core frequencies

available in the MPC7457, however, most SRAM designs will be not be able to operate in this mode using

current technology and, as a result, will select a greater core-to-L3 divisor to provide a longer L3_CLK

period for read and write access to the L3 SRAMs. Therefore, the typical L3_CLK frequency shown in

Table 10 is considered to be the practical maximum in a typical system. The maximum L3_CLK frequency

for any application of the MPC7457 will be a function of the AC timings of the MPC7457, the AC timings

for the SRAM, bus loading, and printed-circuit board trace length, and may be greater or less than the value

given in Table 10. Note that SYSCLK input jitter and L3_CLK[0:1] output jitter are already comprehended

in the L3 bus AC timing specifications and do not need to be separately accounted for in an L3 AC timing

analysis. Clock skews, where applicable, do need to be accounted for in an AC timing analysis.

Motorola is similarly limited by system constraints and cannot perform tests of the L3 interface on a

socketed part on a functional tester at the maximum frequencies of Table 10. Therefore, functional operation

and AC timing information are tested at core-to-L3 divisors which result in L3 frequencies at 250 MHz or

lower.

Table 10. L3_CLK Output AC Timing Specifications

At recommended operating conditions. See Table 4.

All Speed Grades

Parameter

Symbol

Unit

Notes

Minimum

Typical

Maximum

L3 clock frequency

f_{L3_CLK}

t_{L3_CLK}

t_CHCL/t_{L3_CLK}

t_L3CSKW1

—

200

5.0

—

MHz

L3 clock cycle time

L3 clock duty cycle

—

L3 clock output-to-output skew (L3_CLK0 to

L3_CLK1)

—

100

L3 clock output-to-output skew

(L3_CLK[0:1] to L3_ECHO_CLK[1,3])

t_L3CSKW2

—

100

L3 clock jitter

± 75

Notes:

1. The maximum L3 clock frequency (and minimum L3 clock period) will be system dependent. See Section 1.5.2.3,

“L3 Clock AC Specifications,” for an explanation that this maximum frequency is not functionally tested at speed by

Motorola. The minimum L3 clock frequency and period are f_SYSCLKand t_SYSCLK, respectively.

2. The nominal duty cycle of the L3 output clocks is 50% measured at midpoint voltage.

3. Maximum possible skew between L3_CLK0 and L3_CLK1. This parameter is critical to the address and control

signals which are common to both SRAM chips in the L3.

4. Maximum possible skew between L3_CLK0 and L3_ECHO_CLK1 or between L3_CLK1 and L3_ECHO_CLK3 for

PB2 or Late Write SRAM. This parameter is critical to the read data signals because the processor uses the

feedback loop to latch data driven from the SRAM, each of which drives data based on L3_CLK0 or L3_CLK1.

5. Guaranteed by design and not tested. The input jitter on SYSCLK affects L3 output clocks and the L3 address, data,

and control signals equally and, therefore, is already comprehended in the AC timing and does not have to be

considered in the L3 timing analysis. The clock-to-clock jitter shown here is uncertainty in the internal clock period

caused by supply voltage noise or thermal effects. This is also comprehended in the AC timing specifications and

need not be considered in the L3 timing analysis.

MPC7457 RISC Microprocessor Hardware Specifications

MOTOROLA

Electrical and Thermal Characteristics

The L3_CLK timing diagram is shown in Figure 7.

t_{L3_CLK}

t_CHCL

t_L3CR

t_L3CF

L3_CLK0

L3_CLK1

t_L3CSKW1

For PB2 or Late Write:

L3_ECHO_CLK1

t_L3CSKW2

L3_ECHO_CLK3

Figure 7. L3_CLK_OUT Output Timing Diagram

1.5.2.4

L3 Bus AC Specifications

The MPC7457 L3 interface supports three different types of SRAM: source-synchronous, double data rate

(DDR) MSUG2 SRAM, Late Write SRAMs, and pipeline burst (PB2) SRAMs. Each requires a different

protocol on the L3 interface and a different routing of the L3 clock signals. The type of SRAM is

programmed in L3CR[22:23] and the MPC7457 then follows the appropriate protocol for that type. The

designer must connect and route the L3 signals appropriately for each type of SRAM. Following are some

observations about the L3 interface.

•

The routing for the point-to-point signals (L3_CLK[0:1], L3DATA[0:63], L3DP[0:7], and

L3_ECHO_CLK[0:3]) to a particular SRAM must be delay matched.

•

For 1-Mbyte of SRAM, use L3_ADDR[16:0] (L3_ADDR[0] is LSB)

For 2-Mbyte of SRAM, use L3_ADDR[17:0] (L3_ADDR[0] is LSB)

For 4-Mbyte of SRAM, use L3_ADDR[18:0] (L3_ADDR[0] is LSB)

No pull-up resistors are required for the L3 interface

For high speed operations, L3 interface address and control signals should be a ‘T’ with minimal

stubs to the two loads; data and clock signals should be point-to-point to their single load. Figure 8

shows the AC test load for the L3 interface.

Output

GV_DD/2

Z₀= 50 Ω

R_L= 50 Ω

Figure 8. AC Test Load for the L3 Interface

In general, if routing is short, delay-matched, and designed for incident wave reception and minimal

reflection, there is a high probability that the AC timing of the MPC7457 L3 interface will meet the

maximum frequency operation of appropriately chosen SRAMs. This is despite the pessimistic,

guard-banded AC specifications (see Table 12, Table 13, and Table 14), the limitations of functional testers

described in Section 1.5.2.3, “L3 Clock AC Specifications,” and the uncertainty of clocks and signals which

inevitably make worst-case critical path timing analysis pessimistic.

MOTOROLA

MPC7457 RISC Microprocessor Hardware Specifications

Electrical and Thermal Characteristics

More specifically, certain signals within groups should be delay-matched with others in the same group

while intergroup routing is less critical. Only the address and control signals are common to both SRAMs

and additional timing margin is available for these signals. The double-clocked data signals are grouped

with individual clocks as shown in Figure 9 or Figure 11, depending on the type of SRAM. For example,

for the MSUG2 DDR SRAM (see Figure 9); L3DATA[0:31], L3DP[0:3], and L3_CLK[0] form a closely

coupled group of outputs from the MPC7457; while L3DATA[0:15], L3DP[0:1], and L3_ECHO_CLK[0]

form a closely coupled group of inputs.

The MPC7450 RISC Microprocessor Family User’s Manual refers to logical settings called ‘sample points’

used in the synchronization of reads from the receive FIFO. The computation of the correct value for this

setting is system-dependent and is described in the MPC7450 RISC Microprocessor Family User’s Manual.

Three specifications are used in this calculation and are given in Table 11. It is essential that all three

specifications are included in the calculations to determine the sample points, as incorrect settings can result

in errors and unpredictable behavior. For more information, see the MPC7450 RISC Microprocessor Family

User’s Manual.

Table 11. Sample Points Calculation Parameters

Parameter

Symbol

Max

Unit

Notes

Delay from processor clock to internal_L3_CLK

Delay from internal_L3_CLK to L3_CLK[n] output pins

Delay from L3_ECHO_CLK[n] to receive latch

Notes:

t_AC

t_CO

t_ECI

3/4

t_{L3_CLK}

1. This specification describes a logical offset between the internal clock edge used to launch the L3 address and

control signals (this clock edge is phase-aligned with the processor clock edge) and the internal clock edge used to

launch the L3_CLK[n] signals. With proper board routing, this offset ensures that the L3_CLK[n] edge will arrive at

the SRAM within a valid address window and provide adequate setup and hold time. This offset is reflected in the

L3 bus interface AC timing specifications, but must also be separately accounted for in the calculation of sample

points and, thus, is specified here.

2. This specification is the delay from a rising or falling edge on the internal_L3_CLK signal to the corresponding rising

or falling edge at the L3CLK[n] pins.

3. This specification is the delay from a rising or falling edge of L3_ECHO_CLK[n] to data valid and ready to be

sampled from the FIFO.

1.5.2.4.1 Effects of L3OHCR Settings on L3 Bus AC Specifications

The AC timing of the L3 interface can be adjusted using the L3 Output Hold Control Register (L3OCHR).

Each field controls the timing for a group of signals. The AC timing specifications presented herein represent

the AC timing when the register contains the default value of 0x0000_0000. Incrementing a field delays the

associated signals, increasing the output valid time and hold time of the affected signals. In the special case

of delaying an L3_CLK signal, the net effect is to decrease the output valid and output hold times of all

signals being latched relative to that clock signal. The amount of delay added is summarized in Table 12.

Note that these settings affect output timing parameters only and do not impact input timing parameters of

the L3 bus in any way.

MPC7457 RISC Microprocessor Hardware Specifications

MOTOROLA

Electrical and Thermal Characteristics

Table 12. Effect of L3OHCR Settings on L3 Bus AC Timing

At recommended operating conditions. See Table 4.

Output Valid Time

Output Hold Time

Note

Unit

Affected

Signals

Field name¹

Value

Parameter

Change ³

Symbol ²

Parameter

Change ³

Symbol ²

L3AOH

L3_ADDR[18:0],

L3_CNTL[0:1]

0b00

0b01

t_L3CHOV

t_L3CHOX

+50

0b10

+100

+150

+100

+150

0b11

L3CLKn_OH

All signals

latched by

SRAM

connected to

L3_CLKn

0b000

0b001

0b010

0b011

0b100

0b101

0b110

0b111

0b000

0b001

0b010

0b011

0b100

0b101

0b111

t_L3CHOV

t_L3CHDV

t_L3CLDV

t_L3CHOX

t_L3CHDX

t_L3CLDX,

– 50

– 100

– 150

– 200

– 250

– 300

– 350

– 100

– 150

– 200

– 250

– 300

– 350

L3DOHn

L3_DATA[n:n+7]

, L3_DP[n/8]

t_L3CHDV

t_L3CHDX

t_L3CLDV

t_L3CLDX,

+ 50

+ 100

+ 150

+ 200

+ 250

+ 300

+ 350

+ 50

+ 100

+ 150

+ 200

+ 250

+ 300

+ 350

Notes:

1. See the MPC7450 RISC Microprocessor Family User’s Manual for specific information regarding L3OHCR.

2. See Table 13 and Table 14 for more information.

3. Approximate delay verified by simulation; not tested or characterized

4. Default value

5. Increasing values of L3CLKn_OH delay the L3_CLKn signal, effectively decreasing the output valid and output hold

times of all signals latched relative to that clock signal by the SRAM; see Figure 9 and Figure 11.

1.5.2.4.2 L3 Bus AC Specifications for DDR MSUG2 SRAMs

When using DDR MSUG2 SRAMs at the L3 interface, the parts should be connected as shown in Figure 9.

Outputs from the MPC7457 are actually launched on the edges of an internal clock phase-aligned to

SYSCLK (adjusted for core and L3 frequency divisors). L3_CLK0 and L3_CLK1 are this internal clock

output with 90° phase delay, so outputs are shown synchronous to L3_CLK0 and L3_CLK1. Output valid

MOTOROLA

MPC7457 RISC Microprocessor Hardware Specifications

Electrical and Thermal Characteristics

times are typically negative when referenced to L3_CLKn because the data is launched one-quarter period

before L3_CLKn to provide adequate setup time at the SRAM after the delay-matched address, control,

data, and L3_CLKn signals have propagated across the printed-wiring board.

Inputs to the MPC7457 are source-synchronous with the CQ clock generated by the DDR MSUG2 SRAMs.

These CQ clocks are received on the L3_ECHO_CLKn inputs of the MPC7457. An internal circuit delays

the incoming L3_ECHO_CLKn signal such that it is positioned within the valid data window at the internal

receiving latches. This delayed clock is used to capture the data into these latches which comprise the

receive FIFO. This clock is asynchronous to all other processor clocks. This latched data is subsequently

read out of the FIFO synchronously to the processor clock. The time between writing and reading the data

is set by the using the sample point settings defined in the L3CR register.

Table 13 provides the L3 bus interface AC timing specifications for the configuration as shown in Figure 9,

assuming the timing relationships shown in Figure 10 and the loading shown in Figure 8.

Table 13. L3 Bus Interface AC Timing Specifications for MSUG2

At recommended operating conditions. See Table 4.

All Speed Grades

Parameter

Symbol

Unit

Notes

Min

Max

L3_CLK rise and fall time

t_L3CR, t_L3CF

—

– 0.35

2.1

0.75

—

Setup times: Data and parity

Input hold times: Data and parity

Valid times: Data and parity

t_L3DVEH, t_L3DVEL

t_L3DXEH, t_L3DXEL

t_L3CHDV, t_L3CLDV

2, 3, 4, 9

2, 4, 9

—

(– t_L3CLK/4) +

0.60

5, 6, 7, 8

Valid times: All other outputs

t_L3CHOV

t_L3CHDX, t_L3CLDX,

t_L3CHOX

—

(t_L3CLK/4) +

0.65

5, 7, 8

5, 6, 7, 8

5, 7, 8

Output hold times: Data and parity

Output hold times: All other outputs

(t_L3CLK/4) –

0.60

—

(t_L3CLK/4) –

0.50

—

L3_CLK to high impedance: Data and

parity

t_L3CLDZ

—

(– t_L3CLK/4) +

0.60

MPC7457 RISC Microprocessor Hardware Specifications

MOTOROLA

Electrical and Thermal Characteristics

Table 13. L3 Bus Interface AC Timing Specifications for MSUG2 (continued)

At recommended operating conditions. See Table 4.

All Speed Grades

Parameter

Symbol

Unit

Notes

Min

Max

L3_CLK to high impedance: All other

outputs

t_L3CHOZ

—

(t_L3CLK/4) +

0.65

Notes:

1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GV_DD

2. For DDR, all input specifications are measured from the midpoint of the signal in question to the midpoint voltage

of the rising or falling edge of the input L3_ECHO_CLKn (see Figure 10). Input timings are measured at the pins.

3. For DDR, the input data will typically follow the edge of L3_ECHO_CLKn as shown in Figure 10. For consistency

with other input setup time specifications, this will be treated as negative input setup time.

4. t_{L3_CLK}/4 is one-fourth the period of L3_CLKn. This parameter indicates that the MPC7457 can latch an input signal

that is valid for only a short time before and a short time after the midpoint between the rising and falling (or falling

and rising) edges of L3_ECHO_CLKn at any frequency.

5. All output specifications are measured from the midpoint voltage of the rising (or for DDR write data, also the falling)

edge of L3_CLK to the midpoint of the signal in question. The output timings are measured at the pins. All output

timings assume a purely resistive 50-Ω load (see Figure 8).

6. For DDR, the output data will typically lead the edge of L3_CLKn as shown in Figure 10. For consistency with other

output valid time specifications, this will be treated as negative output valid time.

7. t_{L3_CLK}/4 is one-fourth the period of L3_CLKn. This parameter indicates that the specified output signal is actually

launched by an internal clock delayed in phase by 90°. Therefore, there is a frequency component to the output valid

and output hold times such that the specified output signal will be valid for approximately one L3_CLK period

starting three-fourths of a clock before the edge on which the SRAM will sample it and ending one-fourth of a clock

period after the edge it will be sampled.

8. Assumes default value of L3OHCR. See Section 1.5.2.4.1, “Effects of L3OHCR Settings on L3 Bus AC

Specifications” for more information.

9. L3 input setup and hold times are actually functions of L3 clock frequency in a manner similar to L3 output timing

characteristics. The timing parameter values shown are based upon characterization at 200 MHz. Motorola is

currently studying these parameters in order to provide the values in a format that accurately reflects this frequency

dependence.

MOTOROLA

MPC7457 RISC Microprocessor Hardware Specifications

Electrical and Thermal Characteristics

Figure 9 shows the typical connection diagram for the MPC7457 interfaced to MSUG2 DDR SRAMs.

SRAM 0

SA[18:0]

L3ADDR[18:0]

MPC7457

B3 GND

L3_CNTL[0]

L3_CNTL[1]

GND

LBO GND

Denotes

L3_ECHO_CLK[0]

Receive(SRAM

to MPC7457)

Aligned Signals

{L3DATA[0:15], L3DP[0:1]}

L3_CLK[0]

D[0:17]

{L3DATA[16:31], L3DP[2:3]}

L3_ECHO_CLK[1]

GV_DD/2 ¹

D[18:35]

Denotes

Transmit

SRAM 1

SA[18:0]

(MPC7457 to

SRAM)

Aligned Signals

B3 GND

GND

LBO GND

L3ECHO_CLK[2]

{L3_DATA[32:47],L3DP[4:5]}

D[0:17]

L3_CLK[1]

{L3DATA[48:63], L3DP[6:7]}

L3_ECHO_CLK[3]

GV_DD/2 ¹

D[18:35]

Note:

1. Or as recommended by SRAM manufacturer for single-ended clocking.

Figure 9. Typical Source Synchronous 4-Mbyte L3 Cache DDR Interface

MPC7457 RISC Microprocessor Hardware Specifications

MOTOROLA

Electrical and Thermal Characteristics

Figure 10 shows the L3 bus timing diagrams for the MPC7457 interfaced to MSUG2 SRAMs.

Outputs

L3_CLK[0,1]

t_L3CHOV

t_L3CHOZ

t_L3CHOX

ADDR, L3CNTL

L3DATA WRITE

t_L3CLDV

t_L3CLDZ

t_L3CHDV

t_L3CHDX

t_L3CLDX

Note: t_L3CHDVand t_L3CLDVas drawn here will be negative numbers, that is, output valid time will be

time before the clock edge.

Inputs

L3_ECHO_CLK[0,1,2,3]

t_L3DXEL

t_L3DVEL

t_L3DVEH

L3 Data and Data

Parity Inputs

t_L3DXEH

Note: t_L3DVEHand t_L3DVELas drawn here are negative numbers, that is, input setup time is

time after the clock edge.

VM = Midpoint Voltage (GV_DD/2)

Figure 10. L3 Bus Timing Diagrams for L3 Cache DDR SRAMs

1.5.2.4.3 L3 Bus AC Specifications for PB2 and Late Write SRAMs

When using PB2 or Late Write SRAMs at the L3 interface, the parts should be connected as shown in

Figure 11. These SRAMs are synchronous to the MPC7457; one L3_CLKn signal is output to each SRAM

to latch address, control, and write data. Read data is launched by the SRAM synchronous to the delayed

L3_CLKn signal it received. The MPC7457 needs a copy of that delayed clock which launched the SRAM

read data to know when the returning data will be valid. Therefore, L3_ECHO_CLK1 and

L3_ECHO_CLK3 must be routed halfway to the SRAMs and returned to the MPC7457 inputs

L3_ECHO_CLK0 and L3_ECHO_CLK2, respectively. Thus, L3_ECHO_CLK0 and L3_ECHO_CLK2 are

phase-aligned with the input clock received at the SRAMs. The MPC7457 will latch the incoming data on

the rising edge of L3_ECHO_CLK0 and L3_ECHO_CLK2.

Table 14 provides the L3 bus interface AC timing specifications for the configuration shown in Figure 11,

assuming the timing relationships of Figure 12 and the loading of Figure 8.

MOTOROLA

MPC7457 RISC Microprocessor Hardware Specifications

Electrical and Thermal Characteristics

Table 14. L3 Bus Interface AC Timing Specifications for PB2 and Late Write SRAMs

At recommended operating conditions. See Table 4.

All Speed Grades

Parameter

Symbol

Unit

Notes

Min

Max

L3_CLK rise and fall time

t_L3CR, t_L3CF

t_L3DVEH

t_L3DXEH

t_L3CHDV

t_L3CHOV

t_L3CHDX

t_L3CHOX

t_L3CHDZ

t_L3CHOZ

—

0.1

—

0.75

—

1, 2

2, 3

Setup times: Data and parity

Input hold times: Data and parity

Valid times: Data and parity

0.7

2.5

1.8

—

2, 3

—

2, 4, 5, 6

5, 6

Valid times: All other outputs

—

Output hold times: Data and parity

Output hold times: All other outputs

L3_CLK to high impedance: Data and parity

L3_CLK to high impedance: All other outputs

Notes:

1.4

1.0

—

2, 4, 5, 6

2, 5, 6

—

3.0

—

1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GV_DD

2. Timing behavior and characterization are currently being evaluated.

3. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising

edge of the input L3_ECHO_CLKn (see Figure 10). Input timings are measured at the pins.

4. All output specifications are measured from the midpoint voltage of the rising edge of L3_CLKn to the midpoint of

the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive

50-Ω load (see Figure 10).

5. t_{L3_CLK}/4 is one-fourth the period of L3_CLKn. This parameter indicates that the specified output signal is actually

launched by an internal clock delayed in phase by 90°. Therefore, there is a frequency component to the output valid

and output hold times such that the specified output signal will be valid for approximately one L3_CLK period

starting three-fourths of a clock before the edge on which the SRAM will sample it and ending one-fourth of a clock

period after the edge it will be sampled.

6. Assumes default value of L3OHCR. See Section 1.5.2.4.1, “Effects of L3OHCR Settings on L3 Bus AC

Specifications” for more information.

MPC7457 RISC Microprocessor Hardware Specifications

MOTOROLA

Electrical and Thermal Characteristics

Figure 11 shows the typical connection diagram for the MPC7457 interfaced to PB2 SRAMs or Late Write

SRAMs.

SRAM 0

SA[16:0]

L3_ADDR[16:0]

L3_CNTL[0]

L3_CNTL[1]

MPC7457

L3_ECHO_CLK[0]

Denotes

Receive (SRAM

to MPC7457)

Aligned Signals

{L3_DATA[0:15], L3_DP[0:1]}

DQ[0:17]

GND

L3_CLK[0]

GND

{L3_DATA[16:31], L3_DP[2:3]}

GV_DD/2 ¹

DQ[18:36]

L3_ECHO_CLK[1]

L3_ECHO_CLK[2]

Denotes

Transmit

(MPC7457 to

SRAM)

SRAM 1

SA[16:0]

Aligned Signals

{L3_DATA[32:47], L3_DP[4:5]}

L3_CLK[1]

GND

DQ[0:17]

GND

{L3_DATA[48:63], L3_DP[6:7]}

GV_DD/2 ¹

DQ[18:36]

L3_ECHO_CLK[3]

Note:

1. Or as recommended by SRAM manufacturer for single-ended clocking.

Figure 11. Typical Synchronous 1-MByte L3 Cache Late Write or PB2 Interface

MOTOROLA

MPC7457 RISC Microprocessor Hardware Specifications

Electrical and Thermal Characteristics

Figure 12 shows the L3 bus timing diagrams for the MPC7457 interfaced to PB2 or Late Write SRAMs.

Outputs

L3_CLK[0,1]

L3_ECHO_CLK[1,3]

t_L3CHOX

t_L3CHOV

ADDR, L3_CNTL

t_L3CHOZ

t_L3CHDX

t_L3CHDV

L3DATA WRITE

t_L3CHDZ

Inputs

L3_ECHO_CLK[0,2]

t_L3DVEH

t_L3DXEH

Parity Inputs

L3 Data and Data

VM = Midpoint Voltage (GV_DD/2)

Figure 12. L3 Bus Timing Diagrams for Late Write or PB2 SRAMs

1.5.2.5

IEEE 1149.1 AC Timing Specifications

Table 15 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 14 through

Figure 17.

Table 15. JTAG AC Timing Specifications (Independent of SYSCLK) ¹

At recommended operating conditions. See Table 4.

Parameter

TCK frequency of operation

Symbol

Min

Max

Unit

Notes

f_TCLK

t_TCLK

33.3

—

MHz

TCK cycle time

TCK clock pulse width measured at 1.4 V

TCK rise and fall times

TRST assert time

t_JHJL

—

t_JRand t_JF

t_TRST

—

Input setup times:

Boundary-scan data

TMS, TDI

t_DVJH

t_IVJH

—

Input hold times:

Boundary-scan data

TMS, TDI

t_DXJH

t_IXJH

—

Valid times:

Boundary-scan data

TDO

t_JLDV

t_JLOV

MPC7457 RISC Microprocessor Hardware Specifications

MOTOROLA

Electrical and Thermal Characteristics

Table 15. JTAG AC Timing Specifications (Independent of SYSCLK) ¹(continued)

At recommended operating conditions. See Table 4.

Parameter

Symbol

Min

Max

Unit

Notes

Output hold times:

Boundary-scan data

TDO

t_JLDX

t_JLOX

—

TCK to output high impedance:

Boundary-scan data

TDO

4, 5

t_JLDZ

t_JLOZ

Notes:

1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal

in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load

(see Figure 13). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.

3. Non-JTAG signal input timing with respect to TCK.

4. Non-JTAG signal output timing with respect to TCK.

5. Guaranteed by design and characterization.

Figure 13 provides the AC test load for TDO and the boundary-scan outputs of the MPC7457.

Output

OV_DD/2

Z₀= 50 Ω

R_L= 50 Ω

Figure 13. Alternate AC Test Load for the JTAG Interface

Figure 14 provides the JTAG clock input timing diagram.

TCLK

t_JHJL

t_JR

t_JF

t_TCLK

VM = Midpoint Voltage (OV_DD/2)

Figure 14. JTAG Clock Input Timing Diagram

Figure 15 provides the TRST timing diagram.

TRST

t_TRST

VM = Midpoint Voltage (OV_DD/2)

Figure 15. TRST Timing Diagram

MOTOROLA

MPC7457 RISC Microprocessor Hardware Specifications

Electrical and Thermal Characteristics

Figure 16 provides the boundary-scan timing diagram.

TCK

t_DVJH

t_DXJH

Boundary

Data Inputs

Input

Data Valid

t_JLDV

t_JLDX

Boundary

Data Outputs

Output Data Valid

t_JLDZ

Boundary

Data Outputs

Output Data Valid

VM = Midpoint Voltage (OV_DD/2)

Figure 16. Boundary-Scan Timing Diagram

Figure 17 provides the test access port timing diagram.

TCK

TDI, TMS

TDO

t_IVJH

t_IXJH

Input

Data Valid

t_JLOV

t_JLOX

Output Data Valid

t_JLOZ

Output Data Valid

TDO

VM = Midpoint Voltage (OV_DD/2)

Figure 17. Test Access Port Timing Diagram

MPC7457 RISC Microprocessor Hardware Specifications

MOTOROLA

Pin Assignments

1.6 Pin Assignments

Figure 18 (Part A) shows the pinout of the MPC7447, 360 CBGA package as viewed from the top surface.

Part B shows the side profile of the CBGA package to indicate the direction of the top surface view.

Part A

10 11 12 13 14 15 16 17 18 19

Not to Scale

Part B

Substrate Assembly

Encapsulant

View

Die

Figure 18. Pinout of the MPC7447, 360 CBGA Package as Viewed from the Top Surface

MOTOROLA

MPC7457 RISC Microprocessor Hardware Specifications

Pin Assignments

Figure 19 (Part A) shows the pinout of the MPC7457, 483 CBGA package as viewed from the top surface.

Part B shows the side profile of the CBGA package to indicate the direction of the top surface view.

Part A

10 11 12 13 14 15 16 17 18 19 20 21 22

Not to Scale

Part B

Substrate Assembly

Encapsulant

View

Die

Figure 19. Pinout of the MPC7457, 483 CBGA Package as Viewed from the Top Surface

MPC7457 RISC Microprocessor Hardware Specifications

MOTOROLA

Pinout Listings

1.7 Pinout Listings

Table 16 provides the pinout listing for the MPC7447, 360 CBGA package. Table 17 provides the pinout

listing for the MPC7457, 483 CBGA package.

NOTE

This pinout is not compatible with the MPC750, MPC7400, or MPC7410

360 BGA package.

Table 16. Pinout Listing for the MPC7447, 360 CBGA Package

Signal Name

A[0:35]

Pin Number

Active

I/O

I/F Select ¹

Notes

E11, H1, C11, G3, F10, L2, D11, D1, C10,

G2, D12, L3, G4, T2, F4, V1, J4, R2, K5,

W2, J2, K4, N4, J3, M5, P5, N3, T1, V2,

U1, N5, W1, B12, C4, G10, B11

High

I/O

BVSEL

AACK

Low

High

Low

—

Input

I/O

BVSEL

N/A

AP[0:4]

ARTRY

AV_DD

C1, E3, H6, F5, G7

I/O

Input

Output

Input

Output

Input

Output

I/O

Low

High

Low

High

BVSEL

BMODE0

BMODE1

BVSEL

1, 6

CKSTP_IN

CKSTP_OUT

CLK_OUT

D[0:63]

R15, W15, T14, V16, W16, T15, U15, P14,

V13, W13, T13, P13, U14, W14, R12, T12,

W12, V12, N11, N10, R11, U11, W11,

T11, R10, N9, P10, U10, R9, W10, U9,

V9, W5, U6, T5, U5, W7, R6, P7, V6, P17,

R19, V18, R18, V19, T19, U19, W19, U18,

W17, W18, T16, T18, T17, W3, V17, U4,

U8, U7, R7, P6, R8, W8, T8

DBG

Low

High

Low

High

Low

Input

I/O

BVSEL

DP[0:7]

DRDY

T3, W4, T4, W9, M6, V3, N8, W6

Output

Input

I/O

DTI[0:3]

EXT_QUAL

GBL

G1, K1, P1, N1

A11

MOTOROLA

MPC7457 RISC Microprocessor Hardware Specifications

Pinout Listings

Table 16. Pinout Listing for the MPC7447, 360 CBGA Package (continued)

Signal Name

GND

Pin Number

Active

I/O

I/F Select ¹

Notes

B5, C3, D6, D13, E17, F3, G17, H4, H7,

H9, H11, H13, J6, J8, J10, J12, K7, K3,

K9, K11, K13, L6, L8, L10, L12, M4, M7,

M9, M11, M13, N7, P3, P9, P12, R5, R14,

R17, T7, T10, U3, U13, U17, V5, V8, V11,

V15

—

N/A

HIT

Low

High

—

Output

Input

—

BVSEL

—

HRESET

INT

L1_TSTCLK

L2_TSTCLK

No Connect

A6, A13, A14, A15, A16, A17, A18, A19,

B13, B14, B15, B16, B17, B18, B19, C13,

C14, C15, C16, C17, C18, C19, D14, D15,

D16, D17, D18, D19, E12, E13, E14, E15,

E16, E19, F12, F13, F14, F15, F16, F17,

F18, F19, G11, G12, G13, G14, G15,

G16, G19, H14, H15, H16, H17, H18,

H19, J14, J15, J16, J17, J18, J19, K15,

K16, K17, K18, K19, L14, L15, L16, L17,

L18, L19, M14, M15, M16, M17, M18,

M19, N12, N13, N14, N15, N16, N17,

N18, N19, P15, P16, P18, P19

LSSD_MODE

MCP

Low

—

Input

—

BVSEL

N/A

6, 12

OV_DD

B4, C2, C12, D5, E18, F2, G18, H3, J5,

K2, L5, M3, N6, P2, P8, P11, R4, R13,

R16, T6, T9, U2, U12, U16, V4, V7, V10,

V14

PLL_CFG[0:4]

PMON_IN

PMON_OUT

QACK

B8, C8, C7, D7, A7

High

Low

—

Input

Output

Input

Output

I/O

BVSEL

QREQ

SHD[0:1]

SMI

E4, H5

Input

Output

SRESET

SYSCLK

A10

Low

High

Low

TBEN

TBST

F11

MPC7457 RISC Microprocessor Hardware Specifications

MOTOROLA

Pinout Listings

Table 16. Pinout Listing for the MPC7447, 360 CBGA Package (continued)

Signal Name

TCK

Pin Number

Active

I/O

I/F Select ¹

Notes

High

Low

—

Input

Output

Input

I/O

BVSEL

N/A

TDI

TDO

TEA

TEST[0:3]

TEST[4]

TMS

A12, B6, B10, E10

D10

—

High

Low

High

Low

—

TRST

6, 14

TSIZ[0:2]

TT[0:4]

G6, F7, E7

E5, E6, F6, E9, C5

Output

I/O

Output

—

V_DD

H8, H10, H12, J7, J9, J11, J13, K8, K10,

K12, K14, L7, L9, L11, L13, M8, M10, M12

Notes:

1. OV_DDsupplies power to the processor bus, JTAG, and all control signals; and V_DDsupplies power to the processor

core and the PLL (after filtering to become AV_DD). To program the I/O voltage, connect BVSEL to either GND

(selects 1.8 V) or to HRESET (selects 2.5 V). If used, the pull-down resistor should be less than 250 Ω. For actual

recommended value of V_inor supply voltages see Table 4.

2. Unused address pins must be pulled down to GND.

3. These pins require weak pull-up resistors (for example, 4.7 kΩ) to maintain the control signals in the negated state

after they have been actively negated and released by the MPC7447 and other bus masters.

4. This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at

HRESET going high.

5. This signal must be negated during reset, by pull up to OV_DDor negation by ¬HRESET (inverse of HRESET), to

ensure proper operation.

6. Internal pull up on die.

7. Ignored in 60x bus mode.

8. These signals must be pulled down to GND if unused, or if the MPC7447 is in 60x bus mode.

9. These input signals are for factory use only and must be pulled down to GND for normal machine operation.

10.This test signal is recommended to be tied to HRESET; however, other configurations will not adversely affect

performance.

11.These signals are for factory use only and must be left unconnected for normal machine operation.

12.These input signals are for factory use only and must be pulled up to OV_DDfor normal machine operation.

13.This pin can externally cause a performance monitor event. Counting of the event is enabled via software.

14.This signal must be asserted during reset, by pull down to GND or assertion by HRESET, to ensure proper

operation.

MOTOROLA

MPC7457 RISC Microprocessor Hardware Specifications

Pinout Listings

Table 17. Pinout Listing for the MPC7457, 483 CBGA Package

Signal Name

Pin Number

Active

I/O

I/F Select ¹

Notes

A[0:35]

E10, N4, E8, N5, C8, R2, A7, M2, A6, M1,

A10, U2, N2, P8, M8, W4, N6, U6, R5, Y4, P1,

P4, R6, M7, N7, AA3, U4, W2, W1, W3, V4,

AA1, D10, J4, G10, D9

High

I/O

BVSEL

AACK

Low

High

Low

—

Input

I/O

BVSEL

N/A

AP[0:4]

ARTRY

AV_DD

L5, L6, J1, H2, G5

I/O

Input

Output

Input

Output

Input

Output

I/O

Low

High

Low

High

BVSEL

N/A

BMODE0

BMODE1

BVSEL

6, 7

BVSEL

CKSTP_IN

CKSTP_OUT

CLK_OUT

D[0:63]

AB15, T14, R14, AB13, V14, U14, AB14, W16,

AA11, Y11, U12, W13, Y14, U13, T12, W12,

AB12, R12, AA13, AB11, Y12, V11, T11, R11,

W10, T10, W11, V10, R10, U10, AA10, U9,

V7, T8, AB4, Y6, AB7, AA6, Y8, AA7, W8,

AB10, AA16, AB16, AB17, Y18, AB18, Y16,

AA18, W14, R13, W15, AA14, V16, W6, AA12,

V6, AB9, AB6, R7, R9, AA9, AB8, W9

DBG

Low

High

Low

High

Low

Input

I/O

BVSEL

DP[0:7]

DRDY

AA2, AB3, AB2, AA8, R8, W5, U8, AB5

Output

Input

I/O

DTI[0:3])

EXT_QUAL

GBL

P2, T5, U3, P6

MPC7457 RISC Microprocessor Hardware Specifications

MOTOROLA

Pinout Listings

Table 17. Pinout Listing for the MPC7457, 483 CBGA Package (continued)

Signal Name

GND

Pin Number

Active

I/O

I/F Select ¹

Notes

A22, B1, B5, B12, B14, B16, B18, B20, C3,

C9, C21, D7, D13, D15, D17, D19, E2, E5,

E21, F10, F12, F14, F16, F19, G4, G7, G17,

G21, H13, H15, H19, H5, J3, J10, J12, J14,

J17, J21, K5, K9, K11, K13, K15, K19, L10,

L12, L14, L17, L21, M3, M6, M9, M11, M13,

M19, N10, N12, N14, N17, N21, P3, P9, P11,

P13, P15, P19, R17, R21, T13, T15, T19, T4,

T7, T9, U17, U21, V2, V5, V8, V12, V15, V19,

W7, W17, W21, Y3, Y9, Y13, Y15, Y20, AA5,

AA17, AB1, AB22

—

N/A

GV_DD

B13, B15, B17, B19, B21, D12, D14, D16,

D18, D21, E19, F13, F15, F17, F21, G19,

H12, H14, H17, H21, J19, K17, K21, L19,

M17, M21, N19, P17, P21, R15, R19, T17,

T21, U19, V17, V21, W19, Y21

—

N/A

HIT

Low

High

Output

Input

BVSEL

N/A

HRESET

INT

Input

L1_TSTCLK

L2_TSTCLK

L3VSEL

Input

6, 7

L3ADDR[18:0]

H11, F20, J16, E22, H18, G20, F22, G22,

H20, K16, J18, H22, J20, J22, K18, K20, L16,

K22, L18

Output

L3VSEL

L3_CLK[0:1]

L3_CNTL[0:1]

L3DATA[0:63]

V22, C17

L20, L22

High

Low

High

Output

I/O

L3VSEL

AA19, AB20, U16, W18, AA20, AB21, AA21,

T16, W20, U18, Y22, R16, V20, W22, T18,

U20, N18, N20, N16, N22, M16, M18, M20,

M22, R18, T20, U22, T22, R20, P18, R22,

M15, G18, D22, E20, H16, C22, F18, D20,

B22, G16, A21, G15, E17, A20, C19, C18,

A19, A18, G14, E15, C16, A17, A16, C15,

G13, C14, A14, E13, C13, G12, A13, E12,

C12

L3DP[0:7]

AB19, AA22, P22, P16, C20, E16, A15, A12

High

HIgh

Low

—

I/O

Input

I/O

L3VSEL

BVSEL

N/A

L3_ECHO_CLK[0,2] V18, E18

L3_ECHO_CLK[1,3] P20, E14

LSSD_MODE

MCP

Input

—

7, 13

No Connect

A8, A11, B6, B11, C11, D11, D3, D5, E11, E7,

F2, F11, G2, H9

MOTOROLA

MPC7457 RISC Microprocessor Hardware Specifications

Pinout Listings

Table 17. Pinout Listing for the MPC7457, 483 CBGA Package (continued)

Signal Name

OV_DD

Pin Number

Active

I/O

I/F Select ¹

Notes

B3, C5, C7, C10, D2, E3, E9, F5, G3, G9, H7,

J5, K3, L7, M5, N3, P7, R4, T3, U5, U7, U11,

U15, V3, V9, V13, Y2, Y5, Y7, Y10, Y17, Y19,

AA4, AA15

—

N/A

PLL_CFG[0:4]

PMON_IN

PMON_OUT

QACK

QREQ

SHD[0:1]

SMI

A2, F7, C2, D4, H8

High

Low

—

Input

Output

Input

Output

I/O

BVSEL

N/A

L4, L8

Input

Output

Input

Output

Input

I/O

SRESET

SYSCLK

Low

High

Low

High

Low

—

TBEN

TBST

TCK

TDI

TDO

TEA

TEST[0:5]

TEST[6]

TMS

B10, H6, H10, D8, F9, F8

—

High

Low

High

Low

—

TRST

7, 16

TSIZ[0:2]

TT[0:4]

L1,H3,D1

F1, F4, K8, A5, E1

Output

I/O

Output

—

V_DD

J9, J11, J13, J15, K10, K12, K14, L9, L11,

L13, L15, M10, M12, M14, N9, N11, N13, N15,

P10, P12, P14

MPC7457 RISC Microprocessor Hardware Specifications

MOTOROLA

Package Description

Table 17. Pinout Listing for the MPC7457, 483 CBGA Package (continued)

Signal Name

Pin Number

Active

I/O

I/F Select ¹

Notes

VDD_SENSE[0:1]

G11, J8

—

N/A

Notes:

1. OV_DDsupplies power to the processor bus, JTAG, and all control signals except the L3 cache controls (L3CTL[0:1]);

GV_DDsupplies power to the L3 cache interface (L3ADDR[0:17], L3DATA[0:63], L3DP[0:7], L3_ECHO_CLK[0:3],

and L3_CLK[0:1]) and the L3 control signals L3_CNTL[0:1]; and V_DDsupplies power to the processor core and

the PLL (after filtering to become AV_DD). For actual recommended value of V_inor supply voltages, see Table 4.

2. Unused address pins must be pulled down to GND.

3. These pins require weak pull-up resistors (for example, 4.7 kΩ) to maintain the control signals in the negated state

after they have been actively negated and released by the MPC7457 and other bus masters.

4. This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at

HRESET going high.

5. This signal must be negated during reset, by pull up to OV_DDor negation by ¬HRESET (inverse of HRESET), to

ensure proper operation.

6. To program the processor interface I/O voltage, connect BVSEL to either GND (selects 1.8 V) or to HRESET (selects

2.5 V). To program the L3 interface, connect L3VSEL to either GND (selects 1.8 V) or to HRESET (selects 2.5 V).

If used, pull-down resistors should be less than 250 Ω.

7. Internal pull up on die.

8. Ignored in 60x bus mode.

9. These signals must be pulled down to GND if unused or if the MPC7457 is in 60x bus mode.

10.These input signals for factory use only and must be pulled down to GND for normal machine operation.

11.Power must be supplied to GV_DD, even when the L3 interface is disabled or unused.

12.This test signal is recommended to be tied to HRESET; however, other configurations will not adversely affect

performance.

13.These input signals are for factory use only and must be pulled up to OV_DDfor normal machine operation.

14.These signals are for factory use only and must be left unconnected for normal machine operation.

15.This pin can externally cause a performance monitor event. Counting of the event is enabled via software.

16.This signal must be asserted during reset, by pull down to GND or assertion by HRESET, to ensure proper

operation.

17.These pins are internally connected to V_DD. They are intended to allow an external device to detect the core voltage

level present at the processor core. If unused, they must be connected directly to V_DDor left unconnected.

1.8 Package Description

The following sections provide the package parameters and mechanical dimensions for the CBGA package.

1.8.1 Package Parameters for the MPC7447, 360 CBGA

The package parameters are as provided in the following list. The package type is 25 × 25 mm, 360-lead

ceramic ball grid array (CBGA).

Package outline

Interconnects

Pitch

25 × 25 mm

360 (19 × 19 ball array – 1)

1.27 mm (50 mil)

Minimum module height 2.72 mm

Maximum module height 3.24 mm

Ball diameter

0.89 mm (35 mil)

MOTOROLA

MPC7457 RISC Microprocessor Hardware Specifications

Package Description

1.8.2 Mechanical Dimensions for the MPC7447, 360 CBGA

Figure 20 provides the mechanical dimensions and bottom surface nomenclature for the MPC7447, 360

CBGA package.

Capacitor Region

0.2

NOTES:

1. DIMENSIONING AND

TOLERANCING PER ASME

Y14.5M, 1994.

2. DIMENSIONS IN

MILLIMETERS.

A1 CORNER

3. TOP SIDE A1 CORNER

INDEX IS A METALIZED

FEATURE WITH VARIOUS

SHAPES.BOTTOMSIDEA1

CORNER IS DESIGNATED

WITH A BALL MISSING

FROM THE ARRAY.

0.15 A

Millimeters

DIM

MIN

MAX

2.72

0.80

1.10

—

3.20

1.00

1.30

0.6

0.2

2 3 4 5 6 7 8 9 10 111213141516 171819

0.82

0.93

25.00 BSC

—

8.0

—

11.3

—

6.5

10.9

11.1

1.27 BSC

25.00 BSC

0.35 A

—

8.0

—

11.3

360X

—

6.5

0.3 A B C

0.15

9.55

9.75

Figure 20. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC7447,

360 CBGA Package

MPC7457 RISC Microprocessor Hardware Specifications

MOTOROLA

Package Description

1.8.3 Substrate Capacitors for the MPC7447, 360 CBGA

Figure 21 shows the connectivity of the substrate capacitor pads for the MPC7447, 360 CBGA. All

capacitors are 100 nF.

Pad Number

Capacitor

A1 CORNER

-1

-2

GND

V_DD

OV_DD

V_DD

OV_DD

V_DD

OV_DD

V_DD

OV_DD

V_DD

OV_DD

V_DD

C1-1 C2-1 C3-1 C4-1 C5-1 C6-1

C1-2 C2-2 C3-2 C4-2 C5-2 C6-2

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C18-2 C17-2 C16-2 C15-2 C14-2 C13-2

C18-1 C17-1 C16-1 C15-1 C14-1 C13-1

Figure 21. Substrate Bypass Capacitors for the MPC7447, 360 CBGA

MOTOROLA

MPC7457 RISC Microprocessor Hardware Specifications

Package Description

1.8.4 Package Parameters for the MPC7457, 483 CBGA

The package parameters are as provided in the following list. The package type is 29 × 29 mm, 483-lead

ceramic ball grid array (CBGA).

Package outline

Interconnects

29 × 29 mm

483 (22 × 22 ball array – 1)

1.27 mm (50 mil)

—

Pitch

Minimum module height

Maximum module height 3.22 mm

Ball diameter

0.89 mm (35 mil)

1.8.5 Mechanical Dimensions for the MPC7457, 483 CBGA

Figure 21 provides the mechanical dimensions and bottom surface nomenclature for the MPC7457, 483

CBGA package.

MPC7457 RISC Microprocessor Hardware Specifications

MOTOROLA

Package Description

Capacitor Region

0.2

NOTES:

1. DIMENSIONINGAND

TOLERANCING

PER ASME Y14.5M, 1994.

2. DIMENSIONSIN

MILLIMETERS.

A1 CORNER

0.15 A

3. TOP SIDE A1 CORNER

INDEX IS A METALIZED

FEATURE WITH VARIOUS

SHAPES. BOTTOM SIDE.

A1 CORNER IS

DESIGNATED WITH A BALL

MISSING FROM THE

ARRAY.

Millimeters

DIM

MIN

MAX

0.2

2.72

0.80

1.10

3.20

1.00

1.30

0.60

0.93

3 4 5 6 7 8 9 10 111213141516 171819 21 22

1 2

0.82

29.00 BSC

—

8.5

—

12.5

—

8.4

10.9

11.1

1.27 BSC

29.00 BSC

0.35 A

—

8.5

—

12.5

—

8.4

483X

0.3 A B C

9.55

9.75

0.15

Figure 22. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC7457,

483 CBGA Package

MOTOROLA

MPC7457 RISC Microprocessor Hardware Specifications

Package Description

1.8.6 Substrate Capacitors for the MPC7457, 483 CBGA

Figure 23 shows the connectivity of the substrate capacitor pads for the MPC7457, 483 CBGA. All

capacitors are 100 nF.

Pad Number

A1 CORNER

Capacitor

-1

-2

GND

OV_DD

V_DD

C1-1 C2-1 C3-1

C1-2 C2-2 C3-2

C4-1 C5-1 C6-1

C4-2 C5-2 C6-2

GV_DD

V_DD

GV_DD

V_DD

GV_DD

V_DD

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

V_DD

GV_DD

V_DD

C18-2 C17-2 C16-2 C15-2 C14-2 C13-2

C18-1 C17-1 C16-1 C15-1 C14-1 C13-1

OV_DD

V_DD

OV_DD

V_DD

OV_DD

V_DD

Figure 23. Substrate Bypass Capacitors for the MPC7457, 483 CBGA

MPC7457 RISC Microprocessor Hardware Specifications

MOTOROLA

System Design Information

1.9 System Design Information

This section provides system and thermal design recommendations for successful application of the

MPC7457.

1.9.1 PLL Configuration

The MPC7457 PLL is configured by the PLL_CFG[0:4] signals. For a given SYSCLK (bus) frequency, the

PLL configuration signals set the internal CPU and VCO frequency of operation. The PLL configuration for

the MPC7457 is shown in Table 18 for a set of example frequencies. In this example, shaded cells represent

settings that, for a given SYSCLK frequency, result in core and/or VCO frequencies that do not comply with

the 1-GHz column in Table 8. Note that these configurations were different in devices before Rev F; see

Section 1.11.2, “Part Numbers Not Fully Addressed by This Document,” for more information regarding

documentation of prior revisions.

Table 18. MPC7457 Microprocessor PLL Configuration Example for 1267 MHz Parts

Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)

PLL_

CFG[0:4]

Bus (SYSCLK) Frequency

Bus-to-

Core

Multiplier Multiplier

Core-to-

VCO

33.3

MHz

66.6

MHz

100

MHz

133

167

MHz

01000

10000

10100

10110

10010

11010

01010

00100

00010

11000

01100

01111

01110

667

(1333)

667

835

(1333) (1670)

5.5x

733 919

(1466) (1837)

800 1002

600

(1200) (1600) (2004)

6.5x

650 866 1086

(1300) (1730) (2171)

700 931 1169

(1400) (1862) (2338)

7.5x

623

750 1000 1253

(1245) (1500) (2000) (2505)

600

664 800 1064

(1200) (1328) (1600) (2128)

8.5x

638 706 850 1131

(1276) (1412) (1700) (2261)

675 747 900 1197

600

(1200) (1350) (1494) (1800) (2394)

9.5x

633 712 789 950 1264

(1266) (1524) (1578) (1900) (2528)

MOTOROLA

MPC7457 RISC Microprocessor Hardware Specifications

System Design Information

Table 18. MPC7457 Microprocessor PLL Configuration Example for 1267 MHz Parts (continued)

Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)

PLL_

CFG[0:4]

Bus (SYSCLK) Frequency

Bus-to-

Core

Multiplier Multiplier

Core-to-

VCO

33.3

MHz

66.6

MHz

100

MHz

133

167

MHz

10101

10001

10011

00000

10111

11111

01011

11100

11001

00011

11011

00001

00101

00111

01001

01101

11101

00110

10x

10.5x

11x

667

750

830

1000

(1333) (1500) (1660) (2000)

700 938 872 1050

(1400) (1876) (1744) (2100)

733 825 913 1100

(1466) (1650) (1826) (2200)

11.5x

12x

766 863 955 1150

(532) (1726) (1910) (2300)

800 900 996 1200

600

(1200) (1600) (1800) (1992) (2400)

12.5x

13x

600 833 938 1038 1250

(1200) (1666) (1876) (2076) (2500)

650 865 975 1079

(1300) (1730) (1950) (2158)

13.5x

14x

675 900 1013 1121

(1350) (1800) (2026) (2242)

700 933 1050 1162

(1400) (1866) (2100) (2324)

15x

750 1000 1125 1245

(1500) (2000) (2250) (2490)

800 1066 1200

16x

(1600) (2132) (2400)

17x

850 1132

(1900) (2264)

900 1200

18x

600

(1200) (1800) (2400)

20x

667 1000

(1334) (2000)

700 1050

21x

(1400) (2100)

24x

800 1200

(1600) (2400)

28x

933

(1866)

PLL bypass

PLL off, SYSCLK clocks core circuitry directly

MPC7457 RISC Microprocessor Hardware Specifications

MOTOROLA

System Design Information

Table 18. MPC7457 Microprocessor PLL Configuration Example for 1267 MHz Parts (continued)

Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)

PLL_

CFG[0:4]

Bus (SYSCLK) Frequency

Bus-to-

Core

Multiplier Multiplier

Core-to-

VCO

33.3

MHz

66.6

MHz

100

MHz

133

167

MHz

11110

PLL off

PLL off, no core clocking occurs

Notes:

1. PLL_CFG[0:4] settings not listed are reserved.

2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core,

or VCO frequencies which are not useful, not supported, or not tested for by the MPC7455; see Section 1.5.2.1,

“Clock AC Specifications,” for valid SYSCLK, core, and VCO frequencies.

3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly and the PLL is disabled.

However, the bus interface unit requires a 2x clock to function. Therefore, an additional signal, EXT_QUAL, must

be driven at one-half the frequency of SYSCLK and offset in phase to meet the required input setup t_IVKHand hold

time t_IXKH(see Table 9). The result is that the processor bus frequency is one-half SYSCLK while the internal

processor is clocked at SYSCLK frequency. This mode is intended for factory use and emulator tool use only.

Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.

4. In PLL-off mode, no clocking occurs inside the MPC7455 regardless of the SYSCLK input.

MOTOROLA

MPC7457 RISC Microprocessor Hardware Specifications

System Design Information

1.9.2 PLL Power Supply Filtering

The AV power signal is provided on the MPC7457 to provide power to the clock generation PLL. To

ensure stability of the internal clock, the power supplied to the AV input signal should be filtered of any

noise in the 500 kHz to 10 MHz resonant frequency range of the PLL. A circuit similar to the one shown in

Figure 22 using surface mount capacitors with minimum effective series inductance (ESL) is recommended.

The circuit should be placed as close as possible to the AV pin to minimize noise coupled from nearby

circuits. It is often possible to route directly from the capacitors to the AV pin, which is on the periphery

of the 360 CBGA footprint and very close to the periphery of the 483 CBGA footprint, without the

inductance of vias.

The PLL power supply filter previously provided in the MPC7457 RISC Microprocessor Hardware

Specifications has been found to be less effective for Rev 1.1 devices with the low core voltages described

in this specification. As a result, the recommended value for the resistor in the circuit is being evaluated and

a new recommendation is indicated in Figure 24. If the value indicated is not available, the nearest standard

value resistor may be used instead; a higher resistor value is recommended over a lower one. Motorola

continues to evaluate the filtering requirements of the MPC7457 and plans to make updated

recommendations as needed. Note that this recommendation applies to Rev. 1.1 devices only.

400 Ω

V_DD

AV_DD

2.2 µF

Low ESL Surface Mount Capacitors

GND

Figure 24. PLL Power Supply Filter Circuit

1.9.3 Decoupling Recommendations

Due to the MPC7457 dynamic power management feature, large address and data buses, and high operating

frequencies, the MPC7457 can generate transient power surges and high frequency noise in its power

supply, especially while driving large capacitive loads. This noise must be prevented from reaching other

components in the MPC7457 system, and the MPC7457 itself requires a clean, tightly regulated source of

power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each

, OV , and GV

pin of the MPC7457. It is also recommended that these decoupling capacitors

receive their power from separate V , OV /GV , and GND power planes in the PCB, utilizing short

traces to minimize inductance.

These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic surface mount technology (SMT)

capacitors should be used to minimize lead inductance, preferably 0508 or 0603 orientations where

connections are made along the length of the part. Consistent with the recommendations of Dr. Howard

Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993) and contrary to

previous recommendations for decoupling Motorola microprocessors, multiple small capacitors of equal

value are recommended over using multiple values of capacitance.

In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,

feeding the V , GV , and OV planes, to enable quick recharging of the smaller chip capacitors. These

bulk capacitors should have a low equivalent series resistance (ESR) rating to ensure the quick response time

necessary. They should also be connected to the power and ground planes through two vias to minimize

inductance. Suggested bulk capacitors: 100–330 µF (AVX TPS tantalum or Sanyo OSCON).

MOTOROLA

MPC7457 RISC Microprocessor Hardware Specifications

System Design Information

1.9.4 Connection Recommendations

To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal

level. Unused active low inputs should be tied to OV . Unused active high inputs should be connected to

GND. All NC (no-connect) signals must remain unconnected.

Power and ground connections must be made to all external V , OV , GV , and GND pins in the

MPC7457. If the L3 interface is not used, GV

should be connected to the OV power plane, and

L3VSEL should be connected to BVSEL; the remainder of the L3 interface may be left unterminated.

1.9.5 Output Buffer DC Impedance

The MPC7457 processor bus and L3 I/O drivers are characterized over process, voltage, and temperature.

To measure Z , an external resistor is connected from the chip pad to OV or GND. Then, the value of

each resistor is varied until the pad voltage is OV /2 (see Figure 23).

The output impedance is the average of two components, the resistances of the pull-up and pull-down

devices. When data is held low, SW2 is closed (SW1 is open), and R is trimmed until the voltage at the

pad equals OV /2. R then becomes the resistance of the pull-down devices. When data is held high, SW1

is closed (SW2 is open), and R is trimmed until the voltage at the pad equals OV /2. R then becomes

the resistance of the pull-up devices. R and R are designed to be close to each other in value. Then, Z =

(R + R )/2.

OV_DD

R_N

SW2

SW1

Pad

Data

R_P

OGND

Figure 25. Driver Impedance Measurement

Table 20 summarizes the signal impedance results. The impedance increases with junction temperature and

is relatively unaffected by bus voltage.

Table 20. Impedance Characteristics

= 1.5 V, OV = 1.8 V ± 5%, T = 5°–85°C

Impedance

Processor Bus

L3 Bus

Unit

Z₀

Typical

33–42

31–51

34–42

32–44

Ω

Maximum

MPC7457 RISC Microprocessor Hardware Specifications

MOTOROLA

System Design Information

1.9.6 Pull-Up/Pull-Down Resistor Requirements

The MPC7457 requires high-resistive (weak: 4.7-kΩ) pull-up resistors on several control pins of the bus

interface to maintain the control signals in the negated state after they have been actively negated and

released by the MPC7457 or other bus masters. These pins are: TS, ARTRY, SHDO, and SHD1.

Some pins designated as being for factory test must be pulled up to OV or down to GND to ensure proper

device operation. For the MPC7447, 360 BGA, the pins that must be pulled up to OV are: LSSD_MODE

and TEST[0:3]; the pins that must be pulled down to GND are: L1_TSTCLK and TEST[4]. For the

MPC7457, 483 BGA, the pins that must be pulled up to OV are: LSSD_MODE and TEST[0:5]; the pins

that must be pulled down are: L1_TSTCLK and TEST[6]. The CKSTP_IN signal should likewise be pulled

up through a pull-up resistor (weak or stronger: 4.7–1 kΩ) to prevent erroneous assertions of this signal.

In addition, the MPC7457 has one open-drain style output that requires a pull-up resistor (weak or stronger:

4.7–1 kΩ) if it is used by the system. This pin is CKSTP_OUT.

If pull-down resistors are used to configure BVSEL or L3VSEL, the resistors should be less than 250 Ω (see

Table 16). Because PLL_CFG[0:4] must remain stable during normal operation, strong pull-up and

pull-down resistors (1 kΩ or less) are recommended to configure these signals in order to protect against

erroneous switching due to ground bounce, power supply noise or noise coupling.

During inactive periods on the bus, the address and transfer attributes may not be driven by any master and

may, therefore, float in the high-impedance state for relatively long periods of time. Because the MPC7457

must continually monitor these signals for snooping, this float condition may cause excessive power draw

by the input receivers on the MPC7457 or by other receivers in the system. These signals can be pulled up

through weak (10-kΩ) pull-up resistors by the system, address bus driven mode enabled (see the MPC7450

RISC Microprocessor Family Users’ Manual for more information about this mode), or they may be

otherwise driven by the system during inactive periods of the bus to avoid this additional power draw.

Preliminary studies have shown the additional power draw by the MPC7457 input receivers to be negligible

and, in any event, none of these measures are necessary for proper device operation. The snooped address

and transfer attribute inputs are: A[0:35], AP[0:4], TT[0:4], CI, WT, and GBL.

If extended addressing is not used, A[0:3] are unused and must be pulled low to GND through weak

pull-down resistors. If the MPC7457 is in 60x bus mode, DTI[0:3] must be pulled low to GND through weak

pull-down resistors.

The data bus input receivers are normally turned off when no read operation is in progress and, therefore,

do not require pull-up resistors on the bus. Other data bus receivers in the system, however, may require

pull-ups, or that those signals be otherwise driven by the system during inactive periods by the system. The

data bus signals are: D[0:63] and DP[0:7].

If address or data parity is not used by the system, and the respective parity checking is disabled through

HID0, the input receivers for those pins are disabled, and those pins do not require pull-up resistors and

should be left unconnected by the system. If all parity generation is disabled through HID0, all parity

checking should also be disabled through HID0, and all parity pins may be left unconnected by the system.

The L3 interface does not normally require pull-up resistors.

1.9.7 JTAG Configuration Signals

Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the

IEEE 1149.1 specification, but is provided on all processors that implement the PowerPC architecture.

While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, more

reliable power-on reset performance will be obtained if the TRST signal is asserted during power-on reset.

MOTOROLA

MPC7457 RISC Microprocessor Hardware Specifications

System Design Information

Because the JTAG interface is also used for accessing the common on-chip processor (COP) function,

simply tying TRST to HRESET is not practical.

The COP function of these processors allows a remote computer system (typically, a PC with dedicated

hardware and debugging software) to access and control the internal operations of the processor. The COP

interface connects primarily through the JTAG port of the processor, with some additional status monitoring

signals. The COP port requires the ability to independently assert HRESET or TRST in order to fully control

the processor. If the target system has independent reset sources, such as voltage monitors, watchdog timers,

power supply failures, or push-button switches, the COP reset signals must be merged into these signals with

logic.

The arrangement shown in Figure 24 allows the COP port to independently assert HRESET or TRST, while

ensuring that the target can drive HRESET as well. If the JTAG interface and COP header will not be used,

TRST should be tied to HRESET through a 0-Ω isolation resistor so that it is asserted when the system reset

signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during power-on. While

Motorola recommends that the COP header be designed into the system as shown in Figure 24, if this is not

possible, the isolation resistor will allow future access to TRST in the case where a JTAG interface may need

to be wired onto the system in debug situations.

The COP header shown in Figure 24 adds many benefits—breakpoints, watchpoints, register and memory

examination/modification, and other standard debugger features are possible through this interface—and

can be as inexpensive as an unpopulated footprint for a header to be added when needed.

The COP interface has a standard header for connection to the target system, based on the 0.025"

square-post, 0.100" centered header assembly (often called a Berg header). The connector typically has

pin 14 removed as a connector key.

There is no standardized way to number the COP header shown in Figure 24; consequently, many different

pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then

left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter

clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in

Figure 24 is common to all known emulators.

The QACK signal shown in Figure 24 is usually connected to the PCI bridge chip in a system and is an input

to the MPC7457 informing it that it can go into the quiescent state. Under normal operation this occurs

during a low-power mode selection. In order for COP to work, the MPC7457 must see this signal asserted

(pulled down). While shown on the COP header, not all emulator products drive this signal. If the product

does not, a pull-down resistor can be populated to assert this signal. Additionally, some emulator products

implement open-drain type outputs and can only drive QACK asserted; for these tools, a pull-up resistor can

be implemented to ensure this signal is deasserted when it is not being driven by the tool. Note that the

pull-up and pull-down resistors on the QACK signal are mutually exclusive and it is never necessary to

populate both in a system. To preserve correct power-down operation, QACK should be merged via logic

so that it also can be driven by the PCI bridge.

MPC7457 RISC Microprocessor Hardware Specifications

MOTOROLA

System Design Information

SRESET

From Target

Board Sources

(if any)

SRESET

HRESET

QACK

10 kΩ

HRESET

OV_DD

SRESET

OV_DD

0 Ω ⁵

TRST

VDD_SENSE

OV_DD

10 kΩ

2 kΩ

5 ¹

OV_DD

CHKSTP_OUT

10 kΩ

OV_DD

Key

10 kΩ

14 ²

OV_DD

CHKSTP_IN

TMS

KEY

No Pin

CHKSTP_IN

TMS

COP Connector

Physical Pin Out

TDO

TDI

TDO

TDI

TCK

QACK

2 kΩ ³

12 ⁶

OV_DD

10 kΩ ⁴

Notes:

1. RUN/STOP, normally found on pin 5 of the COP header, is not implemented on the MPC7457. Connect

pin 5 of the COP header to OV_DDwith a 10-kΩ pull-up resistor.

2. Key location; pin 14 is not physically present on the COP header.

3. Component not populated. Populate only if debug tool does not drive QACK.

4. Populate only if debug tool uses an open-drain type output and does not actively deassert QACK.

5. If the JTAG interface is implemented, connect HRESET from the target source to TRST from the COP

header though an AND gate to TRST of the part. If the JTAG interface is not implemented, connect

HRESET from the target source to TRST of the part through a 0-Ω isolation resistor.

6. Though defined as a No-Connect, it is a common and recommended practice to use pin 12 as an

Figure 26. JTAG Interface Connection

MOTOROLA

MPC7457 RISC Microprocessor Hardware Specifications

System Design Information

1.9.8 Thermal Management Information

This section provides thermal management information for the ceramic ball grid array (CBGA) package for

air-cooled applications. Proper thermal control design is primarily dependent on the system-level

design—the heat sink, airflow, and thermal interface material. To reduce the die-junction temperature, heat

sinks may be attached to the package by several methods—spring clip to holes in the printed-circuit board

or package, and mounting clip and screw assembly (see Figure 25); however, due to the potential large mass

of the heat sink, attachment through the printed-circuit board is suggested. If a spring clip is used, the spring

force should not exceed 10 pounds.

CBGA Package

Heat Sink

Clip

Thermal

Interface Material

Printed-Circuit Board

Figure 27. Package Exploded Cross-Sectional View with Several Heat Sink Options

The board designer can choose between several types of heat sinks to place on the MPC7457. There are

several commercially available heat sinks for the MPC7457 provided by the following vendors:

Aavid Thermalloy

80 Commercial St.

Concord, NH 03301

Internet: www.aavidthermalloy.com

603-224-9988

408-749-7601

Alpha Novatech

473 Sapena Ct. #15

Santa Clara, CA 95054

Internet: www.alphanovatech.com

International Electronic Research Corporation (IERC) 818-842-7277

413 North Moss St.

Burbank, CA 91502

Internet: www.ctscorp.com

Tyco Electronics

800-522-6752

Chip Coolers™

P.O. Box 3668

Harrisburg, PA 17105-3668

Internet: www.chipcoolers.com

MPC7457 RISC Microprocessor Hardware Specifications

MOTOROLA

System Design Information

603-635-5102

Wakefield Engineering

33 Bridge St.

Pelham, NH 03076

Internet: www.wakefield.com

Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal

performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost.

1.9.8.1 Internal Package Conduction Resistance

For the exposed-die packaging technology, shown in Table 3, the intrinsic conduction thermal resistance

paths are as follows:

•

The die junction-to-case (actually top-of-die since silicon die is exposed) thermal resistance

The die junction-to-ball thermal resistance

Figure 26 depicts the primary heat transfer path for a package with an attached heat sink mounted to a

printed-circuit board.

External Resistance

Radiation

Convection

Heat Sink

Thermal Interface Material

Die/Package

Die Junction

Package/Leads

Internal Resistance

Printed-Circuit Board

Radiation

Convection

External Resistance

(Note the internal versus external package resistance.)

Figure 28. C4 Package with Heat Sink Mounted to a Printed-Circuit Board

Heat generated on the active side of the chip is conducted through the silicon, through the heat sink attach

material (or thermal interface material), and finally to the heat sink where it is removed by forced-air

convection.

Because the silicon thermal resistance is quite small, for a first-order analysis, the temperature drop in the

silicon may be neglected. Thus, the thermal interface material and the heat sink conduction/convective

thermal resistances are the dominant terms.

1.9.8.2 Thermal Interface Materials

A thermal interface material is recommended at the package lid-to-heat sink interface to minimize the

thermal contact resistance. For those applications where the heat sink is attached by spring clip mechanism,

Figure 27 shows the thermal performance of three thin-sheet thermal-interface materials (silicone,

graphite/oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure.

As shown, the performance of these thermal interface materials improves with increasing contact pressure.

MOTOROLA

MPC7457 RISC Microprocessor Hardware Specifications

System Design Information

The use of thermal grease significantly reduces the interface thermal resistance. That is, the bare joint results

in a thermal resistance approximately seven times greater than the thermal grease joint.

Often, heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board

(see Figure 25). Therefore, the synthetic grease offers the best thermal performance, considering the low

interface pressure and is recommended due to the high power dissipation of the MPC7457. Of course, the

selection of any thermal interface material depends on many factors—thermal performance requirements,

manufacturability, service temperature, dielectric properties, cost, etc.

Silicone Sheet (0.006 in.)

Bare Joint

Floroether Oil Sheet (0.007 in.)

Graphite/Oil Sheet (0.005 in.)

Synthetic Grease

1.5

0.5

Contact Pressure (psi)

Figure 29. Thermal Performance of Select Thermal Interface Material

The board designer can choose between several types of thermal interface. Heat sink adhesive materials

should be selected based on high conductivity, yet adequate mechanical strength to meet equipment

shock/vibration requirements. There are several commercially available thermal interfaces and adhesive

materials provided by the following vendors:

The Bergquist Company

18930 West 78 St.

800-347-4572

Chanhassen, MN 55317

Internet: www.bergquistcompany.com

Chomerics, Inc.

781-935-4850

77 Dragon Ct.

Woburn, MA 01888-4014

Internet: www.chomerics.com

MPC7457 RISC Microprocessor Hardware Specifications

MOTOROLA

System Design Information

800-248-2481

Dow-Corning Corporation

Dow-Corning Electronic Materials

2200 W. Salzburg Rd.

Midland, MI 48686-0997

Internet: www.dow.com

Shin-Etsu MicroSi, Inc.

10028 S. 51st St.

Phoenix, AZ 85044

888-642-7674

888-246-9050

Internet: www.microsi.com

Thermagon Inc.

4707 Detroit Ave.

Cleveland, OH 44102

Internet: www.thermagon.com

The following section provides a heat sink selection example using one of the commercially available heat

sinks.

1.9.8.3 Heat Sink Selection Example

For preliminary heat sink sizing, the die-junction temperature can be expressed as follows:

T = T + T + (R + R

+ R ) × P

θsa d

θJC

θint

where:

T is the die-junction temperature

T is the inlet cabinet ambient temperature

T is the air temperature rise within the computer cabinet

is the junction-to-case thermal resistance

θJC

θint

θsa

is the adhesive or interface material thermal resistance

is the heat sink base-to-ambient thermal resistance

P is the power dissipated by the device

During operation, the die-junction temperatures (T ) should be maintained less than the value specified in

Table 4. The temperature of air cooling the component greatly depends on the ambient inlet air temperature

and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (T )

may range from 30° to 40°C. The air temperature rise within a cabinet (T ) may be in the range of 5° to 10°C.

The thermal resistance of the thermal interface material (R ) is typically about 1.5°C/W. For example,

θint

assuming a T of 30°C, a T of 5°C, a CBGA package R

= 0.1, and a typical power consumption (P ) of

θJC

18.7 W, the following expression for T is obtained:

Die-junction temperature: T = 30°C + 5°C + (0.1°C/W + 1.5°C/W + θ ) × 18.7 W

For this example, a R value of 2.1°C/W or less is required to maintain the die junction temperature below

θsa

the maximum value of Table 4.

Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common

figure-of-merit used for comparing the thermal performance of various microelectronic packaging

technologies, one should exercise caution when only using this metric in determining thermal management

because no single parameter can adequately describe three-dimensional heat flow. The final die-junction

operating temperature is not only a function of the component-level thermal resistance, but the system-level

design and its operating conditions. In addition to the component's power consumption, a number of factors

MOTOROLA

MPC7457 RISC Microprocessor Hardware Specifications

System Design Information

affect the final operating die-junction temperature—airflow, board population (local heat flux of adjacent

components), heat sink efficiency, heat sink attach, heat sink placement, next-level interconnect technology,

system air temperature rise, altitude, etc.

Due to the complexity and the many variations of system-level boundary conditions for today's

microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection,

and conduction) may vary widely. For these reasons, we recommend using conjugate heat transfer models

for the board, as well as system-level designs.

For system thermal modeling, the MPC7447 and MPC7457 thermal model is shown in Figure 28. Four

volumes will be used to represent this device. Two of the volumes, solder ball, and air and substrate, are

modeled using the package outline size of the package. The other two, die, and bump and underfill, have the

same size as the die. The silicon die should be modeled 9.64 × 11.0 × 0.74 mm with the heat source applied

as a uniform source at the bottom of the volume. The bump and underfill layer is modeled as 9.64 × 11.0 ×

0.69 mm (or as a collapsed volume) with orthotropic material properties: 0.6 W/(m • K) in the xy-plane and

2 W/(m • K) in the direction of the z-axis. The substrate volume is 25 × 25 × 1.2 mm (MPC7447) or 29 ×

29 × 1.2 mm (MPC7457), and this volume has 18 W/(m • K) isotropic conductivity. The solder ball and air

layer is modeled with the same horizontal dimensions as the substrate and is 0.9 mm thick. It can also be

modeled as a collapsed volume using orthotropic material properties: 0.034 W/(m • K) in the xy-plane

direction and 3.8 W/(m • K) in the direction of the z-axis.

Die

Bump and Underfill

Substrate

Solder and Air

Conductivity

Value

Unit

Bump and Underfill

Side View of Model (Not to Scale)

k_x

k_y

k_z

0.6

W/(m • K)

Substrate

Die

Solder Ball and Air

k_x

k_y

k_z

0.034

3.8

Top View of Model (Not to Scale)

Figure 30. Recommended Thermal Model of MPC7447 and MPC7457

MPC7457 RISC Microprocessor Hardware Specifications

MOTOROLA

Document Revision History

1.10 Document Revision History

Table 21 provides a revision history for this hardware specification.

Table 21. Document Revision History

Revision

Substantive Change(s)

Number

Initial release.

• Removed support for 1.5 V L3 interface voltage from Tables 3 and 4. 1.5 V I/O voltage is not

supported in current MPC7457 devices.

• Added package thermal characteristics values to Table 5, made minor revisions to Section 1.9.8.

• Added preliminary AC timing values to Tables 10 and 12.

• Added footnotes to Table 17.

1.1

Nontechnical reformatting

• Added substrate capacitor information in Sections 1.8.3 and 1.8.6.

• Increased minimum processor and VCO frequencies in Table 8 from 500 MHz and 1000 MHz to 600

MHz and 1200 MHz (respectively).

• Corrected maximum processor frequency for 1300 MHz devices in Table 8 (changed from 1333 MHz

to 1300 MHz).

• Added value for to t_L3CSKW1Table 10.

• Added L3OHCR information in Section 1.5.2.4.1.

• Added values for t_COand t_ECIto Table 11.

• Added Note 8 to Table 13 and Note 6 to Table 14.

• Changed resistor value in PLL filter in Figure 24 from 10 Ω to 400 Ω.

• Added 867 MHz speed grade.

• Corrected Product Code in Tables 22 and 23.

• Added pull-up/pull-down recommendations for CKSTP_IN and PLL_CFG[0:4] to Section 1.9.6.

Corrected numerous errors in lists of pins associated with t_KHOV, t_KHOX, t_IVKH, and t_IXKHin Table 9.

Added support for 1.5 V L3 interface voltage; issues fixed in Rev 1.1.

Corrected typos in Table 12.

Added data to Table 2.

Clarified address bus pull-up resistor recommendations in Section 1.9.6.

Modified Table 9, Figure 5, and Figure 6 to more accurately show when the mode select inputs

(BMODE[0:1], L3VSEL, BVSEL) are sampled and AC timing requirements

Table 10: Added skew and jitter values.

Table 14: Added AC timing values.

Table 23: Updated to reflect past and current part numbers not fully covered by this document.

Table 6: Removed CV_IHand CV_IL; V_IHand V_ILfor SYSCLK input is the same as for other input signals,

and is now noted accordingly in this table.

Table 7: Removed Doze mode power entry (but left footnote 4 for clarity); documentation change only.

Nontechnical formatting

MOTOROLA

MPC7457 RISC Microprocessor Hardware Specifications

Document Revision History

Table 21. Document Revision History (continued)

Revision

Number

Substantive Change(s)

Table 9:Corrected pin lists for input and output AC timing to correctly show HIT as an output-only signal

Added specifications for 1267 MHz devices; removed specs for 1300 MHz devices.

Changed recommendations regarding use of L3 clock jitter in AC timing analysis in Section 1.5.2.3, “L3

Clock AC Specifications”; the L3 jitter is now fully comprehended in the AC timing specs and does not

need to be included in the timing analysis.

MPC7457 RISC Microprocessor Hardware Specifications

MOTOROLA

Ordering Information

1.11 Ordering Information

Ordering information for the parts fully covered by this specification document is provided in

Section 1.11.1, “Part Numbers Fully Addressed by This Document.” Note that the individual part numbers

correspond to a maximum processor core frequency. For available frequencies, contact your local Motorola

sales office. In addition to the processor frequency, the part numbering scheme also includes an application

modifier which may specify special application conditions. Each part number also contains a revision level

code which refers to the die mask revision number. Section 1.11.2, “Part Numbers Not Fully Addressed by

This Document,” lists the part numbers which do not fully conform to the specifications of this document.

These special part numbers require an additional document called a part number specification.

MOTOROLA

MPC7457 RISC Microprocessor Hardware Specifications

Ordering Information

1.11.1 Part Numbers Fully Addressed by This Document

Table 22 provides the Motorola part numbering nomenclature for the MPC7457.

Table 22. Part Numbering Nomenclature

PPC

74x7

nnnn

Product

Code

Part

Identifier

Processor

Application

Modifier

Package

Revision Level

Frequency ¹

PPC ²

7457

7447

RX = CBGA

867

1000

1200

1267

L: 1.3 V ± 50 mV

B: 1.1; PVR = 8002 0101

0 to 105°C

Notes:

1. Processor core frequencies supported by parts addressed by this specification only. Parts addressed by part

number specifications may support other maximum core frequencies.

2. The P prefix in a Motorola part number designates a “Pilot Production Prototype” as defined by Motorola SOP 3-13.

These parts have only preliminary reliability and characterization data. Before pilot production prototypes may be

shipped, written authorization from the customer must be on file in the applicable sales office acknowledging the

qualification status and the fact that product changes may still occur while shipping pilot production prototypes.

1.11.2 Part Numbers Not Fully Addressed by This Document

Parts with application modifiers or revision levels not fully addressed in this specification document are

described in separate part number specifications which supplement and supersede this document. As such

parts are released, these specifications will be listed in this section.

Table 23. Part Numbering Nomenclature

PPC

74x7

nnnn

Product

Code

Part

Identifier

Processor

Frequency

Application

Modifier

Package

Revision Level

PPC

7457

RX = CBGA

1000

867

733

600

1000

867

1000

867

733

600

N: 1.1 V ± 50 mV

B: 1.1; PVR = 8002 0101

0 to 105°C

7447

MPC7457 RISC Microprocessor Hardware Specifications

MOTOROLA

Ordering Information

1.11.3 Part Marking

Parts are marked as the example shown in Figure 29.

PPC7457

RX1200LB

PPC7447

RX1200LB

MMMMMM

ATWLYYWWA

MMMMMM

ATWLYYWWA

7447

7457

BGA

Notes:

MMMMMM is the 6-digit mask number.

ATWLYYWWA is the traceability code.

CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States.

Figure 31. Part Marking for BGA Device

MPC7457 RISC Microprocessor Hardware Specifications

MOTOROLA

Ordering Information

THIS PAGE INTENTIONALLY LEFT BLANK

MPC7457 RISC Microprocessor Hardware Specifications

MOTOROLA

Ordering Information

THIS PAGE INTENTIONALLY LEFT BLANK

MPC7457 RISC Microprocessor Hardware Specifications

MOTOROLA

HOW TO REACH US:

USA/EUROPE/LOCATIONS NOT LISTED:

Motorola Literature Distribution

P.O. Box 5405, Denver, Colorado 80217

1-480-768-2130

(800) 521-6274

JAPAN:

Motorola Japan Ltd.

SPS, Technical Information Center

3-20-1, Minami-Azabu Minato-ku

Tokyo 106-8573 Japan

Information in this document is provided solely to enable system and software implementers to use

Motorola products. There are no express or implied copyright licenses granted hereunder to design

or fabricate any integrated circuits or integrated circuits based on the information in this document.

81-3-3440-3569

ASIA/PACIFIC:

Motorola Semiconductors H.K. Ltd.

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Tai Po Industrial Estate, Tai Po, N.T., Hong Kong

852-26668334

Motorola reserves the right to make changes without further notice to any products herein.

Motorola makes no warranty, representation or guarantee regarding the suitability of its products

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limitation consequential or incidental damages. “Typical” parameters which may be provided in

Motorola data sheets and/or specifications can and do vary in different applications and actual

performance may vary over time. All operating parameters, including “Typicals” must be validated

for each customer application by customer’s technical experts. Motorola does not convey any

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the failure of the Motorola product could create a situation where personal injury or death may

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Freescale > PowerPC" Processors > MPC7XXX, MPC7XX and MPC6XX Host Processors >

MPC7447

MPC7447 : Host Processor

Building on Freescale Semiconductor's (formerly Motorola, Inc.,

Semiconductor Products Sector) continued innovation and

performance leadership in the high-performance host processor

market, the MPC7447 achieves two major milestones in the embedded

world: It delivers 1.3 GHz of performance—making it Freescale's

fastest PowerPC" processor available for embedded applications. It

also dissipates less than 10W while running at 1GHz—a critical

threshold for many power-sensitive embedded designs.

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The MPC7447 host processor is a high-performance, low-power 32-bit

implementation of the PowerPC RISC architecture with a full 128-bit

implementation of Freescale's AltiVec™ technology. Delivering a high

level of performance with efficient power consumption across virtually all

speeds, this innovative PowerPC processor provides networking and

computing product OEMs with a best-in-class solution for a wide range of

host processor applications—including high-performance network

infrastructure and telecommunications equipment, computing products and

embedded systems.

Offered in a 360-pin CBGA package, the MPC7447 processor is

footprint-compatible with Freescale's MPC7445 processor, providing an

easy migration path for OEMs seeking higher performance for their new or

existing PowerPC processor-based applications. The 360-pin MPC7447 is

an ideal choice for space-constrained applications requiring a smaller

embedded CPU footprint. The MPC7447 can reach speeds of 1.3 GHz with

a core voltage of 1.3V and includes 512KB of on-chip L2 cache (a 2X

increase over the MPC7445's L2 cache). A lower-power version of the

MPC7447 is available, operating at speeds of up to 1 GHz with a core

voltage of 1.0V.

The MPC7447 is manufactured on Freescale's 0.13-micron HiPerMOS

silicon-on-insulator (SOI) copper interconnect process technology, enabling

it to deliver superior performance over bulk CMOS technology. In addition

to increased performance, SOI technology offers excellent low power

capability, making the devices ideal for embedded applications in the wired

and wireless telecommunications, networking and imaging arenas.

In addition to achieving a new clock speed milestone, the MPC7447

processor offers the following features designed to optimize performance

and functionality in embedded applications:

● AltiVec™ technology — All members of Freescale's G4 family of

PowerPC processors include a full 128-bit implementation of

Freescale's advanced AltiVec Single Instruction Multiple Data

(SIMD) vector processing technology. AltiVec technology allows

designers to leverage existing PowerPC code and add AltiVec

performance as market and customers' requirements change—helping

speed time-to-market and increase system performance without

upgrading hardware.

● Block address translation (BAT) registers — The MPC7447 offers

8 instruction BAT and data BAT registers to support efficient

embedded operating systems through high-speed mapping of

additional large blocks of data.

● Cache locking — The L1 cache supports cache way locking,

allowing key performance algorithms and code to be locked in the L1

cache.

● Full symmetric multiprocessing (SMP) support — SMP capability

enables customers to achieve significantly higher system performance

by scaling their embedded system designs with multiple Freescale

PowerPC processors.

Product Picture

Block Diagram

MPC7447 Features

Superscalar Microprocessor

The MPC7447 microprocessor features a high-frequency superscalar G4

core capable of issuing four instructions per clock cycle (three instructions

+ branch) into eleven independent execution units:

● Four integer units (3 simple + 1 complex)

● Double-precision floating-point unit

● Four AltiVec units (simple, complex, floating, and permute)

● Load/store unit

● Branch processing unit

Compatibility and Support

● Footprint compatible with MPC7455 and MPC7445 processors.

● As with all PowerPC processors, the MPC7447 is compatible with

the MPC7xx family of processors from Freescale.

● PowerPC processors enjoy the broadest set of operating systems,

compilers, and development tools from third-party tool vendors

belonging to Freescale's Smart Networks Alliance.

Product Features

The MPC7447 processor's 32-bit superscalar core contains:

● Three issue (plus branch) capability

● 128-bit wide vector unit—AltiVec technology

● Integrated 512K on-chip L2 cache (twice the size of previous

generation)

● Full Symmetric Multi-Processing capability (SMP)

● 36-bit physical address space for direct addressability of 64

Gigabytes of memory

● Hardware and Software Tablewalk

● High-bandwidth 133 MHz 64-bit MPX Bus/60x Bus

● 8 BAT registers

● Three power-saving user-programmable modes to reduce power

drawn by processor

● Parity checking support on L1 and L2 cache arrays

Return to Top

Core

I/O

Junction

Operating

Temperature

(Max)

CPU

Operating

Power

Ambient

Temp

(Min)

(oC)

Operating Operating

Performance Frequency Dissipation Dissipation

Voltage

(Spec)

(V)

Voltage

(Max)

(V)

(Max)

(MIPS)

(Max)

(MHz)

(Typ)

(W)

(Max)

(W)

(oC)

5.3,

6.3,

7.3,

7.9,

8.1,

10.3,

11.5,

21,

22,

24.2,

25.6

1386,

1693,

2003,

2310,

2772,

2926.8

600,

733,

867,

1000,

1200,

1267

8.3,

1.1,

1.3

2.5

105

14.8,

15.8,

17.5,

18.3

L1 Cache

Instructional

(Max)

L1 Cache L2 Cache

External Bus

Data

(Max)

Internal

(Max)

Speed

(Max)

(MHz)

Bus Interface

Package Description

(KByte)

60x,

MPX

256

133

FCCBGA 360 25SQ*3.2P1.27

Return to Top

MPC7447 Parametrics

MPC7447 Documentation

Documentation

Application Note

Size Rev Date Last

Order

Name

Vendor ID Format

FREESCALE

Modified Availability

AN1795/D

Designing PowerPC(TM) MPC7400 Systems

pdf 97 1.1 6/05/2003

Minimal Boot Sequence for Executing

Compiled C Programs on PowerPC(TM)

Devices

FREESCALE

11/11/2003

AN1809

pdf 270 1.2

Design Checklist for Freescale Semiconductor FREESCALE

PowerPC(TM) Microprocessors

11/11/2003

AN2077

AN2097

AN2106/D

AN2114/D

AN2115/D

AN2161

AN2180

AN2182

AN2203/D

AN2273

AN2323

AN2435

AN2436

pdf 309 1.6

PowerPC(TM) 60X Bus Implementation

Differences

PowerPC(TM) MPX Bus Implementation

Differences

Complex Fixed-Point Fast Fourier Transform

Optimization for Altivec(TM)

FREESCALE

pdf 135 0.3 8/06/2003

pdf 76 0.1 6/05/2003

pdf 158 2.1 6/03/2003

pdf 151 2.1 6/03/2003

pdf 95 0.1 8/04/2003

pdf 87 0.2 8/04/2003

Complex Floating Point Fast Fourier Transform FREESCALE

Optimization for AltiVec(TM)

FREESCALE

Outstanding Data Tenures on the MPX Bus

FREESCALE

Cache Latencies of the 7451

Setting the Sample Points for the MPC7450 L3 FREESCALE

Cache

pdf 137

FREESCALE 1152

8/14/2001

7/30/2002

MPC7450 RISC Microprocessor Family

Software Optimization Guide

pdf

Building an NFS DHCP/BOOTP Server for Use FREESCALE

with Sandpoint and MVP Linux

PowerPC(TM) MPC7455 I/O Power Evaluation FREESCALE

pdf 213 1.1 6/10/2003

11/11/2003

pdf 101 0.2

Thermal Solutions for PowerPC(TM) Processors FREESCALE

pdf 125

7/28/2003

FREESCALE

11/11/2003

Specifying Power Consumption

pdf 225 0.2

Simplified Mnemonics for PowerPC Instructions FREESCALE

AN2491

AN2540

AN2581

pdf 524

9/30/2003

Synchronizing Instructions for PowerPC(TM) FREESCALE

Instruction Set Architecture

pdf 67 0.1 7/03/2003

10/10/2003

AltiVec Performance Enhancement in a

Multiprocessing Environment

FREESCALE

pdf 224

Common Footprint for the MPC7441,

MPC7445, MPC7447, MPC7447A, and Future

Generations

FREESCALE

AN2656

pdf 95 0.1 6/04/2004

Data Sheets

Size Rev Date Last

Order

Name

Vendor ID Format

Modified Availability

MPC7457 RISC Microprocessor

Hardware Specifications

FREESCALE

pdf

1435

11/10/2003

MPC7457EC

MPC7457 Part Number Specification for FREESCALE

the MPC74x7RXnnnnNx Series

MPC7457 Part Number Specification for FREESCALE

the MPC74x7TRXnnnnNx Series

10/07/2003

MPC7457RXNXPNS

MPC7457TRXNXPNS

pdf 107

pdf 42

5/21/2004

Errata - Click here for important errata information

Size Rev Date Last

Order

Name

Vendor ID Format

Modified Availability

MPC7450 Family Chip Errata for the MPC7457 FREESCALE

and MPC7447

310

6/18/2004

MPC7457CE

pdf

7.1

Fact Sheets

Size Rev Date Last

Order

Name

Vendor ID Format

Modified Availability

MPC7457FS

FREESCALE

pdf

117

8/09/2004

MPC7457 MPC7447 Host Processors

AltiVec Fact Sheet

FREESCALE

pdf

160

171

234

2/20/2003

1/01/1998

2/17/2003

ALTIVECFACT

ALTIVECWP

Freescale Semiconductor's AltiVec

Technology

FREESCALE

pdf

FREESCALE

pdf

PPCSALESFACT/D

PowerPC Processors At-A-Glance

Packaging Information

Size Rev Date Last

Order

Name

Vendor ID Format

FREESCALE pdf

Modified Availability

1014

CBGAPRES

PBGAPRES

TBGAPRESPKG

CBGA Packing Customer Tutorial

PBGA Packaging Customer Tutorial

TBGA Packaging Customer Tutorial

1.0 7/02/2004

1923

1784

8/05/2003

Product Brief

Size Rev Date Last

Order

Name

Vendor ID Format

Modified Availability

MPC7450 RISC Microprocessor Family

Technical Summary

FREESCALE

pdf

596

3/24/2004

MPC7450TS

Product Change Notices

Size Rev Date Last

Order

Name

Vendor ID Format

FREESCALE

Modified Availability

CARRIER TAPE CHANGE FOR

MICROPROCESSORS

CARRIER TAPE CHANGE FOR

MICROPROCESSORS

NEW TRAY FOR 25 X 25 FLIPCHIP BGA

PACKAGE

PCN9023

PCN9041

PCN9224

htm 11

htm 26

htm 62

8/06/2003

FREESCALE

7/24/2003

10/14/2003

Product Numbering Scheme

Size Rev Date Last

Order

Name

Vendor ID Format

FREESCALE

Modified Availability

CPU Part Number Scheme for Freescale

Semiconductor Processors that Implement the

PowerPC Architecture

10/26/1998

PPCCPUPNS

gif 43

Reference Manual

Size Rev Date Last

Order

Name

Vendor ID Format

Modified Availability

AltiVec Technology Programming

Interface Manual

FREESCALE

pdf

ALTIVECPIM

6/01/1999

The Bus Interface for 32-Bit

Microprocessors that Implement the

PowerPC Architecture

MPC7450 RISC Microprocessor Family FREESCALE

User's Manual

FREESCALE

MPC60XBUSRM

pdf 2527 0.1 1/14/2004

10829

MPC7450UM

pdf

3.1 2/23/2004

FREESCALE

MPC7450UM_ZIP

MPC7450 Users Manual (Compressed)

zip 2999

2/10/2003

Programming Environments Manual for

FREESCALE

12/21/2001

MPCFPE32B/AD

32-Bit Implementations of the PowerPC

Architecture

Errata to MPCFPE32B, Programming

Environments Manual for 32-Bit

Implementations of the Power PC

Architecture, Rev. 2

pdf 6909

FREESCALE

10/11/2002

MPCFPE32BAD/AD

pdf

Reliability and Quality Information

Size Rev Date Last

Order

Name

Vendor ID Format

Modified Availability

MC7447N/MC7457N Microprocessor Rev 1.2 FREESCALE

Qualification Report

182

3/30/2004

MC7447_7457RQI

pdf

Reports or Presentations

Size Rev Date Last

Order

Name

Vendor ID Format

Modified Availability

Freescale Semiconductor Host and Integrated

Processor Summary

FREESCALE

pdf

2/10/2003

PPCCPUSUMM

Roadmap

Size Rev Date Last

Order

Name

Vendor ID Format

Modified Availability

Freescale High-Performance PowerPC Processors FREESCALE

Roadmap

4/26/2004

PPCRMAP

pdf 27

Supporting Information

Size Rev Date Last

Order

Name

Vendor ID Format

Modified Availability

Freescale Semiconductor Host Processor Version FREESCALE

4/05/2004

PPCPVR

pdf

White Paper

Size Rev Date Last

Order

Name

Vendor ID Format

Modified Availability

Enhanced TCP/IP Performance with FREESCALE

AltiVec

152

ALTIVECTCPIPWP/D

G4WP

pdf

1.0 1/21/2003

FREESCALE

G4 Architecture White Paper

pdf 53

1/23/2001

5/01/1996

Motorola PowerPC 603 and PowerPC

604 RISC Microprocessor: The

C4/Ceramic-Ball-Grid Array

Interconnect Technology

FREESCALE 112

MPC603OVERALLWP/D

pdf

Thermal Management of a

C4/Ceramic-Ball-Grid Array: The

Motorola PowerPC 603 and PowerPC

604 RISC Microprocessors

Memory Bus Throughput of the

MPC74xx

FREESCALE

MPC603THERMALWP/D

MPC74XXMBUSWP_D

pdf 86

103

5/01/1996

11/24/2003

pdf

1.1

Return to Top

MPC7447 Design Tools

Hardware Tools

Board Testers

Size Rev

Order

Name

Vendor ID Format

# Availability

SCANPLUS

CORELIS

ScanPlus

µMaster 4031

Functional Test and Debug Solutions for boards carrying

Motorola™ and IBM® PowerPC™ processors with COP

debug port (740, 750, 750DD2, 750DD3, 755, 603e, 8240,

8250A, 8255A, 8260A, 8264A, 8265A, 8266A, 7400, 7410,

etc.)

4000-994020-001

INTLTEST

Emulators/Probes/Wigglers

Size Rev

Order

Name

Vendor ID Format

# Availability

BDI1000/BDI2000

Abatron develops and produces high-quality, high-speed

BDM and JTAG Debug Tools (BDI Family) for software

development environments from leading vendors.

BDI1000/BDI2000

10200A

ABATRON

CORELIS

NetICE-R option 2/2M

µMaster 4031

Functional Test and Debug Solutions for boards carrying

Motorola™ and IBM® PowerPC™ processors with COP

debug port (740, 750, 750DD2, 750DD3, 755, 603e, 8240,

8250A, 8255A, 8260A, 8264A, 8265A, 8266A, 7400, 7410,

etc.)

4000-994020--001

WPICE

INTLTEST

WINDRIV

WIND®POWER ICE

Evaluation/Development Boards and Systems

Size Rev

Order

Name

Vendor ID Format

# Availability

PPCEVAL-SP3-7447

Sandpoint X3 Motherboard with Gyrus X3 MPC7447

PMC Module

FREESCALE

SANDPOINTX3

Sandpoint X3 Evaluation System - Motherboard

Open Desktop Workstation

OPEN DESKTOP

WORKSTATION

The open desktop workstation is based on the Genesi

PegasosPPC. The workstation is offered fully configured

with a number of operating system options.

GENESI

PegasosPPC

The Pegasos is an an open hardware platform based on

the CHRP motherboard standard for the PowerPC and

selected Open Firmware so that many operating systems

can work easily on the platform.

PEGASOSPPC

Models

BSDL

Size

Order

Availability

Name

Vendor ID

Format

txt

Rev #

MPC7447 BSDL Model

(03/13/2003)

MPC7447BSDL

FREESCALE

Bus Functional Models

Size Rev

Order

Availability

Name

Vendor ID

FREESCALE

Format

MPC7450 Bus Functional Model

(01/05/2004)

1122

MPC7450BFM

1.2

Full Functional Models

Size Rev

Order

Availability

Name

Vendor ID Format

EP100

EP201

EP300

EP433

ES100

EUREKA

PowerPC Bus Slave

PowerPC Bus Master

PowerPC Bus Arbiter

PowerPC-PCI Bridge

PowerPC System Controller

IBIS

Size Rev

Order

Name

Vendor ID Format

# Availability

MPC7447 Rev 0.2, 360BGA, 2.5v I/O, 2.5v L3 IBIS

Model

(02/10/2003)

MPC7447 Rev 0.2, 360BGA, 2.5v I/O, 1.8v L3 IBIS

Model

(02/10/2003)

FREESCALE

ibs

166

MPC7447AIBIS

MPC7447BIBIS

MPC7447CIBIS

FREESCALE

ibs

155

154

MPC7447 Rev 0.2, 360BGA, 2.5v I/O, 1.5v L3 IBIS

Model

FREESCALE

ibs

(02/10/2003)

MPC7447 Rev 0.2, 360BGA, 1.8v I/O, 2.5v L3 IBIS

Model

(02/10/2003)

MPC7447 Rev 0.2, 360BGA, 1.8v I/O, 1.8v L3 IBIS

Model

(02/10/2003)

MPC7447 Rev 0.2, 360BGA, 1.8v I/O, 1.5v L3 IBIS

Model

(02/10/2003)

MPC7447 Rev 0.2, 360BGA, 1.5v I/O, 2.5v L3 IBIS

Model

(02/10/2003)

MPC7447 Rev 0.2, 360BGA, 1.5v I/O, 1.8v L3 IBIS

Model

(02/10/2003)

MPC7447 Rev 0.2, 360BGA, 1.5v I/O, 1.5v L3 IBIS

Model

FREESCALE

161

151

149

159

148

147

MPC7447DIBIS

MPC7447EIBIS

MPC7447FIBIS

MPC7447GIBIS

MPC7447HIBIS

MPC7447IIBIS

ibs

(02/10/2003)

Timing Models

Size Rev

Order

Availability

Name

Vendor ID Format

SimG4+ Timing Model (for Linux PPC) FREESCALE

(06/25/2004)

SimG4+ Timing Model (for Linux x86) FREESCALE

(06/25/2004)

6052 0.8.1

MPC7447ALINTIME

5514 0.8.1

MPC7447ALINX86TIME

Software

Application Software

Application Development Framework

Size Rev

Order

Availability

Name

Vendor ID Format

KENATI

NPMGMT

NP Management Application Framework

Calculators

Size Rev

Order

Name

Vendor ID Format

FREESCALE

# Availability

L3 Sample Point Calculator

Spreadsheet to assist in calculating L3 sample points.

Use with AN2182. (05/01/2002)

L3SPCALC

xls 30

DINK32

Size Rev

Order

Availability

Name

Vendor ID

FREESCALE

Format

DINK32

ROM-Based Debug Monitor, R13.1.1

Board Support Packages

Name

Vendor ID

KENATI

Format

Size K Rev # Order Availability

NPLINUX

NP Linux

Device Drivers

Name

Vendor ID

KENATI

Format

Size K Rev # Order Availability

NPLINUX

NP Linux

Libraries

Vendor

Size Rev

Order

Name

Format

# Availability

KwikPeg GUI

KADAK's KwikPeg Graphical User Interface (GUI) is derived

from PEG, a professional, high-quality graphic system created

by Swell Software, Inc. to enable you, the embedded system

developer, to easily add graphics to your products.

PN311-1

KADAK

Operating Systems

Size Rev

Order

Name

Vendor ID Format

# Availability

DPP.7XXX.KRN

ENEA

OSE Real-Time Operating System

ThreadX

RTOS. Royalty-free real-time operating system (RTOS)

for embedded applications. ThreadX is small, fast, and

royalty-free making it ideal for high-volume electronic

products.

THREADX

MORPHOS

EXPRESSLOG

MorphOS

MorphOS is designed around the concept of shared

resources and the ability to build up applications using

shared system components. MorphOS is not unix based.

GENESI

AMX PPC32

AMX is a full featured RTOS for the PowerPC family.

AMX has been tested on the EST SBC8260, Embedded

Planet RPX Lite MPC823 and Motorola Ultra 603,

MBX860, MPC860 ADS and MPC860 FADS.

PX382-1

KADAK

KENATI

NPLINUX

NP Linux

Protocol Stacks

Size Rev

Order

Name

Vendor ID Format

# Availability

AnviMSTP

Avnisoft's AvniMSTP is a completely portable ANSI C

compliant implementation of the IEEE 802.1s MSTP. It is

implemented on top of, and includes the AvniPORT platform

abstraction layer to simplify integration with target platforms.

MSTP

AVNISOFT

CMX

CMX TCP/IP

PN713-1

CMX TCP/IP

KwikNet

The KwikNet TCP/IP Stack enables you to add networking

features to your products with a minimum of time and

expense. KwikNet is a compact, high performance stack built

with KADAK's characteristic simplicity, flexibility and

reliability.

KADAK

KENATI

NPSTACK

NP Network Stack

Software Tools

Code Translation

Size

Order

Availability

Name

Vendor ID

Format

Rev #

PA68K-PPC

PA86-PPC

MICROAPL

PortAsm/68K for PowerPC

PortAsm/86 for PowerPC

Compilers

Size Rev

Order

Name

Vendor ID

Format

# Availability

CodeWarrior Development Studio for PowerPC"

Processors

CWEPPC

METROWERKS

CodeWarrior Development Studio. Linux Application

Edition for PowerPC

CWLINPPC

DIAB

METROWERKS

WINDRIV

Diab C/C++ Compiler

Debuggers

Size

Order

Availability

Name

Vendor ID

Format

Rev #

POWERPC

DEBUGGER

GREENHILLS

MULTI Debugger

IDE (Integrated Development Environment)

Size

Order

Availability

Name

Vendor ID

Format

Rev #

IC-SW-OPR

WPIDE

ISYS

winIDEA

WINDRIV

WIND®POWER IDE

Return to Top

Orderable Parts Information

Part Number

Budgetary

Price

QTY

1000+

($US)

Application/

Qualification

Tier

Tape

and

Reel

Pb-Free

Terminations

Package

Description

Status

Info

Order

FCCBGA 360

25SQ*3.2P1.27

KMC7447RX1000NB

Available

FCCBGA 360

25SQ*3.2P1.27

KMC7447RX1267LB

MC7447RX1000LB

MC7447RX1000NB

COMMERCIAL Available

Available

COMMERCIAL Available

FCCBGA 360

25SQ*3.2P1.27

FCCBGA 360

25SQ*3.2P1.27

FCCBGA 360

25SQ*3.2P1.27

COMMERCIAL,

INDUSTRIAL

MC7447RX1000NBR2

MC7447RX1200LB

MC7447RX1267LB

MC7447RX600NB

MC7447RX733NB

MC7447RX867LB

MC7447RX867NB

Yes

Available

FCCBGA 360

25SQ*3.2P1.27

COMMERCIAL,

INDUSTRIAL

FCCBGA 360

25SQ*3.2P1.27

COMMERCIAL,

INDUSTRIAL

FCCBGA 360

25SQ*3.2P1.27

FCCBGA 360

25SQ*3.2P1.27

FCCBGA 360

25SQ*3.2P1.27

No Longer

Manufactured

FCCBGA 360

25SQ*3.2P1.27

Available

NOTE: Are you looking for an obsolete orderable part? Click HERE to check our distributors' inventory.

Return to Top

PPC7457RX1267LB [MOTOROLA]

相关型号：

PPC7457RX1300LB

PPC7457RX600NB

PPC7457RX733NB

PPC7457RX867LB

PPC7457RX867NB

PPC750AIM200C

PPC750AIM200D

PPC750AIM200E

PPC750AIM233C

PPC750AIM233E

PPC750AIM266D

PPC750AIM266E