SN74LS169N
更新时间：2024-09-18 02:34:44
品牌：MOTOROLA
描述：BCD DECADE/MODULO 16 BINARY SYNCHRONOUS BI-DIRECTIONAL COUNTERS
概述
规格参数
数据手册SN74LS169N 概述
BCD DECADE/MODULO 16 BINARY SYNCHRONOUS BI-DIRECTIONAL COUNTERS BCD DECADE /模数16二进制同步双向计数器 计数器
SN74LS169N 规格参数
| 生命周期： | Transferred | 零件包装代码： | DIP |
| 包装说明： | DIP, DIP16,.3 | 针数： | 16 |
| Reach Compliance Code： | unknown | HTS代码： | 8542.39.00.01 |
| 风险等级： | 5.07 | 其他特性： | TCO OUTPUT |
| 计数方向： | BIDIRECTIONAL | 系列： | LS |
| JESD-30 代码： | R-PDIP-T16 | JESD-609代码： | e0 |
| 长度： | 19.175 mm | 负载电容（CL）： | 15 pF |
| 负载/预设输入： | YES | 逻辑集成电路类型： | BINARY COUNTER |
| 最大频率@ Nom-Sup： | 25000000 Hz | 最大I（ol）： | 0.008 A |
| 工作模式： | SYNCHRONOUS | 位数： | 4 |
| 功能数量： | 1 | 端子数量： | 16 |
| 最高工作温度： | 70 °C | 最低工作温度： | |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | DIP |
| 封装等效代码： | DIP16,.3 | 封装形状： | RECTANGULAR |
| 封装形式： | IN-LINE | 电源： | 5 V |
| 最大电源电流（ICC）： | 34 mA | 传播延迟（tpd）： | 23 ns |
| 认证状态： | Not Qualified | 座面最大高度： | 4.44 mm |
| 子类别： | Counters | 最大供电电压 (Vsup)： | 5.25 V |
| 最小供电电压 (Vsup)： | 4.75 V | 标称供电电压 (Vsup)： | 5 V |
| 表面贴装： | NO | 技术： | TTL |
| 温度等级： | COMMERCIAL | 端子面层： | Tin/Lead (Sn/Pb) |
| 端子形式： | THROUGH-HOLE | 端子节距： | 2.54 mm |
| 端子位置： | DUAL | 触发器类型： | POSITIVE EDGE |
| 宽度： | 7.62 mm | 最小 fmax： | 25 MHz |
| Base Number Matches： | 1 |
SN74LS169N 数据手册
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PDF下载SN54/74LS168
SN54/74LS169
BCD DECADE/MODULO
16 BINARY SYNCHRONOUS
BI-DIRECTIONAL COUNTERS
BCD DECADE/MODULO
16 BINARY SYNCHRONOUS
BI-DIRECTIONAL COUNTERS
The SN54/74LS168 and SN54/74LS169 are fully synchronous 4-stage
up/down counters featuring a preset capability for programmable operation,
carry lookahead for easy cascading and a U/D input to control the direction
of counting. The SN54/74LS168 counts in a BCD decade (8, 4, 2, 1)
sequence, while the SN54/74LS169 operates in a Modulo 16 binary
sequence. All state changes, whether in counting or parallel loading, are
initiated by the LOW-to-HIGH transition of the clock.
LOW POWER SCHOTTKY
• Low Power Dissipation 100 mW Typical
• High-Speed Count Frequency 30 MHz Typical
• Fully Synchronous Operation
• Full Carry Lookahead for Easy Cascading
• Single Up/Down Control Input
J SUFFIX
CERAMIC
CASE 620-09
16
1
• Positive Edge-Trigger Operation
• Input Clamp Diodes Limit High-Speed Termination Effects
N SUFFIX
PLASTIC
CASE 648-08
CONNECTION DIAGRAM DIP (TOP VIEW)
16
1
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
D SUFFIX
SOIC
CASE 751B-03
16
1
ORDERING INFORMATION
SN54LSXXXJ
Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
PIN NAMES
LOADING (Note a)
HIGH
LOW
CEP
CET
CP
PE
U/D
Count Enable Parallel (Active LOW) Input
0.5 U.L.
1.0 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.25 U.L.
0.5 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
LOGIC SYMBOL
Count Enable Trickle (Active LOW) Input
Clock Pulse (Active positive going edge) Input
Parallel Enable (Active LOW) Input
Up-Down Count Control Input
Parallel Data Inputs
P –P
0
3
3
Q –Q
0
Flip-Flop Outputs
Terminal Count (Active LOW) Output
10 U.L. 5 (2.5) U.L.
10 U.L. 5 (2.5) U.L.
TC
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.
FAST AND LS TTL DATA
5-302
SN54/74LS168 • SN54/74LS169
STATE DIAGRAMS
SN54/74LS168
UP/DOWN DECADE COUNTER
SN54/74LS169
Count Up
Count Down
SN54/74LS168
UP: TC = Q
DOWN: TC = Q
SN54/74LS169
UP: TC = Q
DOWN: TC = Q
Q
Q
(U/D)
Q
Q
Q
Q
Q
Q
(U/D)
(U/D)
0
0
3
1
0
0
1
1
2
2
3
3
Q
Q
(U/D)
3
2
LOGIC DIAGRAMS
SN54/74LS168
FAST AND LS TTL DATA
5-303
SN54/74LS168 • SN54/74LS169
LOGIC DIAGRAMS (continued)
SN54/74LS169
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
V
CC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
T
A
Operating Ambient Temperature Range
54
74
–55
0
25
25
125
70
°C
I
I
Output Current — High
Output Current — Low
54, 74
–0.4
mA
mA
OH
54
74
4.0
8.0
OL
FAST AND LS TTL DATA
5-304
SN54/74LS168 • SN54/74LS169
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Min
Typ
Max
Symbol
Parameter
Input HIGH Voltage
Unit
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
V
2.0
V
IH
54
74
0.7
0.8
Guaranteed Input LOW Voltage for
All Inputs
V
V
V
Input LOW Voltage
V
IL
Input Clamp Diode Voltage
Output HIGH Voltage
–0.65
3.5
–1.5
V
V
V
V
V
= MIN, I = –18 mA
IN
IK
CC
54
74
2.5
2.7
= MIN, I
OH
= MAX, V = V
IN
CC
IH
OH
or V per Truth Table
IL
3.5
V
V
= V
CC
MIN,
= V or V
IL IH
54, 74
74
0.25
0.35
0.4
0.5
V
V
I
= 4.0 mA
= 8.0 mA
CC
IN
OL
OL
V
OL
Output LOW Voltage
I
per Truth Table
Input HIGH Current
Other Inputs
CET Input
20
40
µA
mA
mA
V
CC
V
CC
V
CC
= MAX, V = 2.7 V
IN
I
I
IH
Other Input
CET Input
0.1
0.2
= MAX, V = 7.0 V
IN
Input LOW Current
Other Input
CET Input
–0.4
–0.8
= MAX, V = 0.4 V
IN
IL
I
I
Short Circuit Current (Note 1)
Power Supply Current
–20
–100
34
mA
mA
V
V
= MAX
= MAX
OS
CC
CC
CC
Note 1: Not more than one output should be shorted at one time, nor for more than 1 second.
FUNCTIONAL DESCRIPTION
The SN54/74LS168 and SN54/74LS169 use edge-
triggered D-type flip-flops that have no constraints on
changing the control or data input signals in either state of the
Clock. The only requirement is that the various inputs attain
thedesiredstateatleastaset-uptimebeforetherisingedgeof
the clock and remain valid for the recommended hold time
thereafter.
The Terminal Count (TC) output is normally HIGH and goes
LOW, providedthatCETisLOW, whenacounterreacheszero
in the COUNT DOWN mode or reaches 15 (9 for the
SN54/74LS168)in the COUNT UP mode. The TC output state
is not a function of the Count Enable Parallel (CEP) input level.
The TC output of the SN54/74LS168 decade counter can also
be LOW in the illegal states 11, 13 and 15, which can occur
when power is turned on or via parallel loading. If illegal state
occurs, the SN54/74LS168 will return to the legitimate
sequence within two counts. Since the TC signal is derived by
decoding the flip-flop states, there exists the possibility of
decoding spikes on TC. For this reason the use of TC as a
clock signal is not recommended.
Theparallel load operation takes precedence over the other
operations, as indicated in the Mode Select Table. When PE is
LOW, the data on the P –P inputs enters the flip-flops on the
0
3
next rising edge of the Clock. In order for counting to occur,
both CEP and CET must be LOW and PE must be HIGH. The
U/D input then determines the direction of counting.
MODE SELECT TABLE
PE
CEP
CET
U/D
Action on Rising Clock Edge
L
H
H
X
L
L
X
L
L
X
H
L
Load (Pn º Qn)
Count Up (increment)
Count Down (decrement)
H
H
H
X
X
H
X
X
No Change (Hold)
No Change (Hold)
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
FAST AND LS TTL DATA
5-305
SN54/74LS168 • SN54/74LS169
AC CHARACTERISTICS (T = 25°C, V
CC
= 5.0 V)
A
Limits
Typ
Symbol
Parameter
Unit
Test Conditions
Min
Max
f
Maximum Clock Frequency
25
32
MHz
MAX
t
t
Propagation Delay,
Clock to TC
23
23
35
35
PLH
PHL
ns
ns
ns
ns
t
t
Propagation Delay,
Clock to any Q
13
15
20
23
PLH
PHL
V
C
= 5.0 V
CC
= 15 pF
L
t
t
Propagation Delay,
CET to TC
15
15
20
20
PLH
PHL
t
t
Propagation Delay,
U/D to TC
17
19
25
29
PLH
PHL
AC SETUP REQUIREMENTS (T = 25°C)
A
Limits
Typ
Symbol
Parameter
Clock Pulse Width
Unit
Test Conditions
Min
Max
t
t
25
ns
W
Setup Time,
Data or Enable
20
25
30
0
ns
ns
ns
ns
s
s
s
h
Setup Time
PE
t
t
t
V
CC
= 5.0 V
Setup Time
U/D
Hold Time
Any Input
FAST AND LS TTL DATA
5-306
SN54/74LS168 • SN54/74LS169
AC WAVEFORMS
Figure 1. Clock to Output Delays,
Count Frequency, and Clock Pulse Width
Figure 2. Count Enable Trickle Input
To Terminal Count Output Delays
•
•
•
•
•
•
Figure 3. Clock to Terminal Delays
Figure 4. Setup Time (t ) and Hold (t )
s
h
for Parallel Data Inputs
Figure 6. Up-Down Input to
Terminal Count Output Delays
The shaded areas indicate when the
input is permitted to change for
predictable output performance.
Figure 5. Setup Time and Hold Time for
Count Enable and Parallel Enable Inputs,
and Up-Down Control Inputs
FAST AND LS TTL DATA
5-307
Case 751B-03 D Suffix
16-Pin Plastic
SO-16
-A-
16
1
9
8
P
C
-B-
R X 45°
G
-T-
J
M
F
D
°
°
°
°
K
Case 648-08 N Suffix
16-Pin Plastic
-A-
16
1
9
B
S
8
F
L
C
K
-T-
M
H
J
G
D
°
°
°
°
Case 620-09 J Suffix
16-Pin Ceramic Dual In-Line
-A-
16
9
-B-
1
8
L
C
-T-
K
M
N
E
J
F
G
D
°
°
°
°
FAST AND LS TTL DATA
5-308
Motorolareserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representationorguaranteeregarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
andspecifically disclaims any and all liability, includingwithoutlimitationconsequentialorincidentaldamages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
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against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
Literature Distribution Centers:
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◊
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|
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|
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