MP28225DL-LF-Z [MPS]
Switching Regulator, Current-mode, 1600kHz Switching Freq-Max, PDSO14, 3 X 4 MM, ROHS COMPLIANT, MO-229VEED-5, QFN-14;
| 型号： | MP28225DL-LF-Z |
| 厂家： | 
MONOLITHIC POWER SYSTEMS |
| 描述： | Switching Regulator, Current-mode, 1600kHz Switching Freq-Max, PDSO14, 3 X 4 MM, ROHS COMPLIANT, MO-229VEED-5, QFN-14 光电二极管 |
| 文件： | 总11页 (文件大小：699K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MP28225
14.5V, 1A, 1.3MHz Synchronous
Step-Down Converter
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The MP28225 is an internally compensated
1.3MHz fixed frequency PWM synchronous
step-down regulator with a 2.5V to 6V bias
supply (VCC). MP28225 operates from a 3V to
14.5V input and generates an adjustable output
voltage from 0.8V to 0.9xVIN at up to 1A load
current.
•
•
•
•
•
•
•
•
•
•
•
•
•
1A Output Current
Input Supply Range: 3V to 14.5V
All Ceramic Output Capacitors Design
Up to 95% Efficiency
1.3MHz Fixed Switching Frequency
Adjustable Output from 0.8V to 0.9xVIN
Internal Soft-Start
Power Okay Pin
Frequency Synchronization Input
Thermal Shutdown
The MP28225 integrates an 80mΩ high-side
switch and an 80mΩ synchronous rectifier for
high efficiency without an external Schottky
diode. With peak current mode control and
internal compensation, it is stable with a output
ceramic capacitor and a small inductor. Fault
Cycle-by-Cycle Current Limiting
Hiccup Short Circuit Protection
14-Lead, 3mm x 4mm QFN Package
protection
includes
hiccup
short-circuit
protection, cycle-by-cycle current limiting and
thermal shutdown. Other features include
frequency synchronization and internal soft-
start.
APPLICATIONS
•
•
•
•
µP/ASIC/DSP/FPGA Core and I/O Supplies
Printers and LCD TVs
Network and Telecom Equipment
Point of Load Regulators
The MP28225 is available in a small 3mm x
4mm 14-lead QFN packages.
“MPS” and “The Future of Analog IC Technology” are Trademarks of Monolithic
Power Systems, Inc.
TYPICAL APPLICATION
Efficiency vs.
Load Current
95
85
75
65
5,10
IN
VCC
7
BS
8
4,11
14
SW
EN/SYNC
POK
FB
OFF ON
13
9
GND
1,3,12
V
=5V, V
=5V, V
=3.3V
=1.8V
IN
OUT
V
V
V
IN
IN
IN
OUT
55
45
=12V, V
=12V, V
=3.3V
OUT
=1.8V
OUT
0
250
500
750
1000
LOAD CURRENT (mA)
MP28225 Rev. 1.0
3/11/2011
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2011 MPS. All Rights Reserved.
1
MP28225 – 14.5V, 1A, 1.3MHz SYNCHRONOUS STEP-DOWN CONVERTER
ORDERING INFORMATION
Part Number*
Package
Top Marking
Free Air Temperature (TA)
QFN14 (3mm x 4mm)
MP28225DL
28225
-40°C to +85°C
* For Tape & Reel, add suffix –Z (e.g. MP28225DL–Z).
For RoHS Compliant packaging, add suffix –LF (e.g. MP28225DL–LF–Z)
PACKAGE REFERENCE
TOP VIEW
PIN 1 ID
AGND
N/C
PGND
SW
1
2
3
4
5
6
7
14 FB
13 EN/SYNC
12 PGND
11 SW
IN
10 IN
N/C
BS
POK
VCC
9
8
EXPOSED PAD
ON BACKSIDE
Thermal Resistance (4)
QFN14 (3mm x 4mm) .............48 ...... 10...°C/W
θJA
θJC
ABSOLUTE MAXIMUM RATINGS (1)
IN to GND .....................................-0.3V to +18V
SW to GND...........................-0.3V to VIN + 0.3V
.............................-2.5V to VIN + 2.5V for < 50ns
FB, EN/SYNC, VCC to GND...........-0.3V to +6.5V
BS to SW .....................................-0.3V to +6.5V
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-to-
ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation will cause excessive die temperature, and the
regulator will go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
(2)
Continuous Power Dissipation (TA = +25°C)
………………………………………………....2.6W
Junction Temperature...............................150°C
Lead Temperature ....................................260°C
Storage Temperature............... -65°C to +150°C
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
Recommended Operating Conditions (3)
Supply Voltage VIN ...........................3V to 14.5V
Bias Voltage VCC ................................2.5V to 6V
Output Voltage VOUT..................0.8V to 0.9 x VIN
Maximum Junction Temp. (TJ)............... +125°C
MP28225 Rev. 1.0
3/11/2011
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2011 MPS. All Rights Reserved.
2
MP28225 – 14.5V, 1A, 1.3MHz SYNCHRONOUS STEP-DOWN CONVERTER
ELECTRICAL CHARACTERISTICS (5)
VCC = 3.6V, VIN=12V, TA = +25°C, unless otherwise noted.
Parameters
Condition
Min
Typ
750
1
Max
Units
µA
VEN = VCC
VCC Supply Current
VCC Shutdown Current
VFB = 0.85V
VEN = 0V, VCC= 6V
µA
VCC Under Voltage Lockout
Threshold
Rising Edge
2.9
V
VCC Under Voltage Lockout
Hysteresis
IN Shutdown Current
IN Under Voltage Lockout
Threshold, Rising Edge
200
3
mV
µA
V
VEN = 0V
2.9
IN Under Voltage Lockout
Hysteresis
300
mV
TA = +25°C
-40°C ≤ TA ≤ +85°C
VFB = 0.85V
-40°C ≤ TA ≤ +85°C
-40°C ≤ TA ≤ +85°C
0.780
0.772
0.800
0.820
0.828
V
V
nA
V
Regulated FB Voltage
FB Input Current
EN High Threshold
EN Low Threshold
Internal Soft-Start Time
High-Side Switch On-Resistance
Low-Side Switch On-Resistance
SW Leakage Current
±50
1.6
0.4
10
V
120
80
80
µs
mΩ
mΩ
µA
ISW = 300mA
ISW = -300mA
VEN = 0V, VIN = 12V, VSW = 0V or 12V
-10
BS Under Voltage Lockout
Threshold
1.8
V
High-Side Switch Current Limit
Low-Side Switch Current Limit
Oscillator Frequency
Maximum Synch Frequency
Minimum Synch Frequency
Minimum On Time
Sourcing
Sinking
2.3
1.7
1
A
A
MHz
MHz
MHz
ns
1.3
2
1
50
90
150
1.6
Maximum Duty Cycle
Thermal Shutdown Threshold
%
°C
Hysteresis = 20°C
Note:
5) Production test at +25°C. Specifications over the temperature range are guaranteed by design and characterization.
MP28225 Rev. 1.0
3/11/2011
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2011 MPS. All Rights Reserved.
3
MP28225 – 14.5V, 1A, 1.3MHz SYNCHRONOUS STEP-DOWN CONVERTER
PIN FUNCTIONS
Pin #
Name
Description
Bias Supply. This supplies power to both the internal control circuit and the gate drivers. A
decoupling capacitor to ground is required close to this pin.
8
VCC
Input Supply. This supplies power to the high side switch. A decoupling capacitor to ground
is required close to this pin to reduce switching spikes.
5, 10
4, 11
IN
Switch Node Connection to the Inductor. These pins connect to the internal high and low-
side power MOSFET switches. All SW pins must be connected together externally.
SW
1, 3,
12
PGND,
AGND
Ground. Connect these pins with larger copper areas to the negative terminals of the input
and output capacitors.
Bootstrap. A capacitor between this pin and SW provides a floating supply for the high-side
gate driver.
7
BS
Feedback. This is the input to the error amplifier. An external resistive divider connected
between the output and GND is compared to the internal 0.8V reference to set the
regulation voltage.
14
FB
Enable and Frequency Synchronization Input Pin. Forcing this pin below 0.4V shuts down
13
EN/SYNC the part. Forcing this pin above 1.6V turns on the part. Applying a 1MHz to 2MHz clock
signal to this pin synchronizes the internal oscillator frequency to the external source.
9
POK
N/C
Power Okay Pin.
No Connect.
2, 6
MP28225 Rev. 1.0
3/11/2011
www.MonolithicPower.com
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© 2011 MPS. All Rights Reserved.
4
MP28225 – 14.5V, 1A, 1.3MHz SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS
VOUT = 1.8V, TA = +25ºC, unless otherwise noted.
MP28225 Rev. 1.0
3/11/2011
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2011 MPS. All Rights Reserved.
5
MP28225 – 14.5V, 1A, 1.3MHz SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VOUT = 1.8V, TA = +25ºC, unless otherwise noted.
MP28225 Rev. 1.0
3/11/2011
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2011 MPS. All Rights Reserved.
6
MP28225 – 14.5V, 1A, 1.3MHz SYNCHRONOUS STEP-DOWN CONVERTER
FUNCTIONAL BLOCK DIAGRAM
POK
VCC
UVLO
UVLO
0.88V
0.72V
IN
IN
+
- -
EN
+
- -
BS
EN/SYNC
LOGIC
EN
EN/SYNC
- -
+
EXCLK
PWM
CURRENT
LOGIC
COMPARATOR
CLK
SW
SW
OSC
SLOPE
0.5pF
17pF
1.2 MEG
SLOPE
COMPENSATION
AND PEAK
CURRENT LIMIT
COMP
--
+
+
FB
0.8V
GND
GND
SOFT
-START
Figure 1—Functional Block Diagram
MP28225 Rev. 1.0
3/11/2011
www.MonolithicPower.com
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© 2011 MPS. All Rights Reserved.
7
MP28225 – 14.5V, 1A, 1.3MHz SYNCHRONOUS STEP-DOWN CONVERTER
capacitor exceeds the sensed output voltage at the
FB pin.
FUNCTIONAL DESCRIPTION
PWM Control
Over Current Protection
The MP28225 is a constant frequency peak-current-
mode control PWM switching regulator. Refer to the
functional block diagram. The high side N-Channel
DMOS power switch turns on at the beginning of
each clock cycle. The current in the inductor
increases until the PWM current comparator trips to
turn off the high side DMOS switch. The peak
inductor current at which the current comparator
shuts off the high side power switch is controlled by
the COMP voltage at the output of feedback error
amplifier. The transconductance from the COMP
voltage to the output current is set at 11.25A/V.
The MP28225 offers cycle-to-cycle current limiting
for both high-side and low-side switches. The high-
side current limit is relatively constant regardless of
duty cycles. When the output is shorted to ground,
causing the output voltage to drop below 70% of its
nominal output, the IC is shut down momentarily and
begins discharging the soft start capacitor. It will
restart with a full soft-start when the soft- start
capacitor is fully discharged. This hiccup process is
repeated until the fault is removed.
Power Good Output
The MP28225 includes an open-drain Power Good
output that indicates whether the regulator output is
within ±10% of its nominal output. When the output
voltage moves outside this range, the POK output is
pulled to ground. There is a 30µs deglitch time when
the POK output change its state.
This current-mode control greatly simplifies the
feedback compensation design by approximating the
switching converter as a single-pole system. Only
Type II compensation network is needed, which is
integrated into the MP28225. The loop bandwidth is
adjusted by changing the upper resistor value of the
resistor divider at the FB pin. The internal
compensation in the MP28225 simplifies the
Bootstrap (BST PIN)
The gate driver for the high-side N-channel DMOS
power switch is supplied by a bootstrap capacitor
connected between the BS and SW pins. When the
low-side switch is on, the capacitor is charged
through an internal boost diode. When the high-side
switch is off and the high-side switch turns on, the
voltage on the bootstrap capacitor is boosted above
the input voltage and the internal bootstrap diode
prevents the capacitor from discharging.
compensation
design,
minimizes
external
component counts, and keeps the flexibility of
external compensation for optimal stability and
transient response.
Enable and Frequency Synchronization
(EN/SYNC PIN)
This is a dual function input pin. Forcing this pin
below 0.4V for longer than 4us shuts down the part;
forcing this pin above 1.6V for longer than 4µs turns
on the part. Applying a 1MHz to 2MHz clock signal
to this pin also synchronizes the internal oscillator
frequency to the external clock. When the external
clock is used, the part turns on after detecting the
first few clocks regardless of duty cycles. If any ON
or OFF period of the clock is longer than 4µs, the
signal will be intercepted as an enable input and
disables the synchronization.
No external bootstrap diode is required for typical
applications. For applications with low input VCC
voltage or where output voltage is very close to input
voltage, an external Schottky diode may be
connected from the VCC to BS pins to charge the
bootstrapped capacitor more strongly for increased
gate drive voltage. When using the external
bootstrap diode, a resistor at the regulator output or
a minimal load current may be required as the
bootstrapped capacitor always see the supply
voltage even when the part is disabled.
Soft-Start and Output Pre-Bias Startup
When the soft-start period starts, an internal current
source begins charging an internal soft-start
capacitor. During soft-start, the voltage on the soft-
start capacitor is connected to the non-inverting
input of the error amplifier. The soft-start period lasts
until the voltage on the soft-start capacitor exceeds
the reference voltage of 0.8V. At this point the
reference voltage takes over at the non-inverting
error amplifier input. The soft-start time is internally
set at 120µs. If the output of the MP28225 is pre-
biased to a certain voltage during startup, the IC will
disable the switching of both high-side and low-side
switches until the voltage on the internal soft-start
Input UVLO
Both VCC and IN pins have input UVLO detection.
Until both VCC and IN voltage exceed under voltage
lockout threshold, the parts remain in shutdown
condition. There are also under voltage lockout
hysesteres at both VCC and IN pins.
MP28225 Rev. 1.0
3/11/2011
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2011 MPS. All Rights Reserved.
8
MP28225 – 14.5V, 1A, 1.3MHz SYNCHRONOUS STEP-DOWN CONVERTER
Selecting the Inductor
APPLICATION INFORMATION
A 0.47µH to 1µH inductor with DC current rating at
least 25% higher than the maximum load current is
recommended for most applications. For best
efficiency, the inductor DC resistance shall be <10mΩ.
See Table 2 for recommended inductors and
manufacturers. For most designs, the inductance value
can be derived from the following equation:
Setting the Output Voltage
The external resistor divider sets the output voltage
(see Figure 1). The feedback resistor R1 also sets the
feedback loop bandwidth with the internal
compensation capacitor (see Figure 1). The relation
between R1 and feedback loop bandwidth (fC),
output capacitance (CO) is as follows:
1.24×106
fC(KHz)× CO(uF)
VOUTx(V − VOUT
)
IN
R1(KΩ) =
.
L =
V x∆ILxfOSC
IN
The feedback loop bandwidth (fC) is no higher
than 1/10th of switching frequency of MP28225. In
the case of ceramic capacitor as CO, it’s usually
set to be in the range of 50KHz and 150KHz for
optimal transient performance and good phase
margin. If electrolytic capacitor is used, the loop
bandwidth is no higher than 1/4th of the ESR zero
frequency (fESR). fESR is given by:
where ∆IL is Inductor Ripple Current. Choose inductor
ripple current approximately 30% of the maximum
load current, 1A.The maximum inductor peak current
is:
∆IL
2
IL(MAX) = ILOAD
+
1
Under light load conditions, larger inductance is
recommended for improved efficiency
fESR
=
2π×RESR× CO
For example, choose fC=70KHz with ceramic
capacitor, CO=47uF, R1 is estimated to be
400KΩ. R2 is then given by:
Input Capacitor Selection
The input capacitor reduces the surge current drawn
from the input and switching noise from the device.
The input capacitor impedance at the switching
frequency shall be less than input source impedance to
prevent high frequency switching current passing to
the input. Ceramic capacitors with X5R or X7R
dielectrics are highly recommended because of their
low ESR and small temperature coefficients. For most
applications, a 47µF capacitor is sufficient.
R1
VOUT
R2 =
−1
0.8V
Table 1—Resistor Selection vs. Output
Voltage Setting
COUT
(ceramic)
VOUT (V) R1 (kΩ) R2 (kΩ)
L (µH)
1.2
1.5
1.8
2.5
3.3
400
400
400
400
400
806
453
316
187
127
0.47µH-1µH
0.47µH-1µH
0.47µH-1µH
0.47µH-1µH
0.47µH-1µH
47µF
47µF
47µF
47µF
47µF
Table 2—Suggested Surface Mount Inductors
Max
DCR
(mꢀ)
Current
Rating
(A)
Inductance
(µH)
Dimensions
L x W x H (mm3)
Manufacturer
Part Number
Wurth Electronics
744310055
744310095
0.55
0.95
4.5
7.4
14
11
7×6.9×3
7×6.9×3
TOKO
B1015AS-1R0N
1
11
6.9
8.4×8.3×4
MP28225 Rev. 1.0
3/11/2011
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2011 MPS. All Rights Reserved.
9
MP28225 – 14.5V, 1A, 1.3MHz SYNCHRONOUS STEP-DOWN CONVERTER
Output Capacitor Selection
The output capacitor keeps output voltage ripple small
and ensures regulation loop stable. The output
capacitor impedance shall be low at the switching
frequency. Ceramic capacitors with X5R or X7R
dielectrics are recommended. If electrolytic capacitor
is used, pay attention to output ripple voltage,
extra heating, and the selection of feedback
resistor R1 (refer to “Output Voltage Setting”
section) due to large ESR of electrolytic capacitor.
The output ripple ∆VOUT is approximately:
VOUTx(V − VOUT
)
1
IN
∆VOUT
≤
x(ESR +
)
V xfOSCxL
8xfOSCxC3
IN
PC Board Layout
The high current paths (GND, IN and SW) should be
placed very close to the device with short, direct and
wide traces. Two input ceramic capacitors (2 ×
(10µF~22µF)) are recommended to be placed on
both sides of MP28225DQ and keep them as
close as possible to “IN” and “GND” pins. A RC
(see Figure1, R4=10ꢀ, C4=1µF ceramic
capacitor) low pass filter is recommended for
VCC supply. C4 must be placed as close as
possible to “VCC” pin and “GND” pin. The external
feedback resistors shall be placed next to the FB pin.
Keep the switching node SW short and away from the
feedback network. Please see EV28225 datasheet for
detailed info.
MP28225 Rev. 1.0
3/11/2011
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2011 MPS. All Rights Reserved.
10
MP28225 – 14.5V, 1A, 1.3MHz SYNCHRONOUS STEP-DOWN CONVERTER
PACKAGE INFORMATION
QFN14 (3mm x 4mm)
1.60
1.80
2.90
3.10
0.30
0.50
PIN 1 ID
SEE DETAIL A
PIN 1 ID
MARKING
1
14
0.18
0.30
3.20
3.40
3.90
4.10
PIN 1 ID
INDEX AREA
0.50
BSC
7
8
TOP VIEW
BOTTOM VIEW
PIN 1 ID OPTION A
0.30x45º TYP.
PIN 1 ID OPTION B
R0.20 TYP.
0.80
1.00
0.20 REF
0.00
0.05
SIDE VIEW
DETAIL A
2.90
1.70
NOTE:
0.70
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETER MAX.
4) DRAWING CONFORMS TO JEDEC MO-229, VARIATION VEED-5.
5) DRAWING IS NOT TO SCALE.
0.25
3.30
0.50
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP28225 Rev. 1.0
3/11/2011
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2011 MPS. All Rights Reserved.
11
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