MP8758GL [MPS]
High Efficiency, 10A, 18V Synchronous, Step-Down Converter;
| 型号： | MP8758GL |
| 厂家： | 
MONOLITHIC POWER SYSTEMS |
| 描述： | High Efficiency, 10A, 18V Synchronous, Step-Down Converter |
| 文件： | 总21页 (文件大小：867K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MP8758
High Efficiency, 10A, 18V
Synchronous, Step-Down Converter
The Future of Analog IC Technology
DESCRIPTION
The MP8758 is
frequency, synchronous, rectified, step-down
converter. It offers a very compact solution to
achieve a 10A output current over a wide input-
supply range with excellent load and line
regulation.
FEATURES
•
•
•
•
Wide 5V to 18V Operating Input Range
10A Continuous Output Current
Low RDS(ON) Internal Power MOSFETs
Proprietary Switching Loss Reduction
Technique
a
fully-integrated, high
•
•
•
•
•
•
Internal Soft Start
Output Discharge
500kHz Switching Frequency
OCP, OVP, UVP and Thermal Shutdown
Latch off Reset via EN or Power Cycle
Output Adjustable from 0.604V to 5.5V
MP8758 employs the Constant-On-Time (COT)
control scheme, which provides fast transient
response, eases loop stabilization. The COT
control scheme provides seamless transition to
PFM mode at light load operation which boosts
the light load efficiency.
APPLICATIONS
Under voltage lockout is internally set as 4.5V.
An open drain power good signal indicates
output voltage is within its nominal voltage
range.
•
•
•
•
•
•
Tablet PC
Networking Systems
Set-Top Box and Multi-Function Printer
Personal Video Recorders
Flat Panel Television and Monitors
Distributed Power Systems
Full protection features include OCP, OVP, and
thermal shutdown.
MP8758 requires minimum number of external
components and are available in QFN21
(3mmx4mm) package.
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Products, Quality Assurance page.
“MPS” and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
MP8758 Rev. 1.0
1/13/2015
www.MonolithicPower.com
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© 2015 MPS. All Rights Reserved.
1
MP8758–18V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER
ORDERING INFORMATION
Part Number
Package
Top Marking
MP8758GL
QFN-21 (3mmx4mm)
See Below
* For Tape & Reel, add suffix –Z (e.g. MP8758GL-Z)
TOP MARKING
MP: MPS prefix;
Y: year code;
W: week code:
8758: first four digits of the part number;
LLL: lot number;
PACKAGE REFERENCE
TOP VIEW
PG
13
NC
18
EN
VCC GND FB
17
16
15
14
BST
1
2
3
VIN
12
19
VIN
SW
SW
20
21
PGND
PGND
PGND
PGND
11
10
9
4
5
6
7
8
NC VOUT VOUT NC AGND NC
EXPOSED PAD
ON BACKSIDE
MP8758 Rev. 1.0
1/13/2015
www.MonolithicPower.com
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© 2015 MPS. All Rights Reserved.
2
MP8758–18V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER
Thermal Resistance (5)
QFN-21 (3mmx4mm)..............50 ......12 ...°C/W
θJA θJC
ABSOLUTE MAXIMUM RATINGS (1)
Supply Voltage VIN .......................................24V
VSW ............................................. -0.3V to 24.3V
VSW (30ns) ........................................ -3V to 28V
VSW (5ns) .......................................... -6V to 28V
VBST ..................................................VSW + 5.5V
VEN ..............................................................12V
Enable Current IEN (2)................................ 2.5mA
All Other Pins............................. –0.3V to +5.5V
Notes:
1) Exceeding these ratings may damage the device.
2) Refer to Page 13 of Configuring the EN Control.
3) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-to-
ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD(MAX)=(TJ(MAX)-
TA)/θJA. Exceeding the maximum allowable power dissipation
will cause excessive die temperature, and the regulator will go
into thermal shutdown. Internal thermal shutdown circuitry
protects the device from permanent damage.
(3)
Continuous Power Dissipation (TA=+25°C)
QFN21 .....................................................2.5W
Junction Temperature..............................150°C
Lead Temperature ...................................260°C
Storage Temperature...............-65°C to +150°C
4) The device is not guaranteed to function outside of its
operating conditions.
5) Measured on JESD51-7, 4-layer PCB.
Recommended Operating Conditions (4)
Supply Voltage VIN ............................. 5V to 18V
Output Voltage VOUT................... 0.604V to 5.5V
Enable Current IEN ......................................1mA
Operating Junction Temp. (TJ). -40°C to +125°C
MP8758 Rev. 1.0
1/13/2015
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© 2015 MPS. All Rights Reserved.
3
MP8758–18V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER
ELECTRICAL CHARACTERISTICS
VIN = 12V, TJ = 25°C, unless otherwise noted.
Parameters
Symbol Condition
Min
Typ
Max
Units
Supply Current
Supply Current (Shutdown)
ISD
IQ
V
EN = 0V
EN = 2V,
0
1
μA
μA
V
Supply Current (Quiescent)
160
190
220
VFB = 0.65V
MOSFET
High-side Switch On Resistance
HSRDS-ON
25
mΩ
TJ =25°C
Low-side Switch On Resistance
LSRDS-ON
SWLKG
9
0
mΩ
μA
TJ =25°C
Switch Leakage
VEN = 0V, VSW = 0V
1
Current Limit
Low-side Valley Current Limit
ILIMIT
10
11
12
A
Switching frequency and minimum off time
Switching frequency
Minimum Off Time(6)
FSW
400
250
500
300
600
350
kHz
ns
TOFF
Over-voltage and Under-voltage Protection
OVP Threshold
OVP Delay
VOVP
TOVPDEL
VUVP
125
55
130
2.5
60
135
65
%VREF
μs
UVP Threshold
UVP Delay
%VREF
μs
TUVPDEL
12
Reference And Soft Start
Reference Voltage
Feedback Current
Soft Start Time
VREF
IFB
598
604
10
610
50
mV
nA
VFB = 0.604V
TSS
1.6
1.95
ms
Enable And UVLO
Enable Input Low Voltage
Enable Hysteresis
VILEN
1.15
1.25
100
3
1.35
4.85
V
VEN-HYS
mV
V
EN = 2V
Enable Input Current
IEN
μA
VEN = 0V
0
VCC Under Voltage Lockout
Threshold Rising
VCCVth
4.5
V
VCC Under Voltage Lockout
Threshold Hysteresis
VCCHYS
500
mV
MP8758 Rev. 1.0
1/13/2015
www.MonolithicPower.com
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© 2015 MPS. All Rights Reserved.
4
MP8758–18V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER
ELECTRICAL CHARACTERISTICS (continued)
VIN = 12V, TJ = 25°C, unless otherwise noted.
Parameters
Symbol
Condition
Min
Typ
Max
Units
VCC Regulator
VCC Regulator
VCC
4.8
5.1
5
5.3
V
VCC Load Regulation
Icc=8mA
%
Power Good
FB Rising (Good)
FB Falling (Fault)
FB Rising (Fault)
FB Falling (Good)
PGVth-Hi
PGVth-Lo
PGVth-Hi
PGVth-Lo
95
85
%VREF
115
105
450
Power Good Low to High Delay
PGTd
VPG
μs
V
Power Good Sink Current
Capability
Sink 4mA
0.4
1
Power Good Leakage Current
IPG LEAK
VPG = 3.3V
μA
Thermal Protection
Thermal Shutdown(6)
TSD
150
25
°C
°C
Thermal Shutdown Hysteresis
Note:
6) Guaranteed by design.
MP8758 Rev. 1.0
1/13/2015
www.MonolithicPower.com
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5
MP8758–18V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER
PIN FUNCTIONS
PIN #
Name
Description
Bootstrap. A capacitor connected between SW and BST pins is required to form a
floating supply across the high-side switch driver.
1
BST
Switch Output. Connect this pin to the inductor and bootstrap capacitor. This pin is
driven up to the VIN voltage by the high-side switch during the on-time of the PWM
duty cycle. The inductor current drives the SW pin negative during the off-time. The on-
resistance of the low-side switch and the internal diode fixes the negative voltage. Use
wide and short PCB traces to make the connection. Try to minimize the area of the SW
pattern.
2, 3
SW
4
5, 6
7
NC
VOUT
NC
Not Connected.
Buck regulator output voltage sense. Connect this pin to the output capacitor of the
regulator directly
Not Connected.
Analog ground. The internal reference is referred to AGND. Connect the GND of the
FB divider resistor to AGND for better load regulation.
8
AGND
NC
9
Not Connected.
10,11
Exposed
Pad 20,21
PGND
VIN
Power Ground. Use wide PCB traces and multiple vias to make the connection.
12
Exposed
Pad 19
Supply Voltage. The VIN pin supplies power for internal MOSFET and regulator. The
MP8758 operates from a +5V to +18V input rail. An input capacitor is needed to
decouple the input rail. Use wide PCB traces and multiple vias to make the connection.
Power good output, the output of this pin is an open drain signal and is high if the
output voltage is higher than 95% of the nominal voltage. There is a delay from FB ≥
95% to PG goes high.
13
PG
Feedback. An external resistor divider from the output to GND, tapped to the FB pin,
sets the output voltage. Place the resistor divider as close to FB pin as possible. Avoid
vias on the FB traces.
14
15
FB
Ground pin. This pin needs to be connected to either PGND or AGND for normal
operation.
GND
Internal 5V LDO output. The driver and control circuits are powered from this voltage.
Decouple with a minimum 1µF ceramic capacitor as close to the pin as possible. X7R
or X5R grade dielectric ceramic capacitors are recommended for their stable
temperature characteristics.
16
VCC
Enable. EN is a digital input, which are used to enable or disable the regulators. Once
17
18
EN
NC
EN=1, the regulator output will be turned on; when EN=0, the regulator will be turned
off.
Not connected.
MP8758 Rev. 1.0
1/13/2015
www.MonolithicPower.com
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© 2015 MPS. All Rights Reserved.
6
MP8758–18V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS
VIN =12V, VOUT =5V, L=2µH, TJ=+25°C, unless otherwise noted.
MP8758 Rev. 1.0
1/13/2015
www.MonolithicPower.com
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© 2015 MPS. All Rights Reserved.
7
MP8758–18V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN =12V, VOUT =5V, L=2µH, TJ=+25°C, unless otherwise noted.
MP8758 Rev. 1.0
1/13/2015
www.MonolithicPower.com
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© 2015 MPS. All Rights Reserved.
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MP8758–18V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN =12V, VOUT =5V, L=2µH, TJ=+25°C, unless otherwise noted.
MP8758 Rev. 1.0
1/13/2015
www.MonolithicPower.com
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© 2015 MPS. All Rights Reserved.
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MP8758–18V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER
FUNCTIONAL BLOCK DIAGRAM
VCC
VOUT
VIN
BSTREG
BST
VIN
Soft-
start
POR&
Reference
0.6V VREF
On Time
One Shot
FB
EN
Gate
SW
Min off time
Control
Logic
VOUT
PGND
PG
SW
OCP
POK
OVP
%Vref
130% Vref
Fault
Logic
95
AGND
UVP
60%Vref
Figure 1—Functional Block Diagram
MP8758 Rev. 1.0
1/13/2015
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MP8758–18V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER
OPERATION
PWM Operation
continuous-conduction-mode (CCM). The CCM
operation is shown in Figure 2. When VFB is
The MP8758 is fully integrated synchronous
rectified step-down switch mode converter.
Constant-on-time (COT) control is employed to
provide fast transient response and easy loop
stabilization. At the beginning of each cycle, the
high-side MOSFET (HS-FET) is turned ON when
the feedback voltage (VFB) is below the reference
voltage (VREF), which indicates insufficient output
voltage. The ON period is determined by both the
output voltage and input voltage to make the
switching frequency fairy constant over input
voltage range.
below VREF, HS-MOSFET is turned on for a fixed
interval which is determined by one- shot on-
timer. The one shot timer is controlled by input
and output voltage so that the switching
frequency could be fairly fixed at 500kHz for
different input/output conditions. When the HS-
MOSFET is turned off, the LS-MOSFET is turned
on until next period.
In CCM mode operation, the switching frequency
is fairly constant and it is called PWM mode.
Light-Load Operation
After the ON period elapses, the HS-FET is
turned off, or becomes OFF state. It is turned ON
again when VFB drops below VREF. By repeating
operation this way, the converter regulates the
output voltage. The integrated low-side MOSFET
(LS-FET) is turned on when the HS-FET is in its
OFF state to minimize the conduction loss. There
will be a dead short between input and GND if
both HS-FET and LS-FET are turned on at the
same time. It’s called shoot-through. In order to
avoid shoot-through, a dead-time (DT) is
internally generated between HS-FET off and LS-
FET on, or LS-FET off and HS-FET on.
With the load decreases, the inductor current
decreases too. Once the inductor current touches
zero, the operation is transition from continuous-
conduction-mode (CCM) to discontinuous-
conduction-mode (DCM).
The light load operation is shown in Figure 3.
When VFB is below VREF, HS-MOSFET is turned
on for a fixed interval. When the HS-MOSFET is
turned off, the LS-MOSFET is turned on until the
inductor current reaches zero. In DCM operation,
the VFB does not reach VREF when the inductor
current is approaching zero. The LS-FET driver
turns into tri-state (high Z) whenever the inductor
current reaches zero. As a result, the efficiency
at light load condition is greatly improved. At light
load condition, the HS-FET is not turned ON as
frequently as at heavy load condition. This is
called skip mode.
An internal compensation is applied for COT
control to make a more stable operation even
when ceramic capacitors are used as output
capacitors, this internal compensation will then
improve the jitter performance without affect the
line or load regulation.
At light load or no load condition, the output
drops very slowly and the MP8758 reduces the
switching frequency naturally and then high
efficiency is achieved at light load.
Heavy-Load Operation
Figure 2—Heavy Load Operation
Figure 3—Light Load Operation
When the output current is high and the inductor
current is always above zero amps, it is called
MP8758 Rev. 1.0
1/13/2015
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11
MP8758–18V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER
As the output current increases from the light
resistor. Ceramic capacitors usually can not be
used as output capacitor.
load condition, the time period within which the
current modulator regulates becomes shorter.
The HS-FET is turned ON more frequently.
Hence, the switching frequency increases
correspondingly. The output current reaches the
critical level when the current modulator time is
zero. The critical level of the output current is
determined as follows:
To realize the stability, the ESR value should be
chosen as follow:
TSW
TON
2
+
0.7× π
(2)
RESR
≥
COUT
TSW is the switching period.
(V − VOUT )× VOUT
IN
(1)
The MP8758 has built in internal ramp
compensation to make sure the system is stable
even without the help of output capacitor’s ESR;
and thus the pure ceramic capacitor solution can
be applicant. The pure ceramic capacitor solution
can significantly reduce the output ripple, total
BOM cost and the board area.
IOUT
=
2×L×F × V
S
IN
It turns into PWM mode once the output current
exceeds the critical level. After that, the switching
frequency stays fairly constant over the output
current range.
Jitter and FB Ramp Slope
Figure 6 shows a typical output circuit in PWM
mode without an external ramp circuit. Turn to
application information section for design steps
without external compensation.
Jitter occurs in both PWM and skip modes when
noise in the VFB ripple propagates a delay to the
HS-FET driver, as shown in Figures 4 and 5.
Jitter can affect system stability, with noise
immunity proportional to the steepness of VFB’s
downward slope. However, VFB ripple does not
directly affect noise immunity.
SW
L
Vo
C4
R1
R2
VS L OPE1
FB
VNOISE
CAP
VF B
VR E F
HS Driver
Figure 6—Simplified Circuit in PWM Mode without
External Ramp Compensation
J itter
When using a large-ESR capacitor on the output,
add a ceramic capacitor with a value of 10uF or
less to in parallel to minimize the effect of ESL.
Figure 4—Jitter in PWM Mode
VS L OP E 2
VNOISE
VFB
Operating with external ramp compensation
VREF
The MP8758 is usually able to support ceramic
output capacitors without external ramp, however,
in some of the cases, the internal ramp may not
be enough to stabilize the system, and external
ramp compensation is needed. Skip to
application information section for design steps
with external ramp compensation.
HS Driver
Jitter
Figure 5—Jitter in Skip Mode
Operating without external ramp
The traditional constant-on-time control scheme
is intrinsically unstable if output capacitor’s ESR
is not large enough as an effective current-sense
MP8758 Rev. 1.0
1/13/2015
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12
MP8758–18V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER
L
Vo
SW
Vo
C4
R4
ESR
R1
R1
R2
IR4
IC4
FB
R9
IFB
Ro
Ceramic
Cout
R2
FB
Figure 8—Simplified Circuit in skip Mode
Figure 7—Simplified Circuit in PWM Mode with
External Ramp Compensation
The downward slope of the VFB ripple in skip
mode can be determined as follow:
Figure 7 shows a simplified external ramp
compensation (R4 and C4) for PWM mode.
Chose R1, R2, R9 and C4 of the external ramp to
meet the following condition:
−VREF
(8)
VSLOPE2
=
( R +R //Ro)×C
(
)
1
2
OUT
Where Ro is the equivalent load resistor.
⎛
⎜
⎝
⎞
⎟
⎠
R1 ×R2
R1 + R2
1
1
5
<
×
+ R9
(3)
As described in Figure 5, VSLOPE2 in the skip mode
is lower than that is in the PWM mode, so it is
reasonable that the jitter in the skip mode is
larger. If one wants a system with less jitter
during light load condition, the values of the VFB
resistors should not be too big, however, that will
decrease the light load efficiency.
2π×FSW × C4
Where:
IR4 = IC4 +IFB ≈ IC4
(4)
And the Vramp on the VFB can then be estimated
as:
EN Control
V − VOUT
R4 ×C4
R1 //R2
IN
The regulator turns on when EN goes high.
Conversely it turns off when EN goes low.
(5)
VRAMP
=
×TON ×
R1 //R2 +R9
The downward slope of the VFB ripple then
follows
For automatic start-up the EN pin can be pulled
up to input voltage through a resistive voltage
divider. Choose the values of the pull-up resistor
(RUP from Vin pin to EN pin) and the pull-down
resistor (RDOWN from EN pin to GND) to
determine the automatic start-up voltage:
−VRAMP
−VOUT
R4 ×C4
(6)
VSLOPE1
=
=
T
off
As can be seen from equation (6), if there is
instability in PWM mode, we can reduce either
R4 or C4. If C4 can not be reduced further due to
limitation from equation (3), then we can only
reduce R4. For a stable PWM operation, the
Vslope1 should be design follow equation (7).
RUP + R
(9)
V
= 1.25×
DOWN (V)
IN−START
RDOWN
For example, for RUP=150kΩ and RDOWN=51kΩ,
the V is set at 4.93V.
IN−START
TSW
T
+
ON -RESRCOUT
Io×10-3
TSW -Ton
To avoid noise, a 10nF ceramic capacitor from
EN to GND is recommended.
0.7×π
2
(7)
-Vslope1
≥
VOUT +
2×L×COUT
There is an internal Zener diode on the EN pin,
which clamps the EN pin voltage to prevent it
from running away. The maximum pull up current
assuming a worst case 12V internal Zener clamp
should be less than 1mA.
Io is the load current.
In skip mode, the downward slope of the VFB
ripple is the same whether the external ramp is
used or not. Figure 8 shows the simplified circuit
of the skip mode when both the HS-FET and LS-
FET are off.
MP8758 Rev. 1.0
1/13/2015
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13
MP8758–18V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER
Therefore, when EN is driven by an external logic
When the FB voltage drops to 85% of REF
voltage, the PGOOD pin will be pulled low.
signal, the EN voltage should be lower than
12V.when EN is connected with VIN through a
pull-up resistor or a resistive voltage divider, the
resistance selection should ensure the maximum
pull up current less than 1mA.
Over Current Protection
MP8758 has cycle-by-cycle over current limiting
control. The current-limit circuit employs a
"valley" current-sensing algorithm. The part use
the Rds(on) of the low side MOSFET as a
current-sensing element. If the magnitude of the
current-sense signal is above the current-limit
threshold, the PWM is not allowed to initiate a
new cycle.
If using a resistive voltage divider and VIN higher
than 12V, the allowed minimum pull-up resistor
RUP should meet the following equation:
V (V)−12
RUP(kΩ)
12
IN
(10)
−
< 1(m A )
RDOWN(kΩ)
The trip level is fixed internally. The inductor
current is monitored by the voltage between GND
Especially, just using the pull-up resistor RUP (the
pull-down resistor is not connected), the V
IN-START
pin and SW pin. GND is used as the positive
current sensing node so that GND should be
connected to the source terminal of the bottom
MOSFET.
is determined by input UVLO, and the minimum
resistor value is:
V (V)−12
IN
(11)
RUP (kΩ) >
1( m A )
Since the comparison is done during the high
side MOSFET OFF and low side MOSFET ON
state, the OC trip level sets the valley level of the
inductor current. Thus, the load current at over-
current threshold, IOC, can be calculated as
follows:
A typical pull-up resistor is 499kꢀ.
Soft Start
The MP8758 employs soft start (SS) mechanism
to ensure smooth output during power-up. When
the EN pin becomes high, the internal reference
voltage ramps up gradually; hence, the output
voltage ramps up smoothly, as well. Once the
reference voltage reaches the target value, the
soft start finishes and it enters into steady state
operation.
ΔI
inductor
IOC = I_limit +
(12)
2
In an over-current condition, the current to the
load exceeds the current to the output capacitor;
thus the output voltage tends to fall off.
Eventually, it will end up with crossing the under
voltage protection threshold and shutdown. And
fault latching can be reset by EN going low or
Power-cycling of VIN.
If the output is pre-biased to a certain voltage
during startup, the IC will disable the switching of
both high-side and low-side switches until the
voltage on the internal reference exceeds the
sensed output voltage at the FB node.
Over/Under-Voltage Protection (OVP/UVP)
MP8758 monitors a resistor divided feedback
voltage to detect over and under voltage. When
the feedback voltage becomes higher than 115%
of the target voltage, the controller will enter
Dynamic Regulation Period. During this period,
the LS will off when the LS current goes to -1A,
this will then discharge the output and try to keep
it within the normal range. If the dynamic
regulation can not limit the increasing of the Vo,
once the feedback voltage becomes higher than
130% of the feedback voltage, the OVP
comparator output goes high and the circuit
latches as the high-side MOSFET driver off
Power Good (PG)
The MP8758 has power-good (PGOOD) output
used to indicate whether the output voltage of the
regulator is ready or not. The PGOOD pin is the
open drain of a MOSFET. It should be connected
to VCC or other voltage source through a resistor
(e.g. 100k,). After the input voltage is applied, the
MOSFET is turned on so that the PGOOD pin is
pulled to GND before SS is ready. After FB
voltage reaches 95% of REF voltage, the
PGOOD pin is pulled high after a delay. The
PGOOD delay time is 0.45ms.
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MP8758–18V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER
and the low-side MOSFET turn on acting as an -
1A current source.
MP8758 discharges the output when EN=low, or
the controller is turned off by the protection
functions (UVP & OCP, OCP, OVP, UVLO, and
thermal shutdown). The part discharges the
output using an internal 6ꢀ MOSFET.
When the feedback voltage becomes lower than
60% of the target voltage, the UVP comparator
output goes high if the UV still occurs after 26us
delay; then the fault latch will be triggered---
latches HS off and LS on; the LS FET keeps on
until the inductor current goes zero. Also fault
latching can be reset by EN going low or Power-
cycling of VIN.
UVLO Protection
The MP8758 has under-voltage lock-out
protection (UVLO). When the VCC voltage is
higher than the UVLO rising threshold voltage,
the part will be powered up. It shuts off when the
VCC voltage is lower than the UVLO falling
threshold voltage. This is non-latch protection. If
an application requires a higher under-voltage
lockout (UVLO), use the EN pin as shown in
Figure 9 to adjust the input voltage UVLO by
using two external resistors. It is recommended
to use the enable resistors to set the UVLO
falling threshold (VSTOP) above 4.5V. The rising
threshold (VSTART) should be set to provide
enough hysteresis to allow for any input supply
variations.
MP8758
IN
RUP
EN Comparator
EN
RDOWN
Figure 9—Adjustable UVLO
Thermal Shutdown
Thermal shutdown is employed in the MP8758.
The junction temperature of the IC is internally
monitored. If the junction temperature exceeds
the threshold value (typical 150ºC), the converter
shuts off. This is a non-latch protection. There is
about 25ºC hysteresis. Once the junction
temperature drops to about 125ºC, it initiates a
SS.
Output Discharge
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MP8758–18V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER
APPLICATION INFORMATION
Setting the Output Voltage---without external
compensation
Setting the Output Voltage ―with external
compensation
SW
The MP8758 can usually support different type of
output capacitors, including POSCAP, electrolytic
capacitor and also ceramic capacitors without
external ramp compensation. The output voltage
is then set by feedback resistors R1 and R2. As
Figure 10 shows.
L
Vo
R4
R1
R2
FB
C4
R9
Ceramic
SW
L
Vo
Figure11—Simplified Circuit of Ceramic Capacitor
If the system is not stable enough when low ESR
ceramic capacitor is used in the output, an
external voltage ramp should be added to FB
through resistor R4 and capacitor C4.
C4
R1
R2
FB
CAP
The output voltage is influenced by ramp voltage
VRAMP besides R divider as shown in Figure 11.
The VRAMP can be calculated as shown in
equation (5). R2 should be chosen reasonably, a
small R2 will lead to considerable quiescent
current loss while too large R2 makes the FB
noise sensitive. It is recommended to choose a
Figure10—Simplified Circuit of POS Capacitor
First, choose a value for R2. R2 should be
chosen reasonably, a small R2 will lead to
considerable quiescent current loss while too
large R2 makes the FB noise sensitive. Typically,
set the current through R2 at around 5-10uA will
make a good balance between system stability
and also the no load loss. Then R1 is determined
as follow with the output ripple considered:
1
value within 5kꢀ-50kꢀ for R2, using
a
comparatively larger R2 when Vo is low, etc.,
1.05V, and a smaller R2 when Vo is high. And
the value of R1 then is determined as follow:
R2
(14)
R1=
VOUT
−
ΔVOUT − VREF
V
R2
FB(AVG)
2
-
(13)
R1 =
⋅R2
(VOUT -VFB(AVG) ) R4+R9
VREF
The VFB(AVG) is the average value on the FB,
VFB(AVG) varies with the Vin, Vo, and load
condition, etc., its value on the skip mode would
be lower than that of the PWM mode, which
means the load regulation is strictly related to the
ΔVOUT is the output ripple, refer to equation (23).
Other than feedback resistors, a feed forward
cap C4 is usually applied for a better transient
performance, especially when ceramic caps are
applied for their small capacitance, a cap value
around 100pF-1nF is suggested for a better
transient while also keep the system stable with
enough noise immunity. In case the system is
noise sensitive because of the zero induced by
this cap, add a resistor-usually named as R9
between this cap and FB to form a pole, this
resistor can be set according to equation (16) as
in the following section.
VFB(AVG). Also the line regulation is related to the
VFB(AVG). If one wants to gets a better load or line
regulation, a lower Vramp is suggested, as long
as the criterion shown in equation (7) can be met.
For PWM operation, VFB(AVG) value can be
deduced from the equation below.
1
R1 //R2
V
= VREF + V
×
(15)
FB(AVG)
RAMP
2
R1 //R2 +R9
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MP8758–18V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER
Usually, R9 is set to 0ꢀ, and it can also be set
X7R ceramic dielectrics are recommended
because they are fairly stable with temperature
fluctuations.
following equation (16) for a better noise
immunity. It should also set to be 5 times smaller
than R1//R2 to minimize its influence on Vramp.
The capacitors must also have a ripple current
rating greater than the maximum input ripple
current of the converter. The input ripple current
can be estimated as follows:
1
R9 =
(16)
2π×C4 ×2F
SW
Using equation (14) to calculate the R1 can be
complicated. To simplify the calculation, a DC-
blocking capacitor Cdc can be added to filter the
DC influence from R4 and R9. Figure 12 shows
VOUT
VOUT
(18)
ICIN = IOUT
×
×(1−
)
V
V
IN
IN
a
simplified circuit with external ramp
The worst-case condition occurs at VIN = 2VOUT
where:
,
compensation and a DC-blocking capacitor. With
this capacitor, R1 can easily be obtained by
using the simplified equation for PWM mode
operation:
IOUT
ICIN
=
(19)
2
1
For simplification, choose the input capacitor with
an RMS current rating greater than half of the
maximum load current.
(VOUT − VREF − VRAMP
)
2
R1 =
R2
(17)
1
VREF + VRAMP
The input capacitance value determines the input
voltage ripple of the converter. If there is an input
voltage ripple requirement in the system, choose
the input capacitor that meets the specification.
2
Cdc is suggested to be at least 10 times larger
than C4 for better DC blocking performance, and
should also not larger than 0.47uF considering
start up performance. In case one wants to use
larger Cdc for a better FB noise immunity,
combined with reduced R1 and R2 to limit the
Cdc in a reasonable value without affecting the
system start up. Be noted that even when the
Cdc is applied, the load and line regulation are
still Vramp related.
The input voltage ripple can be estimated as
follows:
IOUT
SW ×CIN
VOUT
VOUT
ΔV =
×
×(1−
)
(20)
IN
F
V
V
IN
IN
Under worst-case conditions where VIN = 2VOUT
:
SW
L
Vo
IOUT
4 FSW ×CIN
1
ΔV =
×
(21)
IN
FB
R4
R1
R2
C4
Output Capacitor
Cdc
Ceramic
The output capacitor is required to maintain the
DC output voltage. Ceramic or POSCAP
capacitors are recommended. The output voltage
ripple can be estimated as:
Figure12—Simplified Circuit of Ceramic Capacitor
with DC blocking capacitor
VOUT
V
1
(22)
)
ΔVOUT
=
×(1− OUT )×(RESR
+
FSW ×L
V
8×FSW ×COUT
Input Capacitor
IN
The input current to the step-down converter is
discontinuous and therefore requires a capacitor
to supply the AC current to the step-down
converter while maintaining the DC input voltage.
Ceramic capacitors are recommended for best
performance and should be placed as close to
the VIN pin as possible. Capacitors with X5R and
In the case of ceramic capacitors, the impedance
at the switching frequency is dominated by the
capacitance. The output voltage ripple is mainly
caused by the capacitance. For simplification, the
output voltage ripple can be estimated as:
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MP8758–18V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER
VOUT
VOUT
VOUT
SW × ΔIL
VOUT
(26)
(23)
L =
×(1−
)
ΔVOUT
=
×(1−
)
8×F 2 ×L×COUT
V
F
V
IN
SW
IN
Where ΔIL is the peak-to-peak inductor ripple
current.
The output voltage ripple caused by ESR is very
small. Therefore, an external ramp is needed to
stabilize the system. The external ramp can be
generated through resistor R4 and capacitor C4.
The inductor should not saturate under the
maximum inductor peak current, where the peak
inductor current can be calculated by:
In the case of POSCAP capacitors, the ESR
dominates the impedance at the switching
frequency. The ramp voltage generated from the
ESR is high enough to stabilize the system.
Therefore, an external ramp is not needed. A
minimum ESR value around 12mꢀ is required to
ensure stable operation of the converter. For
simplification, the output ripple can be
approximated as:
VOUT
VOUT
(27)
ILP = IOUT
+
×(1−
)
2FSW ×L
V
IN
PCB Layout Guide
1. The high current paths (PGND, IN, and SW)
should be placed very close to the device
with short, direct and wide traces.
2. Put the input capacitors as close to the IN
and PGND pins as possible.
VOUT
V
ΔVOUT
=
×(1− OUT )×RESR
(24)
3. Put the decoupling capacitor as close to the
VCC and AGND pins as possible. Place the
Cap close to VCC if the distance is long. And
place >3 Vias if via is required to reduce the
leakage inductance.
FSW ×L
V
IN
Maximum output capacitor limitation should be
also considered in design application. MP8758
has an around 1.6ms soft-start time period. If the
output capacitor value is too large, the output
voltage can’t reach the design value during the
soft-start time, and then it will fail to regulate. The
maximum output capacitor value Co_max can be
limited approximately by:
4. Keep the switching node SW short and away
from the feedback network.
5. The external feedback resistors should be
placed next to the FB pin. Make sure that
there is no via on the FB trace.
CO _MAX = (ILIM_ AVG −IOUT )× Tss / VOUT
(25)
6. Keep the BST voltage path as short as
possible.
Where, ILIM_AVG is the average start-up current
during soft-start period. Tss is the soft-start time.
7. Keep the IN and PGND pads connected with
large copper and use at least two layers for
IN and PGND trace to achieve better thermal
performance. Also, add several Vias with
10mil_drill/18mil_copper_width close to the
IN and PGND pads to help on thermal
dissipation.
Inductor
The inductor is necessary to supply constant
current to the output load while being driven by
the switched input voltage. A larger-value
inductor will result in less ripple current that will
result in lower output ripple voltage. However, a
larger-value inductor will have a larger physical
footprint, higher series resistance, and/or lower
saturation current. A good rule for determining
the inductance value is to design the peak-to-
peak ripple current in the inductor to be in the
range of 30% to 40% of the maximum output
current, and that the peak inductor current is
below the maximum switch current limit. The
inductance value can be calculated by:
8. Four-layer layout is strongly recommended to
achieve better thermal performance.
Note:
Please refer to the PCB Layout Application Note
for more details.
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MP8758–18V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER
Figure 13—Recommend Layout
Recommend Design Example
The detailed application schematic is shown in
Some design examples are provided below when
the ceramic capacitors are applied:
Figure 14 and Figure 15 for 1.35V and 5V
applications when low ESR caps are applied.
The typical performance and circuit waveforms
have been shown in the Typical Performance
Characteristics section. For more possible
applications of this device, please refer to related
Evaluation Board Data Sheets.
Table 2—Design Example
VOUT
(V)
Cout
(F)
L
(μH)
R4
(Ω)
C4
(F)
R1
(kΩ)
R2
(kΩ)
1.05
1.2
1.35
3.3
5
22μx3
22μx3
22μx3
22ux4
22ux4
1.2
1.2
1.2
2
NS
NS
NS
1M
1M
220p
220p
220p
220p
220p
59
82
102
82
100
100
88.7
150
18
2
18
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MP8758–18V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER
TYPICAL APPLICATION
Figure 14 — Typical Application Circuit with Low ESR Ceramic Output Capacitor
VIN=5-18V, VOUT=1.35V
Figure 15 — Typical Application Circuit with Low ESR Ceramic Output Capacitor
VIN=7-18V, VOUT=5V
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MP8758–18V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER
PACKAGE INFORMATION
QFN21 (3mmX4mm)
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
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