MX25L6436EM2I-10 [Macronix]
Flash, 16MX4, PDSO8, 0.200 INCH, ROHS COMPLIANT, SOP-8;
| 型号： | MX25L6436EM2I-10 |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | Flash, 16MX4, PDSO8, 0.200 INCH, ROHS COMPLIANT, SOP-8 时钟 光电二极管 内存集成电路 |
| 文件： | 总68页 (文件大小：3231K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MX25L6436E
MX25L12836E
MX25L6436E/MX25L12836E
HIGH PERFORMANCE
SERIAL FLASH SPECIFICATION
P/N: PM1514
REV. 1.1, NOV. 18, 2009
1
MX25L6436E
MX25L12836E
Contents
FEATURES ..................................................................................................................................................................5
GENERAL DESCRIPTION .........................................................................................................................................7
Table 1. Additional Features ..............................................................................................................................7
PIN CONFIGURATION ................................................................................................................................................8
PIN DESCRIPTION......................................................................................................................................................8
BLOCK DIAGRAM.......................................................................................................................................................9
DATA PROTECTION..................................................................................................................................................10
Table 2. Protected Area Sizes.......................................................................................................................... 11
Table 3. 4K-bit Secured OTP Definition............................................................................................................ 11
Memory Organization...............................................................................................................................................12
Table 4-1. Memory Organization for MX25L6436E.........................................................................................12
Table 4-2. Memory Organization for MX25L12836E.......................................................................................13
DEVICE OPERATION................................................................................................................................................14
Figure 1. Serial Modes Supported (for Normal Serial mode)........................................................................... 14
COMMAND DESCRIPTION.......................................................................................................................................15
Table 5. Command Sets...................................................................................................................................15
(1) Write Enable (WREN).................................................................................................................................17
(2) Write Disable (WRDI)..................................................................................................................................17
(3) Read Identification (RDID)..........................................................................................................................17
(4) Read Status Register (RDSR)....................................................................................................................18
(5) Write Status Register (WRSR)....................................................................................................................19
Protection Modes .............................................................................................................................................19
(6) Read Data Bytes (READ) ...........................................................................................................................20
(7) Read Data Bytes at Higher Speed (FAST_READ) .....................................................................................20
(8) Dual Read Mode (DREAD).........................................................................................................................20
(9) Quad Read Mode (QREAD) .......................................................................................................................20
(10) Sector Erase (SE).....................................................................................................................................21
(11) Block Erase (BE).......................................................................................................................................21
(12) Block Erase (BE32K)................................................................................................................................21
(13) Chip Erase (CE)........................................................................................................................................22
(14) Page Program (PP)...................................................................................................................................22
(15) 4 x I/O Page Program (4PP).....................................................................................................................23
Program/Erase Flow(1) with read array data ...................................................................................................24
Program/Erase Flow(2) without read array data ..............................................................................................25
(16) Continuously program mode (CP mode) ..................................................................................................26
(17) Parallel Mode (Highly recommended for production throughputs increasing).......................................... 26
(18) Deep Power-down (DP)............................................................................................................................27
(19) Release from Deep Power-down (RDP), Read Electronic Signature (RES) ............................................ 27
(20) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4) .......................................... 27
Table 6. ID Definitions .....................................................................................................................................28
(21) Enter Secured OTP (ENSO).....................................................................................................................28
(22) Exit Secured OTP (EXSO)........................................................................................................................28
(23) Read Security Register (RDSCUR) ..........................................................................................................28
P/N: PM1514
REV. 1.1, NOV. 18, 2009
2
MX25L6436E
MX25L12836E
Security Register Definition..............................................................................................................................29
(24) Write Security Register (WRSCUR)..........................................................................................................29
(25) Write Protection Selection (WPSEL).........................................................................................................30
BP and SRWD if WPSEL=0 .............................................................................................................................30
The individual block lock mode is effective after setting WPSEL=1................................................................. 31
WPSEL Flow ....................................................................................................................................................32
(26) Single Block Lock/Unlock Protection (SBLK/SBULK)............................................................................... 33
Block Lock Flow ...............................................................................................................................................33
Block Unlock Flow............................................................................................................................................34
(27) Read Block Lock Status (RDBLOCK).......................................................................................................35
(28) Gang Block Lock/Unlock (GBLK/GBULK).................................................................................................35
(29) Clear SR Fail Flags (CLSR)......................................................................................................................35
(30) Enable SO to Output RY/BY# (ESRY)......................................................................................................35
(31) Disable SO to Output RY/BY# (DSRY).....................................................................................................35
(32) Read DMC mode (RDDMC) .....................................................................................................................36
Discoverable Memory Capabilities (DMC) Signature and Parameter Identification Data Values (Advanced
Information)......................................................................................................................................................36
Parameter ID (0) (Advanced Information).......................................................................................................37
Parameter ID (1) (Advanced Information)........................................................................................................38
Parameter ID (2) (Advanced Information)........................................................................................................38
POWER-ON STATE...................................................................................................................................................39
ELECTRICAL SPECIFICATIONS..............................................................................................................................40
ABSOLUTE MAXIMUM RATINGS...................................................................................................................40
Figure 2. Maximum Negative Overshoot Waveform ........................................................................................40
CAPACITANCE TA = 25°C, f = 1.0 MHz...........................................................................................................40
Figure 3. Maximum Positive Overshoot Waveform..........................................................................................40
Figure 4. OUTPUT LOADING .........................................................................................................................41
Table 7-1. MX25L6436E DC CHARACTERISTICS .........................................................................................42
Table 7-2. MX25L12836E DC CHARACTERISTICS .......................................................................................43
Table 8-1. MX25L6436E AC CHARACTERISTICS ........................................................................................44
Table 8-2. MX25L12836E AC CHARACTERISTICS ......................................................................................45
Timing Analysis........................................................................................................................................................47
Figure 5. Serial Input Timing ............................................................................................................................47
Figure 6. Output Timing....................................................................................................................................47
Figure 7. WP# Setup Timing and Hold Timing during WRSR when SRWD=1................................................. 48
Figure 8. Write Enable (WREN) Sequence (Command 06)............................................................................. 48
Figure 9. Write Disable (WRDI) Sequence (Command 04).............................................................................. 48
Figure 10. Read Identification (RDID) Sequence (Command 9F).................................................................... 49
Figure 11. Read Status Register (RDSR) Sequence (Command 05) .............................................................. 49
Figure 12. Write Status Register (WRSR) Sequence (Command 01)............................................................. 49
Figure 13. Read Data Bytes (READ) Sequence (Command 03) .................................................................... 50
Figure 14. Read at Higher Speed (FAST_READ) Sequence (Command 0B) ................................................ 50
Figure 15. Dual Read Mode Sequence (Command 3B)...................................................................................50
Figure 16. Quad Read Mode Sequence (Command 6B).................................................................................51
Figure 17. Sector Erase (SE) Sequence (Command 20)................................................................................51
Figure 18. Block Erase (BE/EB32K) Sequence (Command D8/52)................................................................ 51
P/N: PM1514
REV. 1.1, NOV. 18, 2009
3
MX25L6436E
MX25L12836E
Figure 19. Chip Erase (CE) Sequence (Command 60 or C7)......................................................................... 52
Figure 20. Page Program (PP) Sequence (Command 02).............................................................................. 52
Figure 21. 4 x I/O Page Program (4PP) Sequence (Command 38)................................................................ 52
Figure 22. Continuously Program (CP) Mode Sequence with Hardware Detection (Command AD)............... 53
Figure 23-1. Enter Parallel Mode (ENPLM) Sequence (Command 55) .......................................................... 54
Figure 23-2. Exit Parallel Mode (EXPLM) Sequence (Command 45)............................................................. 54
Figure 23-3. Parallel Mode Read Identification (Parallel RDID) Sequence (Command 9F) ........................... 54
Figure 23-4. Parallel Mode Read Electronic Manufacturer & Device ID (Parallel REMS) Sequence (Command
90)....................................................................................................................................................................55
Figure 23-5. Parallel Mode Release from Deep Power-down (RDP) and Read Electronic Signature (RES)
Sequence.........................................................................................................................................................55
Figure 23-6. Parallel Mode Read Array (Parallel READ) Sequence (Command 03) ...................................... 56
Figure 23-7. Parallel Mode Page Program (Parallel PP) Sequence (Command 02) ...................................... 56
Figure 24. Deep Power-down (DP) Sequence (Command B9)....................................................................... 56
Figure 25. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB)
.........................................................................................................................................................................57
Figure 26. Release from Deep Power-down (RDP) Sequence (Command AB) .............................................57
Figure 27. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF or CF)..
.........................................................................................................................................................................58
Figure 28. Write Protection Selection (WPSEL) Sequence (Command 68).................................................... 58
Figure 29. Single Block Lock/Unlock Protection (SBLK/SBULK) Sequence (Command 36/39)..................... 59
Figure 30. Read Block Protection Lock Status (RDBLOCK) Sequence (Command 3C)................................ 59
Figure 31. Gang Block Lock/Unlock (GBLK/GBULK) Sequence (Command 7E/98)...................................... 59
Figure 32. Power-up Timing.............................................................................................................................60
Table 9. Power-Up Timing ...............................................................................................................................60
INITIAL DELIVERY STATE...............................................................................................................................60
RECOMMENDED OPERATING CONDITIONS.........................................................................................................61
ERASE AND PROGRAMMING PERFORMANCE....................................................................................................62
DATA RETENTION ....................................................................................................................................................62
LATCH-UP CHARACTERISTICS..............................................................................................................................62
ORDERING INFORMATION......................................................................................................................................63
PART NAME DESCRIPTION.....................................................................................................................................64
PACKAGE INFORMATION........................................................................................................................................65
REVISION HISTORY .................................................................................................................................................67
P/N: PM1514
REV. 1.1, NOV. 18, 2009
4
MX25L6436E
MX25L12836E
64/128M-BIT [x 1/x 2/x 4] CMOS MXSMIOTM (SERIAL MULTI I/O) FLASH MEMORY
FEATURES
GENERAL
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
• 64Mb: 67,108,864 x 1 bit structure or 33,554,432 x 2 bits (2 x I/O mode) structure or 16,777,216 x 4 bits (4 x I/O
mode) structure
128Mb: 134,217,728 x 1 bit structure or 67,108,864 x 2 bits (2 x I/O mode) structure or 33,554,432 x 4 bits (4 x I/
O mode) structure
• 2048 Equal Sectors with 4K bytes each (64Mb)
4096 Equal Sectors with 4K bytes each (128Mb)
- Any Sector can be erased individually
• 256 Equal Blocks with 32K bytes each (64Mb)
512 Equal Blocks with 32K bytes each (128Mb)
- Any Block can be erased individually
• 128 Equal Blocks with 64K bytes each (64Mb)
256 Equal Blocks with 64K bytes each (128Mb)
- Any Block can be erased individually
• Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
VCC = 2.7~3.6V
- Normal read
- 50MHz
- Fast read (Normal Serial Mode)
- 1 x I/O: 104MHz with 8 dummy cycles
- 2 x I/O: 70MHz with 8 dummy cycles
- 4 x I/O: 70MHz with 8 dummy cycles
- Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)
- Byte program time: 9us (typical)
- Continuously Program mode (automatically increase address under word program mode)
- Fast erase time: 60ms (typ.)/sector (4K-byte per sector) ; 0.7s(typ.) /block (64K-byte per block); 50s(typ.) /chip
for 64Mb, 80s(typ.) /chip for 128Mb
• Low Power Consumption
- Low active read current: 45mA(max.) at 104MHz and 30mA(max.) at 33MHz
- Low active programming current: 25mA (max.)
- Low active erase current: 25mA (max.)
- Low standby current: 100uA (max.)
- Deep power down current: 128Mb is 40uA (max.), 64Mb is 30uA (max.)
• Typical 100,000 erase/program cycles
• 20 years data retention
P/N: PM1514
REV. 1.1, NOV. 18, 2009
5
MX25L6436E
MX25L12836E
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- BP0-BP3 block group protect
- Flexible individual block protect when OTP WPSEL=1
- Additional 4K bits secured OTP for unique identifier
• Auto Erase and Auto Program Algorithms
Automatically erases and verifies data at selected sector
-
-
Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse width (Any page to be programed should have page in the erased state first.)
• Status Register Feature
• Electronic Identification
JEDEC 1-byte Manufacturer ID and 2-byte Device ID
- RES command for 1-byte Device ID
-
- Both REMS, REMS2 and REMS4 commands for 1-byte Manufacturer ID and 1-byte Device ID
• Support Discoverable Memory Capabilities (DMC) Signature
HARDWARE FEATURES
• SCLK Input
Serial clock input
• SI/SO0
-
Serial Data Input or Serial Data Multiple Output for 2 x I/O mode and 4 x I/O mode
• SO/SO1/PO7
-
Serial Data Output or Serial Data Multiple Output for 2 x I/O mode and 4 x I/O mode or Parallel Data
• WP#/SO2
-
Hardware write protection or serial data Multiple Output for 4 x I/O mode
• NC/SO3
-
NC pin or serial data Multiple Output for 4 x I/O mode
• PO0~PO6
-
For parallel mode data (only 128Mb provide parallel mode)
• PACKAGE
-
16-pin SOP (300mil) only for MX25L12836E
-
-
8-pin SOP (200mil) only for MX25L6436E
- All Pb-free devices are RoHS Compliant
P/N: PM1514
REV. 1.1, NOV. 18, 2009
6
MX25L6436E
MX25L12836E
GENERAL DESCRIPTION
MX25L6436E is 67,108,864 bits serial Flash memory, which is configured as 8,388,608 x 8 internally. When it is
in 2 x I/O or 4 x I/O mode, the structure becomes 33,554,432 bits x 2 or 16,777,216 bits x 4. MX25L12836E is
134,217,728 bits serial Flash memory, which is configured as 16,777,216 x 8 internally. When it is in two or 4 x I/O
mode, the structure becomes 67,108,864 bits x 2 or 33,554,432 bits x 4. The MX25L6436E/12836E features a se-
rial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are
a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled
by CS# input.
MX25L6436E/12836E provides high performance read mode, which may latch address and data on both rising and
falling edge of clock. By using this high performance read mode, the data throughput may be doubling. Moreover,
the performance may reach direct code execution, the RAM size of the system may be reduced and further saving
system cost.
MX25L6436E/12836E, MXSMIOTM (Serial Multi I/O) flash memory, provides sequential read operation on whole
chip and multi-I/O features.
When it is in dual I/O mode, the SI/SO0 pin is for address/dummy bits input and data output, and the SO pin be-
come SO1 pin for data output. When it is in quad I/O mode, the SI/SO0 pin is for address/dummy bits input and data
output, and the SO pin, WP# pin, NC pin become SO1 pin, SO2 pin and SO3 pin for data output. Parallel mode is
also provided in this device. It features 8 bit input/output for increasing throughputs. This feature is recommended to
be used for factory production purpose.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the speci-
fied page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis, or word basis for Continuously Program mode, and erase command is executes on sector (4K-byte),
block (32K-byte/64K-byte), or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
When the device is not in operation and CS# is high, it is put in standby mode and draws less than 100uA DC cur-
rent.
The MX25L6436E/12836E utilizes Macronix's proprietary memory cell, which reliably stores memory contents even
after 100,000 program and erase cycles.
Table 1. Additional Features
Additional
Features
Protection and Security
Read Performance
1 I/O Read (104 Dual Read (70 Quad Read
Flexible or
Individual block (or
sector) protection
8 I/O Parallel
Mode
4K-bit
Part
secured OTP
MHz)
MHz)
(70 MHz)
Name
(6 MHz)
MX25L6436E
MX25L12836E
V
V
V
V
V
V
(Note 1)
Additional
Features
Identifier
RES
REMS
REMS2
REMS4
RDID
Part
Name
(command: AB hex) (command: 90 hex) (command: EF hex) (command: DF hex) (command: 9F hex)
MX25L6436E
MX25L12836E
16 (hex)
17 (hex)
C2 16 (hex)
C2 17 (hex)
C2 16 (hex)
C2 17 (hex)
C2 16 (hex)
C2 17 (hex)
C2 20 17 (hex)
C2 20 18 (hex)
Note 1: Only MX25L12836E provide parallel mode.
P/N: PM1514
REV. 1.1, NOV. 18, 2009
7
MX25L6436E
MX25L12836E
PIN CONFIGURATION
16-PIN SOP (300mil) for MX25L12836E
8-PIN SOP (200mil) for MX25L6436E
1
2
3
4
5
6
7
8
SCLK
SI/SO0
PO6
NC/SO3
VCC
16
15
14
13
12
11
10
9
1
2
3
4
CS#
SO/SO1
WP#/SO2
GND
VCC
8
7
6
5
NC/SO3
SCLK
NC
PO5
PO2
PO4
PO1
SI/SO0
PO3
PO0
GND
CS#
WP#/SO2
SO/SO1/PO7
PIN DESCRIPTION
SYMBOL
DESCRIPTION
CS#
Chip Select
Serial Data Input / Serial Data Multiple
Output (for 2 x I/O or 4 x I/O mode)
Serial Data Output (for 1 x I/O) /Serial
Data Multiple Output (for 2 x I/O or 4 x I/
O mode) / Parallel Data Output/Input
Clock Input
SI/SO0
SO/SO1/
PO7
SCLK
Write protection: connect to GND or
WP#/SO2 Serial Data Multiple Output (for 4 x I/O
mode)
NC pin (Not connect) or Serial Data
Multiple Output (for 4 x I/O mode)
NC/SO3
VCC
GND
+ 3.3V Power Supply
Ground
Parallel data output/input (PO0~PO6 can
PO0~PO6 be connected to NC in Serial Mode), NC
on MX25L6436E
NC
No Connection
P/N: PM1514
REV. 1.1, NOV. 18, 2009
8
MX25L6436E
MX25L12836E
BLOCK DIAGRAM
Address
Generator
Memory Array
Page Buffer
Y-Decoder
Data
Register
SI/SO0
SRAM
Buffer
Sense
Amplifier
CS#
WP#/SO2
NC/SO3
Mode
Logic
State
Machine
HV
Generator
SCLK
Clock Generator
Output
Buffer
SO/SO1
P/N: PM1514
REV. 1.1, NOV. 18, 2009
9
MX25L6436E
MX25L12836E
DATA PROTECTION
MX25L6436E/12836E is designed to offer protection against accidental erasure or programming caused by spuri-
ous system level signals that may exist during power transition. During power up the device automatically resets
the state machine in the standby mode. In addition, with its control register architecture, alteration of the memory
contents only occurs after successful completion of specific command sequences. The device also incorporates
several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or sys-
tem noise.
• Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
other command to change data. The WEL bit will return to reset stage under following situation:
- Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP, 4PP) command completion
- Continuously Program mode (CP) instruction completion
- Sector Erase (SE) command completion
- Block Erase (BE, BE32K) command completion
- Chip Erase (CE) command completion
- Single Block Lock/Unlock (SBLK/SBULK) instruction completion
- Gang Block Lock/Unlock (GBLK/GBULK) instruction completion
•
Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from
writing all commands except Release from Deep Power Down mode command (RDP) and Read Electronic Sig-
nature command (RES).
I. Block lock protection
- The Software Protected Mode (SPM) uses (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected
as read only. The protected area definition is shown as table of "Protected Area Sizes", the protected areas are
more flexible which may protect various area by setting value of BP0-BP3 bits. Please refer to table of "Protect-
ed Area Sizes".
- The Hardware Protected Mode (HPM) use WP#/SO2 to protect the (BP3, BP2, BP1, BP0) bits and SRWD bit.
If the system goes into 4 x I/O mode, the feature of HPM will be disabled.
- MX25L6436E/12836E provide individual block (or sector) write protect & unprotect. User may enter the mode
with WPSEL command and conduct individual block (or sector) write protect with SBLK instruction, or SBULK
for individual block (or sector) unprotect. Under the mode, user may conduct whole chip (all blocks) protect with
GBLK instruction and unlock the whole chip with GBULK instruction.
P/N: PM1514
REV. 1.1, NOV. 18, 2009
10
MX25L6436E
MX25L12836E
Table 2. Protected Area Sizes
Status bit
Protection Area
BP3 BP2 BP1 BP0 64Mb
128Mb
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0 (none)
0 (none)
1 (2 blocks, block 126th-127th)
2 (4 blocks, block 124th-127th)
3 (8 blocks, block 120th-127th)
4 (16 blocks, block 112nd-127th)
5 (32 blocks, block 96th-127th)
6 (64 blocks, block 64th-127th)
7 (128 blocks, all)
1 (2 blocks, block 254th-255th)
2 (4 blocks, block 252nd-255th)
3 (8 blocks, block 248th-255th)
4 (16 blocks, block 240th-255th)
5 (32 blocks, block 224th-255th)
6 (64 blocks, block 192nd-255th)
7 (128 blocks, block 128th-255th)
8 (256 blocks, all)
8 (128 blocks, all)
9 (128 blocks, all)
9 (256 blocks, all)
10 (128 blocks, all)
10 (256 blocks, all)
11 (128 blocks, all)
11 (256 blocks, all)
12 (128 blocks, all)
12 (256 blocks, all)
13 (128 blocks, all)
13 (256 blocks, all)
14 (128 blocks, all)
14 (256 blocks, all)
15 (128 blocks, all)
15 (256 blocks, all)
Note: The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP3, BP2, BP1, BP0) are 0.
II. Additional 4K-bit secured OTP for unique identifier: to provide 4K-bit One-Time Program area for setting de-
vice unique serial number - Which may be set by factory or system maker. Please refer to Table 3. 4K-bit Se-
cured OTP Definition.
- Security register bit 0 indicates whether the chip is locked by factory or not.
- To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with ENSO command), and going
through normal program procedure, and then exiting 4K-bit secured OTP mode by writing EXSO command.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR (write security register)
command to set customer lock-down bit1 as "1". Please refer to table of "Security Register Definition" for secu-
rity register bit definition and table of "4K-bit Secured OTP Definition" for address range definition.
- Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit Se-
cured OTP mode, array access is not allowed.
Table 3. 4K-bit Secured OTP Definition
Address range
xxx000~xxx00F
xxx010~xxx1FF
Size
Standard Factory Lock
ESN (electrical serial number)
N/A
Customer Lock
128-bit
3968-bit
Determined by customer
P/N: PM1514
REV. 1.1, NOV. 18, 2009
11
MX25L6436E
MX25L12836E
Memory Organization
Table 4-1. Memory Organization for MX25L6436E
Block(64K-byte) Block(32K-byte) Sector (4K-byte)
Address Range
2047
7FF000h
7FFFFFh
255
individual 16 sectors
lock/unlock unit:4K-byte
2040
2039
7F8000h
7F7000h
7F8FFFh
7F7FFFh
127
254
253
252
251
250
2032
2031
7F0000h
7EF000h
7F0FFFh
7EFFFFh
2024
2023
7E8000h
7E7000h
7E8FFFh
7E7FFFh
126
individual block
lock/unlock unit:64K-byte
2016
2015
7E0000h
7DF000h
7E0FFFh
7DFFFFh
2008
2007
7D8000h
7D7000h
7D8FFFh
7D7FFFh
125
2000
7D0000h
7D0FFFh
individual block
lock/unlock unit:64K-byte
47
02F000h
02FFFFh
5
4
3
2
1
0
40
39
028000h
027000h
028FFFh
027FFFh
2
1
individual block
lock/unlock unit:64K-byte
32
31
020000h
01F000h
020FFFh
01FFFFh
24
23
018000h
017000h
018FFFh
017FFFh
16
15
010000h
00F000h
010FFFh
00FFFFh
8
7
008000h
007000h
008FFFh
007FFFh
individual 16 sectors
lock/unlock unit:4K-byte
0
0
000000h
000FFFh
P/N: PM1514
REV. 1.1, NOV. 18, 2009
12
MX25L6436E
MX25L12836E
Table 4-2. Memory Organization for MX25L12836E
Block(64K-byte) Block(32K-byte)
Sector
4095
Address Range
FFF000h
FFFFFFh
511
individual 16 sectors
lock/unlock unit:4K-byte
4088
4087
FF8000h
FF7000h
FF8FFFh
FF7FFFh
255
510
4080
4079
FF0000h
FEF000h
FF0FFFh
FEFFFFh
509
4072
4071
FE8000h
FE7000h
FE8FFFh
FE7FFFh
254
508
individual block
lock/unlock unit:64K-byte
4064
4063
FE0000h
FDF000h
FE0FFFh
FDFFFFh
507
4056
4055
FD8000h
FD7000h
FD8FFFh
FD7FFFh
253
506
4048
FD0000h
FD0FFFh
individual block
lock/unlock unit:64K-byte
47
02F000h
02FFFFh
5
40
39
028000h
027000h
028FFFh
027FFFh
2
4
individual block
32
31
020000h
01F000h
020FFFh
01FFFFh
lock/unlock unit:64K-byte
3
24
23
018000h
017000h
018FFFh
017FFFh
1
2
16
15
010000h
00F000h
010FFFh
00FFFFh
1
individual 16 sectors
lock/unlock unit:4K-byte
8
7
008000h
007000h
008FFFh
007FFFh
0
0
0
000000h
000FFFh
P/N: PM1514
REV. 1.1, NOV. 18, 2009
13
MX25L6436E
MX25L12836E
DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended op-
eration.
2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode
until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z.
3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until
next CS# rising edge.
4. For standard single data rate serial mode, input data is latched on the rising edge of Serial Clock (SCLK) and
data shifts out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as Figure 1-1.
5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, DREAD, QREAD, RDBLOCK, RES,
REMS, REMS2, REMS4 and RDDMC the shifted-in instruction sequence is followed by a data-out sequence.
After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR,
SE, BE, BE32K, CE, PP, CP, 4PP, RDP, DP, WPSEL, SBLK, SBULK, GBLK, GBULK, ENSO, EXSO, WRSCUR,
ENPLM, EXPLM, ESRY, DSRY and CLSR the CS# must go high exactly at the byte boundary; otherwise, the in-
struction will be rejected and not executed.
6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglect-
ed and not affect the current operation of Write Status Register, Program, Erase.
Figure 1. Serial Modes Supported (for Normal Serial mode)
CPOL CPHA
shift in
shift out
SCLK
SCLK
(Serial mode 0)
(Serial mode 3)
0
1
0
1
SI
MSB
SO
MSB
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is
supported.
P/N: PM1514
REV. 1.1, NOV. 18, 2009
14
MX25L6436E
MX25L12836E
COMMAND DESCRIPTION
Table 5. Command Sets
RDSR
WRSR
FAST READ
(fast read
data)
COMMAND WREN (write WRDI (write RDID (read
READ
(read data)
DREAD
(1I 2O read)
(read status (write status
(byte)
enable)
disable)
identification)
register)
05
register)
01
Command
(hex)
06
04
9F
03
0B
ADD(24)
8
3B
ADD(24)
8
Input
Data(8)
ADD(24)
Cycles
Dummy
Cycles
sets the
(WEL) write (WEL) write
resets the
outputs
JEDEC
to read out to write new n bytes read n bytes read n bytes read
the values values to out until CS# out until CS# out by Dual
enable latch enable latch ID: 1-byte of the status the status
goes high
goes high
output until
CS# goes
high
bit
bit
Manufacturer
ID & 2-byte
Device ID
register
register
Action
CP
(Continuously
program
mode)
4PP
(quad page
program)
SE
(sector
erase)
PP
(Page
program)
COMMAND
(byte)
QREAD
(1I 4O read)
BE (block BE 32K (block
erase 64KB) erase 32KB) (chip erase)
CE
Command
(hex)
6B
ADD(24)
8
38
20
D8
52
60 or C7
02
AD
Input
ADD(6)+
Data(512)
ADD(24)+
Data(2048)
ADD(24)+
Data(16)
ADD(24)
ADD(24)
ADD(24)
Cycles
Dummy
Cycles
n bytes read quad input to erase the to erase the to erase the
to erase
to program continously
out by Quad to program
output until the selected
selected
sector
selected
64KB block 32KB block
selected
whole chip the selected
page
program
whole
Action
CS# goes
high
page
chip, the
address is
automatically
increase
RDP
(Release
REMS (read
electronic
REMS2 (read REMS4 (read ENSO (enter EXSO (exit
COMMAND DP (Deep
RES (read
ID for 2x I/O ID for 4x I/O
secured
OTP)
secured
OTP)
(byte)
power down) from deep electronic ID) manufacturer
mode)
mode)
power down)
& device ID)
Command
(hex)
B9
AB
AB
90
EF
DF
B1
C1
Input
ADD(24)
ADD(24)
ADD(24)
Cycles
Dummy
Cycles
24
enters deep release from to read out
output the
output the
output the
to enter
the 4K-bit
to exit the 4K-
bit Secured
power down deep power 1-byte Device Manufacturer Manufacturer Manufact-
mode down mode ID ID & Device ID & Device
ID ID
urer ID & Secured OTP OTP mode
device ID mode
Action
P/N: PM1514
REV. 1.1, NOV. 18, 2009
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MX25L6436E
MX25L12836E
ESRY
DSRY
ENPLM
(Enter
Parallel
Mode)
EXPLM (EXIT
Parallel
RDSCUR
(read security (write security
WRSCUR
CLSR (Clear WPSEL (write
COMMAND
(byte)
(enable SO (disable SO
to output RY/ to output RY/
SR Fail
Flags)
protection
selection)
register)
2B
register)
2F
Mode)
BY#)
BY#)
Command
(hex)
70
80
55
45
30
68
Input
Cycles
Dummy
Cycles
to read value to set the to enable SO to disable SO 8xI/O parallel to exit 8xI/ clear security
to enter
of security lock-down bit to output RY/ to output RY/ program-
register bit 6 and enable
O parallel
program-
ming mode
register
as "1" (once BY# during BY# during ming mode
and bit 5
individal
block protect
mode
lock-down,
cannot be
updated)
CP mode
CP mode
Action
SBLK (single
block lock) (single block (block protect
SBULK
RDBLOCK
RDDMC
(Read
DMC)
COMMAND
(byte)
GBLK (gang GBULK (gang
block lock) block unlock)
*Note 2
unlock)
read)
Command
(hex)
36
39
3C
7E
98
5A
ADD(24)
8
Input
ADD(24)
individual
ADD(24)
individual
ADD(24)
Cycles
Dummy
Cycles
Action
read
individual
block or
whole chip
write protect
whole
chip
unprotect
Read DMC
mode
block (64K- block (64K-
byte) or
sector (4K-
byte) write
protect
byte) or
sector
(4K-byte) protect status
unprotect
sector write
Note 1: It is not recommended to adopt any other code not in the command definition table, which will potentially
enter the hidden mode.
Note 2: In individual block write protection mode, all blocks/sectors is locked as defualt.
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MX25L6436E
MX25L12836E
(1) Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP,
CP, SE, BE, BE32K, CE, WRSR, SBLK, SBULK, GBLK and GBULK, which are intended to change the device con-
tent, should be set every time after the WREN instruction setting the WEL bit.
The sequence of issuing WREN instruction is: CS# goes low→ sending WREN instruction code→ CS# goes high.
(Please refer to Figure 8)
(2) Write Disable (WRDI)
The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.
The sequence of issuing WRDI instruction is: CS# goes low→ sending WRDI instruction code→ CS# goes high. (Please
refer to Figure 9)
The WEL bit is reset by following situations:
- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP, 4PP) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase (BE, BE32K) instruction completion
- Chip Erase (CE) instruction completion
- Continuously Program mode (CP) instruction completion
- Single Block Lock/Unlock (SBLK/SBULK) instruction completion
- Gang Block Lock/Unlock (GBLK/GBULK) instruction completion
(3) Read Identification (RDID)
The RDID instruction is for reading the Manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC
Manufacturer ID is C2(hex), the memory type ID is 20(hex) as the first-byte Device ID, and the individual Device ID
of second-byte ID are listed as table of "ID Definitions". (Please refer to Table 6)
The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code → 24-bits ID data out
on SO→ to end RDID operation can use CS# to high at any time during data out. (Please refer to Figure 10)
While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cy-
cle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.
P/N: PM1514
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MX25L6436E
MX25L12836E
(4) Read Status Register (RDSR)
The RDSR instruction is for reading Status Register. The Read Status Register can be read at any time (even in
program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP)
bit before sending a new instruction when a program, erase, or write status register operation is in progress.
The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register
data out on SO (Please refer to Figure 11).
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write
status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status
register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status
register cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable
latch. When WEL bit sets to "1", which means the internal write enable latch is set, the device can accept program/
erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the de-
vice will not accept program/erase/write status register instruction. The program/erase command will be ignored and
will reset WEL bit if it is applied to a protected memory area.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area (as
defined in Table 2) of the device to against the program/erase instruction without hardware protection mode being
set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to
be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE),
Block Erase (BE) and Chip Erase (CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be
executed).
QE bit. The Quad Enable (QE) bit, non-volatile bit, while it is "0" (factory default), it performs non-Quad and WP# is
enable. While QE is "1", it performs Quad I/O mode and WP# is disabled. In the other word, if the system goes into
4 x I/O mode (QE=1), the feature of HPM will be disabled.
SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, default value is "0". SRWD bit is operat-
ed together with Write Protection (WP#/SO2) pin for providing hardware protection mode. The hardware protection
mode requires SRWD sets to 1 and WP#/SO2 pin signal is low stage. In the hardware protection mode, the Write
Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP3,
BP2, BP1, BP0) are read only.
Status Register
bit7
bit6
bit5
BP3
(level of
protected
block)
bit4
BP2
(level of
protected
block)
bit3
BP1
(level of
protected
block)
bit2
BP0
(level of
protected
block)
bit1
bit0
SRWD (status
register write
protect)
QE
(Quad
Enable)
WEL
(write enable
latch)
WIP
(write in
progress bit)
1= Quad
Enable
0=not Quad
Enable
1=write
enable
0=not write 0=not in write
1=write
operation
1=status
register write
disable
(note 1)
(note 1)
(note 1)
(note 1)
enable
operation
Non-volatile Non-volatile Non-volatile Non-volatile Non-volatile Non-volatile
bit bit bit bit bit bit
volatile bit
volatile bit
Note 1: see the Table 2 "Protected Area Size" in page 11.
P/N: PM1514
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MX25L6436E
MX25L12836E
(5) Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the
Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in ad-
vance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1, BP0) bits to define the pro-
tected area of memory (as shown in Table 2). The WRSR also can set or reset the Quad enable (QE) bit and set or
reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#/SO2) pin signal, but
has no effect on bit1(WEL) and bit0 (WIP) of the status register. The WRSR instruction cannot be executed once the
Hardware Protected Mode (HPM) is entered.
The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register
data on SI→ CS# goes high. (Please refer to Figure 12)
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1
during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL)
bit is reset.
Protection Modes
Mode
Status register condition
WP# and SRWD bit status
Memory
Status register can be written
in (WEL bit is set to "1") and
the SRWD, BP0-BP3
Software protection
mode (SPM)
WP#=1 and SRWD bit=0, or
WP#=0 and SRWD bit=0, or
WP#=1 and SRWD=1
The protected area
cannot
be program or erase.
bits can be changed
The SRWD, BP0-BP3 of
status register bits cannot be
changed
The protected area
cannot
be program or erase.
Hardware protection
mode (HPM)
WP#=0, SRWD bit=1
Note: As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in Table 2.
As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM).
Software Protected Mode (SPM):
-
When SRWD bit=0, no matter WP#/SO2 is low or high, the WREN instruction may set the WEL bit and can
change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1,
BP0, is at software protected mode (SPM).
-
When SRWD bit=1 and WP#/SO2 is high, the WREN instruction may set the WEL bit can change the values of
SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software pro-
tected mode (SPM)
Hardware Protected Mode (HPM):
-
When SRWD bit=1, and then WP#/SO2 is low (or WP#/SO2 is low before SRWD bit=1), it enters the hardware
protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2,
BP1, BP0 and hardware protected mode by the WP#/SO2 to against data modification.
Note:
To exit the hardware protected mode requires WP#/SO2 driving high once the hardware protected mode is entered.
If the WP#/SO2 pin is permanently connected to high, the hardware protected mode can never be entered; only can
use software protected mode via BP3, BP2, BP1, BP0.
If the system goes into 4 x I/O mode, the feature of HPM will be disabled.
P/N: PM1514
REV. 1.1, NOV. 18, 2009
19
MX25L6436E
MX25L12836E
(6) Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on
the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address
is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can
be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been
reached.
The sequence of issuing READ instruction is: CS# goes low → sending READ instruction code→3-byte address on
SI → data out on SO → to end READ operation can use CS# to high at any time during data out. (Please refer to
Figure 13)
(7) Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and
data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at
any location. The address is automatically increased to the next higher address after each byte data is shifted out,
so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when
the highest address has been reached.
The sequence of issuing FAST_READ instruction is: CS# goes low→sending FAST_READ instruction code →
3-byte address on SI→ 1-dummy byte (default) address on SI → data out on SO → to end FAST_READ operation
can use CS# to high at any time during data out. (Please refer to Figure 14)
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any im-
pact on the Program/Erase/Write Status Register current cycle.
(8) Dual Read Mode (DREAD)
The DREAD instruction enable double throughput of Serial Flash in read mode. The address is latched on rising
edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maxi-
mum frequency fT. The first address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD instruc-
tion. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruc-
tion, the following data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing DREAD instruction is: CS# goes low
sending DREAD instruction
3-byte address on
→
→
SI
8-bit dummy cycle
data out interleave on SO1 & SO0
to end DREAD operation can use CS# to high at
→
→
→
any time during data out (Please refer to Figure 15 for Dual Read Mode Timing Waveform).
While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
(9) Quad Read Mode (QREAD)
The QREAD instruction enable quad throughput of Serial Flash in read mode. The address is latched on rising edge
of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum
frequency fQ. The first address byte can be at any location. The address is automatically increased to the next high-
er address after each byte data is shifted out, so the whole memory can be read out at a single QREAD instruction.
The address counter rolls over to 0 when the highest address has been reached. Once writing QREAD instruction,
P/N: PM1514
REV. 1.1, NOV. 18, 2009
20
MX25L6436E
MX25L12836E
the following data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing QREAD instruction is: CS# goes low
sending QREAD instruction → 3-byte address on
→
SI
8-bit dummy cycle
data out interleave on SO3, SO2, SO1 & SO0
to end QREAD operation can use
→
→
→
CS# to high at any time during data out (Please refer to Figure 16 for Quad Read Mode Timing Waveform).
While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
(10) Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for
any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before
sending the Sector Erase (SE). Any address of the sector (Table 4-1 & 4-2) is a valid address for Sector Erase (SE)
instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in);
otherwise, the instruction will be rejected and not executed.
The sequence of issuing SE instruction is: CS# goes low → sending SE instruction code→ 3-byte address on SI
→CS# goes high. (Please refer to Figure 17)
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the
tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
sector is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no
change) and the WEL bit still be reset.
(11) Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for
64K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL)
bit before sending the Block Erase (BE). Any address of the block (Table 4-1 & 4-2) is a valid address for Block Erase (BE)
instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in);
otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE instruction is: CS# goes low → sending BE instruction code → 3-byte address on SI
→ CS# goes high. (Please refer to Figure 18)
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the
tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If
the block is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no
change) and the WEL bit still be reset.
(12) Block Erase (BE32K)
The Block Erase (BE32) instruction is for erasing the data of the chosen block to be "1". The instruction is used for
32K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL)
bit before sending the Block Erase (BE32). Any address of the block (Table 4-1 & 4-2) is a valid address for Block
Erase (BE32) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte
P/N: PM1514
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21
MX25L6436E
MX25L12836E
been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE32 instruction is: CS# goes low → sending BE32 instruction code → 3-byte address on
SI → CS# goes high. (Please refer to Figure 18)
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the
tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If
the block is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no
change) and the WEL bit still be reset.
(13) Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruc-
tion must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must go
high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The sequence of issuing CE instruction is: CS# goes low → sending CE instruction code → CS# goes high. (Please
refer to Figure 19)
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE
timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is
protected the Chip Erase (CE) instruction will not be executed, but WEL will be reset.
(14) Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction
must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device programs
only the last 256 data bytes sent to the device. If the entire 256 data bytes are going to be programmed, A7-A0
(The eight least significant address bits) should be set to 0. If the eight least significant address bits (A7-A0) are not
all 0, all transmitted data going beyond the end of the current page are programmed from the start address of the
same page (from the address A7-A0 are all 0). If more than 256 bytes are sent to the device, the data of the last
256-byte is programmed at the request page and previous data will be disregarded. If less than 256 bytes are sent
to the device, the data is programmed at the requested address of the page without effect on other address of the
same page.
The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→ at
least 1-byte on data on SI→ CS# goes high. (Please refer to Figure 20)
The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte
boundary( the latest eighth bit of data being latched in), otherwise, the instruction will be rejected and will not be
executed.
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the
tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If
the page is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no
change) and the WEL bit will still be reset.
P/N: PM1514
REV. 1.1, NOV. 18, 2009
22
MX25L6436E
MX25L12836E
(15) 4 x I/O Page Program (4PP)
The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN)
instruction must execute to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1"
before sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SO0, SO1, SO2,
and SO3, which can raise programer performance and and the effectiveness of application of lower clock less
than 20MHz. For system with faster clock, the Quad page program cannot provide more actual favors, because
the required internal page program time is far more than the time data flows in. Therefore, we suggest that while
executing this command (especially during sending data), user can slow the clock speed down to 20MHz below.
The other function descriptions are as same as standard page program.
The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on
SO[3:0]→ at least 1-byte on data on SO[3:0]→ CS# goes high. (Please refer to Figure 21)
If the page is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no
change) and the WEL bit will still be reset.
P/N: PM1514
REV. 1.1, NOV. 18, 2009
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MX25L12836E
The Program/Erase function instruction function flow is as follows:
Program/Erase Flow(1) with read array data
Start
WREN command
RDSR command*
No
WREN=1?
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
No
WIP=0?
Yes
Read array data
(same address of PGM/ERS)
No
Verify OK?
Yes
Program/erase fail
Program/erase successfully
CLSR(30h) command
Program/erase
another block?
Yes
* Issue RDSR to check BP[3:0].
* If WPSEL=1, issue RDBLOCK to check the block status.
No
Program/erase completed
P/N: PM1514
REV. 1.1, NOV. 18, 2009
24
MX25L6436E
MX25L12836E
Program/Erase Flow(2) without read array data
Start
WREN command
RDSR command*
No
WREN=1?
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
No
WIP=0?
Yes
RDSCUR command
Yes
REGPFAIL/REGEFAIL=1?
No
Program/erase fail
Program/erase successfully
CLSR(30h) command
Program/erase
another block?
Yes
* Issue RDSR to check BP[3:0].
* If WPSEL=1, issue RDBLOCK to check the block status.
No
Program/erase completed
P/N: PM1514
REV. 1.1, NOV. 18, 2009
25
MX25L6436E
MX25L12836E
(16) Continuously program mode (CP mode)
The CP mode may enhance program performance by automatically increasing address to the next higher address
after each byte data has been programmed.
The Continuously program (CP) instruction is for multiple byte program to Flash. A write Enable (WREN) instruction
must execute to set the Write Enable Latch (WEL) bit before sending the Continuously program (CP) instruction.
CS# requires to go high before CP instruction is executing. After CP instruction and address input, two bytes of
data is input sequentially from MSB(bit7) to LSB(bit0). The first byte data will be programmed to the initial address
range with A0=0 and second byte data with A0=1. If only one byte data is input, the CP mode will not process. If
more than two bytes data are input, the additional data will be ignored and only two byte data are valid. Any byte to
be programmed should be in the erase state (FF) first. It will not roll over during the CP mode, once the last unpro-
tected address has been reached, the chip will exit CP mode and reset write Enable Latch bit (WEL) as "0" and CP
mode bit as "0". Please check the WIP bit status if it is not in write progress before entering next valid instruction.
During CP mode, the valid commands are CP command (AD hex), WRDI command (04 hex), RDSR command (05
hex), and RDSCUR command (2B hex). And the WRDI command is valid after completion of a CP programming cy-
cle, which means the WIP bit=0.
The sequence of issuing CP instruction is : CS# goes low → sending CP instruction code → 3-byte address on SI
pin → two data bytes on SI → CS# goes high to low → sending CP instruction and then continue two data bytes
are programmed → CS# goes high to low -> till last desired two data bytes are programmed → CS# goes high to
low →sending WRDI (Write Disable) instruction to end CP mode → send RDSR instruction to verify if CP mode
word program ends, or send RDSCUR to check bit4 to verify if CP mode ends. (Please refer to Figure 22 of CP
mode timing waveform)
Three methods to detect the completion of a program cycle during CP mode:
1) Software method-I: by checking WIP bit of Status Register to detect the completion of CP mode.
2) Software method-II: by waiting for a tBP time out to determine if it may load next valid command or not.
3) Hardware method: by writing ESRY (enable SO to output RY/BY#) instruction to detect the completion of a
program cycle during CP mode. The ESRY instruction must be executed before CP mode execution. Once it is
enable in CP mode, the CS# goes low will drive out the RY/BY# status on SO, "0" indicates busy stage, "1" indi-
cates ready stage, SO pin outputs tri-state if CS# goes high. DSRY (disable SO to output RY/BY#) instruction to
disable the SO to output RY/BY# and return to status register data output during CP mode. Please note that the
ESRY/DSRY command are not accepted unless the completion of CP mode.
If the page is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no
change) and the WEL bit will still be reset.
(17) Parallel Mode (Highly recommended for production throughputs increasing)
The parallel mode provides 8 bit inputs/outputs for increasing throughputs of factory production purpose. The
parallel mode requires 55h command code, after writing the parallel mode command and then CS# going high,
after that, the Memory can be available to accept RDID/RES & REMS/READ/PP command as the normal writing
command procedure. To exit parallel mode, it requires 45h command code, or power-off/on sequence. The
sequence of issuing Paralle Mode instruction is : CS# goes low→sending Parallel Mode Code→CS# goes high (Please
refer to Figure 23-1, Other parallel mode please refer to Figure 23-2~23-7).
a. For normal write command (by SI), No effect
b. Under parallel mode, the fastest access clock freq. will be changed to 6MHz (SCLK pin clock freq.)
c. For parallel mode, the tV will be changed to 70ns.
P/N: PM1514
REV. 1.1, NOV. 18, 2009
26
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MX25L12836E
(18) Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to enter-
ing the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode
requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not ac-
tive and all Write/Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep
power-down mode. It's different from Standby mode.
The sequence of issuing DP instruction is: CS# goes low→ sending DP instruction code→ CS# goes high. (Please
refer to Figure 24)
Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP)
and Read Electronic Signature (RES) instruction. (those instructions allow the ID being reading out). When Power-
down, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby
mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction
code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay
of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2.
(19) Release from Deep Power-down (RDP), Read Electronic Signature (RES)
The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip
Select (CS#) is driven High, the device is put in the standby Power mode. If the device was not previously in the
Deep Power-down mode, the transition to the standby Power mode is immediate. If the device was previously in the
Deep Power-down mode, though, the transition to the standby Power mode is delayed by tRES2, and Chip Select (CS#)
must remain High for at least tRES2(max), as specified in Table 10. Once in the standby mode, the device waits to
be selected, so that it can receive, decode and execute instructions.
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of
ID Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new
design, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be
executed, only except the device is in progress of program/erase/write cycles; there's no effect on the current pro-
gram/erase/write cycles in progress. The sequence is shown as Figure 25, 26.
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeat-
edly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously
in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in
Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at
least tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and
execute instruction.
The RDP instruction is for releasing from Deep Power-down Mode.
(20) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4)
The REMS, REMS2 and REMS4 instruction provides both the JEDEC assigned Manufacturer ID and the specific
Device ID.
The instruction is initiated by driving the CS# pin low and shift the instruction code "90h", "CFh", "DFh" or "EFh" fol-
lowed by two dummy bytes and one bytes address (A7~A0). After which, the Manufacturer ID for MXIC (C2h) and
the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 27.
The Device ID values are listed in table of ID Definitions. If the one-byte address is initially set to 01h, then the De-
vice ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read
continuously, alternating from one to the other. The instruction is completed by driving CS# high.
P/N: PM1514
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MX25L6436E
MX25L12836E
Table 6. ID Definitions
Command Type
MX25L6436E
MX25L12836E
manufacturer ID memory type memory density manufacturer ID memory type memory density
RDID
RES
C2
20
electronic ID
16
17
C2
20
electronic ID
17
18
manufacturer ID
C2
device ID
16
manufacturer ID
C2
device ID
17
REMS/REMS2/
REMS4
(21) Enter Secured OTP (ENSO)
The ENSO instruction is for entering the additional 4K-bit Secured OTP mode. The additional 4K-bit Secured OTP
is independent from main array, which may use to store unique serial number for system identifier. After entering
the Secured OTP mode, and then follow standard read or program, procedure to read out the data or update data.
The Secured OTP data cannot be updated again once it is lock-down.
The sequence of issuing ENSO instruction is: CS# goes low → sending ENSO instruction to enter Secured OTP
mode → CS# goes high.
Please note that WRSR/WRSCUR/WPSEL/SBLK/GBLK/SBULK/GBULK/CE/BE/SE/BE32K commands are not ac-
ceptable during the access of secure OTP region, once Security OTP is lock down, only read related commands
are valid.
(22) Exit Secured OTP (EXSO)
The EXSO instruction is for exiting the additional 4K-bit Secured OTP mode.
The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP
mode→ CS# goes high.
(23) Read Security Register (RDSCUR)
The RDSCUR instruction is for reading the value of Security Register. The Read Security Register can be read at
any time (even in program/erase/write status register/write security register condition) and continuously.
The sequence of issuing RDSCUR instruction is : CS# goes low → sending RDSCUR instruction → Security Regis-
ter data out on SO → CS# goes high.
The definition of the Security Register is as below:
Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory before ex- factory
or not. When it is "0", it indicates non-factory lock; "1" indicates factory-lock.
Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for cus-
tomer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 4K-bit Secured
OTP area cannot be update any more. While it is in 4K-bit Secured OTP mode, array access is not allowed.
P/N: PM1514
REV. 1.1, NOV. 18, 2009
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MX25L12836E
Continuously Program Mode( CP mode) bit. The Continuously Program Mode bit indicates the status of CP
mode, "0" indicates not in CP mode; "1" indicates in CP mode.
Program Fail Flag bit. While a program failure happened, the Program Fail Flag bit would be set. This bit will also
be set when the user attempts to program a protected main memory region or a locked OTP region. This bit can in-
dicate whether one or more of program operations fail, and can be reset by command CLSR (30h).
Erase Fail Flag bit. While a erase failure happened, the Erase Fail Flag bit would be set. This bit will also be set
when the user attempts to erase a protected main memory region or a locked OTP region. This bit can indicate
whether one or more of erase operations fail, and can be reset by command CLSR (30h).
Write Protection Select bit. The Write Protection Select bit indicates that WPSEL has been executed successfully.
Once this bit has been set (WPSEL=1), all the blocks or sectors will be write-protected after the power-on every
time. Once WPSEL has been set, it cannot be changed again, which means it's only for individual WP mode.
Under the individual block protection mode (WPSEL=1), hardware protection is performed by driving WP#=0. Once
WP#=0 all array blocks/sectors are protected regardless of the contents of SRAM lock bits.
Security Register Definition
bit7
bit6
bit5
bit4
bit3
x
bit2
x
bit1
bit0
Continuously
Program
mode
(CP mode)
LDSO
(lock-down
4K-bit Se- Secured OTP
cured OTP)
4K-bit
WPSEL
E_FAIL
P_FAIL
0 = not
0=normal
Erase
succeed
1=indicate
Erase failed
(default=0)
0=normal
Program
succeed
1=indicate
Program
failed
0=normal
WP mode
1=individual
WP mode
(default=0)
lockdown
1 = lock-
down
(cannot
program/
erase
0 =
nonfactory
lock
1 = factory
lock
0=normal
Program
mode
1=CP mode
(default=0)
reserved
reserved
(default=0)
OTP)
non-volatile
bit
non-volatile non-volatile
volatile bit
Read Only
volatile bit
Read Only
volatile bit
Read Only
volatile bit
Read Only
volatile bit
Read Only
bit
bit
OTP
OTP
Read Only
(24) Write Security Register (WRSCUR)
The WRSCUR instruction is for changing the values of Security Register Bits. Unlike write status register, the WREN
instruction is not required before sending WRSCUR instruction. The WRSCUR instruction may change the values
of bit1 (LDSO bit) for customer to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is set to "1", the Se-
cured OTP area cannot be updated any more.
The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high.
The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
P/N: PM1514
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MX25L12836E
(25) Write Protection Selection (WPSEL)
There are two write protection methods, (1) BP protection mode (2) individual block protection mode. If WPSEL=0,
flash is under BP protection mode . If WPSEL=1, flash is under individual block protection mode. The default value
of WPSEL is “0”. WPSEL command can be used to set WPSEL=1. Please note that WPSEL is an OTP bit. Once
WPSEL is set to 1, there is no chance to recovery WPSEL back to “0”. If the flash is put on BP mode, the indi-
vidual block protection mode is disabled. Contrarily, if flash is on the individual block protection mode, the BP mode
is disabled.
Every time after the system is powered-on, and the Security Register bit 7 is checked to be WPSEL=1, all
the blocks or sectors will be write protected by default. User may only unlock the blocks or sectors via SBULK
and GBULK instruction. Program or erase functions can only be operated after the Unlock instruction is conducted.
BP protection mode, WPSEL=0:
ARRAY is protected by BP3~BP0 and BP3~BP0 bits are protected by “SRWD=1 and WP#=0”, where SRWD is bit 7
of status register that can be set by WRSR command.
Individual block protection mode, WPSEL=1:
Blocks are individually protected by their own SRAM lock bits which are set to “1” after power up. SBULK and SBLK
command can set SRAM lock bit to “0” and “1”. When the system accepts and executes WPSEL instruction, the bit
7 in security register will be set. It will activate SBLK, SBULK, RDBLOCK, GBLK, GBULK etc instructions to conduct
block lock protection and replace the original Software Protect Mode (SPM) use (BP3~BP0) indicated block meth-
ods.Under the individual block protection mode (WPSEL=1), hardware protection is performed by driving WP#=0.
Once WP#=0 all array blocks/sectors are protected regardless of the contents of SRAM lock bits.
The sequence of issuing WPSEL instruction is: CS# goes low → sending WPSEL instruction to enter the individual
block protect mode → CS# goes high. (Figure 28)
WPSEL instruction function flow is as follows:
BP and SRWD if WPSEL=0
WPB pin
BP3 BP2 BP1 BP0
SRWD
64KB
64KB
64KB
(1) BP3~BP0 is used to define the protection group region.
(The protected area size see Table2)
(2) “SRWD=1 and WPB=0” is used to protect BP3~BP0. In this
case, SRWD and BP3~BP0 of status register bits can not
be changed by WRSR
.
.
.
64KB
P/N: PM1514
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MX25L12836E
The individual block lock mode is effective after setting WPSEL=1
4KB
4KB
SRAM
SRAM
• Power-Up: All SRAM bits=1 (all blocks are default protected).
All array cannot be programmed/erased
TOP 4KBx16
Sectors
• SBLK/SBULK(36h/39h):
- SBLK(36h) : Set SRAM bit=1 (protect) : array can not be
programmed /erased
4KB
SRAM
SRAM
- SBULK(39h): Set SRAM bit=0 (unprotect): array can be
programmed /erased
64KB
- All top 4KBx16 sectors and bottom 4KBx16 sectors
and other 64KB uniform blocks can be protected and
unprotected SRAM bits individually by SBLK/SBULK
command set.
SRAM
Uniform
64KB blocks
• GBLK/ GBULK(78h/98h):
- GBLK(78h):Set all SRAM bits=1,whole chip are protected
and cannot be programmed / erased.
- GBULK(98h):Set all SRAM bits=0,whole chip are
unprotected and can be programmed / erased.
- All sectors and blocks SRAM bits of whole chip can be
protected and unprotected at one time by GBLK/GBULK
command set.
64KB
4KB
SRAM
SRAM
Bottom
4KBx16
Sectors
• RDBLOCK(3Ch):
- use RDBLOCK mode to check the SRAM bits status after
SBULK /SBLK/GBULK/GBLK command set.
4KB
SBULK / SBLK / GBULK / GBLK / RDBLOCK
P/N: PM1514
REV. 1.1, NOV. 18, 2009
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MX25L6436E
MX25L12836E
WPSEL Flow
start
RDSCUR(2Bh) command
Yes
WPSEL=1?
No
WPSEL disable,
block protected by BP[3:0]
WPSEL(68h) command
RDSR command
No
WIP=0?
Yes
RDSCUR(2Bh) command
No
WPSEL=1?
Yes
WPSEL set successfully
WPSEL set fail
WPSEL enable.
Block protected by individual lock
(SBLK, SBULK, … etc).
P/N: PM1514
REV. 1.1, NOV. 18, 2009
32
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MX25L12836E
(26) Single Block Lock/Unlock Protection (SBLK/SBULK)
These instructions are only effective after WPSEL was executed. The SBLK instruction is for write protection a spec-
ified block (or sector) of memory, using A23-A16 or (A23-A12) address bits to assign a 64Kbyte block (or 4K bytes
sector) to be protected as read only. The SBULK instruction will cancel the block (or sector) write protection state.
This feature allows user to stop protecting the entire block (or sector) through the chip unprotect command (GBULK).
The WREN (Write Enable) instruction is required before issuing SBLK/SBULK instruction.
The sequence of issuing SBLK/SBULK instruction is: CS# goes low → send SBLK/SBULK (36h/39h) instruction →
send 3 address bytes assign one block (or sector) to be protected on SI pin → CS# goes high. (Figure 29)
The CS# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not be executed.
SBLK/SBULK instruction function flow is as follows:
Block Lock Flow
Start
RDSCUR(2Bh) command
No
WPSEL=1?
WPSEL command
Yes
WREN command
SBLK command
( 36h + 24bit address )
RDSR command
No
WIP=0?
Yes
RDBLOCK command
( 3Ch + 24bit address )
No
Data = FFh ?
Yes
Block lock successfully
Block lock fail
Yes
Lock another block?
No
Block lock completed
P/N: PM1514
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MX25L12836E
Block Unlock Flow
start
RDSCUR(2Bh) command
No
WPSEL=1?
Yes
WPSEL command
WREN command
SBULK command
( 39h + 24bit address )
RDSR command
WIP=0?
No
Yes
Yes
Unlock another block?
Unlock block completed?
P/N: PM1514
REV. 1.1, NOV. 18, 2009
34
MX25L6436E
MX25L12836E
(27) Read Block Lock Status (RDBLOCK)
This instruction is only effective after WPSEL was executed. The RDBLOCK instruction is for reading the status of
protection lock of a specified block (or sector), using A23-A16 (or A23-A12) address bits to assign a 64K bytes block (4K
bytes sector) and read protection lock status bit which the first byte of Read-out cycle. The status bit is"1" to indicate
that this block has be protected, that user can read only but cannot write/program /erase this block. The status bit is
"0" to indicate that this block hasn't be protected, and user can read and write this block.
The sequence of issuing RDBLOCK instruction is: CS# goes low → send RDBLOCK (3Ch) instruction → send 3 ad-
dress bytes to assign one block on SI pin → read block's protection lock status bit on SO pin → CS# goes high. (Please
refer to Figure 30)
(28) Gang Block Lock/Unlock (GBLK/GBULK)
These instructions are only effective after WPSEL was executed. The GBLK/GBULK instruction is for enable/disable
the lock protection block of the whole chip.
The WREN (Write Enable) instruction is required before issuing GBLK/GBULK instruction.
The sequence of issuing GBLK/GBULK instruction is: CS# goes low → send GBLK/GBULK (7Eh/98h) instruction →
CS# goes high. (Please refer to Figure 31)
The CS# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed.
(29) Clear SR Fail Flags (CLSR)
The CLSR instruction is for resetting the Program/Erase Fail Flag bit of Security Register. It should be executed be-
fore program/erase another block during programming/erasing flow without read array data.
The sequence of issuing CLSR instruction is: CS# goes low → send CLSR instruction code → CS# goes high.
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
(30) Enable SO to Output RY/BY# (ESRY)
The ESRY instruction is for outputing the ready/busy status to SO during CP mode.
The sequence of issuing ESRY instruction is: CS# goes low → sending ESRY instruction code → CS# goes high.
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
(31) Disable SO to Output RY/BY# (DSRY)
The DSRY instruction is for resetting ESRY during CP mode. The ready/busy status will not output to SO after
DSRY issued.
The sequence of issuing DSRY instruction is: CS# goes low → send DSRY instruction code → CS# goes high.
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
P/N: PM1514
REV. 1.1, NOV. 18, 2009
35
MX25L6436E
MX25L12836E
(32) Read DMC mode (RDDMC)
MX25L6436E/12836E features DMC mode. Host system can retrieve the operating characteristics, structure and
vendor-specified information such as identifying information, memory size, operating voltages and timing informa-
tion of this device by DMC mode. Writes the DMC Query command "5AH". The system can read DMC information
at the addresses given. A reset command is required to exit DMC mode and go back to ready array mode. The sys-
tem can write the DMC Query command only when the device is in read mode.
The identification data values in under DMC table. The sequence of issuing RDDMC instruction is CS# goes low
→ send RDDMC (5A) instruction → send 3 address bytes on SI pin → send 1 dummy byte on SI pin → read DMC
code → CS# goes high.
Discoverable Memory Capabilities (DMC) Signature and Parameter Identification Data Values (Advanced
Information)
Address (h)
Description
Address (Bit)
Data
Comment
(Byte Mode)
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
53h
46h
44h
50h
00h
Discoverable Memory Capabilities
Signature
Hex: 50444653
Minor Revision
Major Revision
Start from 0x00
Start from 0x01
DMC Revision
01h
02h
Number of Parameter Header
Reserved
Parameter ID(0)
Parameter Minor Revision
Parameter Major Revision
Parameter Length (in DW)
Reserved
00h
00h
01h
02h
Start from 0x00
Start from 0x01
Based on Intel draft
Parameter Table Pointer
20h
Reserved
Parameter ID(1)
Parameter Minor Revision
Parameter Major Revision
Parameter Length (in DW)
Reserved
01h
00h
01h
00h
Start from 0x00
Start from 0x01
Reserved
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
Parameter Table Pointer
00h
Address reserved
Reserved
Parameter ID(2)
Parameter Minor Revision
Parameter Major Revision
Parameter Length (in DW)
Reserved
02h
00h
01h
02h
Start from 0x00
Start from 0x01
Parameter Table Pointer
Reserved
28h
Reserved
P/N: PM1514
REV. 1.1, NOV. 18, 2009
36
MX25L6436E
MX25L12836E
Parameter ID (0) (Advanced Information)
Description
Address (h)
(Byte Mode)
Address (Bit)
Data
Comment
00=reserved
01=4KB erase
10=reserved
00
Minimum Block/Sector Erase sizes
Write Granularity
01
01
11=64KB erase
02
03
1
0= 1Byte 1=64Byte
20h
00=N/A
01=use 50h opcode
11=use 06h opcode
Write Enable Command Required for
Writing to Volatile Status Registers
00
04
05
06
07
08
09
10
11
12
13
14
15
Reserved
Reserved
Reserved
4KB Erase Support
(00h=not supported)
4KB Erase Opcode
21h
20h
Supports Single Input Address Dual Output
Fast read
0=not supported
1=support
16
17
18
19
20
21
1
00=3Byte 01=4Byte
10=reserved
Number of bytes used in addressing for
flash array read, write and erase
00
11=reserved
0=not supported
1=support
0=not supported
1=support
0=not supported
1=support
Supports Double Transfer Rate Clocking
0
0
0
22h
Supports Dual Input Address Dual Output
Fast read
Supports Quad Input Address Quad Output
Fast read
22
23
24
25
26
27
28
29
30
31
Reserved
Reserved
Reserved
23h
07FFFFFFh
03FFFFFFh
128Mbits
64Mbits
Flash Size in bits
24h to 27h
31:00
P/N: PM1514
REV. 1.1, NOV. 18, 2009
37
MX25L6436E
MX25L12836E
Parameter ID (1) (Advanced Information)
Address (h)
(Byte Mode)
Undefined.
Description
Address (Bit)
Data
Comment
Reserved
31:00
0000h
Reserved
Parameter ID (2) (Advanced Information)
Description
Address (h)
(Byte Mode)
Address (Bit)
Data
Comment
2000h=2.00V
2800h=2.80V
3600h=3.60V
1650h=1.65V
2250h=2.25V
2350h=2.35V
2700h=2.70V
00=not supported
00=not supported
0=not supported
1=support
Vcc Supply Maximum Voltage
Vcc Supply Minimum Voltage
31h:30h
15:00
3600h
33h:32h
31:16
2700h
Vpp Supply Maximum Voltage
Vpp Supply Minimum Voltage
01:00
03:02
00
00
Supports Vio Function
04
0
34h
0=not supported
1=support
reserved
0=not supported
1=support
Supports HOLD# Function
Reserved
05
07:06
08
0
Reserved
1
Parallel Mode Capable (Note1)
Supports Single Input Address Quad Output
Fast read
0=not supported
1=support
0=not supported
1=support
0=not supported
1=support
0=not supported
1=support
0=not supported
1=support
0=not supported
1=support
0=not supported
1=support
0=not supported
1=support
09
10
11
12
13
14
15
16
17
1
1
1
1
1
1
1
1
1
Supports Continuous Program Mode
Supports Deep Power Down Mode
OTP Capable
35h
Supports Sector Group Protect
Supports 64KB Block Protect
Supports 4KB Sector Protect
Supports 64KB Block Erase
Supports 32KB Block Erase
36h
37h
0=not supported
1=support
Reserved
Reserved
23:18
31:24
Reserved
Reserved
Reserved
Reserved
Note1: Parallel Mode is only available on 16SOP package.
8SOP do not supprot it,so the value will be set to "0".
P/N: PM1514
REV. 1.1, NOV. 18, 2009
38
MX25L6436E
MX25L12836E
POWER-ON STATE
The device is at below states when power-up:
- Standby mode ( please note it is not Deep Power-down mode)
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage unless the VCC achieves below correct
level:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal Power-on Reset (POR) circuit may protect the device from data corruption and inadvertent data change
during power up state.
For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not
guaranteed. The read, write, erase, and program command should be sent after the time delay:
- tVSL after VCC reached VCC minimum level
The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.
Please refer to the figure of "Power-up Timing".
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended.
(generally around 0.1uF)
P/N: PM1514
REV. 1.1, NOV. 18, 2009
39
MX25L6436E
MX25L12836E
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
RATING
VALUE
Industrial grade
-40°C to 85°C
-55°C to 125°C
-0.5V to 4.6V
-0.5V to 4.6V
-0.5V to 4.6V
Ambient Operating Temperature
Storage Temperature
Applied Input Voltage
Applied Output Voltage
VCC to Ground Potential
NOTICE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is stress rating only and functional operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended period may affect reliability.
2. Specifications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see Figure 2, 3.
Figure 3. Maximum Positive Overshoot Waveform
Figure 2. Maximum Negative Overshoot Waveform
20ns
20ns
20ns
Vss
Vcc + 2.0V
Vcc
Vss-2.0V
20ns
20ns
20ns
CAPACITANCE TA = 25°C, f = 1.0 MHz
SYMBOL PARAMETER
MIN.
TYP
MAX.
UNIT
pF
CONDITIONS
VIN = 0V
CIN
Input Capacitance
6
8
COUT Output Capacitance
pF
VOUT = 0V
P/N: PM1514
REV. 1.1, NOV. 18, 2009
40
MX25L6436E
MX25L12836E
Figure 4. OUTPUT LOADING
DEVICE UNDER
TEST
2.7K ohm
+3.3V
CL
6.2K ohm
DIODES=IN3064
OR EQUIVALENT
CL=30/15pF Including jig capacitance
P/N: PM1514
REV. 1.1, NOV. 18, 2009
41
MX25L6436E
MX25L12836E
Table 7-1. MX25L6436E DC CHARACTERISTICS
(Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V)
SYMBOL PARAMETER
NOTES
MIN.
MAX.
± 2
UNITS TEST CONDITIONS
ILI
Input Load Current
1
1
1
uA VCC = VCC Max, VIN = VCC or GND
uA VCC = VCC Max, VIN = VCC or GND
uA VIN = VCC or GND, CS# = VCC
ILO
Output Leakage Current
± 2
ISB1 VCC Standby Current
100
Deep Power-down
Current
ISB2
30
45
40
30
25
uA VIN = VCC or GND, CS# = VCC
f=104MHz, fQ=70MHz (4 x I/O read)
mA
SCLK=0.1VCC/0.9VCC, SO=Open
fT=70MHz (2 x I/O read)
mA
ICC1 VCC Read
1
1
SCLK=0.1VCC/0.9VCC, SO=Open
f=33MHz, SCLK=0.1VCC/0.9VCC,
SO=Open
mA
VCC Program Current
ICC2
(PP)
mA Program in Progress, CS# = VCC
VCC Write Status
ICC3
Program status register in progress,
CS#=VCC
20
25
mA
Register (WRSR) Current
VCC Sector Erase
Current (SE)
ICC4
1
1
mA Erase in Progress, CS#=VCC
mA Erase in Progress, CS#=VCC
VCC Chip Erase Current
ICC5
(CE)
20
VIL
VIH
VOL
Input Low Voltage
Input High Voltage
Output Low Voltage
-0.5
0.8
V
V
0.7VCC VCC+0.4
0.4
V
V
IOL = 1.6mA
IOH = -100uA
VOH Output High Voltage
VCC-0.2
Notes :
1. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and speeds).
2. Typical value is calculated by simulation.
P/N: PM1514
REV. 1.1, NOV. 18, 2009
42
MX25L6436E
MX25L12836E
Table 7-2. MX25L12836E DC CHARACTERISTICS
(Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V)
SYMBOL PARAMETER
NOTES
MIN.
MAX.
± 2
UNITS TEST CONDITIONS
ILI
Input Load Current
1
1
1
uA VCC = VCC Max, VIN = VCC or GND
uA VCC = VCC Max, VIN = VCC or GND
uA VIN = VCC or GND, CS# = VCC
ILO
Output Leakage Current
± 2
ISB1 VCC Standby Current
100
Deep Power-down
Current
ISB2
40
45
40
30
25
uA VIN = VCC or GND, CS# = VCC
f=104MHz, fQ=70MHz (4 x I/O read)
mA
SCLK=0.1VCC/0.9VCC, SO=Open
fT=70MHz (2 x I/O read)
mA
ICC1 VCC Read
1
1
SCLK=0.1VCC/0.9VCC, SO=Open
f=33MHz, SCLK=0.1VCC/0.9VCC,
SO=Open
mA
VCC Program Current
ICC2
(PP)
mA Program in Progress, CS# = VCC
VCC Write Status
ICC3
Program status register in progress,
CS#=VCC
20
25
mA
Register (WRSR) Current
VCC Sector Erase
Current (SE)
ICC4
1
1
mA Erase in Progress, CS#=VCC
mA Erase in Progress, CS#=VCC
VCC Chip Erase Current
ICC5
(CE)
20
VIL
Input Low Voltage
Input High Voltage
-0.5
0.8
V
V
VIH
0.7VCC VCC+0.4
IOL = 1.6mA;
IOL = 140uA for parallel mode
VOL
Output Low Voltage
0.4
V
IOH = -100uA;
IOH = 65uA for parallel mode
VOH Output High Voltage
VCC-0.2
V
Notes :
1. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and speeds).
2. Typical value is calculated by simulation.
P/N: PM1514
REV. 1.1, NOV. 18, 2009
43
MX25L6436E
MX25L12836E
Table 8-1. MX25L6436E AC CHARACTERISTICS
(Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V)
Symbol Alt. Parameter
Min.
Typ.
Max.
Unit
Clock Frequency for the following instructions:
fSCLK
fC FAST_READ, PP, SE, BE, CE, DP, RES,RDP
WREN, WRDI, RDID, RDSR, WRSR
104
MHz
fRSCLK
fTSCLK
f4PP
fR Clock Frequency for READ instructions
fT Clock Frequency for DREAD instructions
fQ Clock Frequency for QREAD instructions
Clock Frequency for 4PP (Quad page program)
50
70
70
20
MHz
MHz
MHz
MHz
ns
Fast_Read
Read
4.5
9
tCH(1) tCLH Clock High Time
ns
Fast_Read
Read
4.5
9
0.1
0.1
8
ns
ns
V/ns
V/ns
ns
tCL(1)
tCLL Clock Low Time
Clock Rise Time (3) (peak to peak)
Clock Fall Time (3) (peak to peak)
tCLCH(2)
tCHCL(2)
tSLCH tCSS CS# Active Setup Time (relative to SCLK)
tCHSL CS# Not Active Hold Time (relative to SCLK)
tDVCH tDSU Data In Setup Time
5
2
ns
ns
tCHDX
tCHSH
tSHCH
tDH Data In Hold Time
5
5
8
ns
ns
ns
CS# Active Hold Time (relative to SCLK)
CS# Not Active Setup Time (relative to SCLK)
Read
15
ns
tSHSL(3) tCSH CS# Deselect Time
Write/Erase/
Program
2.7V-3.6V
3.0V-3.6V
50
ns
10
8
ns
ns
ns
tSHQZ(2) tDIS Output Disable Time
Clock Low to Output Valid
1 I/O
9
Loading: 15pF
tCLQV
tV
2 I/O & 4 I/O
Loading: 30pF 2 I/O & 4 I/O
9.5
12
ns
ns
ns
ns
ns
us
VCC=2.7V~3.6V
tCLQX
tWHSL(4)
tSHWL(4)
tDP(2)
tHO Output Hold Time
Write Protect Setup Time
Write Protect Hold Time
2
20
100
CS# High to Deep Power-down Mode
CS# High to Standby Mode without Electronic Signature
Read
10
tRES1(2)
100
us
tRES2(2)
tW
CS# High to Standby Mode with Electronic Signature Read
Write Status Register Cycle Time
Byte-Program
100
100
300
5
300
2
2
80
1
us
ms
us
ms
ms
s
s
s
ms
ms
40
9
tBP
tPP
tSE
tBE
tBE
tCE
tWPS
tWSR
Page Program Cycle Time
1.4
60
0.5
0.7
50
Sector Erase Cycle Time (4KB)
Block Erase Cycle Time (32KB)
Block Erase Cycle Time (64KB)
Chip Erase Cycle Time
Write Protection Selection Time
Write Security Register Time
1
Notes:
1. tCH + tCL must be greater than or equal to 1/ f (fC or fR).
2. Value guaranteed by characterization, not 100% tested in production.
3. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
P/N: PM1514
REV. 1.1, NOV. 18, 2009
44
MX25L6436E
MX25L12836E
Table 8-2. MX25L12836E AC CHARACTERISTICS
(Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V)
Symbol Alt. Parameter
Min.
Max.
Unit
Clock Frequency for the following
Serial
104
MHz
instructions:
fSCLK
fC
FAST_READ, PP, SE, BE, CE, DP, RES,
RDP, WREN, WRDI, RDID, RDSR, WRSR
Parallel
6
MHz
fRSCLK
fTSCLK
f4PP
fR Clock Frequency for READ instructions
fT Clock Frequency for DREAD instructions
fQ Clock Frequency for QREAD instructions
50
70
70
20
MHz
MHz
MHz
MHz
Clock Frequency for 4PP (Quad page program)
4.5
(Fast_Read)
Serial
ns
tCH(1) tCLH Clock High Time
Serial
Parallel
9 (Read)
ns
ns
30
4.5
(Fast_Read)
Serial
ns
tCL(1)
tCLL Clock Low Time
Serial
Parallel
Serial
Parallel
Serial
Parallel
9 (Read)
ns
ns
30
0.1
0.25
0.1
0.25
8
V/ns
V/ns
V/ns
V/ns
ns
tCLCH(2)
tCHCL(2)
Clock Rise Time (3) (peak to peak)
Clock Fall Time (3) (peak to peak)
tSLCH tCSS CS# Active Setup Time (relative to SCLK)
tCHSL CS# Not Active Hold Time (relative to SCLK)
5
ns
Serial
Parallel
Serial
Parallel
Serial
Parallel
2
10
5
10
5
30
8
ns
ns
ns
ns
ns
ns
ns
tDVCH tDSU Data In Setup Time
tCHDX
tDH Data In Hold Time
tCHSH
tSHCH
CS# Active Hold Time (relative to SCLK)
CS# Not Active Setup Time (relative to SCLK)
Read
15
ns
tSHSL(3) tCSH CS# Deselect Time
tSHQZ(2) tDIS Output Disable Time
Write/Erase/
Program
2.7V-3.6V
Serial
3.0V-3.6V
Serial
50
ns
ns
ns
10
8
Parallel
20
9
ns
ns
ns
ns
ns
1 I/O
Loading: 15pF
Loading: 30pF
Clock Low to Output Valid
VCC=2.7V~3.6V
2 I/O & 4 I/O
2 I/O & 4 I/O
Parallel
9.5
12
70
tCLQV
tV
P/N: PM1514
REV. 1.1, NOV. 18, 2009
45
MX25L6436E
MX25L12836E
Symbol Alt. Parameter
Min.
2
20
Typ.
Max.
Unit
ns
ns
ns
us
tCLQX
tWHSL(4)
tSHWL(4)
tDP(2)
tHO Output Hold Time
Write Protect Setup Time
Write Protect Hold Time
CS# High to Deep Power-down Mode
CS# High to Standby Mode without Electronic
Signature Read
100
10
tRES1(2)
tRES2(2)
100
us
us
CS# High to Standby Mode with Electronic Signature
Read
100
tW
tBP
tPP
tSE
tBE
tBE
tCE
tWPS
tWSR
Write Status Register Cycle Time
Byte-Program
Page Program Cycle Time
Sector Erase Cycle Time (4KB)
Block Erase Cycle Time (32KB)
Block Erase Cycle Time (64KB)
Chip Erase Cycle Time
Write Protection Selection Time
Write Security Register Time
40
9
100
300
5
300
2
2
200
1
ms
us
ms
ms
s
s
s
ms
ms
1.4
60
0.5
0.7
80
1
Notes:
1. tCH + tCL must be greater than or equal to 1/ f (fC or fR).
2. Value guaranteed by characterization, not 100% tested in production.
3.Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
P/N: PM1514
REV. 1.1, NOV. 18, 2009
46
MX25L6436E
MX25L12836E
Timing Analysis
Figure 5. Serial Input Timing
tSHSL
tSHCH
tCHCL
CS#
tCHSL
tSLCH
tCHSH
SCLK
tDVCH
tCHDX
tCLCH
MSB
LSB
SI
High-Z
SO
Figure 6. Output Timing
CS#
tCH
SCLK
tCLQV
tCLQV
tCL
tSHQZ
tCLQX
SO
tCLQX
LSB
tQLQH
tQHQL
ADDR.LSB IN
SI
P/N: PM1514
REV. 1.1, NOV. 18, 2009
47
MX25L6436E
MX25L12836E
Figure 7. WP# Setup Timing and Hold Timing during WRSR when SRWD=1
WP#
CS#
tSHWL
tWHSL
0
1
2
3
4
5
6
7
8
9
10 11 12
13 14
15
SCLK
01
SI
High-Z
SO
Figure 8. Write Enable (WREN) Sequence (Command 06)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
06
SI
High-Z
SO
Figure 9. Write Disable (WRDI) Sequence (Command 04)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
04
SI
High-Z
SO
P/N: PM1514
REV. 1.1, NOV. 18, 2009
48
MX25L6436E
MX25L12836E
Figure 10. Read Identification (RDID) Sequence (Command 9F)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
28 29 30 31
SCLK
SI
Command
9F
Manufacturer Identification
Device Identification
High-Z
SO
D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13
D3 D2 D1 D0
MSB
MSB
Figure 11. Read Status Register (RDSR) Sequence (Command 05)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI
command
05
Status Register Out
High-Z
D7 D6 D5 D4 D3 D2 D1 D0
MSB
SO
Figure 12. Write Status Register (WRSR) Sequence (Command 01)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
Status
Register In
command
01
SI
D7 D6 D5 D4 D3 D2 D1 D0
MSB
High-Z
SO
P/N: PM1514
REV. 1.1, NOV. 18, 2009
49
MX25L6436E
MX25L12836E
Figure 13. Read Data Bytes (READ) Sequence (Command 03)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
03
24 ADD Cycles
A23 A22 A21
MSB
A3 A2 A1 A0
SI
Data Out 2
Data Out 1
High-Z
D7 D6 D5 D4 D3 D2 D1 D0 D7
MSB MSB
SO
Figure 14. Read at Higher Speed (FAST_READ) Sequence (Command 0B)
CS#
47
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
28 29 30 31
0
1
2
3
4
5
6
7
8
9
10
SCLK
Command
0B
8 Dummy Cycles
24 ADD Cycles
SI
A23 A22 A21
A3 A2 A1 A0
Data Out 1
Data Out 2
High-Z
SO
D7 D6 D5 D4 D3 D2 D1 D0 D7
MSB
Figure 15. Dual Read Mode Sequence (Command 3B)
CS#
30 31 32
39 40 41 42 43 44 45
0
1
2
3
4
5
6
7
8
9
SCLK
Data Out
2
Data Out
1
8 dummy
cycle
Command
24 ADD Cycle
A22 A21
A2 A0
D4 D2
D6 D4
D0
3B
D6
D7
SI/SIO0
High Impedance
D7 D5
D1
D5 D3
SO/SIO1
P/N: PM1514
REV. 1.1, NOV. 18, 2009
50
MX25L6436E
MX25L12836E
Figure 16. Quad Read Mode Sequence (Command 6B)
CS#
29 30 31 32 33
38 39 40 41 42
0
1
2
3
4
5
6
7
8
9
SCLK
…
…
Data
Out 2
Data
Out 3
Command
6B
8 dummy cycles
24 ADD Cycles
Data
Out 1
…
A23A22
A2 A1 A0
D4 D0 D4 D0 D4
SI/SO0
High Impedance
High Impedance
High Impedance
SO/SO1
WP#/SO2
NC/SO3
D5 D1 D5 D1 D5
D6 D2 D6 D2 D6
D7 D3 D7 D3 D7
Figure 17. Sector Erase (SE) Sequence (Command 20)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
…
24 ADD Cycles
Command
20
…
A23 A22
A2 A1 A0
SI
MSB
Figure 18. Block Erase (BE/EB32K) Sequence (Command D8/52)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
…
24 ADD Cycles
Command
D8/52
…
A23 A22
A2 A1 A0
SI
MSB
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MX25L6436E
MX25L12836E
Figure 19. Chip Erase (CE) Sequence (Command 60 or C7)
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
60 or C7
Figure 20. Page Program (PP) Sequence (Command 02)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
02
24 ADD Cycles
Data Byte 1
Data Byte 256
A23 A22 A21
MSB
A3 A2 A1 A0
D7 D6 D5 D4 D3 D2
MSB
D0
D1
D7 D6 D5 D4 D3 D2 D1 D0
SI
Figure 21. 4 x I/O Page Program (4PP) Sequence (Command 38)
CS#
524 525
10 11 12 13 14 15 16 17
0
1
2
3
4
5
6
7
8
9
SCLK
Data
Byte 256
Data Data
Byte 1 Byte 2
Command
38
6 ADD cycles
D4 D0 D4 D0
D4 D0
A20 A16 A12 A8 A4 A0
SI/SIO0
D5 D1 D5 D1
D6 D2 D6 D2
D7 D3 D7 D3
D5 D1
D6 D2
D7 D3
SO/SIO1
WP#/SIO2
A21 A17 A13 A9 A5 A1
A22 A18 A14 A10 A6 A2
NC/SIO3
A23 A19 A15 A11 A7 A3
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MX25L6436E
MX25L12836E
Figure 22. Continuously Program (CP) Mode Sequence with Hardware Detection (Command AD)
CS#
SCLK
SI
20 2122 23 24
0
1
30 31 31 32
47 48
0
7
7
8
0
6
7 8
0
1
6 7 8 9
Command
AD (hex)
data in
Byte n-1, Byte n
Valid
Command (1)
data in
04 (hex)
05 (hex)
24-bit address
Byte 0, Byte1
high impedance
status (2)
S0
Note:
(1) During CP mode, the valid commands are CP command (AD hex), WRDI command (04 hex), RDSR command
(05 hex), and RDSCUR command (2B hex).
(2) Once an internal programming operation begins, CS# goes low will drive the status on the SO pin and CS#
goes high will return the SO pin to tri-state.
(3) To end the CP mode, either reaching the highest unprotected address or sending Write Disable (WRDI) com-
mand (04 hex) may achieve it and then it is recommended to send RDSR command (05 hex) to verify if CP
mode is ended.
P/N: PM1514
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MX25L12836E
Figure 23-1. Enter Parallel Mode (ENPLM) Sequence (Command 55)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
55
SI
High-Z
SO
Figure 23-2. Exit Parallel Mode (EXPLM) Sequence (Command 45)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
45
SI
High-Z
SO
Figure 23-3. Parallel Mode Read Identification (Parallel RDID) Sequence (Command 9F)
CS#
1
3
4
5
6
7
8
9
10
0
2
SCLK
SI
Command
9F
Device Identification
High-Z
PO7~0
Manufacturer Identification
Notes :
1. There are 3 data bytes which would be output sequentially for Manufacturer and Device ID 1'st byte (Memory
Type) and Device ID 2'nd byte (Memory Density).
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Figure 23-4. Parallel Mode Read Electronic Manufacturer & Device ID (Parallel REMS) Sequence (Command
90)
CS#
0
1
2
3
4
5
6
7
8
9 10
28
30 31 32 33
29
SCLK
Command
90
24 ADD Cycles
SI
A0
A1
A3 A2
A23 A22 A21
Device Identification
High-Z
PO7~0
Manufacturer Identification
Notes :
1. A0=0 will output the Manufacturer ID first and A0=1 will output Device ID first. A1~A23 don't care.
Figure 23-5. Parallel Mode Release from Deep Power-down (RDP) and Read Electronic Signature (RES) Se-
quence
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38
SCLK
24 ADD Cycles
t
RES2
Instruction
AB
SI
A23 A22 A21
A3 A2 A1 A0
Electronic Signature Out
High Impedance
PO7~0
Byte Output
Deep Power-down Mode
Stand-by Mode
Notes :
1. Under parallel mode, the fastest access clock freg. will be changed to 6MHz(SCLK pin clock freg.)
To release from Deep Power-down mode and read ID in parallel mode, which requires a parallel mode com-
mand (55h) before the read status register command.
To exit parallel mode, it requires a (45h) command or power-off/on sequence.
P/N: PM1514
REV. 1.1, NOV. 18, 2009
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MX25L6436E
MX25L12836E
Figure 23-6. Parallel Mode Read Array (Parallel READ) Sequence (Command 03)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33
n-1 n
SCLK
Command
03
24 ADD Cycles
…
SI
A23 A22 A21
MSB
A3 A2 A1 A0
High-Z
PO7~0
D0~D7 D0~D7
Byte n-1 Byte n
D0~D7
Byte 2
D0~D7
Byte 1
Figure 23-7. Parallel Mode Page Program (Parallel PP) Sequence (Command 02)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34
286 287
SCLK
Command
02
24 ADD Cycles
A23 A22 A21
A3 A2 A1 A0
SI
MSB
High-Z
PO7~0
MSB
Data Byte1
Data Byte2
Data Byte3
Data Byte255
Data Byte256
Figure 24. Deep Power-down (DP) Sequence (Command B9)
CS#
t
DP
0
1
2
3
4
5
6
7
SCLK
SI
Command
B9
Stand-by Mode
Deep Power-down Mode
P/N: PM1514
REV. 1.1, NOV. 18, 2009
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MX25L6436E
MX25L12836E
Figure 25. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38
39
SCLK
Command
AB
24 ADD Cycles
t
RES2
…
SI
A23 A22 A21
MSB
A3 A2 A1 A0
Electronic Signature Out
High-Z
D7
D1
D0
D6 D5 D4 D3 D2
SO
MSB
Deep Power-down Mode
Stand-by Mode
Figure 26. Release from Deep Power-down (RDP) Sequence (Command AB)
CS#
t
RES1
0
1
2
3
4
5
6
7
SCLK
SI
Command
AB
High-Z
SO
Deep Power-down Mode
Stand-by Mode
P/N: PM1514
REV. 1.1, NOV. 18, 2009
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MX25L12836E
Figure 27. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF or CF)
CS#
0
1
2
3
4
5
6
7
8
9
10
47
30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
28
29
SCLK
Command
90
24 ADD Cycles
SI
A0
A1
A3 A2
A23 A22 A21
Manufacturer ID
Device ID
High-Z
SO
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
MSB
MSB
MSB
Notes:
1. A0=0 will output the Manufacturer ID first and A0=1 will output Device ID first. A1~A23 is don't care.
2. Instruction is either 90(hex) or EF(hex) or DF(hex) or CF(hex).
Figure 28. Write Protection Selection (WPSEL) Sequence (Command 68)
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
68
P/N: PM1514
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MX25L6436E
MX25L12836E
Figure 29. Single Block Lock/Unlock Protection (SBLK/SBULK) Sequence (Command 36/39)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
36/39
24 Bit Address
Cycles
A23 A22
A2 A1 A0
SI
MSB
Figure 30. Read Block Protection Lock Status (RDBLOCK) Sequence (Command 3C)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
3C
24 ADD Cycles
SI
A23 A22 A21
MSB
A3 A2 A1 A0
Block Protection Lock status out
High-Z
D7 D6 D5 D4 D3 D2 D1 D0
MSB
SO
Figure 31. Gang Block Lock/Unlock (GBLK/GBULK) Sequence (Command 7E/98)
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
7E/98
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MX25L6436E
MX25L12836E
Figure 32. Power-up Timing
V
CC
V
(max)
CC
Chip Selection is Not Allowed
V
(min)
CC
Device is fully accessible
tVSL
time
Note: VCC (max.) is 3.6V and VCC (min.) is 2.7V.
Table 9. Power-Up Timing
Symbol
Parameter
Min.
Max.
Unit
tVSL(1)
VCC(min) to CS# low
300
us
Note: 1. The parameter is characterized only.
INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status
Register contains 00h (all Status Register bits are 0).
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MX25L12836E
RECOMMENDED OPERATING CONDITIONS
At Device Power-Up
AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up. (e.g.
Vcc and CS# ramp up simultaneously) If the timing in the figure is ignored, the device may not operate correctly.
VCC(min)
VCC
GND
tSHSL
tVR
CS#
tCHSL
tSLCH
tCHSH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
tCLCH
MSB IN
LSB IN
SI
High Impedance
SO
Figure A. AC Timing at Device Power-Up
Symbol
tVR
Parameter
VCC Rise Time
Notes
Min.
20
Max.
500000
Unit
us/V
1
Notes :
1. Sampled, not 100% tested.
2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to
"AC CHARACTERISTICS" table.
P/N: PM1514
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MX25L12836E
ERASE AND PROGRAMMING PERFORMANCE
PARAMETER
TYP. (1)
40
Max. (2)
100
300
2
UNIT
ms
ms
s
Write Status Register Cycle Time
Sector Erase Time (4KB)
Block Erase Time (64KB)
Block Erase Time (32KB)
60
0.7
0.5
2
s
64Mb
50
80
s
Chip Erase Time
128Mb
80
200
300
5
s
Byte Program Time (via page program command)
Page Program Time
9
us
1.4
ms
cycles
Erase/Program Cycle
100,000
Note:
1. Typical program and erase time assumes the following conditions: 25°C, 3.3V, and checker board pattern.
2. Under worst conditions of 85°C and 2.7V.
3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming com-
mand.
4. The maximum chip programming time is evaluated under the worst conditions of 0°C, VCC=3.0V, and 100K cy-
cle with 90% confidence level.
DATA RETENTION
PARAMETER
Condition
Min.
Max.
UNIT
Data retention
55˚C
20
years
LATCH-UP CHARACTERISTICS
MIN.
MAX.
Input Voltage with respect to GND on all power pins, SI, CS#
Input Voltage with respect to GND on SO
Current
-1.0V
-1.0V
-100mA
2 VCCmax
VCC + 1.0V
+100mA
Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.
P/N: PM1514
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MX25L6436E
MX25L12836E
ORDERING INFORMATION
64Mb
OPERATING
CURRENT
MAX. (mA)
STANDBY
CURRENT
MAX. (uA)
CLOCK
(MHz)
PART NO.
TEMPERATURE PACKAGE
Remark
8-SOP
-40°C~85°C
MX25L6436EM2I-10G
104
45
100
Pb-free
(200mil)
128Mb
OPERATING
CURRENT
MAX. (mA)
STANDBY
CURRENT
MAX. (uA)
CLOCK
(MHz)
PART NO.
TEMPERATURE PACKAGE
Remark
16-SOP
-40°C~85°C
MX25L12836EMI-10G
104
45
100
Pb-free
(300mil)
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MX25L6436E
MX25L12836E
PART NAME DESCRIPTION
MX 25 L 12836E
M
I
10 G
OPTION:
G: Pb-free
SPEED:
10: 104MHz
TEMPERATURE RANGE:
I: Industrial (-40° C to 85° C)
PACKAGE:
M: 300mil 16-SOP
M2: 200mil 8-SOP
DENSITY & MODE:
12836E: 128Mb standard type
6436E: 64Mb standard type
TYPE:
L: 3V
DEVICE:
25: Serial Flash
P/N: PM1514
REV. 1.1, NOV. 18, 2009
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MX25L6436E
MX25L12836E
PACKAGE INFORMATION
P/N: PM1514
REV. 1.1, NOV. 18, 2009
65
MX25L6436E
MX25L12836E
P/N: PM1514
REV. 1.1, NOV. 18, 2009
66
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MX25L12836E
REVISION HISTORY
Revision No. Description
Page
Date
1.1
1. Added 64Mb general feature description.
P5
NOV/18/2009
2. Aligned pin name.
P7,10,18,19,
P23,48,50
P5
P6,14,16,36
P36~38
P37
3. Update dummy cycle at 2 x I/O, 4 x I/O read mode.
4. Rename CFI to DMC.
5. Added DMC contents.
6. Revised Address 19 Data.
7. Revised Address 09 Data.
P38
P/N: PM1514
REV. 1.1, NOV. 18, 2009
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MX25L6436E
MX25L12836E
Macronix's products are not designed, manufactured, or intended for use for any high risk applications in which
the failure of a single component could cause death, personal injury, severe physical damage, or other substan-
tial harm to persons or property, such as life-support systems, high temperature automotive, medical, aircraft
and military application. Macronix and its suppliers will not be liable to you and/or any third party for any claims,
injuries or damages that may be incurred due to use of Macronix's products in the prohibited applications.
Copyright© Macronix International Co., Ltd. 2009. All Rights Reserved. Macronix, MXIC, MXIC Logo, MX Logo,
MXSMIO, are trademarks or registered trademarks of Macronix International Co., Ltd.. The names and brands
of other companies are for identification purposes only and may be claimed as the property of the respective
companies.
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M
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68
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