MX25U51245GMI00_技术文档

MX25U51245G

1.8V, 512M-BIT [x 1/x 2/x 4]

CMOS MXSMIO^®(SERIAL MULTI I/O)

FLASH MEMORY

Key Features

• Multi I/O Support - Single I/O, Dual I/O and Quad I/O

• Support DTR (Double Transfer Rate) Mode

• 8/16/32/64 byte Wrap-Around Read Mode

MX25U51245G

Contents

1. FEATURES ..............................................................................................................................................................5

2. GENERAL DESCRIPTION .....................................................................................................................................7

Table 1. Read performance Comparison ....................................................................................................7

3. PIN CONFIGURATIONS .........................................................................................................................................8

Table 2. PIN DESCRIPTION.......................................................................................................................8

4. BLOCK DIAGRAM...................................................................................................................................................9

5. MEMORY ORGANIZATION...................................................................................................................................10

6. DATA PROTECTION.............................................................................................................................................. 11

6-1. Block lock protection................................................................................................................................ 12

Table 3. Protected Area Sizes...................................................................................................................12

6-2. Additional 8K-bit secured OTP ................................................................................................................ 13

Table 4. 8K-bit Secured OTP Deﬁnition ....................................................................................................13

7. DEVICE OPERATION............................................................................................................................................14

7-1. 256Mb Address Protocol.......................................................................................................................... 16

7-2. Quad Peripheral Interface (QPI) Read Mode .......................................................................................... 19

8. COMMAND SET ....................................................................................................................................................20

Table 5. Read/Write Array Commands......................................................................................................20

Table 6. Read/Write Array Commands (4 Byte Address Command Set) ..................................................21

Table 7. Register/Setting Commands........................................................................................................22

Table 8. ID/Security Commands................................................................................................................23

Table 9. Reset Commands........................................................................................................................24

9. REGISTER DESCRIPTION....................................................................................................................................25

9-1. Status Register ........................................................................................................................................ 25

9-2. Conﬁguration Register............................................................................................................................. 26

9-3. Security Register ..................................................................................................................................... 28

Table 10. Security Register Deﬁnition .......................................................................................................28

10. COMMAND DESCRIPTION.................................................................................................................................29

10-1. Write Enable (WREN).............................................................................................................................. 29

10-2. Write Disable (WRDI)............................................................................................................................... 30

10-3. Read Identiﬁcation (RDID)....................................................................................................................... 31

10-4. Release from Deep Power-down (RDP), Read Electronic Signature (RES) ........................................... 32

10-5. Read Electronic Manufacturer ID & Device ID (REMS)........................................................................... 34

10-6. QPI ID Read (QPIID) ............................................................................................................................... 35

Table 11. ID Deﬁnitions ............................................................................................................................35

10-7. Read Status Register (RDSR)................................................................................................................. 36

10-8. Read Conﬁguration Register (RDCR)...................................................................................................... 37

10-9. Write Status Register (WRSR)................................................................................................................. 40

Table 12. Protection Modes.......................................................................................................................41

10-10. Enter 4-byte mode (EN4B) ...................................................................................................................... 44

10-11. Exit 4-byte mode (EX4B) ......................................................................................................................... 44

10-12. Read Data Bytes (READ) ........................................................................................................................ 45

10-13. Read Data Bytes at Higher Speed (FAST_READ) .................................................................................. 46

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10-14. Dual Output Read Mode (DREAD).......................................................................................................... 47

10-15. 2 x I/O Read Mode (2READ) ................................................................................................................... 48

10-16. Quad Read Mode (QREAD) .................................................................................................................... 49

10-17. 4 x I/O Read Mode (4READ) ................................................................................................................... 50

10-18. 4 x I/O Double Transfer Rate Read Mode (4DTRD)................................................................................ 52

10-19. Preamble Bit ........................................................................................................................................... 54

10-20. 4 Byte Address Command Set................................................................................................................. 58

10-21. Performance Enhance Mode................................................................................................................... 63

10-22. Burst Read............................................................................................................................................... 68

10-23. Fast Boot ................................................................................................................................................. 69

10-24. Sector Erase (SE).................................................................................................................................... 72

10-25. Block Erase (BE32K)............................................................................................................................... 73

10-26. Block Erase (BE) ..................................................................................................................................... 74

10-27. Chip Erase (CE)....................................................................................................................................... 75

10-28. Page Program (PP) ................................................................................................................................. 76

10-29. 4 x I/O Page Program (4PP).................................................................................................................... 78

10-30. Deep Power-down (DP)........................................................................................................................... 79

10-31. Enter Secured OTP (ENSO).................................................................................................................... 80

10-32. Exit Secured OTP (EXSO)....................................................................................................................... 80

10-33. Read Security Register (RDSCUR)......................................................................................................... 80

10-34. Write Security Register (WRSCUR)......................................................................................................... 80

10-35. Write Protection Selection (WPSEL)........................................................................................................ 81

10-36. Advanced Sector Protection .................................................................................................................... 83

10-37. Program Suspend and Erase Suspend ................................................................................................... 91

Table 13. Acceptable Commands During Suspend..................................................................................92

10-38. Program Resume and Erase Resume..................................................................................................... 93

10-39. No Operation (NOP) ................................................................................................................................ 94

10-40. Software Reset (Reset-Enable (RSTEN) and Reset (RST)) ................................................................... 94

11. Serial Flash Discoverable Parameter (SFDP)...................................................................................................96

11-1. Read SFDP Mode (RDSFDP).................................................................................................................. 96

Table 14. Signature and Parameter Identiﬁcation Data Values ................................................................97

Table 15. Parameter Table (0): JEDEC Flash Parameter Tables..............................................................99

Table 16. Parameter Table (1): 4-Byte Instruction Tables .......................................................................106

Table 17. Parameter Table (2): Macronix Flash Parameter Tables .........................................................108

12. RESET................................................................................................................................................................ 110

Table 18. Reset Timing-(Power On)........................................................................................................110

Table 19. Reset Timing-(Other Operation) ..............................................................................................110

13. POWER-ON STATE........................................................................................................................................... 111

14. ELECTRICAL SPECIFICATIONS...................................................................................................................... 112

Table 20. ABSOLUTE MAXIMUM RATINGS ..........................................................................................112

Table 21. CAPACITANCE TA = 25°C, f = 1.0 MHz..................................................................................112

Table 22. DC CHARACTERISTICS ........................................................................................................114

Table 23. AC CHARACTERISTICS.........................................................................................................115

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15. OPERATING CONDITIONS............................................................................................................................... 117

Table 24. Power-Up/Down Voltage and Timing ......................................................................................119

15-1. INITIAL DELIVERY STATE.....................................................................................................................119

16. ERASE AND PROGRAMMING PERFORMANCE............................................................................................120

17. DATA RETENTION ............................................................................................................................................120

18. LATCH-UP CHARACTERISTICS......................................................................................................................120

19. ORDERING INFORMATION..............................................................................................................................121

20. PART NAME DESCRIPTION.............................................................................................................................122

21. PACKAGE INFORMATION................................................................................................................................123

22. REVISION HISTORY .........................................................................................................................................126

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MX25U51245G

1.8V 512M-BIT [x 1/x 2/x 4] CMOS MXSMIO^(SERIAL MULTI I/O)

FLASH MEMORY

1. FEATURES

GENERAL

•

Supports Serial Peripheral Interface -- Mode 0 and Mode 3

Single Power Supply Operation

- 1.65 to 2.0 volt for read, erase, and program operations

512Mb: 536,870,912 x 1 bit structure or 268,435,456 x 2 bits (two I/O mode) structure or 134,217,728 x 4 bits (four

I/O mode) structure

•

Protocol Support

- Single I/O, Dual I/O and Quad I/O

•

Latch-up protected to 100mA from -1V to Vcc +1V

Fast read for SPI mode

- Support fast clock frequency up to 166MHz

- Support Fast Read, 2READ, DREAD, 4READ, QREAD instructions

- Support DTR (Double Transfer Rate) Mode

- Conﬁgurable dummy cycle number for fast read operation

Quad Peripheral Interface (QPI) available

•

Equal Sectors with 4K byte each, or Equal Blocks with 32K byte each or Equal Blocks with 64K byte each

- Any Block can be erased individually

•

Programming :

- 256byte page buffer

- Quad Input/Output page program(4PP) to enhance program performance

Typical 100,000 erase/program cycles

20 years data retention

•

SOFTWARE FEATURES

•

Input Data Format

- 1-byte Command code

•

Advanced Security Features

- Block lock protection

The BP0-BP3 and T/B status bits deﬁne the size of the area to be protected against program and erase

instructions

- Advanced sector protection function

Additional 8K bit security OTP

•

Features unique identiﬁer

Factory locked identiﬁable, and customer lockable

Command Reset

-

•

Program/Erase Suspend and Resume operation

Electronic Identiﬁcation

JEDEC 1-byte manufacturer ID and 2-byte device ID

- RES command for 1-byte Device ID

-

- REMS command for 1-byte manufacturer ID and 1-byte device ID

Support Serial Flash Discoverable Parameters (SFDP) mode

•

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MX25U51245G

HARDWARE FEATURES

•

SCLK Input

- Serial clock input

SI/SIO0

- Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode

SO/SIO1

- Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode

WP#/SIO2

- Hardware write protection or serial data Input/Output for 4 x I/O read mode

RESET#

- Hardware Reset pin

RESET#/SIO3 * or NC/SIO3 *

- Hardware Reset pin or Serial input & Output for 4 x I/O read mode

or

- No Connection or Serial input & Output for 4 x I/O read mode

* Depends on part number options

PACKAGE

•

- 16-pin SOP (300mil)

- 24-Ball BGA (5x5 ball array)

- 8-land WSON (8x6mm 3.4 x 4.3EP)

- All devices are RoHS Compliant and Halogen-free

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2. GENERAL DESCRIPTION

MX25U51245G is 512Mb bits Serial NOR Flash memory, which is conﬁgured as 67,108,864 x 8 internally. When

it is in two or four I/O mode, the structure becomes 268,435,456 bits x 2 or 134,217,728 bits x 4. MX25U51245G

feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in

single I/O mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO).

Serial access to the device is enabled by CS# input.

When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits

input and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# and RESET# pin become SIO0

pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output.

The MX25U51245G MXSMIO^(Serial Multi I/O) provides sequential read operation on whole chip.

After program/erase command is issued, auto program/erase algorithms which program/erase and verify the

speciﬁed page or sector/block locations will be executed. Program command is executed on byte basis, or page (256

bytes) basis, or word basis for erase command is executed on sector (4K-byte), block (32K-byte), or block (64K-byte),

or whole chip basis.

To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read

command can be issued to detect completion status of a program or erase operation via WIP bit.

Advanced security features enhance the protection and security functions, please see security features section for

more details.

When the device is not in operation and CS# is high, it is put in standby mode.

The MX25U51245G utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after

100,000 program and erase cycles.

Table 1. Read performance Comparison

Dual Output Quad Output

Dual IO

Fast Read

(MHz)

Quad IO

Fast Read

(MHz)

Quad I/O DT

Read

Numbers of

Dummy Cycles

Fast Read

(MHz)

Fast Read

(MHz)

Fast Read

(MHz)

4

6

-

84*

104

133

166

70

42

52*

66

133

133*

166

133

133*

166

104

133*

166

84*

104

133

8

10

100

Note: * mean default status

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3. PIN CONFIGURATIONS

16-PIN SOP (300mil)

Table 2. PIN DESCRIPTION

1

2

3

4

5

6

7

8

SCLK

SI/SIO0

NC

NC/SIO3

VCC

16

15

14

13

12

11

10

9

SYMBOL

CS#

SCLK

DESCRIPTION

Chip Select

Clock Input

RESET#

NC

DNU

RESET#

Hardware Reset Pin Active low ^(Note1)

Serial Data Input (for 1 x I/O)/ Serial

Data Input & Output (for 2xI/O or 4xI/

O read mode)

DNU

GND

CS#

WP#/SIO2

SO/SIO1

SI/SIO0

Serial Data Output (for 1 x I/O)/ Serial

Data Input & Output (for 2xI/O or 4xI/

O read mode)

SO/SIO1

8-WSON (8x6mm 3.4 x 4.3EP)

Write Protection Active Low or Serial

WP#/SIO2 Data Input & Output (for 4xI/O read

1

2

3

4

VCC

CS#

SO/SIO1

WP#/SIO2

GND

8

7

6

5

RESET#/SIO3

SCLK

mode)

No Connection or Serial Data Input &

Output (for 4xI/O read mode)

NC/SIO3 *

SI/SIO0

Hardware Reset Pin Active low or

RESET#/SIO3 * Serial Data Input & Output (for 4xI/O

read mode)

VCC

GND

NC

Power Supply

Ground

No Connection

Do Not Use (It may connect to

internal signal inside)

24-Ball BGA (5x5 ball array)

1

2

3

4

5

DNU

* Depends on part number options.

A

B

C

D

E

NC

RESET#

VCC

DNU

NC

Note:

1. The pin of RESET#, RESET#/SIO3 or WP#/SIO2

will remain internal pull up function while this pin is

not physically connected in system conﬁguration.

However, the internal pull up function will be

disabled if the system has physical connection to

RESET#, RESET#/SIO3 or WP#/SIO2 pin.

NC

SCLK

GND

CS#

WP#/SIO2

NC

SO/SIO1 SI/SIO0 NC/SIO3

NC

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4. BLOCK DIAGRAM

Address

Generator

Memory Array

Y-Decoder

SI/SIO0

SO/SIO1

SIO2 *

Data

SIO3 *

Register

WP# *

SRAM

Buffer

Sense

Amplifier

HOLD# *

RESET# *

CS#

Mode

Logic

State

Machine

HV

Generator

SCLK

Clock Generator

Output

Buffer

* Depends on part number options.

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5. MEMORY ORGANIZATION

Block(64K-byte) Block(32K-byte)

Sector

16383

Address Range

3FFF000h

3FFFFFFh

2047

individual 16 sectors

lock/unlock unit:4K-byte

16376

16375

3FF8000h

3FF7000h

3FF8FFFh

3FF7FFFh

1023

2046

2045

2044

2043

2042

16368

16367

3FF0000h

3FEF000h

3FF0FFFh

3FEFFFFh

16360

16359

3FE8000h

3FE7000h

3FE8FFFh

3FE7FFFh

1022

individual block

lock/unlock unit:64K-byte

16352

16351

3FE0000h

3FDF000h

3FE0FFFh

3FDFFFFh

16344

16343

3FD8000h

3FD7000h

3FD8FFFh

3FD7FFFh

1021

16336

3FD0000h

3FD0FFFh

individual block

lock/unlock unit:64K-byte

47

002F000h

002FFFFh

5

4

3

2

1

0

40

39

0028000h

027000h

0028FFFh

0027FFFh

2

1

individual block

lock/unlock unit:64K-byte

32

31

0020000h

001F000h

0020FFFh

001FFFFh

24

23

0018000h

0017000h

0018FFFh

0017FFFh

16

15

0010000h

000F000h

0010FFFh

000FFFFh

individual 16 sectors

lock/unlock unit:4K-byte

8

7

0008000h

0007000h

0008FFFh

0007FFFh

0

0000000h

0000FFFh

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MX25U51245G

6. DATA PROTECTION

During power transition, there may be some false system level signals which result in inadvertent erasure or

programming. The device is designed to protect itself from these accidental write cycles.

The state machine will be reset as standby mode automatically during power up. In addition, the control register

architecture of the device constrains that the memory contents can only be changed after speciﬁc command

sequences have completed successfully.

In the following, there are several features to protect the system from the accidental write cycles during VCC power-

up and power-down or from system noise.

•

Valid command length checking: The command length will be checked whether it is at byte base and completed

on byte boundary.

Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before

other command to change data.

Deep Power Down Mode: By entering deep power down mode, the ﬂash device also is under protected from

writing all commands except Release from deep power down mode command (RDP) and Read Electronic

Signature command (RES), Erase/Program suspend command, Erase/Program resume command and softreset

command.

•

Advanced Security Features: there are some protection and security features which protect content from

inadvertent write and hostile access.

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MX25U51245G

6-1. Block lock protection

- The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0 and T/B) bits to allow part of memory to be

protected as read only. The protected area deﬁnition is shown as "Table 3. Protected Area Sizes", the protected

areas are more ﬂexible which may protect various area by setting value of BP0-BP3 bits.

- The Hardware Protected Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and Status

Register Write Protect bit.

- In four I/O and QPI mode, the feature of HPM will be disabled.

Table 3. Protected Area Sizes

Protected Area Sizes (T/B bit = 0)

Status bit

Protect Level

512Mb

BP3

0

BP2

BP1

0

BP0

0

1

0

1

0 (none)

0

1

1 (1 block, protected block 1023rd)

0

1

0

2 (2 blocks, protected block 1022nd~1023rd)

3 (4 blocks, protected block 1020th~1023rd)

4 (8 blocks, protected block 1016th~1023rd)

5 (16 blocks, protected block 1008th~1023rd)

6 (32 blocks, protected block 992nd~1023rd)

7 (64 blocks, protected block 960th~1023rd)

8 (128 blocks, protected block 896th~1023rd)

9 (256 blocks, protected block 768th~1023rd)

10 (512 blocks, protected block 512nd~1023rd)

11 (1024 blocks, protected all)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

12 (1024 blocks, protected all)

1

0

1

13 (1024 blocks, protected all)

1

0

14 (1024 blocks, protected all)

1

15 (1024 blocks, protected all)

Protected Area Sizes (T/B bit = 1)

Status bit

Protect Level

512Mb

BP3

0

BP2

0

BP1

0

BP0

0

0 (none)

0

1

1 (1 block, protected block 0th)

2 (2 blocks, protected block 0th~1st)

3 (4 blocks, protected block 0th~3rd)

4 (8 blocks, protected block 0th~7th)

5 (16 blocks, protected block 0th~15th)

6 (32 blocks, protected block 0th~31st)

7 (64 blocks, protected block 0th~63rd)

8 (128 blocks, protected block 0th~127th)

9 (256 blocks, protected block 0th~255th)

10 (512 blocks, protected block 0th~511th)

11 (1024 blocks, protected all)

12 (1024 blocks, protected all)

13 (1024 blocks, protected all)

14 (1024 blocks, protected all)

15 (1024 blocks, protected all)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

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MX25U51245G

6-2. Additional 8K-bit secured OTP

The secured OTP for unique identiﬁer: to provide 8K-bit one-time program area for setting device unique serial

number. Which may be set by factory or system customer.

- Security register bit 0 indicates whether the chip is locked by factory or not.

- To program the 8K-bit secured OTP by entering secured OTP mode (with Enter Security OTP command), and

going through normal program procedure, and then exiting secured OTP mode by writing Exit Security OTP

command.

- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register)

command to set customer lock-down bit1 as "1". Please refer to "Table 10. Security Register Deﬁnition" for

security register bit deﬁnition and "Table 4. 8K-bit Secured OTP Deﬁnition" for address range deﬁnition.

- Note: Once lock-down by factory or customer, the corresponding range cannot be changed any more. While in

secured OTP mode, array access is not allowed.

Table 4. 8K-bit Secured OTP Deﬁnition

Address range

xxx000~xxx1FF

xxx200~xxx3FF

Size

Lock-down

4096-bit

Determined by Customer

Determined by Factory

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MX25U51245G

7. DEVICE OPERATION

1. Before a command is issued, status register should be checked to ensure device is ready for the intended

operation.

2. When incorrect command is inputted to this device, this device becomes standby mode and keeps the standby

mode until next CS# falling edge. In standby mode, SO pin of this device should be High-Z.

3. When correct command is inputted to this device, this device becomes active mode and keeps the active mode

until next CS# rising edge.

4. Input data is latched on the rising edge of Serial Clock (SCLK) and data shifts out on the falling edge of SCLK.

The difference of Serial mode 0 and mode 3 is shown as "Serial Modes Supported".

5. For the following instructions: RDID, RDSR, RDSCUR, READ/READ4B, FAST_READ/FAST_READ4B,

2READ/2READ4B, DREAD/DREAD4B, 4READ/4READ4B, QREAD/QREAD4B, RDSFDP, RES, REMS,

QPIID, RDDPB, RDSPB, RDLR, RDEAR, RDFBR, RDCR, the shifted-in instruction sequence is followed by a

data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions:

WREN, WRDI, WRSR, SE/SE4B, BE32K/BE32K4B, BE/BE4B, CE, PP/PP4B, 4PP/4PP4B, DP, ENSO, EXSO,

WRSCUR, EN4B, EX4B, WPSEL, GBLK, GBULK, SUSPEND, RESUME, NOP, RSTEN, RST, EQIO, RSTQIO

the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.

6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is

neglected and not affect the current operation of Write Status Register, Program, Erase.

Figure 1. Serial Modes Supported

CPOL CPHA

shift in

shift out

SCLK

(Serial mode 0)

(Serial mode 3)

0

1

0

1

SI

MSB

SO

MSB

Note:

CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not

transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is

supported.

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MX25U51245G

Figure 2. Serial Input Timing

tSHSL

tSHCH

tCHCL

CS#

tCHSL

tSLCH

tCHSH

SCLK

tDVCH

tCHDX

tCLCH

MSB

LSB

SI

High-Z

SO

Figure 3. Output Timing (STR mode)

CS#

tCH

SCLK

tCLQV

tCL

tSHQZ

tCLQX

LSB

SO

SI

ADDR.LSB IN

Figure 4. Output Timing (DTR mode)

CS#

tCH

SCLK

tCLQV

tCLQX

tCLQV

tCL

tSHQZ

tCLQX

LSB

SO

SI

ADDR.LSB IN

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MX25U51245G

7-1. 256Mb Address Protocol

The original 24 bit address protocol of Serial NOR Flash can only access density size below 128Mb. For the

memory device of 256Mb and above, the 32bit address is requested for access higher memory size. The

MX25U51245G provides three different methods to access the whole density:

(1) Command entry 4-byte address mode:

Issue Enter 4-Byte mode command to set up the 4BYTE bit in Conﬁguration Register bit. After 4BYTE bit has

been set, the number of address cycle become 32-bit.

(2) Extended Address Register (EAR):

conﬁgure the memory device into four 128Mb segments to select which one is active through the EAR<0-1>.

(3) 4-byte Address Command Set:

When issuing 4-byte address command set, 4-byte address (A31-A0) is requested after the instruction code.

Please note that it is not necessary to issue EN4B command before issuing any of 4-byte command set.

Enter 4-Byte Address Mode

In 4-byte Address mode, all instructions are 32-bits address clock cycles. By using EN4B and EX4B to enable and

disable the 4-byte address mode.

When 4-byte address mode is enabled, the EAR<0-1> becomes "don't care" for all instructions requiring 4-byte

address. The EAR function will be disabled when 4-byte mode is enabled.

Extended Address Register

The device provides an 8-bit volatile register for extended Address Register: it identiﬁes the extended address (A31~A24)

above 128Mb density by using original 3-byte address.

Extended Address Register (EAR)

Bit 7

A31

Bit 6

A30

Bit 5

A29

Bit 4

A28

Bit 3

A27

Bit 2

A26

Bit 1

A25

Bit 0

A24

For the MX25U51245G the A31 to A26 are Don't Care. During EAR, reading these bits will read as 0. The bit 0 is

default as "0".

P/N: PM2244

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Figure 7. EAR Operation Segments

03FFFFFFh

EAR<1-0>= 11

03000000h

02FFFFFFh

EAR<1-0>= 10

EAR<1-0>= 01

02000000h

01FFFFFFh

01000000h

00FFFFFFh

EAR<1-0>= 00

00000000h

When under EAR mode, Read, Program, Erase operates in the selected segment by using 3-byte address mode.

For the read operation, the whole array data can be continually read out with one command. Data output starts from

the selected top or bottom 128Mb, but it can cross the boundary. When the last byte of the segment is reached,

the next byte (in a continuous reading) is the ﬁrst byte of the next segment. However, the EAR (Extended Address

Register) value does not change. The random access reading can only be operated in the selected segment.

The Chip erase command will erase the whole chip and is not limited by EAR selected segment. However, the

sector erase ,block erase , program operation are limited in selected segment and will not cross the boundary.

Figure 5. Write EAR Register (WREAR) Sequence (SPI Mode)

CS#

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

Mode 3

Mode 0

SCLK

command

C5h

EAR In

SI

4

2

1

0

7

6

5

3

MSB

High-Z

SO

Figure 6. Write EAR Register (WREAR) Sequence (QPI Mode)

CS#

Mode 3

Mode 0

Mode 3

Mode 0

0

1

2

3

SCLK

EAR in

Command

C5h

H0 L0

SIO[3:0]

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Figure 8. Read EAR (RDEAR) Sequence (SPI Mode)

CS#

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

Mode 3

Mode 0

SCLK

SI

command

C8h

EAR Out

High-Z

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

MSB

Figure 9. Read EAR (RDEAR) Sequence (QPI Mode)

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

N

SCLK

SIO[3:0]

C8h

H0 L0 H0 L0 H0 L0

H0 L0

MSB LSB

EAR Out

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7-2. Quad Peripheral Interface (QPI) Read Mode

QPI protocol enables user to take full advantage of Quad I/O Serial NOR Flash by providing the Quad I/O interface

in command cycles, address cycles and as well as data output cycles.

Enable QPI mode

By issuing command EQIO(35h), the QPI mode is enabled.

Figure 10. Enable QPI Sequence

CS#

MODE 3

MODE 0

2

3

4

5

6

7

0

1

SCLK

SIO0

35h

SIO[3:1]

Reset QPI (RSTQIO)

To reset the QPI mode, the RSTQIO (F5H) command is required. After the RSTQIO command is issued, the device

returns from QPI mode (4 I/O interface in command cycles) to SPI mode (1 I/O interface in command cycles).

Note:

For EQIO and RSTQIO commands, CS# high width has to follow "write spec" tSHSL for next instruction.

Figure 11. Reset QPI Mode

CS#

SCLK

SIO[3:0]

F5h

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8. COMMAND SET

Table 5. Read/Write Array Commands

4READ

2READ

(2 x I/O read

command)

Command

(byte)

READ

FAST READ

DREAD

(1I 2O read)

QREAD

(1I 4O read) I/O DT Read)

4DTRD (Quad

(4 I/O read start

from bottom

128Mb)

(normal read) (fast read data)

Mode

Address Bytes

1st byte

SPI

3/4

SPI

3/4

SPI

3/4

SPI

3/4

SPI/QPI

3/4

SPI

3/4

SPI/QPI

3/4

03 (hex)

ADD1

ADD2

ADD3

0B (hex)

ADD1

ADD2

ADD3

Dummy*

BB (hex)

ADD1

ADD2

ADD3

Dummy*

3B (hex)

ADD1

ADD2

ADD3

Dummy*

EB (hex)

ADD1

6B (hex)

ADD1

ADD2

ADD3

Dummy*

ED (hex)

ADD1

2nd byte

3rd byte

ADD2

4th byte

ADD3

5th byte

Dummy*

Data Cycles

n bytes read

out until CS# out until CS# out by 2 x I/O

goes high

n bytes read

out by Dual

until CS# goes output until

n bytes read Quad I/O read n bytes read

n bytes read

out (Double

for bottom

out by Quad

goes high

128Mb with 6

output until Transfer Rate)

Action

high

CS# goes high dummy cycles CS# goes high by 4xI/O until

CS# goes high

4PP

(quad page

program)

BE 32K

(block erase

32KB)

BE

Command

(byte)

PP

SE

CE

(chip erase)

(block erase

64KB)

(page program)

(sector erase)

Mode

Address Bytes

1st byte

SPI/QPI

3/4

SPI

3/4

SPI/QPI

3/4

SPI/QPI

3/4

SPI/QPI

3/4

SPI/QPI

0

02 (hex)

38 (hex)

ADD1

ADD2

ADD3

20 (hex)

ADD1

ADD2

ADD3

52 (hex)

ADD1

ADD2

ADD3

D8 (hex)

ADD1

ADD2

ADD3

60 or C7 (hex)

2nd byte

3rd byte

4th byte

5th byte

Data Cycles

1-256

to program the quad input to

selected page program the selected sector selected 32K selected block

selected page block

to erase the

to erase the to erase whole

chip

Action

* Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in conﬁguration register.

Notes 2: Please note the address cycles above are based on 3-byte address mode. After enter 4-byte address

mode by EN4B command, the address cycles will be increased to 4byte.

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Table 6. Read/Write Array Commands (4 Byte Address Command Set)

4DTRD4B

(Quad I/O DT

Read)

Command

(byte)

FAST

READ4B

2READ4B

DREAD4B

4READ4B

QREAD4B

Mode

Address Bytes

1st byte

SPI

4

SPI

4

SPI

4

SPI

4

SPI/QPI

4

SPI

4

SPI/QPI

4

13 (hex)

0C (hex)

BC (hex)

3C (hex)

EC (hex)

6C (hex)

EE (hex)

2nd byte

3rd byte

ADD1

ADD2

ADD3

ADD4

ADD1

ADD2

ADD1

ADD2

ADD1

ADD2

ADD1

ADD2

ADD1

ADD2

ADD1

ADD2

4th byte

ADD3

5th byte

ADD4

6th byte

Dummy*

Data Cycles

read data byte read data byte read data byte Read data byte read data byte

by by

Read data

n bytes read

out (Double

by 2 x I/O with by Dual Output by 4 x I/O with byte by Quad

4 byte address 4 byte address 4 byte address with 4 byte 4 byte address Output with 4 Transfer Rate)

Action

address

byte address by 4xI/O until

CS# goes high

BE4B

(block erase

64KB)

SPI/QPI

4

BE32K4B

(block erase (Sector erase

32KB)

SPI/QPI

4

SE4B

Command

(byte)

PP4B

4PP4B

4KB)

SPI/QPI

4

Mode

Address Bytes

1st byte

SPI/QPI

4

SPI

4

12 (hex)

3E (hex)

DC (hex)

5C (hex)

21 (hex)

2nd byte

3rd byte

ADD1

ADD2

ADD3

ADD4

ADD1

ADD2

ADD3

ADD4

ADD1

ADD2

ADD3

ADD4

ADD1

ADD2

ADD3

ADD4

ADD1

ADD2

ADD3

ADD4

4th byte

5th byte

6th byte

Data Cycles

1-256

to program the Quad input to

to erase the

selected page program the selected (64KB) selected (32KB) selected (4KB)

with 4byte

address

selected page

with 4byte

address

block with

sector with

Action

4byte address 4byte address 4byte address

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Table 7. Register/Setting Commands

RDCR

(read

WRSR

RDEAR

WREAR

RDSR

(read status

register)

Command

(byte)

WREN

WRDI

(write status/ (read extended (write extended

(write enable) (write disable)

conﬁguration conﬁguration

address

register)

address

register)

SPI/QPI

15 (hex)

register)

SPI/QPI

01 (hex)

Values

Mode

1st byte

SPI/QPI

06 (hex)

SPI/QPI

04 (hex)

SPI/QPI

05 (hex)

SPI/QPI

C8 (hex)

SPI/QPI

C5 (hex)

2nd byte

3rd byte

4th byte

Values

5th byte

Data Cycles

1-2

1

sets the (WEL)

write enable

latch bit

resets the

(WEL) write

enable latch bit status register conﬁguration

to read out the to read out the to write new read extended write extended

values of the values of the values of the

address

register

address

register

status/

conﬁguration

register

Action

register

PGM/ERS

Suspend

(Suspends

Program/

Erase)

PGM/ERS

Resume

(Resumes

Program/

Erase)

WPSEL

(Write Protect

Selection)

EN4B

(enter 4-byte

mode)

EX4B

(exit 4-byte

mode)

Command

(byte)

EQIO

(Enable QPI)

RSTQIO

(Reset QPI)

Mode

1st byte

SPI

QPI

SPI/QPI

B7 (hex)

SPI/QPI

E9 (hex)

SPI/QPI

68 (hex)

35 (hex)

F5 (hex)

B0 (hex)

30 (hex)

2nd byte

3rd byte

4th byte

5th byte

Data Cycles

to enter and

Entering the Exiting the QPI to enter 4-byte to exit 4-byte

enable individal QPI mode

block protect

mode

mode and set mode and clear

4BYTE bit as 4BYTE bit to

Action

mode

"1"

be "0"

DP

(Deep power

down)

RDP (Release

from deep

power down)

SBL

RDFBR

WRFBR

ESFBR

Command

(byte)

(Set Burst

Length)

SPI/QPI

(read fast boot (write fast boot (erase fast

register)

SPI

register)

SPI

boot register)

Mode

1st byte

SPI/QPI

SPI

B9 (hex)

AB (hex)

C0 (hex)

16(hex)

17(hex)

18(hex)

2nd byte

3rd byte

4th byte

5th byte

Data Cycles

1-4

4

enters deep

power down

mode

release from

deep power

down mode

to set Burst

length

Action

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Table 8. ID/Security Commands

REMS

(read electronic

manufacturer & (QPI ID Read)

device ID)

RDID

RES

ENSO

EXSO

Command

(byte)

QPIID

(read identiﬁc- (read electronic

RDSFDP

(enter secured (exit secured

ation)

ID)

OTP)

Mode

Address Bytes

1st byte

SPI

0

SPI/QPI

0

SPI

0

QPI

0

SPI/QPI

3

SPI/QPI

0

SPI/QPI

0

9F (hex)

AB (hex)

90 (hex)

AF (hex)

5A (hex)

B1 (hex)

C1 (hex)

2nd byte

3rd byte

4th byte

5th byte

x

ADD1

ADD2

ADD1

ADD3

Dummy(8)^{(Note 4)}

outputs JEDEC to read out

output the

ID in QPI

interface

Read SFDP

mode

to enter the

secured OTP secured OTP

to exit the

ID: 1-byte

Manufacturer

ID & 2-byte

Device ID

1-byte Device Manufacturer

ID

ID & Device ID

mode

Action

RDSCUR

WRSCUR

GBLK

GBULK

(gang block

unlock)

WRLR

(write Lock

register)

SPI

RDLR

(read Lock

register)

SPI

WRSPB

(SPB bit

program)

SPI

Command

(byte)

(read security (write security (gang block

register)

SPI/QPI

0

register)

SPI/QPI

0

lock)

SPI

0

Mode

Address Bytes

1st byte

SPI

0

4

2B (hex)

2F (hex)

7E (hex)

98 (hex)

2C (hex)

2D (hex)

E3 (hex)

ADD1

ADD2

ADD3

ADD4

2nd byte

3rd byte

4th byte

5th byte

Data Cycles

2

to read value to set the lock- whole chip

whole chip

unprotect

of security

register

down bit as

"1" (once lock-

down, cannot

be updated)

write protect

Action

ESSPB

(all SPB bit

erase)

RDSPB

(read SPB

status)

WRDPB

(write DPB

register)

SPI

RDDPB

RDPASS

WRPASS

PASSULK

Command

(byte)

(read DPB (read password (write password (password

register)

SPI

4

register)

SPI

4

unlock)

SPI

Mode

Address Bytes

1st byte

SPI

4

0

4

E4 (hex)

E2 (hex)

ADD1

ADD2

ADD3

ADD4

E1 (hex)

ADD1

ADD2

ADD3

ADD4

E0 (hex)

ADD1

ADD2

ADD3

ADD4

27 (hex)

ADD1

28 (hex)

ADD1

ADD2

ADD3

ADD4

29 (hex)

ADD1

ADD2

ADD3

ADD4

2nd byte

3rd byte

ADD2

4th byte

ADD3

5th byte

ADD4

6th byte

Dummy(8)^{(Note 4)}

Data Cycles

1

8

Action

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Table 9. Reset Commands

RST

(Reset

Memory)

Command

(byte)

NOP

RSTEN

(No Operation) (Reset Enable)

Mode

SPI/QPI

00 (hex)

SPI/QPI

66 (hex)

SPI/QPI

99 (hex)

1st byte

2nd byte

3rd byte

4th byte

5th byte

Action

Note 1: ADD=00H will output the manufacturer ID ﬁrst and ADD=01H will output device ID ﬁrst.

Note 2: It is not recommended to adopt any other code not in the command deﬁnition table, which will potentially enter the hid-

den mode.

Note 3: The RSTEN command must be executed before executing the RST command. If any other command is issued

in-between RSTEN and RST, the RST command will be ignored.

Note 4: The number in parentheses after “ADD” or “Data” or “Dummy” stands for how many clock cycles it has. For example,

"Data(8)" represents there are 8 clock cycles for the data in. Please note the number after "ADD" are based on 3-byte

address mode, for 4-byte address mode, which will be increased.

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9. REGISTER DESCRIPTION

9-1. Status Register

The deﬁnition of the status register bits is as below:

WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write

status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status

register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status

register cycle.

WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable

latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/

erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the

device will not accept program/erase/write status register instruction. The program/erase command will be ignored

if it is applied to a protected memory area. To ensure both WIP bit & WEL bit are both set to 0 and available for next

program/erase/operations, WIP bit needs to be conﬁrm to be 0 before polling WEL bit. After WIP bit conﬁrmed, WEL

bit needs to be conﬁrm to be 0.

BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area

(as deﬁned in Table 3) of the device to against the program/erase instruction without hardware protection mode being

set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to

be executed. Those bits deﬁne the protected area of the memory to against Page Program (PP), Sector Erase (SE),

Block Erase 32KB (BE32K), Block Erase (BE) and Chip Erase (CE) instructions (only if Block Protect bits (BP3:BP0)

set to 0, the CE instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as default. Which is un-protected.

QE bit. The Quad Enable (QE) bit, non-volatile bit, while it is "0" (factory default), it performs non-Quad and WP#,

RESET# are enable. While QE is "1", it performs Quad I/O mode and WP#, RESET# are disabled. In the other

word, if the system goes into four I/O mode (QE=1), the feature of HPM and RESET will be disabled.

SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection

(WP#/SIO2) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and

WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is

no longer accepted for execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are read only. The

SRWD bit defaults to be "0".

Status Register

bit7

bit6

bit5

BP3

(level of

protected

block)

bit4

BP2

(level of

protected

block)

bit3

BP1

(level of

protected

block)

bit2

BP0

(level of

protected

block)

bit1

bit0

SRWD (status

register write

protect)

QE

(Quad

Enable)

WEL

(write enable

latch)

WIP

(write in

progress bit)

1=status

register write

disabled

0=status

register write

enabled

1=Quad

Enable

0=not Quad

Enable

1=write

enable

0=not write 0=not in write

1=write

operation

(note 1)

enable

operation

Non-volatile Non-volatile Non-volatile Non-volatile Non-volatile Non-volatile

bit bit bit bit bit bit

volatile bit

Note 1: see the "Table 3. Protected Area Sizes".

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MX25U51245G

9-2. Conﬁguration Register

The Conﬁguration Register is able to change the default status of Flash memory. Flash memory will be conﬁgured

after the CR bit is set.

ODS bit

The output driver strength (ODS2, ODS1, ODS0) bits are volatile bits, which indicate the output driver level (as

deﬁned in Output Driver Strength Table) of the device. The Output Driver Strength is defaulted as 30 Ohms when

delivered from factory. To write the ODS bits requires the Write Status Register (WRSR) instruction to be executed.

TB bit

The Top/Bottom (TB) bit is a non-volatile OTP bit. The Top/Bottom (TB) bit is used to conﬁgure the Block Protect

area by BP bit (BP3, BP2, BP1, BP0), starting from TOP or Bottom of the memory array. The TB bit is defaulted as

“0”, which means Top area protect. When it is set as “1”, the protect area will change to Bottom area of the memory

device. To write the TB bits requires the Write Status Register (WRSR) instruction to be executed.

PBE bit

The Preamble Bit Enable (PBE) bit is a volatile bit. It is used to enable or disable the preamble bit data pattern

output on dummy cycles. The PBE bit is defaulted as “0”, which means preamble bit is disabled. When it is set as “1”,

the preamble bit will be enabled, and inputted into dummy cycles. To write the PBE bits requires the Write Status

Register (WRSR) instruction to be executed.

4BYTE Indicator bit

By writing EN4B instruction, the 4BYTE bit may be set as "1" to access the address length of 32-bit for memory area

of higher density (large than 128Mb). The default state is "0" as the 24-bit address mode. The 4BYTE bit may be

cleared by power-off or writing EX4B instruction to reset the state to be "0".

Conﬁguration Register

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

DC1

DC0

PBE

TB

ODS 2

ODS 1

ODS 0

(Dummy

cycle 1)

(Dummy

cycle 0)

4 BYTE

(Preamble bit (top/bottom (output driver (output driver (output driver

Enable)

selected)

strength)

0=3-byte

address

mode

1=4-byte

address

mode

0=Top area

protect

1=Bottom

area protect

(Default=0)

0=Disable

1=Enable

(note 2)

(note 1)

(Default=0)

volatile bit

OTP

volatile bit

Note 1: see "Output Driver Strength Table"

Note 2: see "Dummy Cycle and Frequency Table (MHz)"

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MX25U51245G

Output Driver Strength Table

ODS2

ODS1

ODS0

Description

146 Ohms

76 Ohms

52 Ohms

41 Ohms

34 Ohms

30 Ohms

26 Ohms

Note

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Impedance at VCC/2

(Typical)

24 Ohms (Default)

Dummy Cycle and Frequency Table (MHz)

Numbers of

Dual Output Fast Quad Output

DC[1:0]

Dummy clock

Fast Read

Read

Fast Read

cycles

00 (default)

8

6

8

133

166

133

166

133

104

133

166

01

10

11

10

Numbers of

Dummy clock

Dual IO Fast

Read

DC[1:0]

cycles

00 (default)

4

6

8

84

01

10

11

104

133

166

10

Numbers of

Dummy clock

Quad IO Fast

Read

Quad I/O DTR

Read

DC[1:0]

cycles

00 (default)

6

4

8

84

70

104

133

52

42

66

01

10

11

10

100

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MX25U51245G

9-3. Security Register

The deﬁnition of the Security Register bits is as below:

Write Protection Selection bit. Please reference to "Write Protection Selection bit"

Erase Fail bit. The Erase Fail bit shows the status of last Erase operation. The bit will be set to "1" if the erase

operation failed or the erase region was protected. It will be automatically cleared to "0" if the next erase operation

succeeds. Please note that it will not interrupt or stop any operation in the ﬂash memory.

Program Fail bit. The Program Fail bit shows the status of the last Program operation. The bit will be set to "1" if

the program operation failed or the program region was protected. It will be automatically cleared to "0" if the next

program operation succeeds. Please note that it will not interrupt or stop any operation in the ﬂash memory.

Erase Suspend bit. Erase Suspend Bit (ESB) indicates the status of Erase Suspend operation. Users may use

ESB to identify the state of ﬂash memory. After the ﬂash memory is suspended by Erase Suspend command, ESB

is set to "1". ESB is cleared to "0" after erase operation resumes.

Program Suspend bit. Program Suspend Bit (PSB) indicates the status of Program Suspend operation. Users may

use PSB to identify the state of ﬂash memory. After the ﬂash memory is suspended by Program Suspend command,

PSB is set to "1". PSB is cleared to "0" after program operation resumes.

Secured OTP Indicator bit. The Secured OTP indicator bit shows the secured OTP area is locked by factory or

not. When it is "0", it indicates non-factory lock; "1" indicates factory-lock.

Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for

customer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the Secured OTP

area cannot be updated any more. While it is in secured OTP mode, main array access is not allowed.

Table 10. Security Register Deﬁnition

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

ESB

(Erase

PSB

(Program

LDSO

(indicate if

Secured OTP

indicator bit

WPSEL

E_FAIL

P_FAIL

Reserved

Suspend bit) Suspend bit) lock-down)

0=normal

Program

succeed

1=indicate

Program

failed

0 = not lock-

0=normal

Erase

succeed

1=indicate

Erase failed

(default=0)

0=Erase

is not

suspended suspended

1= Erase 1= Program

suspended suspended

0=Program

is not

0=normal

WP mode

1=individual

mode

down

1 = lock-down

(cannot

program/

erase

0 = non-

factory

lock

1 = factory

lock

-

(default=0)

OTP)

Non-volatile

bit

Non-volatile

bit (OTP)

Non-volatile

bit (OTP)

Volatile bit

(OTP)

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MX25U51245G

10. COMMAND DESCRIPTION

10-1. Write Enable (WREN)

The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP/

PP4B, 4PP/4PP4B, SE/SE4B, BE32K/BE32K4B, BE/BE4B, CE, and WRSR, which are intended to change the

device content WEL bit should be set every time after the WREN instruction setting the WEL bit.

The sequence of issuing WREN instruction is: CS# goes low→sending WREN instruction code→ CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care in

SPI mode.

Figure 12. Write Enable (WREN) Sequence (SPI Mode)

CS#

0

1

2

3

4

5

6

7

Mode 3

Mode 0

SCLK

Command

06h

SI

High-Z

SO

Figure 13. Write Enable (WREN) Sequence (QPI Mode)

CS#

0

1

Mode 3

SCLK

Mode 0

Command

SIO[3:0]

06h

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MX25U51245G

10-2. Write Disable (WRDI)

The Write Disable (WRDI) instruction is to reset Write Enable Latch (WEL) bit.

The sequence of issuing WRDI instruction is: CS# goes low→sending WRDI instruction code→CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care in

SPI mode.

The WEL bit is reset by following situations:

- Power-up

- Reset# pin driven low

- WRDI command completion

- WRSR command completion

- PP/PP4B command completion

- 4PP/4PP4B command completion

- SE/SE4B command completion

- BE32K/BE32K4B command completion

- BE/BE4B command completion

- CE command completion

- PGM/ERS Suspend command completion

- Softreset command completion

- WRSCUR command completion

- WPSEL command completion

- GBLK command completion

- GBULK command completion

- WREAR command completion

- WRLR command completion

- WRSPB command completion

- ESSPB command completion

- WRDPB command completion

- WRFBR command completion

- ESFBR command completion

Figure 14. Write Disable (WRDI) Sequence (SPI Mode)

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

SCLK

Command

04h

SI

High-Z

SO

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MX25U51245G

Figure 15. Write Disable (WRDI) Sequence (QPI Mode)

CS#

0

1

Mode 3

SCLK

Mode 0

Command

SIO[3:0]

04h

10-3. Read Identiﬁcation (RDID)

The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Macronix

Manufacturer ID and Device ID are listed as "Table 11. ID Deﬁnitions".

The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code→24-bits ID data out

on SO→ to end RDID operation can drive CS# to high at any time during data out.

While Program/Erase operation is in progress, it will not decode the RDID instruction, therefore there's no effect on

the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby

stage.

Figure 16. Read Identiﬁcation (RDID) Sequence (SPI mode only)

CS#

0

1

2

3

4

5

6

7

8

9

10

13 14 15 16 17 18

28 29 30 31

Mode 3

Mode 0

SCLK

SI

Command

9Fh

Manufacturer Identification

Device Identification

High-Z

SO

7

6

5

2

1

0

15 14 13

MSB

3

2

1

0

MSB

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MX25U51245G

10-4. Release from Deep Power-down (RDP), Read Electronic Signature (RES)

The Release from Deep Power-down (RDP) instruction is completed by driving Chip Select (CS#) High. When Chip

Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the

Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in

the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip

Select (CS#) must remain High for at least tRES2(max), as speciﬁed in "Table 23. AC CHARACTERISTICS".

Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute

instructions. The RDP instruction is only for releasing from Deep Power Down Mode. Reset# pin goes low will

release the Flash from deep power down mode.

RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as Table 11 ID

Deﬁnitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new design,

please use RDID instruction.

Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device is in

progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly

if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in

Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in Deep

Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least

tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute

instruction.

Figure 17. Read Electronic Signature (RES) Sequence (SPI Mode)

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38

SCLK

Command

ABh

t

3 Dummy Bytes

RES2

SI

23 22 21

MSB

3

2

1

0

Electronic Signature Out

High-Z

7

6

5

4

3

2

0

1

SO

MSB

Deep Power-down Mode

Stand-by Mode

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MX25U51245G

Figure 18. Read Electronic Signature (RES) Sequence (QPI Mode)

CS#

MODE 3

0

1

2

3

4

5

6

7

SCLK

MODE 0

3 Dummy Bytes

Command

ABh

SIO[3:0]

X

H0 L0

MSB LSB

Data Out

Data In

Stand-by Mode

Deep Power-down Mode

Figure 19. Release from Deep Power-down (RDP) Sequence (SPI Mode)

CS#

t

RES1

0

1

2

3

4

5

6

7

Mode 3

Mode 0

SCLK

SI

Command

ABh

High-Z

SO

Deep Power-down Mode

Stand-by Mode

Figure 20. Release from Deep Power-down (RDP) Sequence (QPI Mode)

CS#

t

RES1

Mode 3

Mode 0

0

1

SCLK

Command

SIO[3:0]

ABh

Deep Power-down Mode

Stand-by Mode

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MX25U51245G

10-5. Read Electronic Manufacturer ID & Device ID (REMS)

The REMS instruction returns both the JEDEC assigned manufacturer ID and the device ID. The Device ID values

are listed in Table 11 of ID Deﬁnitions.

The REMS instruction is initiated by driving the CS# pin low and sending the instruction code "90h" followed by two

dummy bytes and one address byte (A7~A0). After which the manufacturer ID for Macronix (C2h) and the device

ID are shifted out on the falling edge of SCLK with the most signiﬁcant bit (MSB) ﬁrst. If the address byte is 00h,

the manufacturer ID will be output ﬁrst, followed by the device ID. If the address byte is 01h, then the device ID will

be output ﬁrst, followed by the manufacturer ID. While CS# is low, the manufacturer and device IDs can be read

continuously, alternating from one to the other. The instruction is completed by driving CS# high.

Figure 21. Read Electronic Manufacturer & Device ID (REMS) Sequence (SPI Mode only)

CS#

0

1

2

3

4

5

6

7

8

9 10

Mode 3

Mode 0

SCLK

Command

90h

2 Dummy Bytes

SI

15 14 13

3

2

1

0

High-Z

SO

CS#

47

28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

SCLK

ADD (1)

7

6

5

4

3

2

0

1

SI

Manufacturer ID

Device ID

7

6

5

4

3

2

1

0

7

6

5

4

3

2

0

1

SO

MSB

Notes:

(1) ADD=00H will output the manufacturer's ID ﬁrst and ADD=01H will output device ID ﬁrst.

P/N: PM2244

Rev. 1.1, June 29, 2017

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MX25U51245G

10-6. QPI ID Read (QPIID)

User can execute this QPIID Read instruction to identify the Device ID and Manufacturer ID. The sequence of issue

QPIID instruction is CS# goes low→sending QPI ID instruction→Data out on SO→CS# goes high. Most signiﬁcant

bit (MSB) ﬁrst.

After the command cycle, the device will immediately output data on the falling edge of SCLK. The manufacturer ID,

memory type, and device ID data byte will be output continuously, until the CS# goes high.

Table 11. ID Deﬁnitions

Command Type

MX25U51245G

Manufacturer ID

C2

Memory type

Memory density

3A

RDID

RES

9Fh

25

Electronic ID

3A

Device ID

3A

ABh

90h

AFh

Manufacturer ID

REMS

QPIID

C2

Manufacturer ID

C2

Memory type

25

Memory density

3A

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MX25U51245G

10-7. Read Status Register (RDSR)

The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even

in program/erase/write status register condition). It is recommended to check the Write in Progress (WIP) bit before

sending a new instruction when a program, erase, or write status register operation is in progress.

The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register data

out on SO.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

Figure 22. Read Status Register (RDSR) Sequence (SPI Mode)

CS#

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

Mode 3

Mode 0

SCLK

SI

command

05h

Status Register Out

High-Z

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

MSB

Figure 23. Read Status Register (RDSR) Sequence (QPI Mode)

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

N

SCLK

SIO[3:0]

05h

H0 L0 H0 L0 H0 L0

H0 L0

MSB

LSB

Status Byte Status Byte Status Byte

Status Byte

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MX25U51245G

10-8. Read Conﬁguration Register (RDCR)

The RDCR instruction is for reading Conﬁguration Register Bits. The Read Conﬁguration Register can be read at

any time (even in program/erase/write conﬁguration register condition). It is recommended to check the Write in

Progress (WIP) bit before sending a new instruction when a program, erase, or write conﬁguration register operation

is in progress.

The sequence of issuing RDCR instruction is: CS# goes low→ sending RDCR instruction code→ Conﬁguration

Register data out on SO.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

Figure 24. Read Conﬁguration Register (RDCR) Sequence (SPI Mode)

CS#

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

Mode 3

Mode 0

SCLK

SI

command

15h

Configuration register Out

High-Z

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

MSB

Figure 25. Read Conﬁguration Register (RDCR) Sequence (QPI Mode)

CS#

Mode 3

Mode 0

N

0

1

2

3

4

5

6

7

SCLK

SIO[3:0]

15h

H0 L0 H0 L0 H0 L0

H0 L0

MSB

LSB

Config. Byte Config. Byte Config. Byte

Config. Byte

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MX25U51245G

For user to check if Program/Erase operation is ﬁnished or not, RDSR instruction ﬂow are shown as follows:

Figure 26. Program/Erase ﬂow with read array data

start

WREN command

RDSR command*

No

WEL=1?

Yes

Program/erase command

Write program data/address

(Write erase address)

RDSR command

No

WIP=0?

Yes

RDSR command

Read WEL=0, BP[3:0], QE,

and SRWD data

Read array data

(same address of PGM/ERS)

No

Verify OK?

Yes

Program/erase successfully

Program/erase fail

Yes

Program/erase

another block?

* Issue RDSR to check BP[3:0].

* If WPSEL = 1, issue RDSPB and RDDPB to check the block status.

No

Program/erase completed

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Rev. 1.1, June 29, 2017

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MX25U51245G

Figure 27. Program/Erase ﬂow without read array data (read P_FAIL/E_FAIL ﬂag)

start

WREN command

RDSR command*

No

WEL=1?

Yes

Program/erase command

Write program data/address

(Write erase address)

RDSR command

No

WIP=0?

Yes

RDSR command

Read WEL=0, BP[3:0], QE,

and SRWD data

RDSCUR command

P_FAIL/E_FAIL =1 ?

Yes

No

Program/erase successfully

Program/erase fail

Yes

Program/erase

another block?

* Issue RDSR to check BP[3:0].

* If WPSEL = 1, issue RDSPB and RDDPB to check the block status.

No

Program/erase completed

P/N: PM2244

Rev. 1.1, June 29, 2017

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MX25U51245G

10-9. Write Status Register (WRSR)

The WRSR instruction is for changing the values of Status Register Bits and Conﬁguration Register Bits. Before

sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write

Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1,

BP0) bits to deﬁne the protected area of memory (as shown in Table 3). The WRSR also can set or reset the Quad

enable (QE) bit and set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#/

SIO2) pin signal, but has no effect on bit1(WEL) and bit0 (WIP) of the status register. The WRSR instruction cannot

be executed once the Hardware Protected Mode (HPM) is entered.

The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register

data on SI→CS# goes high.

The CS# must go high exactly at the 8 bits or 16 bits data boundary; otherwise, the instruction will be rejected and

not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes

high. The Write in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress.

The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write

Enable Latch (WEL) bit is reset.

Figure 28. Write Status Register (WRSR) Sequence (SPI Mode)

CS#

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Mode 3

Mode 0

SCLK

command

01h

Status

Register In

Configuration

Register In

SI

4

15 14

13

12 11

10 9

8

2

1

0

7

6

5

3

MSB

High-Z

SO

Note : The CS# must go high exactly at 8 bits or 16 bits data boundary to completed the write register command.

Figure 29. Write Status Register (WRSR) Sequence (QPI Mode)

CS#

Mode 3

Mode 0

Mode 3

Mode 0

0

1

2

3

4

5

SCLK

CR in

SR in

Command

01h

H0 L0 H1 L1

SIO[3:0]

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MX25U51245G

Software Protected Mode (SPM):

-

When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can

change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is deﬁned by BP3, BP2, BP1,

BP0 and T/B bit, is at software protected mode (SPM).

-

When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values

of SRWD, BP3, BP2, BP1, BP0. The protected area, which is deﬁned by BP3, BP2, BP1, BP0 and T/B bit, is at

software protected mode (SPM)

Note:

If SRWD bit=1 but WP#/SIO2 is low, it is impossible to write the Status Register even if the WEL bit has previously

been set. It is rejected to write the Status Register and not be executed.

Hardware Protected Mode (HPM):

-

When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware

protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2,

BP1, BP0 and T/B bit and hardware protected mode by the WP#/SIO2 to against data modiﬁcation.

Note:

To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is entered.

If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be entered; only

can use software protected mode via BP3, BP2, BP1, BP0 and T/B bit.

If the system enter QPI or set QE=1, the feature of HPM will be disabled.

Table 12. Protection Modes

Mode

Status register condition

WP# and SRWD bit status

Memory

Status register can be written

in (WEL bit is set to "1") and

the SRWD, BP0-BP3

Software protection

mode (SPM)

WP#=1 and SRWD bit=0, or

WP#=0 and SRWD bit=0, or

WP#=1 and SRWD=1

The protected area

cannot

be program or erase.

bits can be changed

The SRWD, BP0-BP3 of

status register bits cannot be

changed

The protected area

cannot

be program or erase.

Hardware protection

mode (HPM)

WP#=0, SRWD bit=1

Note:

1. As deﬁned by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in

Table 3.

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MX25U51245G

Figure 30. WRSR ﬂow

start

WREN command

RDSR command

No

WEL=1?

Yes

WRSR command

Write status register data

RDSR command

No

WIP=0?

Yes

RDSR command

Read WEL=0, BP[3:0], QE,

and SRWD data

No

Verify OK?

Yes

WRSR successfully

WRSR fail

P/N: PM2244

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MX25U51245G

Figure 31. WP# Setup Timing and Hold Timing during WRSR when SRWD=1

WP#

CS#

tSHWL

tWHSL

0

1

2

3

4

5

6

7

8

9

10 11 12

13 14

15

SCLK

01h

SI

High-Z

SO

Note: WP# must be kept high until the embedded operation ﬁnish.

P/N: PM2244

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MX25U51245G

10-10. Enter 4-byte mode (EN4B)

The EN4B instruction enables accessing the address length of 32-bit for the memory area of higher density (larger

than 128Mb). The device default is in 24-bit address mode; after sending out the EN4B instruction, the bit5 (4BYTE

bit) of Conﬁguration Register will be automatically set to "1" to indicate the 4-byte address mode has been enabled.

Once the 4-byte address mode is enabled, the address length becomes 32-bit instead of the default 24-bit. There

are three methods to exit the 4-byte mode: writing exit 4-byte mode (EX4B) instruction, Reset or power-off.

All instructions are accepted normally, and just the address bit is changed from 24-bit to 32-bit.

The following command don't support 4bye address: RDSFDP, RES and REMS.

The sequence of issuing EN4B instruction is: CS# goes low → sending EN4B instruction to enter 4-byte mode(

automatically set 4BYTE bit as "1") → CS# goes high.

10-11.Exit 4-byte mode (EX4B)

The EX4B instruction is executed to exit the 4-byte address mode and return to the default 3-bytes address mode.

After sending out the EX4B instruction, the bit5 (4BYTE bit) of Conﬁguration Register will be cleared to be "0" to

indicate the exit of the 4-byte address mode. Once exiting the 4-byte address mode, the address length will return to

24-bit.

The sequence of issuing EX4B instruction is: CS# goes low → sending EX4B instruction to exit 4-byte mode

(automatically clear the 4BYTE bit to be "0") → CS# goes high.

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MX25U51245G

10-12. Read Data Bytes (READ)

The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on

the falling edge of SCLK at a maximum frequency fR. The ﬁrst address byte can be at any location. The address

is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can

be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been

reached.

The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the

4-byte address read mode or to deﬁne EAR bit. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B)

Mode section.

The sequence of issuing READ instruction is: CS# goes low→sending READ instruction code→ 3-byte or 4-byte

address on SI→ data out on SO→to end READ operation can use CS# to high at any time during data out.

Figure 32. Read Data Bytes (READ) Sequence (SPI Mode only)

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38 39

SCLK

command

03h

24-Bit Address

(Note)

23 22 21

MSB

3

2

1

0

SI

Data Out 1

Data Out 2

High-Z

2

7

6

5

4

3

1

7

0

SO

MSB

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the

address cycles will be increased.

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MX25U51245G

10-13. Read Data Bytes at Higher Speed (FAST_READ)

The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and

data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The ﬁrst address byte can be at

any location. The address is automatically increased to the next higher address after each byte data is shifted out,

so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when

the highest address has been reached.

The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the

4-byte address read mode or to deﬁne EAR bit. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B)

Mode section.

Read on SPI Mode The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ

instruction code→ 3-byte or 4-byte address on SI→ 8 dummy cycles (default)→ data out on SO→ to end FAST_

READ operation can use CS# to high at any time during data out.

While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any

impact on the Program/Erase/Write Status Register current cycle.

Figure 33. Read at Higher Speed (FAST_READ) Sequence (SPI Mode)

CS#

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31

Mode 3

Mode 0

SCLK

Command

0Bh

24-Bit Address

(Note)

SI

23 22 21

3

2

1

0

High-Z

SO

CS#

47

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

SCLK

Configurable

Dummy Cycle

7

6

5

4

3

2

0

1

SI

DATA OUT 2

DATA OUT 1

7

6

5

4

3

2

1

0

7

6

5

4

3

2

0

1

SO

MSB

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the

address cycles will be increased.

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MX25U51245G

10-14. Dual Output Read Mode (DREAD)

The DREAD instruction enable double throughput of Serial NOR Flash in read mode. The address is latched on

rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a

maximum frequency fT. The ﬁrst address byte can be at any location. The address is automatically increased to the

next higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD

instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD

instruction, the following data out will perform as 2-bit instead of previous 1-bit.

The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the

4-byte address read mode or to deﬁne EAR bit. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B)

Mode section.

The sequence of issuing DREAD instruction is: CS# goes low

sending DREAD instruction 3-byte or 4-byte

→

address on SIO0 8 dummy cycles (default) on SIO0

data out interleave on SIO1 & SIO0

to end DREAD

→

operation can use CS# to high at any time during data out.

While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact

on the Program/Erase/Write Status Register current cycle.

Figure 34. Dual Read Mode Sequence

CS#

30 31 32

39 40 41 42 43 44 45

0

1

2

3

4

5

6

7

8

9

SCLK

…

Data Out

1

Configurable

Dummy Cycle

Command

24 ADD Cycle

2

…

A23 A22

A1 A0

D4 D2

D6 D4

D7 D5

3B

D6

D7

D0

SI/SIO0

High Impedance

D1

D5 D3

SO/SIO1

Notes:

1. Please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address

cycles will be increased.

2. Conﬁguration Dummy cycle numbers will be different depending on the bit6 & bit7 (DC0 & DC1) setting in

conﬁguration register.

P/N: PM2244

Rev. 1.1, June 29, 2017

47

MX25U51245G

10-15. 2 x I/O Read Mode (2READ)

The 2READ instruction enable double throughput of Serial NOR Flash in read mode. The address is latched on

rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a

maximum frequency fT. The ﬁrst address byte can be at any location. The address is automatically increased to the

next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ

instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ

instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit.

The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the

4-byte address read mode or to deﬁne EAR bit. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B)

Mode section.

The sequence of issuing 2READ instruction is: CS# goes low sending 2READ instruction 3-byte or 4-byte

→

address interleave on SIO1 & SIO0 4 dummy cycles (default) on SIO1 & SIO0 data out interleave on SIO1 &

→

SIO0 to end 2READ operation can use CS# to high at any time during data out.

→

While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact

on the Program/Erase/Write Status Register current cycle.

Figure 35. 2 x I/O Read Mode Sequence (SPI Mode only)

CS#

Mode 3

Mode 0

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

10

17 18 19 20 21 22 23 24 25 26 27 28 29 30

SCLK

Data

Configurable

Dummy Cycle

12 ADD Cycles

(Note)

Command

Out 1

Out 2

D6 D4 D2 D0 D6 D4 D2 D0

A22 A20 A18

A4 A2 A0

BBh

SI/SIO0

D7 D5 D3 D1 D7 D5 D3 D1

A23 A21 A19

A5 A3 A1

SO/SIO1

Notes:

1. Please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address

cycles will be increased.

2. Conﬁguration Dummy cycle numbers will be different depending on the bit6 & bit7 (DC0 & DC1) setting in

conﬁguration register.

P/N: PM2244

Rev. 1.1, June 29, 2017

48

MX25U51245G

10-16. Quad Read Mode (QREAD)

The QREAD instruction enable quad throughput of Serial NOR Flash in read mode. The address is latched on

rising edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a

maximum frequency fQ. The ﬁrst address byte can be at any location. The address is automatically increased to the

next higher address after each byte data is shifted out, so the whole memory can be read out at a single QREAD

instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing QREAD

instruction, the following data out will perform as 4-bit instead of previous 1-bit.

The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the

4-byte address read mode or to deﬁne EAR bit. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B)

Mode section.

The sequence of issuing QREAD instruction is: CS# goes low

sending QREAD instruction → 3-byte or 4-byte

→

address on SI

8 dummy cycle (Default)

data out interleave on SIO3, SIO2, SIO1 & SIO0

to end QREAD

→

operation can use CS# to high at any time during data out.

While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any impact

on the Program/Erase/Write Status Register current cycle.

Figure 36. Quad Read Mode Sequence

CS#

29 30 31 32 33

38 39 40 41 42

0

1

2

3

4

5

6

7

8

9

SCLK

…

Configurable

dummy cycles

Data

Out 1

Data Data

Out 2 Out 3

Command

6B

24 ADD Cycles

…

A23A22

A2 A1 A0

D4 D0 D4 D0 D4

SIO0

SIO1

SIO2

SIO3

High Impedance

D5 D1 D5 D1 D5

D6 D2 D6 D2 D6

D7 D3 D7 D3 D7

Notes:

1. Please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address

cycles will be increased.

2. Conﬁguration Dummy cycle numbers will be different depending on the bit6 & bit7 (DC0 & DC1) setting in

conﬁguration register.

P/N: PM2244

Rev. 1.1, June 29, 2017

49

MX25U51245G

10-17. 4 x I/O Read Mode (4READ)

The 4READ instruction enable quad throughput of Serial NOR Flash in read mode. A Quad Enable (QE) bit of status

Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCLK,

and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency

fQ. The ﬁrst address byte can be at any location. The address is automatically increased to the next higher address

after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address

counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following

address/dummy/data out will perform as 4-bit instead of previous 1-bit.

The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the

4-byte address read mode or to deﬁne EAR bit. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B)

Mode section.

4 x I/O Read on SPI Mode (4READ) The sequence of issuing 4READ instruction is: CS# goes low sending

→

4READ instruction 3-byte or 4-byte address interleave on SIO3, SIO2, SIO1 & SIO0 6 dummy cycles (Default)

→

data out interleave on SIO3, SIO2, SIO1 & SIO0 to end 4READ operation can use CS# to high at any time

→

during data out.

4 x I/O Read on QPI Mode (4READ) The 4READ instruction also support on QPI command mode. The sequence

of issuing 4READ instruction QPI mode is: CS# goes low sending 4READ instruction 3-byte or 4-byte address

→

interleave on SIO3, SIO2, SIO1 & SIO0 6 dummy cycles (Default) data out interleave on SIO3, SIO2, SIO1 &

→

SIO0 to end 4READ operation can use CS# to high at any time during data out.

→

While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact

on the Program/Erase/Write Status Register current cycle.

P/N: PM2244

Rev. 1.1, June 29, 2017

50

MX25U51245G

Figure 37. 4 x I/O Read Mode Sequence (SPI Mode)

CS#

23 24

10 11 12 13 14 15 16 17 18 19 20 21 22

Mode 3

Mode 0

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

SCLK

Data

Out 1

Data

Out 2 Out 3

Data

Command

EA/EBh

6 ADD Cycles

Performance

enhance

indicator (Note 1)

Configurable

Dummy Cycle (Note 3)

A20 A16 A12 A8 A4 A0

D4 D0 D4 D0 D4 D0

P4 P0

SIO0

SIO1

SIO2

SIO3

A21 A17 A13 A9 A5 A1

A22 A18 A14 A10 A6 A2

D5 D1 D5 D1 D5 D1

D6 D2 D6 D2 D6 D2

P5 P1

P6 P2

A23 A19 A15 A11 A7 A3

D7 D3 D7 D3 D7 D3

P7 P3

Notes:

1. Hi-impedance is inhibited for the two clock cycles.

2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited.

3. Conﬁguration Dummy cycle numbers will be different depending on the bit6 & bit7 (DC0 & DC1) setting in

conﬁguration register.

4. Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the

address cycles will be increased.

Figure 38. 4 x I/O Read Mode Sequence (QPI Mode)

CS#

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

MODE 3

MODE 0

MODE 3

MODE 0

SCLK

A20-

A23

A16-

A19

A12-

A15

A8-

A11

A4-

A7

A0-

A3

EBh

H0 L0

H1 L1 H2 L2

H3 L3

SIO[3:0]

X

MSB

Data Out

24-bit Address

(Note)

Configurable

Dummy Cycle

Data In

Notes:

1. Please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address

cycles will be increased.

2. Conﬁguration Dummy cycle numbers will be different depending on the bit6 & bit7 (DC0 & DC1) setting in

conﬁguration register.

P/N: PM2244

Rev. 1.1, June 29, 2017

51

MX25U51245G

10-18. 4 x I/O Double Transfer Rate Read Mode (4DTRD)

The 4DTRD instruction enables Double Transfer Rate throughput on quad I/O of Serial NOR Flash in read mode. A

Quad Enable (QE) bit of status Register must be set to "1" before sending the 4DTRD instruction. The address (interleave

on 4 I/O pins) is latched on both rising and falling edge of SCLK, and data (interleave on 4 I/O pins) shift out on

both rising and falling edge of SCLK. The 8-bit address can be latched-in at one clock, and 8-bit data can be read

out at one clock, which means four bits at rising edge of clock, the other four bits at falling edge of clock. The ﬁrst

address byte can be at any location. The address is automatically increased to the next higher address after each

byte data is shifted out, so the whole memory can be read out at a single 4DTRD instruction. The address counter

rolls over to 0 when the highest address has been reached. Once writing 4DTRD instruction, the following address/

dummy/data out will perform as 8-bit instead of previous 1-bit.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

While Program/Erase/Write Status Register cycle is in progress, 4DTRD instruction is rejected without any impact

on the Program/Erase/Write Status Register current cycle.

P/N: PM2244

Rev. 1.1, June 29, 2017

52

MX25U51245G

Figure 39. Fast Quad I/O DT Read (4DTRD) Sequence (SPI Mode)

CS#

0

7

8

9

10

11

16

17

18

Mode 3

Mode 0

SCLK

…

Performance

Enhance Indicator

Command

3 ADD Cycles

Configurable

Dummy Cycle

…

SIO0

SIO1

EDh

A20 A16

A21 A17

A4 A0 P4 P0

D4 D0 D4 D0 D4

D5 D1 D5 D1 D5

…

P5

A5 A1

A6 A2

P1

…

P2

P3

A22 A18

A23 A19

P6

P7

SIO2

SIO3

D6 D2 D6 D2 D6

D7 D3 D7 D3 D7

A3

A7

Notes:

1. Hi-impedance is inhibited for this clock cycle.

2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) will result in entering the performance enhance mode.

3. Conﬁguration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in

conﬁguration register.

4. Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address

cycles will be increased.

Figure 40. Fast Quad I/O DT Read (4DTRD) Sequence (QPI Mode)

CS#

0

1

2

3

4

5

10

11

12

Mode 3

Mode 0

SCLK

…

Command

3 ADD Cycles

A16 A12 A8

Performance

Enhance Indicator

Configurable

Dummy Cycle

A20

|

A4

|

A0

|

SIO[3:0]

EDh

P1 P0

H0 L0 H1 L1 H2

A23

A19 A15 A11

A7

A3

Notes:

1. Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address

cycles will be increased.

2. Conﬁguration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in

conﬁguration register.

P/N: PM2244

Rev. 1.1, June 29, 2017

53

MX25U51245G

10-19. Preamble Bit

The Preamble Bit data pattern supports system/memory controller to determine valid window of data output more

easily and improve data capture reliability while the ﬂash memory is running in high frequency.

Preamble Bit data pattern can be enabled or disabled by setting the bit4 of Conﬁguration register (Preamble bit

Enable bit). Once the CR<4> is set, the preamble bit is inputted into dummy cycles.

Enabling preamble bit will not affect the function of enhance mode bit. In Dummy cycles, performance enhance

mode bit still operates with the same function. Preamble bit will output after performance enhance mode bit.

The preamble bit is a ﬁxed 8-bit data pattern (00110100). While dummy cycle number reaches 10, the complete

8 bits will start to output right after the performance enhance mode bit. While dummy cycle is not sufﬁcient of 10

cycles, the rest of the preamble bits will be cut. For example, 8 dummy cycles will cause 6 preamble bits to output,

and 6 dummy cycles will cause 4 preamble bits to output.

Figure 41. SDR 1I/O (10DC)

CS#

SCLK

…

Dummy

cycle

Command

cycle

Address cycle

Preamble bits

…

An

A0

CMD

SI

…

SO

7

6

5

4

3

2

1

0

D7 D6

Figure 42. SDR 1I/O (8DC)

CS#

SCLK

…

Dummy cycle

Preamble bits

Command

cycle

Address cycle

…

SI

CMD

An

A0

…

7

6

5

4

3

2

D7 D6 D5 D4

SO

P/N: PM2244

Rev. 1.1, June 29, 2017

54

MX25U51245G

Figure 43. SDR 2I/O (10DC)

CS#

SCLK

…

Dummy cycle

Preamble bits

Command

cycle

Address cycle

Toggle

bits

…

A(n-1)

A0

A1

CMD

SIO0

7

6

5

4

3

2

1

0

D6 D4 D2 D0

…

An

D7 D5 D3 D1

SIO1

Figure 44. SDR 2I/O (8DC)

CS#

SCLK

…

Dummy cycle

Preamble bits

Command

cycle

Address cycle

Toggle

bits

…

A(n-1)

A0

A1

CMD

SIO0

SIO1

7

6

5

4

3

2

D6 D4 D2 D0

…

An

D7 D5 D3 D1

P/N: PM2244

Rev. 1.1, June 29, 2017

55

MX25U51245G

Figure 45. SDR 4I/O (10DC)

CS#

SCLK

…

Dummy cycle

Preamble bits

Command

cycle

Address cycle

Toggle

bits

…

A(n-3)

A0

A1

CMD

7

6

5

4

3

2

1

0

D4 D0

SIO0

SIO1

…

A(n-2)

A(n-1)

An

D5

D1

A2

A3

7

6

5

4

3

2

1

0

D6 D2

D7 D3

SIO2

SIO3

Figure 46. SDR 4I/O (8DC)

CS#

SCLK

…

Dummy cycle

Preamble bits

Command

cycle

Address cycle

Toggle

bits

…

A(n-3)

A0

A1

CMD

7

6

5

4

3

2

D4 D0

SIO0

SIO1

SIO2

…

A(n-2)

A(n-1)

An

2

D5

D1

A2

A3

D6 D2

D7 D3

…

7

6

5

4

3

SIO3

P/N: PM2244

Rev. 1.1, June 29, 2017

56

MX25U51245G

Figure 47. DTR4IO (6DC)

CS#

SCLK

…

Dummy cycle

Preamble bits

Command

cycle

Address cycle

Toggle

Bits

…

A0

7

6

5

4

3

2

1

0

D4 D0 D4 D0 D4 D0 D4 D0

D5 D1 D5 D1 D5 D1 D5 D1

CMD

SIO0

SIO1

SIO2

A(n-3)

A(n-2)

A(n-1)

…

A1

A2

7

6

5

4

3

2

1

0

D6 D2 D6 D2 D6 D2 D6 D2

D7 D3 D7 D3 D7 D3 D7 D3

A3

…

SIO3

An

P/N: PM2244

Rev. 1.1, June 29, 2017

57

MX25U51245G

10-20. 4 Byte Address Command Set

The operation of 4-byte address command set was very similar to original 3-byte address command set. The

only different is all the 4-byte command set request 4-byte address (A31-A0) followed by instruction code. The

command set support 4-byte address including: READ4B, Fast_Read4B, DREAD4B, 2READ4B, QREAD4B,

4READ4B, 4DTRD4B, PP4B, 4PP4B, SE4B, BE32K4B, BE4B. Please note that it is not necessary to issue EN4B

command before issuing any of 4-byte command set.

Figure 48. Read Data Bytes using 4 Byte Address Sequence (READ4B)

CS#

0

1

2

3

4

5

6

7

8

9

10

36 37 38 39 40 41 42 43 44 45 46 47

SCLK

Command

13h

32-bit address

31 30 29

MSB

3

2

1

0

SI

DataOut 1

DataOut 2

7

High Impedance

2

SO

7

6

5

4

3

1

0

MSB

Figure 49. Read Data Bytes at Higher Speed using 4 Byte Address Sequence (FASTREAD4B)

CS#

0

1

2

3

4

5

6

7

8

9

10

36 37 38 39

SCLK

Command

0Ch

32-bit address

31 30 29

3

2

1

0

SI

High Impedance

SO

CS#

55

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54

SCLK

Configurable

Dummy cycles

SI

7

6

5

4

3

2

0

1

DATAOUT2

DATAOUT1

7

6

5

4

3

2

1

0

7

SO

7

6

5

4

3

2

0

1

MSB

Note:

1. Conﬁguration Dummy cycle numbers will be different depending on the bit6 & bit7 (DC0 & DC1) setting in

conﬁguration register.

P/N: PM2244

Rev. 1.1, June 29, 2017

58

MX25U51245G

Figure 50. 2 x I/O Fast Read using 4 Byte Address Sequence (2READ4B)

CS#

Mode 3

Mode 0

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

10

21 22 23 24 25 26 27 28 29 30 31 32 33 34

SCLK

Data

Configurable

Dummy Cycle

16 ADD Cycles

Command

Out 1

Out 2

D6 D4 D2 D0 D6 D4 D2 D0

A30 A28 A26

A31 A29 A27

A4 A2 A0

BCh

SI/SIO0

D7 D5 D3 D1 D7 D5 D3 D1

A5 A3 A1

SO/SIO1

Note:

1. Conﬁguration Dummy cycle numbers will be different depending on the bit6 & bit7 (DC0 & DC1) setting in

conﬁguration register.

Figure 51. 4 I/O Fast Read using 4 Byte Address sequence (4READ4B)

CS#

23 24 25 26

Mode 3

Mode 0

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22

SCLK

Command

8 ADD Cycles

Performance

Data

Out 1

Data

Out 2

Data

Out 3

enhance

indicator

Configurable

Dummy Cycle

A16

A12 A8 A4 A0

D4 D0 D4 D0 D4 D0

A28 A24

A29 A25

A20

P4 P0

ECh

SIO0

SIO1

SIO2

SIO3

A21 A17 A13 A9 A5 A1

P5 P1

P6 P2

P7 P3

D5 D1 D5 D1 D5 D1

D6 D2 D6 D2 D6 D2

A30 A26 A22 A18 A14 A10 A6 A2

A31 A27

A23 A19 A15 A11 A7 A3

D7 D3 D7 D3 D7 D3

Note:

1. Conﬁguration Dummy cycle numbers will be different depending on the bit6 & bit7 (DC0 & DC1) setting in

conﬁguration register.

P/N: PM2244

Rev. 1.1, June 29, 2017

59

MX25U51245G

Figure 52. Fast Quad I/O DT Read (4DTRD4B) Sequence (SPI Mode)

CS#

0

7

8

9

10

11

12

17

18

19

Mode 3

Mode 0

SCLK

…

Performance

Enhance Indicator

Command

4 ADD Cycles

Configurable

Dummy Cycle

…

SIO0

SIO1

A28 A24

A29 A25

EEh

A4 A0 P4 P0

D4 D0 D4 D0 D4

D5 D1 D5 D1 D5

P5

A5 A1

A6 A2

P1

…

P2

P3

A30 A26

A31 A27

P6

P7

SIO2

SIO3

D6 D2 D6 D2 D6

D7 D3 D7 D3 D7

A3

A7

Note:

1. Conﬁguration Dummy cycle numbers will be different depending on the bit6 & bit7 (DC0 & DC1) setting in

conﬁguration register.

Figure 53. Fast Quad I/O DT Read (4DTRD4B) Sequence (QPI Mode)

CS#

0

1

2

3

4

5

6

11

12

13

Mode 3

Mode 0

SCLK

…

Command

4 ADD Cycles

Performance

Enhance Indicator

Configurable

Dummy Cycle

A28 A24 A20

A16 A12 A8

A4

|

A0

|

SIO[3:0]

|

EEh

|

P1 P0

H0 L0 H1 L1 H2

A31 A27 A23

A19 A15 A11

A7

A3

Note:

1. Conﬁguration Dummy cycle numbers will be different depending on the bit6 & bit7 (DC0 & DC1) setting in

conﬁguration register.

P/N: PM2244

Rev. 1.1, June 29, 2017

60

MX25U51245G

Figure 54. Sector Erase (SE4B) Sequence (SPI Mode)

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

37 38 39

SCLK

32-Bit Address

Command

21h

SI

31 30

MSB

2

1

0

Figure 55. Block Erase 32KB (BE32K4B) Sequence (SPI Mode)

CS#

0

1

2

3

4

5

6

7

8

9

37 38 39

Mode 3

Mode 0

SCLK

Command

5Ch

32-Bit Address

SI

2

1

0

31 30

MSB

Figure 56. Block Erase (BE4B) Sequence (SPI Mode)

CS#

0

1

2

3

4

5

6

7

8

9

Mode 3

Mode 0

37 38 39

SCLK

Command

DCh

32-Bit Address

2

SI

1

0

31 30

MSB

P/N: PM2244

Rev. 1.1, June 29, 2017

61

MX25U51245G

Figure 57. Page Program (PP4B) Sequence (SPI Mode)

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

10

36 37 38 39 40 41 42 43 44 45 46 47

SCLK

Command

12h

Data Byte 1

32-Bit Address

31 30 29

MSB

3

2

1

0

7

6

5

4

3

2

0

1

SI

MSB

CS#

48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

SCLK

Data Byte 2

Data Byte 3

Data Byte 256

7

6

5

4

3

2

0

7

6

5

4

3

2

0

7

6

5

4

3

2

0

1

SI

MSB

Figure 58. 4 x I/O Page Program (4PP4B) Sequence (SPI Mode only)

CS#

10 11 12 13 14 15 16 17 18 19 20 21 22 23

9

0

1

2

3

4

5

6

7

8

Mode 3

Mode 0

SCLK

Data Data Data Data

8 Address cycle

Command

3Eh

Byte 2 Byte 3 Byte 4 Byte 4

A16

A8 A4 A0

A12

A28 A24 A20

4

0

4

0

4

0

4

0

SIO0

SIO1

SIO2

SIO3

A29 A25 A21 A17 A13 A9 A5 A1

5

6

7

1

2

3

5

6

7

1

2

3

5

6

7

1

2

3

5

6

7

1

2

3

A30 A26 A22

A14 A10 A6 A2

A18

A7

A31 A27 A23 A19 A15 A11

A3

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MX25U51245G

10-21. Performance Enhance Mode

The device could waive the command cycle bits if the two cycle bits after address cycle toggles.

Performance enhance mode is supported in both SPI and QPI mode.

In QPI mode, “EBh” "ECh" "EDh" "EEh" and SPI “EBh” "ECh" "EDh" "EEh" commands support enhance mode. The

performance enhance mode is not supported in dual I/O mode.

To enter performance-enhancing mode, P[7:4] must be toggling with P[3:0]; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh

can make this mode continue and skip the next 4READ instruction. To leave enhance mode, P[7:4] is no longer

toggling with P[3:0]; likewise P[7:0]=FFh, 00h, AAh or 55h along with CS# is afterwards raised and then lowered.

Issuing ”FFh” data cycle can also exit enhance mode. The system then will leave performance enhance mode and

return to normal operation.

After entering enhance mode, following CS# go high, the device will stay in the read mode and treat CS# go low of

the ﬁrst clock as address instead of command cycle.

Another sequence of issuing 4READ instruction especially useful in random access is : CS# goes low sending

→

4 READ instruction 3-bytes or 4-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 performance enhance

→

toggling bit P[7:0] 4 dummy cycles (Default) data out still CS# goes high CS# goes low (reduce 4 Read

→

instruction)

3-bytes or 4-bytes random access address.

→

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MX25U51245G

Figure 59. 4 x I/O Read Performance Enhance Mode Sequence (SPI Mode)

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22

n

SCLK

Data

Out 2

Data

Out n

Command

6 ADD Cycles

(Note 3)

Performance

enhance

Out 1

indicator (Note 1)

Configurable

Dummy Cycle (Note 2)

P4 P0

D4 D0 D4 D0

D4 D0

A20 A16 A12 A8 A4 A0

EBh

SIO0

SIO1

SIO2

A21 A17 A13 A9 A5 A1

A22 A18 A14 A10 A6 A2

D5 D1 D5 D1

D6 D2 D6 D2

D5 D1

D6 D2

P5 P1

P6 P2

A23 A19 A15 A11 A7 A3

D7 D3 D7 D3

D7 D3

P7 P3

SIO3

CS#

n+1

...........

n+7......n+9 ........... n+13

...........

Mode 3

Mode 0

SCLK

Data

Out 1

Data

Out 2

Data

Out n

6 ADD Cycles

(Note 3)

Performance

enhance

indicator (Note 1)

Configurable

Dummy Cycle (Note 2)

D4 D0 D4 D0

D4 D0

P4 P0

A20 A16 A12 A8 A4 A0

SIO0

SIO1

SIO2

SIO3

D5 D1 D5 D1

D6 D2 D6 D2

D5 D1

D6 D2

A21 A17 A13 A9 A5 A1

A22 A18 A14 A10 A6 A2

P5 P1

P6 P2

D7 D3 D7 D3

D7 D3

A23 A19 A15 A11 A7 A3

P7 P3

Notes:

1. If not using performance enhance recommend to keep 1 or 0 in performance enhance indicator.

Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF.

2. Conﬁguration Dummy cycle numbers will be different depending on the bit6 & bit7 (DC0 & DC1) setting in

conﬁguration register.

3. Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the

address cycles will be increased.

P/N: PM2244

Rev. 1.1, June 29, 2017

64

MX25U51245G

Figure 60. 4 x I/O Read Performance Enhance Mode Sequence (QPI Mode)

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

SCLK

A20- A16-

A23 A19

A12-

A15

A8-

A11

A4-

A7

A0-

A3

EBh

SIO[3:0]

X

H0 L0 H1 L1

MSB LSB MSB LSB

P(7:4)P(3:0)

Data In

Data Out

performance

enhance

indicator (Note 3)

Configurable

Dummy Cycle (Note 1)

CS#

SCLK

n+1 .............

Mode 0

A20- A16-

A23 A19

A12-

A15

A8-

A11

A4-

A7

A0-

A3

SIO[3:0]

X

H0 L0 H1 L1

MSB LSB MSB LSB

P(7:4)P(3:0)

Data Out

6 Address cycles

(Note 2)

performance

enhance

indicator (Note 3)

Configurable

Dummy Cycle (Note 1)

Notes:

1. Conﬁguration Dummy cycle numbers will be different depending on the bit6 & bit7 (DC0 & DC1) setting in

conﬁguration register.

2. Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address

cycles will be increased.

3. Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF.

P/N: PM2244

Rev. 1.1, June 29, 2017

65

MX25U51245G

Figure 61. 4 x I/O DT Read Performance Enhance Mode Sequence (SPI Mode)

CS#

0

7

8

9

10

11

16

17

18

n

Mode 3

Mode 0

SCLK

…

Performance

Enhance Indicator

Command

3 ADD Cycles

Configurable

Dummy Cycle

…

SIO0

SIO1

EDh

A20 A16

A21 A17

A4 A0 P4 P0

D4 D0 D4 D0

D5 D1 D5 D1

D4 D0

D5 D1

…

P5

A5 A1

A6 A2

…

P1

…

P2

P3

A22 A18

A23 A19

P6

P7

SIO2

SIO3

D6 D2 D6 D2

D7 D3 D7 D3

D6 D2

D7 D3

A3

A7

CS#

… …

n+1

n+4

Mode 3

SCLK

…

Mode 0

Performance

Enhance Indicator

3 ADD Cycles

Configurable

Dummy Cycle

…

SIO0

SIO1

A20 A16

A4 A0 P4 P0

D4 D0 D4 D0

D5 D1 D5 D1

…

P5

A5 A1

A6 A2

A21 A17

P1

…

P2

P3

A22 A18

A23 A19

P6

P7

SIO2

SIO3

D6 D2 D6 D2

D7 D3 D7 D3

A3

A7

Notes:

1. Conﬁguration Dummy cycle numbers will be different depending on the bit6 & bit7 (DC0 & DC1) setting in

conﬁguration register.

2. Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address

cycles will be increased.

3. Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF.

P/N: PM2244

Rev. 1.1, June 29, 2017

66

MX25U51245G

Figure 62. 4 x I/O DT Read Performance Enhance Mode Sequence (QPI Mode)

CS#

0

1

2

3

4

5

10

11

12

n

Mode 3

Mode 0

SCLK

…

Command

3 ADD Cycles

A16 A12 A8

Performance

Enhance Indicator

Configurable

Dummy Cycle

A20

|

A4

|

A0

|

SIO[3:0]

EDh

P1 P0

H0 L0 H1 L1

Hn Ln

A23

A19 A15 A11

A7

A3

CS#

n+1

n+4

…

Mode 3

Mode 0

SCLK

…

3 ADD Cycles

Performance

Enhance Indicator

Configurable

Dummy Cycle

A20

|

A16 A12 A8

A4

|

A0

|

SIO[3:0]

P1 P0

H0 L0 H1 L1

A23

A19 A15 A11

A7

A3

Notes:

1. Conﬁguration Dummy cycle numbers will be different depending on the bit6 & bit7 (DC0 & DC1) setting in

conﬁguration register.

2. Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address

cycles will be increased.

3. Reset the performance enhance mode, if P1=P0, ex: AA, 00, FF.

P/N: PM2244

Rev. 1.1, June 29, 2017

67

MX25U51245G

10-22. Burst Read

To set the Burst length, following command operation is required to issue command: “C0h” in the ﬁrst Byte (8-clocks),

following 4 clocks deﬁning wrap around enable with “0h” and disable with“1h”.

The next 4 clocks are to deﬁne wrap around depth. Their deﬁnitions are as the following table:

Data

00h

01h

02h

03h

1xh

Wrap Around

Wrap Depth

8-byte

Yes

No

16-byte

32-byte

64-byte

X

The wrap around unit is deﬁned within the 256Byte page, with random initial address. It is deﬁned as “wrap-around

mode disable” for the default state of the device. To exit wrap around, it is required to issue another “C0h” command

in which data=‘1xh”. Otherwise, wrap around status will be retained until power down or reset command. To change

wrap around depth, it is requried to issue another “C0h” command in which data=“0xh”. QPI “EBh” "ECh" and SPI “EBh”

"ECh" support wrap around feature after wrap around is enabled. Both SPI (8 clocks) and QPI (2 clocks) command

cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode.

Figure 63. SPI Mode

CS#

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Mode 3

Mode 0

SCLK

SIO

D7

D6

D5

D4

D3

D2

D1

D0

C0h

Figure 64. QPI Mode

CS#

0

1

2

3

Mode 3

Mode 0

SCLK

C0h

H0

L0

SIO[3:0]

MSB LSB

Note: MSB=Most Signiﬁcant Bit

LSB=Least Signiﬁcant Bit

P/N: PM2244

Rev. 1.1, June 29, 2017

68

MX25U51245G

10-23. Fast Boot

The Fast Boot Feature provides the ability to automatically execute read operation after power on cycle or reset

without any read instruction.

A Fast Boot Register is provided on this device. It can enable the Fast Boot function and also deﬁne the number of

delay cycles and start address (where boot code being transferred). Instruction WRFBR (write fast boot register) and

ESFBR (erase fast boot register) can be used for the status conﬁguration or alternation of the Fast Boot Register

bit. RDFBR (read fast boot register) can be used to verify the program state of the Fast Boot Register. The default

number of delay cycles is 13 cycles, and there is a 16bytes boundary address for the start of boot code access.

When CS# starts to go low, data begins to output from default address after the delay cycles (default as 13 cycles).

After CS# returns to go high, the device will go back to standard SPI mode and user can start to input command. In

the fast boot data out process from CS# goes low to CS# goes high, a minimum of one byte must be output.

Once Fast Boot feature has been enabled, the device will automatically start a read operation after power on cycle,

reset command, or hardware reset operation.

The fast Boot feature can support Single I/O and Quad I/O interface. If the QE bit of Status Register is “0”, the data

is output by Single I/O interface. If the QE bit of Status Register is set to “1”, the data is output by Quad I/O interface.

Fast Boot Register (FBR)

Bits

Description

FBSA (FastBoot Start

Address)

Bit Status

16 bytes boundary address for the start of boot

code access.

Default State

Type

Non-

Volatile

31 to 4

FFFFFFF

Non-

Volatile

3

2 to 1

0

x

1

11

1

00: 7 delay cycles

01: 9 delay cycles

10: 11 delay cycles

11: 13 delay cycles

0=FastBoot is enabled.

1=FastBoot is not enabled.

FBSD (FastBoot Start

Delay Cycle)

Non-

Volatile

Non-

Volatile

FBE (FastBoot Enable)

Note: If FBSD = 11, the maximum clock frequency is 133 MHz

If FBSD = 10, the maximum clock frequency is 104 MHz

If FBSD = 01, the maximum clock frequency is 84 MHz

If FBSD = 00, the maximum clock frequency is 70 MHz

P/N: PM2244

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69

MX25U51245G

Figure 65. Fast Boot Sequence (QE=0)

CS#

0

-

n+1

n+13 n+15

n+12 n+14

n+10n+11

Mode 3

Mode 0

-

n

n+2

n+4 n+5 n+6

n+8 n+9

n+7

n+3

SCLK

SI

Delay Cycles

Don’t care or High Impedance

Data Out 1

Data Out 2

High Impedance

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

MSB

Note: If FBSD = 11, delay cycles is 13 and n is 12.

If FBSD = 10, delay cycles is 11 and n is 10.

If FBSD = 01, delay cycles is 9 and n is 8.

If FBSD = 00, delay cycles is 7 and n is 6.

Figure 66. Fast Boot Sequence (QE=1)

CS#

-

n

n+1 n+2 n+3 n+5 n+6 n+7 n+8 n+9

0

Mode 3

Mode 0

SCLK

Data

Out 1

Delay Cycles

Data

Out 3

Out 2

Out 4

High Impedance

4

0

4

0

4

0

SIO0

SIO1

SIO2

SIO3

High Impedance

5

6

7

1

5

6

7

1

5

6

1

5

6

7

1

2

3

5

6

7

2

3

2

3

2

3

7

MSB

Note: If FBSD = 11, delay cycles is 13 and n is 12.

If FBSD = 10, delay cycles is 11 and n is 10.

If FBSD = 01, delay cycles is 9 and n is 8.

If FBSD = 00, delay cycles is 7 and n is 6.

P/N: PM2244

Rev. 1.1, June 29, 2017

70

MX25U51245G

Figure 67. Read Fast Boot Register (RDFBR) Sequence

CS#

0

1

2

3

4

5

6

7

8

9

10

37 38 39 40 41

Mode 3

Mode 0

SCLK

Command

16h

SI

Data Out 1

Data Out 2

26 25 24 7 6

High-Z

SO

7

6

5

MSB

Figure 68. Write Fast Boot Register (WRFBR) Sequence

CS#

0

1

2

3

4

5

6

7

8

9

37 38 39

Mode 3

Mode 0

10

SCLK

Command

17h

Fast Boot Register

SI

7

6

26 25 24

5

MSB

High-Z

SO

Figure 69. Erase Fast Boot Register (ESFBR) Sequence

CS#

0

1

2

3

4

5

6

7

Mode 3

Mode 0

SCLK

Command

18h

SI

High-Z

SO

P/N: PM2244

Rev. 1.1, June 29, 2017

71

MX25U51245G

10-24. Sector Erase (SE)

The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used

for any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit

before sending the Sector Erase (SE). Any address of the sector (Please refer to "5. MEMORY ORGANIZATION")

is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the least

signiﬁcant bit of the address byte been latched-in); otherwise, the instruction will be rejected and not executed.

The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the

4-byte address read mode or to deﬁne EAR bit. Address bits [Am-A12] (Am is the most signiﬁcant address) select

the sector address.

To enter the 4-byte address mode, please refer to the enter 4-byte mode (EN4B) Mode section.

The sequence of issuing SE instruction is: CS# goes low→ sending SE instruction code→ 3-byte or 4-byte address

on SI→ CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in

Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets 1 during the tSE

timing, and clears when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the

Block is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector Protect

Mode), the Sector Erase (SE) instruction will not be executed on the block.

Figure 70. Sector Erase (SE) Sequence (SPI Mode)

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

29 30 31

SCLK

24-Bit Address

(Note)

Command

20h

SI

A23 A22

A2 A1 A0

MSB

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the

address cycles will be increased.

Figure 71. Sector Erase (SE) Sequence (QPI Mode)

CS#

Mode 3

0

1

2

3

4

5

6

7

SCLK

Mode 0

24-Bit Address

(Note)

Command

A20- A16- A12- A8- A4-

A0-

A3

SIO[3:0]

20h

A23 A19 A15 A11

A7

MSB

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the

address cycles will be increased.

P/N: PM2244

Rev. 1.1, June 29, 2017

72

MX25U51245G

10-25. Block Erase (BE32K)

The Block Erase (BE32K) instruction is for erasing the data of the chosen block to be "1". The instruction is used

for 32K-byte block erase operation. A Write Enable (WREN) instruction be executed to set the Write Enable

Latch (WEL) bit before sending the Block Erase (BE32K). Any address of the block (Please refer to "5. MEMORY

ORGANIZATION") is a valid address for Block Erase (BE32K) instruction. The CS# must go high exactly at the byte

boundary (the least signiﬁcant bit of address byte been latched-in); otherwise, the instruction will be rejected and not

executed.

Address bits [Am-A15] (Am is the most signiﬁcant address) select the 32KB block address. The default read mode

is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode

or to deﬁne EAR bit. To enter the 4-byte address mode, please refer to the enter 4-byte mode (EN4B) Mode section.

The sequence of issuing BE32K instruction is: CS# goes low→ sending BE32K instruction code→ 3-byte or 4-byte

address on SI→CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

The self-timed Block Erase Cycle time (tBE32K) is initiated as soon as Chip Select (CS#) goes high. The Write in

Progress (WIP) bit still can be checked while during the Block Erase cycle is in progress. The WIP sets during the

tBE32K timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared.

If the Block is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector

Protect Mode), the Block Erase (BE32K) instruction will not be executed on the block.

Figure 72. Block Erase 32KB (BE32K) Sequence (SPI Mode)

CS#

0

1

2

3

4

5

6

7

8

9

29 30 31

Mode 3

Mode 0

SCLK

Command

52h

24-Bit Address

(Note)

SI

A23 A22

A2 A1 A0

MSB

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the

address cycles will be increased.

Figure 73. Block Erase 32KB (BE32K) Sequence (QPI Mode)

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

SCLK

24-Bit Address

(Note)

Command

A20- A16- A12- A8- A4-

A23 A19 A15 A11 A7

A0-

A3

SIO[3:0]

52h

MSB

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the

address cycles will be increased.

P/N: PM2244

Rev. 1.1, June 29, 2017

73

MX25U51245G

10-26. Block Erase (BE)

The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used

for 64K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable

Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (Please refer to "5. MEMORY

ORGANIZATION") is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte

boundary (the least signiﬁcant bit of address byte been latched-in); otherwise, the instruction will be rejected and not

executed.

The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the

4-byte address read mode or to deﬁne EAR bit. To enter the 4-byte address mode, please refer to the enter 4-byte

mode (EN4B) Mode section.

The sequence of issuing BE instruction is: CS# goes low→ sending BE instruction code→ 3-byte or 4-byte address

on SI→ CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in

Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets during the tBE

timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the Block

is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector Protect Mode),

the Block Erase (BE) instruction will not be executed on the block.

Figure 74. Block Erase (BE) Sequence (SPI Mode)

CS#

0

1

2

3

4

5

6

7

8

9

29 30 31

Mode 3

Mode 0

SCLK

Command

D8h

24-Bit Address

(Note)

SI

A23 A22

A2 A1 A0

MSB

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the

address cycles will be increased.

Figure 75. Block Erase (BE) Sequence (QPI Mode)

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

SCLK

24-Bit Address

(Note)

Command

A20- A16- A12- A8- A4-

A0-

A3

SIO[3:0]

D8h

A23 A19 A15 A11

A7

MSB

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the

address cycles will be increased.

P/N: PM2244

Rev. 1.1, June 29, 2017

74

MX25U51245G

10-27. Chip Erase (CE)

The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN)

instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS#

must go high exactly at the byte boundary, otherwise the instruction will be rejected and not executed.

The sequence of issuing CE instruction is: CS# goes low→sending CE instruction code→CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in

Progress (WIP) bit still can be checked while the Chip Erase cycle is in progress. The WIP sets during the tCE

timing, and clears when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared.

When the chip is under "Block protect (BP) Mode" (WPSEL=0). The Chip Erase (CE) instruction will not be

executed, if one (or more) sector is protected by BP3-BP0 bits. It will be only executed when BP3-BP0 all set to "0".

When the chip is under "Advances Sector Protect Mode" (WPSEL=1). The Chip Erase (CE) instruction will be

executed on unprotected block. The protected Block will be skipped. If one (or more) 4K byte sector was protected

in top or bottom 64K byte block, the protected block will also skip the chip erase command.

Figure 76. Chip Erase (CE) Sequence (SPI Mode)

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

SCLK

SI

Command

60h or C7h

Figure 77. Chip Erase (CE) Sequence (QPI Mode)

CS#

0

1

Mode 3

Mode 0

SCLK

Command

60h or C7h

SIO[3:0]

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10-28. Page Program (PP)

The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction

must be executed to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device

programs only the last 256 data bytes sent to the device. If the entire 256 data bytes are going to be programmed,

A7-A0 (The eight least signiﬁcant address bits) should be set to 0. The last address byte (the 8 least signiﬁcant

address bits, A7-A0) should be set to 0 for 256 bytes page program. If A7-A0 are not all zero, transmitted data that

exceed page length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently

selected page. If the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the request

page and previous data will be disregarded. If the data bytes sent to the device has not exceeded 256, the data

will be programmed at the request address of the page. There will be no effort on the other data bytes of the same

page.

The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the

4-byte address read mode or to deﬁne EAR bit. To enter the 4-byte address mode, please refer to the enter 4-byte

mode (EN4B) Mode section.

The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte or 4-byte address

on SI→ at least 1-byte on data on SI→ CS# goes high.

The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte

boundary( the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be

executed.

The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in

Progress (WIP) bit still can be checked while the Page Program cycle is in progress. The WIP sets during the tPP

timing, and clears when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the

page is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector Protect

Mode), the Page Program (PP) instruction will not be executed.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

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Figure 78. Page Program (PP) Sequence (SPI Mode)

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38 39

SCLK

Command

02h

Data Byte 1

24-Bit Address

(Note)

23 22 21

MSB

3

2

1

0

7

6

5

4

3

2

0

1

SI

MSB

CS#

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

SCLK

Data Byte 2

Data Byte 3

Data Byte 256

7

6

5

4

3

2

0

7

6

5

4

3

2

0

7

6

5

4

3

2

0

1

SI

MSB

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the

address cycles will be increased.

Figure 79. Page Program (PP) Sequence (QPI Mode)

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

SCLK

Command

02h

24-Bit Address

(Note)

A20-

A23

A16-

A19

A12-

A15

A8-

A11

A4-

A7

A0-

A3

H255 L255

SIO[3:0]

H0 L0 H1 L1 H2 L2 H3 L3

Data Byte Data Byte Data Byte Data Byte

......

Data Byte

256

Data In

1

2

3

4

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the

address cycles will be increased.

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10-29. 4 x I/O Page Program (4PP)

The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN)

instruction must be executed to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to

"1" before sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1,

SIO2, and SIO3 as address and data input, which can improve programmer performance and the effectiveness of

application. The other function descriptions are as same as standard page program.

The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the

4-byte address read mode or to deﬁne EAR bit. To enter the 4-byte address mode, please refer to the enter 4-byte

mode (EN4B) Mode section.

The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte or 4-byte

address on SIO[3:0]→ at least 1-byte on data on SIO[3:0]→CS# goes high.

If the page is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector

Protect Mode), the Quad Page Program (4PP) instruction will not be executed.

Figure 80. 4 x I/O Page Program (4PP) Sequence (SPI Mode only)

CS#

10 11 12 13 14 15 16 17 18 19 20 21

Data Data Data Data

0

1

2

3

4

5

6

7

8

9

Mode 3

Mode 0

SCLK

Command

38h

6 Address cycle

Byte 1 Byte 2 Byte 3 Byte 4

A16

A8 A4 A0

A12

A20

4

0

4

0

4

0

4

0

SIO0

SIO1

SIO2

SIO3

A21 A17 A13 A9 A5 A1

5

6

7

1

2

3

5

6

7

1

2

3

5

6

7

1

2

3

5

6

7

1

2

3

A22

A14 A10 A6 A2

A18

A7

A23 A19 A15 A11

A3

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the

address cycles will be increased.

P/N: PM2244

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10-30. Deep Power-down (DP)

The Deep Power-down (DP) instruction is for setting the device to minimum power consumption (the standby

current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction

to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction are

ignored. When CS# goes high, it's only in deep power-down mode not standby mode. It's different from Standby

mode.

The sequence of issuing DP instruction is: CS# goes low→sending DP instruction code→CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP)

and Read Electronic Signature (RES) instruction and softreset command. (those instructions allow the ID being

reading out). When Power-down, or software reset command the deep power-down mode automatically stops, and

when power-up, the device automatically is in standby mode. For DP instruction the CS# must go high exactly at the

byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed.

As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode.

Figure 81. Deep Power-down (DP) Sequence (SPI Mode)

CS#

t

DP

0

1

2

3

4

5

6

7

Mode 3

Mode 0

SCLK

SI

Command

B9h

Stand-by Mode

Deep Power-down Mode

Figure 82. Deep Power-down (DP) Sequence (QPI Mode)

CS#

t

DP

Mode 3

Mode 0

0

1

SCLK

Command

SIO[3:0]

B9h

Stand-by Mode

Deep Power-down Mode

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10-31. Enter Secured OTP (ENSO)

The ENSO instruction is for entering the additional 8K-bit secured OTP mode. While device is in secured OTPmode,

main array access is not available. The additional 8K-bit secured OTP is independent from main array and may be

used to store unique serial number for system identiﬁer. After entering the Secured OTP mode, follow standard read

or program procedure to read out the data or update data. The Secured OTP data cannot be updated again once it

is lock-down.

The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP

mode→ CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

Please note that after issuing ENSO command user can only access secure OTP region with standard read or

program procedure. Furthermore, once security OTP is lock down, only read related commands are valid.

10-32. Exit Secured OTP (EXSO)

The EXSO instruction is for exiting the secured OTP mode.

The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP

mode→ CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

10-33. Read Security Register (RDSCUR)

The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read

at any time (even in program/erase/write status register/write security register condition) and continuously.

The sequence of issuing RDSCUR instruction is : CS# goes low→sending RDSCUR instruction→Security Register

data out on SO→ CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

10-34. Write Security Register (WRSCUR)

The WRSCUR instruction is for changing the values of Security Register Bits. The WREN (Write Enable) instruction

is required before issuing WRSCUR instruction. The WRSCUR instruction may change the values of bit1 (LDSO bit)

for customer to lock-down the Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area cannot be

updated any more.

The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.

P/N: PM2244

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MX25U51245G

10-35. Write Protection Selection (WPSEL)

There are two write protection methods provided on this device, (1) Block Protection (BP) mode or (2) Advanced

Sector Protection mode. The protection modes are mutually exclusive. The WPSEL bit selects which protection

mode is enabled. If WPSEL=0 (factory default), BP mode is enabled and Advanced Sector Protection mode is

disabled. If WPSEL=1, Advanced Sector Protection mode is enabled and BP mode is disabled. The WPSEL

command is used to set WPSEL=1. A WREN command must be executed to set the WEL bit before sending the

WPSEL command. Please note that the WPSEL bit is an OTP bit. Once WPSEL is set to “1”, it cannot be

programmed back to “0”.

When WPSEL = 0: Block Protection (BP) mode,

The memory array is write protected by the BP3~BP0 bits.

When WPSEL =1: Advanced Sector Protection mode,

Blocks are individually protected by their own SPB or DPB. On power-up, all blocks are write protected by the

Dynamic Protection Bits (DPB) by default. The Advanced Sector Protection instructions WRLR, RDLR, WRPASS,

RDPASS, PASSULK, WRSPB, ESSPB, WRDPB, RDDPB, GBLK, and GBULK are activated. The BP3~BP0 bits

of the Status Register are disabled and have no effect. Hardware protection is performed by driving WP#=0. Once

WP#=0 all blocks and sectors are write protected regardless of the state of each SPB or DPB.

The sequence of issuing WPSEL instruction is: CS# goes low → send WPSEL instruction to enable the Advanced

Sector Protect mode → CS# goes high.

Write Protection Selection

Start

(Default in BP Mode)

WPSEL=1

WPSEL=0

Set

WPSEL Bit

Advanced

Sector Protection

Block Protection

(BP)

Set

Bit 2 =1

Lock Register

Bit 2 =0

Password

Protection

Solid

Protection

Dynamic

Protection

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MX25U51245G

Figure 83. WPSEL Flow

start

WREN command

RDSCUR command

Yes

WPSEL=1?

No

WPSEL disable,

block protected by BP[3:0]

WPSEL command

RDSR command

No

WIP=0?

Yes

RDSCUR command

No

WPSEL=1?

Yes

WPSEL set successfully

WPSEL set fail

WPSEL enable.

Block protected by Advance Sector Protection

P/N: PM2244

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10-36. Advanced Sector Protection

There are two ways to implement software Advanced Sector Protection on this device. Through these two protection

methods, user can disable or enable the programming or erasing operation to any individual sector or all sectors.

There is a non-volatile (SPB) and volatile (DPB) protection bit related to the single sector in main ﬂash array. Each

of the sectors is protected from programming or erasing operation when the bit is set.

The ﬁgure below helps describing an overview of these methods. The device is default to the Solid mode when

shipped from factory. The detail algorithm of advanced sector protection is shown as follows:

Figure 84. Advanced Sector Protection Overview

Start

Bit 2=1

Bit 2=0

Set

Lock Register ?

Solid Protection Mode

Password Protection Mode

Set 64 bit Password

Set

Bit 6 = 0

SPB Locked

All SPB can not be changeable

SPB Lock Down Bit ?

(SPBLKDN)

Bit 6 = 1

SPB Unlocked

SPB is changeable

Solid Protection Bits

(SPB)

Dynamic Protect Bit Register

(DPB)

Sector Array

SPB=1 Write Protect

DPB=1 sector protect

SPB=0 Write Unprotect

DPB=0 sector unprotect

DPB 0

DPB 1

SA 0

SA 1

SPB 0

SPB 1

DPB 2

SA 2

SPB 2

:

DPB N-1

DPB N

SA N-1

SA N

SPB N-1

SPB N

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MX25U51245G

10-36-1. Lock Register

The Lock Register is a 16-bit register. Lock Register Bit[6] is SPB Lock Down Bit (SPBLKDN) which is assigned to

control all SPB bit status. Lock Register Bit[2] is Password Protection Mode Lock Bit. Both bits are defaulted as 1

when shipping from factory.

When SPBLKDN is 1, SPB can be changed. When it is locked as 0, all SPB can not be changed.

Users can choose their favorite sector protecting method via setting Lock Register Bit[2] using WRLR command.

The device default status was in Solid Protection Mode (Bit[2]=1), Once Bit[2] has been programmed (cleared to

"0"), the device will enable the Password Protection Mode and lock in that mode permanently.

In Solid Protection Mode (Bit[2]=1, factory default), the SPBLKDN can be programmed using the WRLR command

and permanently lock down the SPB bits. After programming SPBLKDN to 0, all SPB can not be changed anymore,

and neither Lock Register Bit[2] nor Bit[6] can be altered anymore.

In Password Protection Mode (Bit[2]=0), the SPBLKDN becomes a volatile bit with default 0 (SPB bit protected).

A correct password is required with PASSULK command to set SPBLKDN to 1. To clear SPBLKDN back to 0, a

Hardware/Software Reset or power-up cycle is required.

If user selects Password Protection mode, the password setting is required. User can set password by issuing

WRPASS command before Lock Register Bit[2] set to 0.

Lock Register

Bits

Description

Bit Status

Default

Type

7

Reserved

SPB Lock Down bit 0: SPB bit Protected

Solid Protection Mode: 1

Password Protection Mode: 0 Bit 2=0: Volatile

Bit 2=1: OTP

6

(SPBLKDN)

1: SPB bit Unprotected

5 to 3

Reserved

Password Protection 0=Password Protection Mode Enable

2

1

OTP

Mode Lock Bit

1= Solid Protection Mode

1 to 0

Reserved

Figure 85. Read Lock Register (RDLR) Sequence

CS#

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

Mode 3

Mode 0

SCLK

SI

command

2Dh

Register Out

High-Z

SO

7

6

5

4

3

2

1

0

15 14 13 12 11 10

MSB

9

8

7

MSB

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MX25U51245G

Figure 86. Write Lock Register (WRLR) Sequence (SPI Mode)

CS#

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Mode 3

Mode 0

SCLK

Command

2Ch

Lock Register In

15 14

13

SI

4

12 11

10

8

2

1

0

9

7

6

5

3

MSB

High-Z

SO

10-36-2. Solid Protection Bits

The Solid Protection Bits (SPBs) are nonvolatile bits for enabling or disabling write-protection to sectors and blocks.

The SPB bits have the same endurance as the Flash memory. An SPB is assigned to each 4KB sector in the bottom

and top 64KB of memory and to each 64KB block in the remaining memory. The factory default state of the SPB bits

is “0”, which has the sector/block write-protection disabled.

When an SPB is set to “1”, the associated sector or block is write-protected. Program and erase operations on the

sector or block will be inhibited. SPBs can be individually set to “1” by the WRSPB command. However, the SPBs

cannot be individually cleared to “0”. Issuing the ESSPB command clears all SPBs to “0”. A WREN command must

be executed to set the WEL bit before sending the WRSPB or ESSPB command.

The SPBLKDN bit must be “1” before any SPB can be modiﬁed. In Solid Protection mode the SPBLKDN bit defaults to “1”

after power-on or reset. Under Password Protection mode, the SPBLKDN bit defaults to “0” after power-on or reset,

and a PASSULK command with a correct password is required to set the SPBLKDN bit to “1”.

The RDSPB command reads the status of the SPB of a sector or block. The RDSPB command returns 00h if the

SPB is “0”, indicating write-protection is disabled. The RDSPB command returns FFh if the SPB is “1”, indicating

write-protection is enabled.

Note: If SPBLKDN=0, commands to set or clear the SPB bits will be ignored.

SPB Register

Bit

Description

Bit Status

Default

Type

00h= SPB for the sector address unprotected

FFh= SPB for the sector address protected

7 to 0 SPB (Solid protected Bit)

00h

Non-volatile

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MX25U51245G

Figure 87. Read SPB Status (RDSPB) Sequence

CS#

0

1

2

3

4

5

6

7

8

9

37 38 39 40 41 42 43 44 45 46 47

Mode 3

Mode 0

SCLK

Command

E2h

32-Bit Address

A31 A30

A2 A1 A0

SI

MSB

Data Out

High-Z

SO

7

6

5

4

3

2

1

0

MSB

Figure 88. SPB Erase (ESSPB) Sequence

CS#

0

1

2

3

4

5

6

7

Mode 3

SCLK

Mode 0

Command

E4h

SI

High-Z

SO

Figure 89. SPB Program (WRSPB) Sequence

CS#

0

1

2

3

4

5

6

7

8

9

37 38 39

Mode 3

Mode 0

SCLK

Command

E3h

32-Bit Address

A31 A30

A2 A1 A0

SI

MSB

P/N: PM2244

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10-36-3. Dynamic Write Protection Bits

The Dynamic Protection features a volatile type protection to each individual sector. It can protect sectors from

unintentional change, and is easy to disable when there are necessary changes.

All DPBs are default as protected (FFh) after reset or upon power up cycle. Via setting up Dynamic Protection bit (DPB)

by write DPB command (WRDPB), user can cancel the Dynamic Protection of associated sector.

The Dynamic Protection only works on those unprotected sectors whose SPBs are cleared. After the DPB state is

cleared to “0”, the sector can be modiﬁed if the SPB state is unprotected state.

DPB Register

Bit

Description

Bit Status

Default

Type

00h= DPB for the sector address unprotected

FFh= DPB for the sector address protected

7 to 0 DPB (Dynamic protected Bit)

FFh

Volatile

Figure 90. Read DPB Register (RDDPB) Sequence

CS#

0

1

2

3

4

5

6

7

8

9

37 38 39 40 41 42 43 44 45 46 47

Mode 3

Mode 0

SCLK

Command

E0h

32-Bit Address

A31 A30

A2 A1 A0

SI

MSB

Data Out

High-Z

SO

7

6

5

4

3

2

1

0

MSB

Figure 91. Write DPB Register (WRDPB) Sequence

CS#

0

1

2

3

4

5

6

7

8

9

37 38 39 40 41 42 43 44 45 46 47

Mode 3

Mode 0

SCLK

Command

E1h

Data Byte 1

32-Bit Address

A31 A30

A2 A1 A0

SI

7

6

5

4

3

2

1

0

MSB

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10-36-4. Password Protection Mode

Password Protection mode potentially provides a higher level of security than Solid Protection mode. In Password

Protection mode, the SPBLKDN bit defaults to “0” after a power-on cycle or reset. When SPBLKDN=0, the SPBs

are locked and cannot be modiﬁed. A 64-bit password must be provided to unlock the SPBs.

The PASSULK command with the correct password will set the SPBLKDN bit to “1” and unlock the SPB bits. After

the correct password is given, a wait of 2us is necessary for the SPB bits to unlock. The Status Register WIP bit will

clear to “0” upon completion of the PASSULK command. Once unlocked, the SPB bits can be modiﬁed. A WREN

command must be executed to set the WEL bit before sending the PASSULK command.

Several steps are required to place the device in Password Protection mode. Prior to entering the Password

Protection mode, it is necessary to set the 64-bit password and verify it. The WRPASS command writes the

password and the RDPASS command reads back the password. Password veriﬁcation is permitted until the

Password Protection Mode Lock Bit has been written to “0”. Password Protection mode is activated by programming

the Password Protection Mode Lock Bit to “0”. This operation is not reversible. Once the bit is programmed, it

cannot be erased. The device remains permanently in Password Protection mode and the 64-bit password can

neither be retrieved nor reprogrammed..

The password is all “1’s” when shipped from the factory. The WRPASS command can only program password bits to “0”.

The WRPASS command cannot program “0’s” back to “1’s”. All 64-bit password combinations are valid password

options. A WREN command must be executed to set the WEL bit before sending the WRPASS command.

● The unlock operation will fail if the password provided by the PASSULK command does not match the stored

password. This will set the P_FAIL bit to “1” and insert a delay before clearing the WIP bit to “0”. User has to

wait 150us before issuing another PASSULK command. This restriction makes it impractical to attempt all

combinations of a 64-bit password (such an effort would take millions of years). Monitor the WIP bit to determine

whether the device has completed the PASSULK command.

● When a valid password is provided, the PASSULK command does not insert the delay before returning the WIP

bit to zero. The SPBLKDN bit will set to “1” and the P_FAIL bit will be “0”.

● It is not possible to set the SPBLKDN bit to “1” if the password had not been set prior to the Password Protection

mode being selected.

Password Register (PASS)

Field

Name

Description

Bits

Function Type

Default State

Non-volatile OTP storage of 64 bit password. The

password is no longer readable after the Password

Protection mode is selected by programming Lock

Register bit 2 to zero.

Hidden

Password

63 to 0 PWD

OTP FFFFFFFFFFFFFFFFh

P/N: PM2244

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MX25U51245G

Figure 92. Read Password Register (RDPASS) Sequence

CS#

0

1

2

3

4

5

6

7

8

39 40

47 48

109 110

Mode 3

Mode 0

SCLK

Command

27h

32-bit Address

8 Dummy

SI

0

Data Out

High-Z

SO

7

6

58 57 56

MSB

Figure 93. Write Password Register (WRPASS) Sequence

CS#

39 40

102 103

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

SCLK

Command

28h

32-bit Address

Password

SI

7

6

58 57 56

0

MSB

High-Z

SO

Figure 94. Password Unlock (PASSULK) Sequence

CS#

39 40

102 103

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

SCLK

Command

29h

32-bit Address

Password

SI

7

6

58 57 56

0

MSB

High-Z

SO

P/N: PM2244

Rev. 1.1, June 29, 2017

89

MX25U51245G

10-36-5. Gang Block Lock/Unlock (GBLK/GBULK)

These instructions are only effective after WPSEL was executed. The GBLK/GBULK instruction is a chip-based

protected or unprotected operation. It can enable or disable all DPB.

The WREN (Write Enable) instruction is required before issuing GBLK/GBULK instruction.

The sequence of issuing GBLK/GBULK instruction is: CS# goes low → send GBLK/GBULK (7Eh/98h) instruction

→CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

The CS# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed.

10-36-6. Sector Protection States Summary Table

Protection Status

Sector State

DPB bit

SPB bit

0

1

0

1

0

1

Unprotect

Protect

P/N: PM2244

Rev. 1.1, June 29, 2017

90

MX25U51245G

10-37. Program Suspend and Erase Suspend

The Suspend instruction interrupts a Program or Erase operation to allow the device conduct other operations.

After the device has entered the suspended state, the memory array can be read except for the page being

programmed or the sector being erased.

Security Register bit 2 (PSB) and bit 3 (ESB) can be read to check the suspend status. The PSB (Program Suspend

Bit) sets to “1” when a program operation is suspended. The ESB (Erase Suspend Bit) sets to “1” when an erase

operation is suspended. The PSB or ESB clears to “0” when the program or erase operation is resumed.

When the Serial NOR Flash receives the Suspend instruction, Program Suspend Latency(tPSL) or Erase Suspend

latency(tESL) is required to complete suspend operation. (Refer to "Table 23. AC CHARACTERISTICS") After the

device has entered the suspended state, the WEL bit is clears to “0” and the PSB or ESB in security register is set to “1”,

then the device is ready to acceptanother command.

However, some commands can be executed without tPSL or tESL latency during the program/erase suspend, and

can be issued at any time during the Suspend.

Please refer to "Table 13. Acceptable Commands During Suspend".

Figure 95. Suspend to Read Latency

tPSL / tESL

Read Command

Suspend Command

CS#

10-37-1. Erase Suspend to Program

The “Erase Suspend to Program” feature allows Page Programming while an erase operation is suspended. Page

Programming is permitted in any unprotected memory except within the sector of a suspended Sector Erase

operation or within the block of a suspended Block Erase operation. The Write Enable (WREN) instruction must be

issued before any Page Program instruction.

A Page Program operation initiated within a suspended erase cannot itself be suspended and must be allowed to

ﬁnish before the suspended erase can be resumed. The Status Register can be polled to determine the status of

the Page Program operation. The WEL and WIP bits of the Status Register will remain “1” while the Page Program

operation is in progress and will both clear to “0” when the Page Program operation completes.

Figure 96. Suspend to Program Latency

tPSL / tESL

Suspend Command

Program Command

CS#

P/N: PM2244

Rev. 1.1, June 29, 2017

91

MX25U51245G

Table 13. Acceptable Commands During Suspend

Command Name Command Code

Commands which require tPSL/tESL delay

Suspend Type

Program Suspend

Erase Suspend

READ

03h

•

FAST READ

0Bh

BBh

3Bh

EBh

6Bh

ECh

EDh

EEh

0Ch

BCh

3Ch

5Ah

9Fh

AFh

C0h

B1h

C1h

06h

30h

2Dh

E2h

16h

E0h

35h

F5h

2READ

DREAD

4READ

QREAD

4READ4B

4DTRD

4DTRD4B

FASTREAD4B

2READ4B

DREAD4B

RDSFDP

RDID

QPIID

SBL

ENSO

EXSO

WREN

RESUME

RDLR

RDSPB

RDFBR

RDDPB

EQIO

RSTQIO

Commands not required tPSL/tESL delay

WRDI

RDSR

RDCR

RDSCUR

RES

04h

05h

15h

2Bh

ABh

90h

66h

99h

00h

•

REMS

RSTEN

RST

NOP

P/N: PM2244

Rev. 1.1, June 29, 2017

92

MX25U51245G

10-38. Program Resume and Erase Resume

The Resume instruction resumes a suspended Program or Erase operation. After the device receives the Resume

instruction, the WEL and WIP bits are set to “1” and the PSB or ESB is cleared to “0”.The program or erase

operation will continue until it is completed or until another Suspend instruction is received.

To issue another Suspend instruction, the minimum resume-to-suspend latency (tPRS or tERS) is required.

However, in order to ﬁnish the program or erase progress, a period equal to or longer than the typical timing is

required.

To issue other command except suspend instruction, a latency of the self-timed Page Program Cycle time (tPP) or

Sector Erase (tSE) is required. The WEL and WIP bits are cleared to “0” after the Program or Erase operation is

completed.

Note:

The Resume instruction will be ignored during Performance Enhance Mode. Make sure the Serial NOR Flash has

exited the Performance Enhance Mode before issuing the Resume instruction.

Figure 97. Resume to Read Latency

tSE / tBE / tPP

Read Command

Resume Command

CS#

Figure 98. Resume to Suspend Latency

tPRS / tERS

Suspend

Resume

Command

CS#

Command

P/N: PM2244

Rev. 1.1, June 29, 2017

93

MX25U51245G

10-39. No Operation (NOP)

The “No Operation” command is only able to terminate the Reset Enable (RSTEN) command and will not affect any

other command.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

during SPI mode.

10-40. Software Reset (Reset-Enable (RSTEN) and Reset (RST))

The Software Reset operation combines two instructions: Reset-Enable (RSTEN) command and Reset (RST)

command. It returns the device to standby mode. All the volatile bits and settings will be cleared then, which makes

the device return to the default status as power on.

To execute Reset command (RST), the Reset-Enable (RSTEN) command must be executed ﬁrst to perform the

Reset operation. If there is any other command to interrupt after the Reset-Enable command, the Reset-Enable will

be invalid.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

If the Reset command is executed during program or erase operation, the operation will be disabled, the data under

processing could be damaged or lost.

The reset time is different depending on the last operation. For details, please refer to "Table 19. Reset Timing-

(Other Operation)" for tREADY2.

P/N: PM2244

Rev. 1.1, June 29, 2017

94

MX25U51245G

Figure 99. Software Reset Recovery

Stand-by Mode

66

99

CS#

tREADY2

Mode

Note: Refer to "Table 19. Reset Timing-(Other Operation)" for tREADY2.

Figure 100. Reset Sequence (SPI mode)

tSHSL

CS#

Mode 3

Mode 0

Mode 3

Mode 0

SCLK

SIO0

Command

66h

Command

99h

Figure 101. Reset Sequence (QPI mode)

tSHSL

CS#

MODE 3

MODE 0

MODE 3

MODE 0

SCLK

MODE 0

Command

SIO[3:0]

66h

99h

P/N: PM2244

Rev. 1.1, June 29, 2017

95

MX25U51245G

11. Serial Flash Discoverable Parameter (SFDP)

11-1. Read SFDP Mode (RDSFDP)

The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional

and feature capabilities of serial ﬂash devices in a standard set of internal parameter tables. These parameter tables

can be interrogated by host system software to enable adjustments needed to accommodate divergent features

from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on

CFI.

The sequence of issuing RDSFDP instruction is CS# goes low→send RDSFDP instruction (5Ah)→send 3 address

bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP operation can use CS#

to high at any time during data out.

SFDP is a JEDEC standard, JESD216B.

Figure 102. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence

CS#

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31

SCLK

Command

5Ah

24 BIT ADDRESS

SI

23 22 21

3

2

1

0

High-Z

SO

CS#

47

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

SCLK

Dummy Cycle

7

6

5

4

3

2

0

1

SI

DATA OUT 2

DATA OUT 1

7

6

5

4

3

2

1

0

7

6

5

4

3

2

0

1

SO

MSB

P/N: PM2244

Rev. 1.1, June 29, 2017

96

MX25U51245G

Table 14. Signature and Parameter Identiﬁcation Data Values

SFDP Table (JESD216B) below is for MX25U51245GMI0A, MX25U51245GXDI0A, MX25U51245GMI00,

MX25U51245GXDI00 and MX25U51245GZ4I00

Add (h) DW Add Data (h/b) Data

Description

Comment

(Byte)

(Bit)

(Note1)

(h)

00h

07:00

53h

01h

02h

03h

04h

05h

15:08

23:16

31:24

07:00

15:08

46h

44h

50h

06h

01h

46h

44h

50h

06h

01h

SFDP Signature

Fixed: 50444653h

SFDP Minor Revision Number

Start from 00h

Start from 01h

SFDP Major Revision Number

This number is 0-based. Therefore,

0 indicates 1 parameter header.

Number of Parameter Headers

Unused

06h

07h

08h

23:16

31:24

07:00

02h

FFh

00h

02h

FFh

00h

00h: it indicates a JEDEC speciﬁed

header.

ID number (JEDEC)

Parameter Table Minor Revision

Number

Parameter Table Major Revision

Number

Parameter Table Length

(in double word)

Start from 00h

Start from 01h

09h

0Ah

0Bh

15:08

23:16

31:24

06h

01h

10h

06h

01h

10h

How many DWORDs in the

Parameter table

0Ch

0Dh

0Eh

07:00

15:08

23:16

30h

00h

30h

00h

First address of JEDEC Flash

Parameter table

Parameter Table Pointer (PTP)

Unused

0Fh

31:24

FFh

P/N: PM2244

Rev. 1.1, June 29, 2017

97

MX25U51245G

SFDP Table below is for MX25U51245GMI0A, MX25U51245GXDI0A, MX25U51245GMI00,

MX25U51245GXDI00 and MX25U51245GZ4I00

Add (h) DW Add Data (h/b) Data

Description

Comment

(Byte)

(Bit)

(Note1)

(h)

ID number

(Macronix manufacturer ID)

it indicates Macronix manufacturer

ID

10h

07:00

C2h

Parameter Table Minor Revision

Number

Parameter Table Major Revision

Number

Parameter Table Length

(in double word)

Start from 00h

Start from 01h

11h

12h

13h

15:08

23:16

31:24

00h

01h

04h

00h

01h

04h

How many DWORDs in the

Parameter table

14h

15h

16h

07:00

15:08

23:16

10h

01h

00h

10h

01h

00h

First address of Macronix Flash

Parameter table

Parameter Table Pointer (PTP)

Unused

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

31:24

07:00

15:08

23:16

31:24

07:00

15:08

23:16

31:24

FFh

84h

00h

01h

02h

C0h

00h

FFh

84h

00h

01h

02h

C0h

00h

FFh

ID number

(4-byte Address Instruction)

Parameter Table Minor Revision

Number

Parameter Table Major Revision

Number

Parameter Table Length

(in double word)

4-byte Address Instruction

parameter ID

Start from 00h

Start from 01h

How many DWORDs in the

Parameter table

First address of 4-byte Address

Instruction table

Parameter Table Pointer (PTP)

Unused

P/N: PM2244

Rev. 1.1, June 29, 2017

98

MX25U51245G

Table 15. Parameter Table (0): JEDEC Flash Parameter Tables

SFDP Table below is for MX25U51245GMI0A, MX25U51245GXDI0A, MX25U51245GMI00,

MX25U51245GXDI00 and MX25U51245GZ4I00

Add (h) DW Add Data (h/b) Data

Description

Comment

(Byte)

(Bit)

(Note1)

(h)

00: Reserved, 01: 4KB erase,

10: Reserved,

11: not supported 4KB erase

Block/Sector Erase sizes

Write Granularity

01:00

01b

0: 1Byte, 1: 64Byte or larger

02

03

1b

0b

Write Enable Instruction Required 0: not required

for Writing to Volatile Status

1: required 00h to be written to the

Registers

status register

30h

E5h

0: use 50h instruction

1: use 06h instruction

Write Enable Instruction Select for

Writing to Volatile Status Registers

Note: If target ﬂash status register is

nonvolatile, then bits 3 and 4 must

be set to 00b.

04

0b

Contains 111b and can never be

changed

Unused

07:05

111b

4KB Erase Instruction

31h

32h

33h

15:08

16

20h

1b

20h

FBh

FFh

(1-1-2) Fast Read (Note2)

0=not supported 1=supported

Address Bytes Number used in

addressing ﬂash array

00: 3Byte only, 01: 3 or 4Byte,

10: 4Byte only, 11: Reserved

18:17

19

01b

1b

Double Transfer Rate (DTR)

Clocking

0=not supported 1=supported

(1-2-2) Fast Read

(1-4-4) Fast Read

(1-1-4) Fast Read

Unused

0=not supported 1=supported

20

21

1b

22

1b

23

1b

Unused

31:24

FFh

Flash Memory Density

37h:34h 31:00

1FFF FFFFh

(1-4-4) Fast Read Number of Wait 0 0000b: Not supported; 0 0100b: 4

04:00

38h

0 0100b

states (Note3)

0 0110b: 6; 0 1000b: 8

44h

EBh

08h

6Bh

(1-4-4) Fast Read Number of

Mode Bits (Note4)

Mode Bits:

000b: Not supported; 010b: 2 bits

07:05

010b

EBh

(1-4-4) Fast Read Instruction

39h

3Ah

3Bh

15:08

20:16

(1-1-4) Fast Read Number of Wait 0 0000b: Not supported; 0 0100b: 4

0 1000b

states

0 0110b: 6; 0 1000b: 8

(1-1-4) Fast Read Number of

Mode Bits

Mode Bits:

000b: Not supported; 010b: 2 bits

23:21

31:24

000b

6Bh

(1-1-4) Fast Read Instruction

P/N: PM2244

Rev. 1.1, June 29, 2017

99

MX25U51245G

SFDP Table below is for MX25U51245GMI0A, MX25U51245GXDI0A, MX25U51245GMI00,

MX25U51245GXDI00 and MX25U51245GZ4I00

Add (h) DW Add Data (h/b) Data

Description

Comment

(Byte)

(Bit)

(Note1)

(h)

(1-1-2) Fast Read Number of Wait 0 0000b: Not supported; 0 0100b: 4

04:00

0 1000b

states

0 0110b: 6; 0 1000b: 8

3Ch

08h

(1-1-2) Fast Read Number of

Mode Bits

Mode Bits:

000b: Not supported; 010b: 2 bits

07:05

15:08

20:16

000b

3Bh

(1-1-2) Fast Read Instruction

3Dh

3Eh

3Fh

3Bh

04h

BBh

(1-2-2) Fast Read Number of Wait 0 0000b: Not supported; 0 0100b: 4

0 0100b

states

0 0110b: 6; 0 1000b: 8

(1-2-2) Fast Read Number of

Mode Bits

Mode Bits:

000b: Not supported; 010b: 2 bits

23:21

000b

(1-2-2) Fast Read Instruction

(2-2-2) Fast Read

Unused

31:24

00

BBh

0b

0=not supported 1=supported

03:01

04

111b

1b

40h

FEh

(4-4-4) Fast Read

Unused

07:05

111b

FFh

Unused

43h:41h 31:08

45h:44h 15:00

FFh

Unused

(2-2-2) Fast Read Number of Wait 0 0000b: Not supported; 0 0100b: 4

20:16

46h

0 0000b

000b

states

0 0110b: 6; 0 1000b: 8

00h

(2-2-2) Fast Read Number of

Mode Bits

Mode Bits:

000b: Not supported; 010b: 2 bits

23:21

(2-2-2) Fast Read Instruction

Unused

47h

31:24

FFh

49h:48h 15:00

(4-4-4) Fast Read Number of Wait 0 0000b: Not supported; 0 0100b: 4

20:16

4Ah

0 0100b

states

0 0110b: 6; 0 1000b: 8

44h

(4-4-4) Fast Read Number of

Mode Bits

Mode Bits:

000b: Not supported; 010b: 2 bits

23:21

010b

EBh

0Ch

20h

0Fh

52h

10h

D8h

00h

FFh

(4-4-4) Fast Read Instruction

4Bh

4Ch

4Dh

4Eh

4Fh

50h

51h

52h

53h

31:24

07:00

15:08

23:16

31:24

07:00

15:08

23:16

31:24

EBh

0Ch

20h

0Fh

52h

10h

D8h

00h

FFh

Sector/block size = 2^N bytes (Note5)

0Ch: 4KB; 0Fh: 32KB; 10h: 64KB

Erase Type 1 Size

Erase Type 1 Erase Instruction

Erase Type 2 Size

Sector/block size = 2^N bytes

00h: N/A; 0Fh: 32KB; 10h: 64KB

Erase Type 2 Erase Instruction

Erase Type 3 Size

Sector/block size = 2^N bytes

00h: N/A; 0Fh: 32KB; 10h: 64KB

Erase Type 3 Erase Instruction

Erase Type 4 Size

00h: N/A, This sector type doesn't

exist

Erase Type 4 Erase Instruction

P/N: PM2244

Rev. 1.1, June 29, 2017

100

MX25U51245G

SFDP Table below is for MX25U51245GMI0A, MX25U51245GXDI0A, MX25U51245GMI00,

MX25U51245GXDI00 and MX25U51245GZ4I00

Add (h) DW Add Data (h/b) Data

Description

Comment

(Byte)

(Bit)

(Note1)

(h)

Multiplier value: 0h~Fh (0~15)

Max. time = 2 * (Multiplier + 1) *

Typical Time

Multiplier from typical erase time

to maximum erase time

03:00

0011b

54h

D3h

07:04

08

Count value: 00h~1Fh (0~31)

Typical Time = (Count + 1) * Units

1 1101b

00b

Erase Type 1 Erase Time

(Typical)

Units

00: 1ms, 01: 16ms

10b: 128ms, 11b: 1s

10:09

15:11

17:16

55h

56h

49h

C5h

Count value: 00h~1Fh (0~31)

Typical Time = (Count + 1) * Units

0 1001b

01b

EraseType 2 Erase Time

(Typical)

Units

00: 1ms, 01: 16ms

10b: 128ms, 11b: 1s

Count value: 00h~1Fh (0~31)

Typical Time = (Count + 1) * Units

22:18

1 0001b

Erase Type 3 Erase Time

(Typical)

Units

00: 1 ms, 01: 16 ms

10b: 128ms, 11b: 1s

24:23

29:25

31:30

01b

0 0000b

00b

Count value: 00h~1Fh (0~31)

Typical Time = (Count + 1) * Units

57h

00h

Erase Type 4 Erase Time

(Typical)

Units

00: 1ms, 01: 16ms

10b: 128 ms, 11b: 1 s

Multiplier value: 0h~Fh (0~15)

Max. time = 2 * (Multiplier + 1)

*Typical Time

Multiplier from typical time

to max time for Page or byte

program

03:00

0001b

58h

59h

81h

Page size = 2^N bytes

2^8 = 256 bytes, 8h = 1000b

Page Program Size

07:04

12:08

1000h

Count value: 00h~1Fh (0~31)

Typical Time = (Count + 1) * Units

1 1111b

Page Program Time

(Typical)

DFh

Units

0: 8us, 1: 64us

13

0b

0011b

1b

15:14

17:16

Count value: 0h~Fh (0~15)

Byte Program Time, First Byte Typical Time = (Count + 1) * Units

(Typical)

Units

0: 1us, 1: 8us

18

22:19

23

04h

5Ah

Count value: 0h~Fh (0~15)

Typical Time = (Count + 1) * Units

0000b

0b

Byte Program Time, Additional

Byte

(Typical)

Units

0: 1us, 1: 8us

P/N: PM2244

Rev. 1.1, June 29, 2017

101

MX25U51245G

SFDP Table below is for MX25U51245GMI0A, MX25U51245GXDI0A, MX25U51245GMI00,

MX25U51245GXDI00 and MX25U51245GZ4I00

Add (h) DW Add Data (h/b) Data

Description

Comment

(Byte)

(Bit)

27:24

28

(Note1)

(h)

Count value: 00h~1Fh (0~31)

Typical Time = (Count + 1) * Units

0 0011b

Chip Erase Time

Units

(Typical)

5Bh

E3h

00: 16ms, 01: 256ms

10: 4s, 11: 64s

Reserved: 1b

30:29

31

11b

1b

Reserved

xxx0b: May not initiate a new erase

ꢀ

anywhere

xx0xb: May not initiate a new page

ꢀ

program anywhere

Prohibited Operations During

Program Suspend

x1xxb: May not initiate a read in

ꢀ

03:00

0100b

the program suspended

page size

1xxxb: The erase and program

ꢀ

restrictions in bits 1:0 are

sufﬁcient

xxx0b: May not initiate a new erase

ꢀ

anywhere

5Ch

44h

xx1xb: May not initiate a page

ꢀ

program in the erase

suspended sector size

xx0xb: May not initiate a page

ꢀ

program anywhere

x1xxb: May not initiate a read in

ꢀ

Prohibited Operations During

Erase Suspend

07:04

0100b

the erase suspended sector

size

1xxxb: The erase and program

ꢀ

restrictions in bits 5:4 are

sufﬁcient

Reserved

Reserved: 1b

08

1b

Count value: 0h~Fh (0~15)

Typical Time = (Count + 1) * 64us

Count value: 00h~1Fh (0~31)

Maximum Time = (Count + 1) * Units

Units

00: 128ns, 01: 1us

10: 8us, 11: 64us

Program Resume to Suspend

Interval (Typical)

5Dh

5Eh

01h

07h

12:09

0000b

15:13

17:16

1 1000b

01b

Program Suspend Latency

(Max.)

19:18

Count value: 0h~Fh (0~15)

Typical Time = (Count + 1) * 64us

Count value: 00h~1Fh (0~31)

Maximum Time = (Count + 1) * Units

Units

00: 128ns, 01: 1us

Erase Resume to Suspend

Interval (Typical)

23:20

28:24

0000b

1 1000b

Erase Suspend Latency

(Max.)

5Fh

38h

30:29

01b

10: 8us, 11: 64us

Suspend / Resume supported

Program Resume Instruction

Program Suspend Instruction

Erase Resume Instruction

Erase Suspend Instruction

0= Support 1= Not supported

Instruction to Resume a Program

Instruction to Suspend a Program

Instruction to Resume Write/Erase

Instruction to Suspend Write/Erase

31

0b

60h

61h

62h

63h

07:00

15:08

23:16

31:24

30h

B0h

30h

B0h

30h

B0h

30h

B0h

P/N: PM2244

Rev. 1.1, June 29, 2017

102

MX25U51245G

SFDP Table below is for MX25U51245GMI0A, MX25U51245GXDI0A, MX25U51245GMI00,

MX25U51245GXDI00 and MX25U51245GZ4I00

Add (h) DW Add Data (h/b) Data

Description

Comment

Reserved: 11b

Bit 2: Read WIP bit [0] by 05h Read

(Byte)

(Bit)

(Note1)

(h)

Reserved

01:00

11b

ꢀ

instruction

Status Register Polling Device

Busy

Bit 3: Read bit 7 of Status Register

ꢀ

64h

F7h

07:02

11 1101b

by 70h Read instruction

(0=not supported 1=support)

Bit 07:04, Reserved: 1111b

ꢀ

Count value: 00h~1Fh (0~31)

Release from Deep Power-down Maximum Time = (Count + 1) * Units

12:08

14:13

1 1101b

01b

Units

00: 128ns, 01: 1us

(RDP) Delay

(Max.)

65h

BDh

10: 8us, 11: 64us

Instruction to Exit Deep Power Down

FFh: Don't need command

ꢀ

Instruction to Enter Deep Power

Down

0: Supported 1: Not supported

Methods to exit 4-4-4 mode

xx1xb: issue F5h instruction

ꢀ

15

22:16

23

30:24

31

1010 1011b

(ABh)

1011 1001b

(B9h)

Release from Deep Power-down

(RDP) Instruction

Enter Deep Power Down

Instruction

66h

67h

D5h

5Ch

Deep Power Down Supported

0b

4-4-4 Mode Disable Sequences

4-4-4 Mode Enable Sequences

03:00

1010b

68h

4Ah

Methods to enter 4-4-4 mode

x_x1xxb: issue instruction 35h

ꢀ

07:04

08

0 0100b

Performance Enhance Mode,

Continuous Read, Execute in Place

0: Not supported 1: Supported

0-4-4 Mode Supported

09

1b

xx_xxx1b: Mode Bits[7:0] = 00h will

ꢀ

terminate this mode at the end

of the current read operation.

xx_xx1xb: If 3-Byte address active,

ꢀ

input Fh on DQ0-DQ3 for 8

clocks. If 4-Byte address active,

input Fh on DQ0-DQ3 for 10

clocks.

69h

9Eh

0-4-4 Mode Exit Method

15:10

10 0111b

xx_x1xxb: Reserved

ꢀ

xx_1xxxb: Input Fh (mode bit reset)

ꢀ

on DQ0-DQ3 for 8 clocks.

x1_xxxxb: Mode Bit[7:0]≠Axh

ꢀ

1x_xxxxb: Reserved

ꢀ

xxx1b: Mode Bits[7:0] = A5h Note:

ꢀ

QE must be set prior to using

this mode

0-4-4 Mode Entry Method

19:16

1001h

x1xxb: Mode Bit[7:0]=Axh

ꢀ

1xxxb: Reserved

ꢀ

000b: No QE bit. Detects 1-1-4/1-4-

ꢀ

4 reads based on instruction

6Ah

29h

Quad Enable (QE) bit

Requirements

010b: QE is bit 6 of Status Register.

ꢀ

22:20

23

010b

0b

where 1=Quad Enable or

0=not Quad Enable

111b: Not Supported

ꢀ

HOLD and RESET Disable by bit

4 of Ext. Conﬁguration Register

0: Not supported

P/N: PM2244

Rev. 1.1, June 29, 2017

103

MX25U51245G

SFDP Table below is for MX25U51245GMI0A, MX25U51245GXDI0A, MX25U51245GMI00,

MX25U51245GXDI00 and MX25U51245GZ4I00

Add (h) DW Add Data (h/b) Data

Description

Comment

(Byte)

(Bit)

(Note1)

(h)

Reserved

6Bh

31:24

FFh

xxx_xxx1b: Non-Volatile Status

ꢀ

Register 1, powers-up to last

written value, use instruction

06h to enable write

Volatile or Non-Volatile Register

and Write Enable Instruction for

Status Register 1

06:00

111 0000b

6Ch

6Dh

F0h

50h

x1x_xxxxb: Reserved

ꢀ

1xx_xxxxb: Reserved

ꢀ

Reserved

07

1b

01 0000b

01b

Return the device to its default

power-on state

x1_xxxxb: issue reset enable

ꢀ

instruction 66h, then issue reset

instruction 99h.

xx_xxxx_xxx1b: issue instruction

ꢀ

Soft Reset and Rescue

Sequence Support

13:08

15:14

E9h to exit 4-Byte address

mode (write enable instruction

06h is not required)

xx_xxxx_x1xxb: 8-bit volatile

ꢀ

extended address register used

to deﬁne A[31:A24] bits. Read

with instruction C8h. Write

instruction is C5h, data length

is 1 byte. Return to lowest

memory segment by setting

A[31:24] to 00h and use 3-Byte

addressing.

Exit 4-Byte Addressing

6Eh

23:16

1111 1001b F9h

xx_xx1x_xxxxb: Hardware reset

ꢀ

xx_x1xx_xxxxb: Software reset

ꢀ

(see bits 13:8 in this DWORD)

xx_1xxx_xxxxb: Power cycle

ꢀ

x1_xxxx_xxxxb: Reserved

ꢀ

1x_xxxx_xxxxb: Reserved

ꢀ

P/N: PM2244

Rev. 1.1, June 29, 2017

104

MX25U51245G

SFDP Table below is for MX25U51245GMI0A, MX25U51245GXDI0A, MX25U51245GMI00,

MX25U51245GXDI00 and MX25U51245GZ4I00

Add (h) DW Add Data (h/b) Data

Description

Comment

xxxx_xxx1b: issue instruction

(Byte)

(Bit)

(Note1)

(h)

ꢀ

B7h (preceding write

enable not required)

xxxx_x1xxb: 8-bit volatile extended

ꢀ

address register used

to deﬁne A[31:24] bits.

Read with instruction

C8h. Write instruction

is C5h with 1 byte of

data. Select the active

128 Mbit memory

segment by setting the

appropriate A[31:24]

bits and use 3-Byte

addressing.

Enter 4-Byte Addressing

6Fh

31:24 1000 0101b 85h

xx1x_xxxxb: Supports dedicated

ꢀ

4-Byte address

instruction set. Consult

vendor data sheet

for the instruction set

deﬁnition.

1xxx_xxxxb: Reserved

ꢀ

P/N: PM2244

Rev. 1.1, June 29, 2017

105

MX25U51245G

Table 16. Parameter Table (1): 4-Byte Instruction Tables

SFDP Table below is for MX25U51245GMI0A, MX25U51245GXDI0A, MX25U51245GMI00,

MX25U51245GXDI00 and MX25U51245GZ4I00

Add (h) DW Add Data (h/b) Data

Description

Comment

(Byte)

(Bit)

(Note1)

(h)

Support for (1-1-1) READ

0=not supported 1=supported

00

1b

Command, Instruction=13h

Support for (1-1-1) FAST_READ

Command, Instruction=0Ch

Support for (1-1-2) FAST_READ

Command, Instruction=3Ch

Support for (1-2-2) FAST_READ

Command, Instruction=BCh

Support for (1-1-4) FAST_READ

Command, Instruction=6Ch

Support for (1-4-4) FAST_READ

Command, Instruction=ECh

Support for (1-1-1) Page Program

Command, Instruction=12h

Support for (1-1-4) Page Program

Command, Instruction=34h

Support for (1-4-4) Page Program

Command, Instruction=3Eh

Support for Erase Command –

01

02

03

04

05

06

07

08

1b

0b

1b

C0h

7Fh

Type 1 size, Instruction lookup in 0=not supported 1=supported

next Dword

Support for Erase Command –

Type 2 size, Instruction lookup in 0=not supported 1=supported

next Dword

Support for Erase Command –

Type 3 size, Instruction lookup in 0=not supported 1=supported

next Dword

Support for Erase Command –

Type 4 size, Instruction lookup in 0=not supported 1=supported

next Dword

09

10

11

12

1b

0b

C1h

8Fh

Support for (1-1-1) DTR_Read

0=not supported 1=supported

Command, Instruction=0Eh

Support for (1-2-2) DTR_Read

0=not supported 1=supported

Command, Instruction=BEh

Support for (1-4-4) DTR_Read

0=not supported 1=supported

Command, Instruction=EEh

13

14

15

0b

1b

P/N: PM2244

Rev. 1.1, June 29, 2017

106

MX25U51245G

SFDP Table below is for MX25U51245GMI0A, MX25U51245GXDI0A, MX25U51245GMI00,

MX25U51245GXDI00 and MX25U51245GZ4I00

Add (h) DW Add Data (h/b) Data

Description

Comment

(Byte)

(Bit)

(Note1)

(h)

Support for volatile individual

sector lock Read command,

Instruction=E0h

Support for volatile individual

sector lock Write command,

Instruction=E1h

Support for non-volatile individual

sector lock read command,

Instruction=E2h

Support for non-volatile individual

sector lock write command,

Instruction=E3h

0=not supported 1=supported

16

1b

17

18

19

1b

C2h

FFh

Reserved

23:20

31:24

07:00

15:08

23:16

31:24

1111b

FFh

21h

Reserved

C3h

C4h

C5h

C6h

C7h

FFh

21h

5Ch

DCh

FFh

Instruction for Erase Type 1

Instruction for Erase Type 2

Instruction for Erase Type 3

Instruction for Erase Type 4

FFh=not supported

5Ch

DCh

FFh

P/N: PM2244

Rev. 1.1, June 29, 2017

107

MX25U51245G

Table 17. Parameter Table (2): Macronix Flash Parameter Tables

SFDP Table below is for MX25U51245GMI0A, MX25U51245GXDI0A, MX25U51245GMI00,

MX25U51245GXDI00 and MX25U51245GZ4I00

Add (h) DW Add Data (h/b) Data

Description

Comment

2000h=2.000V

2700h=2.700V

3600h=3.600V

(Byte)

(Bit)

(Note1)

(h)

07:00

15:08

00h

20h

00h

20h

Vcc Supply Maximum Voltage

111h:110h

1650h=1.650V, 1750h=1.750V

2250h=2.250V, 2300h=2.300V

2350h=2.350V, 2650h=2.650V

2700h=2.700V

23:16

31:24

50h

16h

50h

16h

113h: 112h

Vcc Supply Minimum Voltage

H/W Reset# pin

0=not supported 1=supported

00

1b

H/W Hold# pin

0=not supported 1=supported

01

02

03

0b

1b

Deep Power Down Mode

S/W Reset

Reset Enable (66h) should be

issued before Reset Instruction

1001 1001b

(99h)

F99Dh

115h: 114h

S/W Reset Instruction

11:04

Program Suspend/Resume

Erase Suspend/Resume

Unused

0=not supported 1=supported

12

13

14

15

1b

Wrap-Around Read mode

0=not supported 1=supported

Wrap-Around Read mode

Instruction

116h

117h

23:16

C0h

64h

08h:support 8B wrap-around read

16h:8B&16B

32h:8B&16B&32B

Wrap-Around Read data length

31:24

64h

64h:8B&16B&32B&64B

Individual block lock

0=not supported 1=supported

00

01

1b

0b

Individual block lock bit

(Volatile/Nonvolatile)

0=Volatile 1=Nonvolatile

1110 0001b

(E1h)

Individual block lock Instruction

09:02

10

Individual block lock Volatile

protect bit default protect status

0=protect 1=unprotect

0b

CB85h

11Bh: 118h

Secured OTP

Read Lock

Permanent Lock

Unused

0=not supported 1=supported

11

12

1b

0b

13

0b

15:14

31:16

11b

FFh

Unused

FFh

Unused

11Fh: 11Ch 31:00

P/N: PM2244

Rev. 1.1, June 29, 2017

108

MX25U51245G

Note 1: h/b is hexadecimal or binary.

Note 2: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x),

address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1),

(2-2-2), and (4-4-4)

Note 3: Wait States is required dummy clock cycles after the address bits or optional mode bits.

Note 4: Mode Bits is optional control bits that follow the address bits. These bits are driven by the system

controller if they are speciﬁed. (eg,read performance enhance toggling bits)

Note 5: 4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h

Note 6: All unused and undeﬁned area data is blank FFh for SFDP Tables that are deﬁned in Parameter

Identiﬁcation Header. All other areas beyond deﬁned SFDP Table are reserved by Macronix.

P/N: PM2244

Rev. 1.1, June 29, 2017

109

MX25U51245G

12. RESET

Driving the RESET# pin low for a period of tRLRH or longer will reset the device. After reset cycle, the device is at

the following states:

- Standby mode

- All the volatile bits such as WEL/WIP/SRAM lock bit will return to the default status as power on.

- 3-byte address mode

If the device is under programming or erasing, driving the RESET# pin low will also terminate the operation and data

could be lost. During the resetting cycle, the SO data becomes high impedance and the current will be reduced to

minimum.

Figure 103. RESET Timing

CS#

tRHSL

SCLK

tRH

tRS

RESET#

tRLRH

tREADY1 / tREADY2

Table 18. Reset Timing-(Power On)

Symbol Parameter

tRHSL Reset# high before CS# low

Min.

10

Typ.

Max.

Unit

us

tRS

tRH

Reset# setup time

Reset# hold time

15

ns

tRLRH Reset# low pulse width

tREADY1 Reset Recovery time

10

35

us

Table 19. Reset Timing-(Other Operation)

Symbol Parameter

tRHSL Reset# high before CS# low

Min.

10

Typ.

Max.

Unit

us

tRS

tRH

Reset# setup time

Reset# hold time

15

ns

tRLRH Reset# low pulse width

10

us

Reset Recovery time (During instruction decoding)

Reset Recovery time (for read operation)

40

us

Reset Recovery time (for program operation)

tREADY2 Reset Recovery time(for SE4KB operation)

Reset Recovery time (for BE64K/BE32KB operation)

Reset Recovery time (for Chip Erase operation)

Reset Recovery time (for WRSR operation)

310

12

25

1000

40

us

ms

P/N: PM2244

Rev. 1.1, June 29, 2017

110

MX25U51245G

13. POWER-ON STATE

The device is at below states when power-up:

- Standby mode (please note it is not deep power-down mode)

- Write Enable Latch (WEL) bit is reset

The device must not be selected during power-up and power-down stage unless the VCC achieves below correct

level:

- VCC minimum at power-up stage and then after a delay of tVSL

- GND at power-down

Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.

An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change

during power up state. When VCC is lower than VWI (POR threshold voltage value), the internal logic is reset and

the ﬂash device has no response to any command.

For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not

guaranteed. The write, erase, and program command should be sent after the below time delay:

- tVSL after VCC reached VCC minimum level

The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.

Please refer to the "power-up timing".

Note:

- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is

recommended. (generally around 0.1uF)

- At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response

to any command. The data corruption might occur during the stage while a write, program, erase cycle is in

progress.

P/N: PM2244

Rev. 1.1, June 29, 2017

111

MX25U51245G

14. ELECTRICAL SPECIFICATIONS

Table 20. ABSOLUTE MAXIMUM RATINGS

Rating

Value

Ambient Operating Temperature

Storage Temperature

Industrial grade

-40°C to 85°C

-65°C to 150°C

-0.5V to VCC+0.5V

-0.5V to 2.5V

Applied Input Voltage

Applied Output Voltage

VCC to Ground Potential

NOTICE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage

to the device. This is stress rating only and functional operational sections of this speciﬁcation is not implied.

Exposure to absolute maximum rating conditions for extended period may affect reliability.

2. Speciﬁcations contained within the following tables are subject to change.

3. During voltage transitions, all pins may overshoot to VCC+1.0V or -1.0V for period up to 20ns.

Figure 105. Maximum Positive Overshoot Waveform

Figure 104. Maximum Negative Overshoot Waveform

20ns

0V

VCC+1.0V

-1.0V

2.0V

20ns

Table 21. CAPACITANCE TA = 25°C, f = 1.0 MHz

Symbol Parameter

Min.

Typ.

Max.

Unit

pF

Conditions

VIN = 0V

CIN

Input Capacitance

8

COUT Output Capacitance

pF

VOUT = 0V

P/N: PM2244

Rev. 1.1, June 29, 2017

112

MX25U51245G

Figure 106. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL

Input timing reference level

Output timing reference level

0.8VCC

0.2VCC

0.7VCC

0.3VCC

AC

Measurement

Level

0.5VCC

Note: Input pulse rise and fall time are <1ns

Figure 107. OUTPUT LOADING

25K ohm

+1.8V

DEVICE UNDER

TEST

CL

25K ohm

CL=30pF Including jig capacitance

Figure 108. SCLK TIMING DEFINITION

tCLCH

tCHCL

VIH (Min.)

0.5VCC

VIL (Max.)

tCH

tCL

1/fSCLK

P/N: PM2244

Rev. 1.1, June 29, 2017

113

MX25U51245G

Table 22. DC CHARACTERISTICS

Temperature = -40 C to 85 C, VCC = 1.65V ~ 2.0V

°

Symbol Parameter

Notes

Min.

Typ.

Max.

Units Test Conditions

VCC = VCC Max,

uA

ILI

Input Load Current

1

±2

VIN = VCC or GND

VCC = VCC Max,

uA

ILO

Output Leakage Current

1

VOUT = VCC or GND

VIN = VCC or GND,

CS# = VCC

ISB1 VCC Standby Current

20

3

180

50

uA

Deep Power-down

Current

VIN = VCC or GND,

CS# = VCC

ISB2

uA

f=100MHz, (DTR 4 x I/O read)

mA SCLK=0.1VCC/0.9VCC,

SO=Open

25

22

18

13

35

30

25

16

f=133MHz, (4 x I/O read)

mA SCLK=0.1VCC/0.9VCC,

SO=Open

VCC Read

ICC1

1

(Note 3)

f=104MHz, (4 x I/O read)

mA SCLK=0.1VCC/0.9VCC,

SO=Open

f=84MHz,

mA SCLK=0.1VCC/0.9VCC,

SO=Open

VCC Program Current

Program in Progress,

CS# = VCC

ICC2

(PP)

1

30

20

40

mA

VCC Write Status

ICC3

Program status register in

mA

Register (WRSR) Current

progress, CS#=VCC

VCC Sector/Block (32K,

ICC4 64K) Erase Current

(SE/BE/BE32K)

1

30

20

40

mA Erase in Progress, CS#=VCC

VCC Chip Erase Current

ICC5

(CE)

40

mA Erase in Progress, CS#=VCC

VIL

VIH

VOL

Input Low Voltage

Input High Voltage

Output Low Voltage

-0.4

0.3VCC

VCC+0.4

0.2

V

0.7VCC

V

IOL = 100uA

IOH = -100uA

VOH Output High Voltage

VCC-0.2

Notes :

1. Typical values at VCC = 1.8V, T = 25 C. These currents are valid for all product versions (package and speeds).

°

2. Typical value is calculated by simulation.

3. Pattern = Blank

P/N: PM2244

Rev. 1.1, June 29, 2017

114

MX25U51245G

Table 23. AC CHARACTERISTICS

Temperature = -40 C to 85 C, VCC = 1.65V ~ 2.0V

°

Symbol Alt. Parameter

Min.

Typ.

Max. Unit

166 MHz

66 MHz

fSCLK

fC Clock Frequency for all commands(except Read Operation) D.C.

fR Clock Frequency for READ instructions

fRSCLK

Clock Frequency for FAST READ, DREAD, 2READ,

QREAD, 4READ, 4DTRD

see "Dummy Cycle and

Frequency Table (MHz)"

45% x (1/

fSCLK)

fTSCLK

tCH⁽¹⁾

MHz

Others (fSCLK)

ns

tCLH Clock High Time

Normal Read (fRSCLK)

Others (fSCLK)

7

45% x (1/

fSCLK)

tCL⁽¹⁾

tCLL Clock Low Time

Normal Read (fRSCLK)

Clock Rise Time (peak to peak)

Clock Fall Time (peak to peak)

7

0.1

3

4

2

ns

V/ns

ns

tCLCH⁽²⁾

tCHCL⁽²⁾

tSLCH tCSS CS# Active Setup Time (relative to SCLK)

tCHSL CS# Not Active Hold Time (relative to SCLK)

tDVCH tDSU Data In Setup Time

tCHDX

tCHSH

tSHCH

tDH Data In Hold Time

2

3

ns

CS# Active Hold Time (relative to SCLK)

CS# Not Active Setup Time (relative to SCLK)

From Read to next Read

From Write/Erase/Program

to Read Status Register

7

ns

tSHSL tCSH CS# Deselect Time

tSHQZ⁽²⁾tDIS Output Disable Time

30

ns

8

5

8

6

5

ns

us

Loading: 30pF

24-BGA Loading: 15pF

Loading: 10pF

tCLQV

tV Clock Low to Output Valid

Loading: 30pF

16-SOP,

Loading: 15pF

8-WSON

Loading: 10pF

tCLQX

tWHSL⁽³⁾

tSHWL⁽³⁾

tDP⁽²⁾

tHO Output Hold Time

Write Protect Setup Time

Write Protect Hold Time

1

20

100

CS# High to Deep Power-down Mode

CS# High to Standby Mode without Electronic Signature

Read

CS# High to Standby Mode with Electronic Signature Read

Write Status/Conﬁguration Register no-volatile bit Cycle

Time

10

30

40

tRES1⁽²⁾

tRES2⁽²⁾

tW

us

ms

tWREAW

tBP

Write Extended Address Register

Byte-Program

40

25

ns

us

60

tPP

Page Program Cycle Time

0.15

0.75 ms

0.016 + 0.009*

(n/16) ⁽⁶⁾

25

tPP⁽⁵⁾

Page Program Cycle Time (n bytes)

0.75 ms

tSE

tBE32

tBE

Sector Erase Cycle Time

400 ms

1000 ms

2000 ms

Block Erase (32KB) Cycle Time

Block Erase (64KB) Cycle Time

Chip Erase Cycle Time

150

220

150

tCE

300

s

P/N: PM2244

Rev. 1.1, June 29, 2017

115

MX25U51245G

Symbol Alt. Parameter

Min.

Typ.

Max. Unit

tESL⁽⁸⁾

tPSL⁽⁸⁾

tPRS⁽⁹⁾

tERS⁽¹⁰⁾

Erase Suspend Latency

Program Suspend Latency

Latency between Program Resume and next Suspend

Latency between Erase Resume and next Suspend

25

us

0.3

100

400

Notes:

1. tCH + tCL must be greater than or equal to 1/ Frequency.

2. Typical values given for TA=25 C. Not 100% tested.

°

3. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.

4. Test condition is shown as Figure 106 and Figure 107.

5. While programming consecutive bytes, Page Program instruction provides optimized timings by selecting to

program the whole 256 bytes or only a few bytes between 1~256 bytes.

6. “n”=how many bytes to program(n>2). The number of (n/16) will be round up to next integer. In the formula,

while n=1, byte program time=32us. While n=17, byte program time=48us.

7. By default dummy cycle value. Please refer to the "Table 1. Read performance Comparison".

8. Latency time is required to complete Erase/Program Suspend operation until WIP bit is "0".

9. For tPRS, minimum timing must be observed before issuing the next program suspend command. However, a

period equal to or longer than the typical timing is required in order for the program operation to make progress.

10. For tERS, minimum timing must be observed before issuing the next erase suspend command. However, a

period equal to or longer than the typical timing is required in order for the erase operation to make progress.

P/N: PM2244

Rev. 1.1, June 29, 2017

116

MX25U51245G

15. OPERATING CONDITIONS

At Device Power-Up and Power-Down

AC timing illustrated in Figure 109 and Figure 110 are for the supply voltages and the control signals at device

power-up and power-down. If the timing in the ﬁgures is ignored, the device will not operate correctly.

During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be

selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL.

Figure 109. AC Timing at Device Power-Up

VCC(min)

VCC

GND

tVR

tSHSL

CS#

tSHCH

tSLCH

tCHSL

tCHSH

SCLK

tDVCH

tCHCL

tCHDX

tCLCH

MSB IN

LSB IN

SI

High Impedance

SO

Symbol

Parameter

Notes

Min.

Max.

Unit

tVR

VCC Rise Time

1

500000

us/V

Notes :

1. Sampled, not 100% tested.

2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the ﬁgure, please refer to

Table 23. AC CHARACTERISTICS.

P/N: PM2244

Rev. 1.1, June 29, 2017

117

MX25U51245G

Figure 110. Power-Down Sequence

During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.

VCC

CS#

SCLK

Figure 111. Power-up Timing

V

CC

V

(max)

CC

Chip Selection is Not Allowed

V

(min)

CC

Device is fully accessible

tVSL

V

WI

time

P/N: PM2244

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MX25U51245G

Figure 112. Power Up/Down and Voltage Drop

When powering down the device, VCC must drop below VPWD for at least tPWD to ensure the device will initialize

correctly during power up. Please refer to "Figure 112. Power Up/Down and Voltage Drop" and "Table 24. Power-Up/

Down Voltage and Timing" below for more details.

VCC

VCC (max.)

Chip Select is not allowed

VCC (min.)

V_keep

tVSL

Full Device

Access

Allowed

VWI

(max.)

V

PWD

tPWD

Time

Table 24. Power-Up/Down Voltage and Timing

Symbol Parameter

Min.

Max.

Unit

VCC voltage needed to below V_PWDfor ensuring initialization

will occur

V_PWD

0.8

V

Voltage that a re-initialization is necessary if VDD drop

below to VKEEP

V_keep

1.5

V

tPWD

tVSL

VCC

VWI

The minimum duration for ensuring initialization will occur

VCC(min.) to device operation

VCCPower Supply

300

1500

1.65

1.0

us

V

2.0

1.5

Write Inhibit Voltage

V

Note: These parameters are characterized only.

15-1. INITIAL DELIVERY STATE

The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status

Register contains 00h (all Status Register bits are 0).

P/N: PM2244

Rev. 1.1, June 29, 2017

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MX25U51245G

16. ERASE AND PROGRAMMING PERFORMANCE

Parameter

Min.

Typ. ⁽¹⁾

Max. ⁽²⁾

40

Unit

ms

Write Status Register Cycle Time

Sector Erase Cycle Time (4KB)

Block Erase Cycle Time (32KB)

Block Erase Cycle Time (64KB)

Chip Erase Cycle Time

25

150

400

ms

1000

2000

300

ms

220

ms

150

s

Byte Program Time (via page program command)

Page Program Time

25

60

us

0.15

100,000

0.75

ms

Erase/Program Cycle

cycles

Note:

1. Typical program and erase time assumes the following conditions: 25 C, 1.8V, and checkerboard pattern.

°

2. Under worst conditions of 85 C and 1.65V.

°

3. System-level overhead is the time required to execute the ﬁrst-bus-cycle sequence for the programming

command.

4. The maximum chip programming time is evaluated under the worst conditions of 0°C, VCC=1.8V, and 100K

cycle with 90% conﬁdence level.

17. DATA RETENTION

Parameter

Condition

Min.

Max.

Unit

Data retention

55˚C

20

years

18. LATCH-UP CHARACTERISTICS

Min.

Max.

Input Voltage with respect to GND on all power pins

Input current with respect to GND on all non-power pins

Test conditions are compliant to JEDEC JDESD78 standard

1.5 VCCmax

+100mA

-100mA

P/N: PM2244

Rev. 1.1, June 29, 2017

120

MX25U51245G

19. ORDERING INFORMATION

Please contact Macronix regional sales for the latest product selection and available form factors.

PART NO.

MX25U51245GMI0A

MX25U51245GXDI0A

MX25U51245GMI00

MX25U51245GXDI00

MX25U51245GZ4I00

TEMPERATURE

PACKAGE

Remark

-40 C to 85 C

16-SOP (300mil)

°

24-Ball BGA

-40 C to 85 C

°

(5x5 ball array)

Supported password

protection feature

-40 C to 85 C

16-SOP (300mil)

°

24-Ball BGA

Supported password

protection feature

-40 C to 85 C

°

(5x5 ball array)

8-WSON

(8x6mm, 3.4 x 4.3 EP)

Supported password

protection feature

-40 C to 85 C

°

P/N: PM2244

Rev. 1.1, June 29, 2017

121

MX25U51245G

20. PART NAME DESCRIPTION

MX 25 U 51245G

M

I

00

MODEL CODE:

0A: STR, x1 I/O enable

00: STR, x1 I/O enable

TEMPERATURE RANGE:

I: Industrial (-40°C to 85°C)

PACKAGE:

M: 16-SOP (300mil)

XD: 24-Ball BGA (5x5 ball array)

Z4: 8-WSON (8x6mm, 3.4 x 4.3 EP)

DENSITY & MODE:

51245G: 512Mb

TYPE:

U: 1.8V

DEVICE:

25: Serial NOR Flash

P/N: PM2244

Rev. 1.1, June 29, 2017

122

MX25U51245G

21. PACKAGE INFORMATION

P/N: PM2244

Rev. 1.1, June 29, 2017

123

MX25U51245G

P/N: PM2244

Rev. 1.1, June 29, 2017

124

MX25U51245G

P/N: PM2244

Rev. 1.1, June 29, 2017

125

MX25U51245G

22. REVISION HISTORY

Revision No. Description

Page

Date

0.01

1. Content correction

P13,24,30

MAY/22/2015

0.02

1. Modiﬁed "Output Driver Strength Table"

2. Removed USPB function

P27

All

JUL/24/2015

3. Updated suspend/resume descriptions.

4. Updated ISB1 & ISB2

P91-93

P114

5. Modiﬁed "18. LATCH-UP CHARACTERISTICS"

6. Content correction

P120

P13,22,23

0.03

1. Changed Document status to "Preliminary"

2. Added 8-WSON (8x6mm) package

3. Added Ordering Information

4. Updated parameters for DC/AC Characteristics

5. Updated CIN & COUT value

All

MAR/03/2016

P6,8,119,120,123

P119,120

P112,113,118

P110

6. Modiﬁed Min. VCCPower Supply from 1.7V to 1.65V

7. Updated VWI Max. spec

All

P117

8. Content correction

P8,28,34,64-67,

P111,113,118

0.04

1. Added Password Protection

P23,81,83,84,

P88,89,121,122

P114,115,120

P119

AUG/24/2016

2. Updated parameters for DC/AC Characteristics

3. Modiﬁed tVSL value (Min.)

4. Updated tVR values

5. Modiﬁed 8-WSON package outline

6. Content correction

P117,119

P125

P24,54-57

0.05

1. Updated the note for the internal pull up status of RESET#,

RESET#/SIO3 and WP#/SIO2

P8

NOV/15/2016

2. Content correction.

P44,57,64,65

3. Removed Part Number: MX25U51245GZ2I0A

P121

1.0

1. Removed "Preliminary" to align with the product status

2. Content correction.

All

NOV/23/2016

JUN/29/2017

P24,25,28,119

1.1

1. Changed WSON package from Z2 to Z4 and

update package outline.

2. Added "Figure 108. SCLK TIMING DEFINITION"

P6,8,97-108,

P121,122,125

P113

3. Added Note for "Table 24. Power-Up/Down Voltage and Timing" P119

4. Updated n bytes program parameter

5. Format modiﬁcation.

P115,116

P123-125

P/N: PM2244

Rev. 1.1, June 29, 2017

126

MX25U51245G

Except for customized products which have been expressly identiﬁed in the applicable agreement, Macronix's

products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or

household applications only, and not for use in any applications which may, directly or indirectly, cause death,

personal injury, or severe property damages. In the event Macronix products are used in contradicted to their

target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualiﬁed for its

actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/

or distributors shall be released from any and all liability arisen therefrom.

tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, Nbit,

Macronix NBit, eLiteFlash, HybridNVM, HybridFlash, HybridXFlash, XtraROM, Phines, KH Logo, BE-

SONOS, KSMC, Kingtech, MXSMIO, Macronix vEE, Macronix MAP, Rich Book, Rich TV, OctaRAM, OctaBus,

OctaFlash and FitCAM. The names and brands of third party referred thereto (if any) are for identiﬁcation

purposes only.

For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and speciﬁcations without notice.

127


型号：	MX25U51245GMI00
厂家：	MACRONIX INTERNATIONAL
描述：	Flash, 128MX4, PDSO16, SOP-16 时钟光电二极管内存集成电路
文件：	总127页 (文件大小：1532K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MX25U51245GMI00 [Macronix]

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