MX29F805BPC-12 [Macronix]
Flash, 512KX16, 120ns, PDIP42;型号: | MX29F805BPC-12 |
厂家: | MACRONIX INTERNATIONAL |
描述: | Flash, 512KX16, 120ns, PDIP42 光电二极管 内存集成电路 |
文件: | 总34页 (文件大小:187K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ADVANCED INFORMATION
MX29F805T/B
8M-BIT [1Mx8/512Kx16] CMOS FLASH MEMORY
FEATURES
• 1,048,576 x 8/524,288 x 16 switchable
• Dual power supply operation
• Erase suspend/Erase Resume
- Suspends an erase operation to read data from, or
- 5.0V only operation for read, 10.0V for erase and
program operations
• Fast access time: 90/120ns
program data to, another sector that is not being
erased, then resumes the erase.
• Status Reply
• Low power consumption
- Data polling & Toggle bit for detection of program
and erase cycle completion.
- 30mA maximum active current
- 1uA typical standby current
• Sector protection
• Command register architecture
- Word Programming (14us typical)
- Sector Erase (Sector structure 16K-Bytex1,
8K-Bytex2, 32K-Bytex1, and 64K-Byte x15)
• Auto Erase (chip & sector) and Auto Program
-Automaticallyeraseanycombinationofsectorswith
Erase Suspend capability.
• 100 minimum erase/program cycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Boot Code Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
• Low VCC write inhibit is equal to or less than 3.2V
• Package type:
- Automatically program and verify data at specified
address
- 42-pin PDIP
GENERAL DESCRIPTION
The MX29F805T/B is a 8-mega bit Flash memory or-
ganized as 1M bytes of 8 bits or 512K words of 16 bits.
MXIC's Flash memories offer the most cost-effective and
reliable read/write non-volatile random access memory.
The MX29F805T/B is packaged in 42-pin PDIP. It is
designed to be reprogrammed and erased in system or
in standard EPROM programmers.
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining maxi-
mum EPROM compatibility.
MXIC Flash technology reliably stores memory contents
even after 100 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cy-
cling. The MX29F805T/B needs 10V power supply to
perform the High Reliability Erase and auto Program/
Erase algorithms.
The standard MX29F805T/B offers access time as fast
as 90ns, allowing operation of high-speed microproces-
sors without wait states. To eliminate bus contention,
the MX29F805T/B has separate chip enable (CE) and
output enable (OE) controls.
MXIC's Flash memories augment EPROM functionality
with electrical erasure and programming. The
MX29F805T/B uses a command register to manage this
functionality. The command register allows for 100%
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
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1
MX29F805T/B
PIN CONFIGURATIONS
42 PDIP(600 mil)
PIN DESCRIPTION
SYMBOL PIN NAME
A0~A18
Q0~Q14
Q15/A-1
Address Input
Data Input/Output
DU
A18
A17
A7
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
1
A8
2
Q15(Word mode)/LSB addr(Byte mode, for
read operation only)
A9
3
A10
A11
A12
A13
A14
A15
A16
BYTE/VPP
GND
Q15/A-1
Q7
A6
4
A5
5
CE
Chip Enable Input
A4
6
A3
7
BYTE/VPP Word/Byte Selction input, for read operation
only.VPP=VHH for Erase/Program operation.
A2
8
A1
9
A0
10
11
12
13
14
15
16
17
18
19
20
21
CE
GND
OE
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
OE
Output Enable Input
Power Supply Pin (+5V)
Ground Pin
VCC
GND
DU
Q14
Q6
Do Not Use
Q13
Q5
Q12
Q4
VCC
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2
MX29F805T/B
BLOCK STRUCTURE
MX29F805T TOP BOOT SECTOR ADDRESS TABLE
Sector Size
(Kbytes/
Address Range (in hexadecimal)
(x16)
(x8)
Sector A18 A17 A16 A15 A14 A13 A12
Kwords)
Address Range
Address Range
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
32/16
8/4
00000h-07FFFh
08000h-0FFFFh
10000h-17FFFh
18000h-1FFFFh
20000h-27FFFh
28000h-2FFFFh
30000h-37FFFh
38000h-3FFFFh
40000h-47FFFh
48000h-4FFFFh
50000h-57FFFh
58000h-5FFFFh
60000h-67FFFh
68000h-6FFFFh
70000h-77FFFh
78000h-7BFFFh
7C000h-7CFFFh
7D000h-7DFFFh
7E000h-7FFFFh
00000h-0FFFFh
10000h-1FFFFh
20000h-2FFFFh
30000h-3FFFFh
40000h-4FFFFh
50000h-5FFFFh
60000h-6FFFFh
70000h-7FFFFh
80000h-8FFFFh
90000h-9FFFFh
A0000h-AFFFFh
B0000h-BFFFFh
C0000h-CFFFFh
D0000h-DFFFFh
E0000h-EFFFFh
F0000h-F7FFFh
F8000h-F9FFFh
FA000h-FBFFFh
FC000h-FFFFFh
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
1
1
0
1
1
X
8/4
16/8
MX29F805B BOTTOM BOOT SECTOR ADDRESS TABLE
Sector Size
(Kbytes/
Address Range (in hexadecimal)
(x16)
(x8)
Sector A18 A17 A16 A15 A14 A13 A12
Kwords)
Address Range
Address Range
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
0
1
1
X
0
1
16/8
8/4
8/4
00000h-01FFFh
02000h-02FFFh
03000h-03FFFh
04000h-07FFFh
08000h-0FFFFh
10000h-17FFFh
18000h-1FFFFh
20000h-27FFFh
28000h-2FFFFh
30000h-37FFFh
38000h-3FFFFh
40000h-47FFFh
48000h-4FFFFh
50000h-57FFFh
58000h-5FFFFh
60000h-67FFFh
68000h-6FFFFh
70000h-77FFFh
78000h-7FFFFh
00000h-03FFFh
04000h-05FFFh
06000h-07FFFh
08000h-0FFFFh
10000h-1FFFFh
20000h-2FFFFh
30000h-3FFFFh
40000h-4FFFFh
50000h-5FFFFh
60000h-6FFFFh
70000h-7FFFFh
80000h-8FFFFh
90000h-9FFFFh
A0000h-AFFFFh
B0000h-BFFFFh
C0000h-CFFFFh
D0000h-DFFFFh
E0000h-EFFFFh
F0000h-FFFFFh
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
32/16
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
Note: Address range is A18:A-1 in byte mode and A18:A0 in word mode.(for read operation only)
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3
MX29F805T/B
BLOCK DIAGRAM
WRITE
CONTROL
INPUT
PROGRAM/ERASE
STATE
MACHINE
(WSM)
CE
OE
BYTE/VPP
HIGH VOLTAGE
LOGIC
STATE
MX29F805T/B
REGISTER
ADDRESS
LATCH
FLASH
ARRAY
ARRAY
A0-A18
SOURCE
HV
AND
COMMAND
DATA
BUFFER
Y-PASS GATE
DECODER
PGM
SENSE
DATA
COMMAND
DATA LATCH
AMPLIFIER
HV
PROGRAM
DATA LATCH
I/O BUFFER
Q0-Q15/A-1
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MX29F805T/B
AUTOMATIC PROGRAMMING
AUTOMATIC ERASE ALGORITHM
The MX29F805T/B is word programmable using the Au-
tomatic Programming algorithm. The Automatic Pro-
gramming algorithm makes the external system do not
need to have time out sequence nor to verify the data
programmed. The typical chip programming time at
room temperature of the MX29F805T/B is less than 4
seconds.
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stan-
dard microprocessor write timings. The device will au-
tomatically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,
provides the erase verification, and counts the number
of sequences. A status bit toggling between consecu-
tive read cycles provides feedback to the user as to the
status of the programming operation.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 10 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at room temperature is accomplished
in less than 4 second. The Automatic Erase algorithm
automatically programs the entire array prior to electri-
cal erase. The timing and verification of electrical erase
are controlled internally within the device.
Register contents serve as inputs to an internal state-
machine which controls the erase and programming cir-
cuitry. During write cycles, the command register inter-
nally latches address and data needed for the program-
ming and erase operations. During a system write cycle,
addresses are latched on the falling edge, and data are
latched on the rising edge of CE .
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, reli-
ability, and cost effectiveness.The MX29F805T/B elec-
trically erases all bits simultaneously using Fowler-
Nordheim tunneling. The bytes are programmed by us-
ing the EPROM programming mechanism of hot elec-
tron injection.
AUTOMATIC SECTOR ERASE
The MX29F805T/B is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. Sector erase modes al-
low sectors of the array to be erased in one erase cycle.
The Automatic Sector Erase algorithm automatically
programs the specified sector(s) prior to electrical erase.
The timing and verification of electrical erase are con-
trolled internally within the device.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command.After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command regis-
ter to respond to its full command set.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm requires the
user to only write program set-up commands (including
2 unlock write cycle and A0H) and a program command
(program data and address). The device automatically
times the programming pulse width, provides the pro-
gram verification, and counts the number of sequences.
A status bit similar to DATA polling and a status bit tog-
gling between consecutive read cycles, provide feed-
back to the user as to the status of the programming
operation.
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MX29F805T/B
TABLE1. SOFTWARE COMMAND DEFINITIONS(BYTE/VPP=VHH)
First Bus
Bus Cycle
Second Bus Third Bus
Cycle Cycle
Fourth Bus
Cycle
Fifth Bus
Cycle
Sixth Bus
Cycle
Command
Cycle Addr Data Addr Data Addr
Data Addr Data Addr
Data Addr Data
Reset
1
1
4
4
XXXH F0H
RA RD
555H AAH 2AAH 55H 555H 90H ADI
Read
Read Silicon ID Word
Sector Protect Word
Verify
DDI
555H AAH 2AAH 55H 555H 90H (SA) XX00H
x02H XX01H
Porgram
Word
Word
Word
4
6
6
1
1
555H AAH 2AAH 55H 555H A0H PA
PD
Chip Erase
Sector Erase
555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H
555H 10H
SA 30H
555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H
Sector Erase Suspend
Sector Erase Resume
XXXH B0H
XXXH 30H
Note:
1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacture code,A1=0, A0 = 1 for device code. A2 to A18=Do not care.
(Refer to table 3)
DDI = Data of Device identifier : C2H for manufacture code, C4H/4AH (x8) and 22C4/224AH (x16) for device code.
X = X can be VIL or VIH
RA=Address of memory location to be read.
RD=Data to be read at location RA.
2.PA = Address of memory location to be programmed.
PD = Data to be programmed at location PA.
SA = Address to the sector to be erased.
3.The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 in word mode.
Address bit A11~A18=X=Don't care for all address commands except for Program Address (PA) and Sector
Address (SA). Write Sequence may be initiated with A11~A18 in either state.
4. For Sector Protect Verify operation:If read out data is 01H, it means the sector has been protected. If read out data is 00H,
it means the sector is still not being protected.
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6
MX29F805T/B
COMMAND DEFINITIONS
sequences. Note that the Erase Suspend (B0H) and
Erase Resume (30H) commands are valid only while
the Sector Erase operation is in progress. Either of the
two reset command sequences will reset the
device(when applicable).
Device operations are selected by writing specific ad-
dress and data sequences into the command register.
Writing incorrect address and data values or writing them
in the improper sequence will reset the device to the
read mode. Table 1 defines the valid register command
TABLE 2. MX29F805T/B BUS OPERATION
Pins
CE OE BYTE/VPP A0
A1
L
A6
X
A9
Q0 ~ Q15
Mode
Read Silicon ID
L
L
L
L
H/L
H/L
L
VID(2)
VID(2)
C2H (Byte mode)
Manfacturer Code(1)
Read Silicon ID
Device Code(1)
Read
00C2H (Word mode)
H
L
X
C4H/4AH (Byte mode)
22C4H/224AH (Word mode)
L
H
L
L
L
L
L
X
L
H/L
X
A0
X
A1
X
A6
X
A9
DOUT
Standby
X
H
H
X
HIGH Z
HIGH Z
DIN(3)
X
Output Disable
Write(6)
H/L
VHH
X
X
X
X
A0
X
A1
X
A6
L
A9
Sector Protect
Chip Unprotect
Verify Sector Protect
Reset
VID(2) VHH
VID(2) VHH
VID(2)
VID(2)
VID(2)
X
X
X
H
X
L
H/L
X
X
H
X
Code(5)
HIGH Z
X
X
X
X
NOTES:
1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1.
2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.
3. Refer to Table 1 for valid Data-In during a write operation.
4. X can be VIL or VIH.
5. Code=00H/0000H means unprotected.
Code=01H/0001H means protected.
A18~A12=Sector address for sector protect.
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MX29F805T/B
SET-UP AUTOMATIC CHIP/SECTOR ERASE
COMMANDS
READ/RESET COMMAND
The read or reset operation is initiated by writing the
read/reset command sequence into the command reg-
ister. Microprocessor read cycles retrieve array data.
The device remains enabled for reads until the com-
mand register contents are altered.
Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command 80H. Two more "unlock" write cy-
cles are then followed by the chip erase command 10H.
If program-fail or erase-fail happen, the write of F0H will
reset the device to abort the operation. A valid com-
mand must then be written to place the device in the
desired state.
The Automatic Chip Erase does not require the device
to be entirely pre-programmed prior to executing the
Automatic Chip Erase. Upon executing the Automatic
Chip Erase, the device will automatically program and
verify the entire memory for an all-zero data pattern.
When the device is automatically verified to contain an
all-zero pattern, a self-timed chip erase and verify be-
gin. The erase and verify operations are completed when
the data on Q7 is "1" at which time the device returns to
the Read mode. The system is not required to provide
any control or timing during these operations.
SILICON-ID-READ COMMAND
Flash memories are intended for use in applications
where the local CPU alters memory contents. As such,
manufacturer and device codes must be accessible while
the device resides in the target system. PROM pro-
grammers typically access signature codes by raising
A9 to a high voltage(VID). However, multiplexing high
voltage onto address lines is not generally desired sys-
tem design practice.
When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory
array(no erase verification command is required).
The MX29F805T/B contains a Silicon-ID-Read opera-
tion to supplement traditional PROM programming meth-
odology. The operation is initiated by writing the read
silicon ID command sequence into the command reg-
ister. Following the command write, a read cycle with
A1=VIL, A0=VIL retrieves the manufacturer code of C2H/
00C2H. A read cycle with A1=VIL, A0=VIH returns the
device code of C4H/22C4H for MX29F805T, 4AH/224AH
for MX29F805B.
If the Erase operation was unsuccessful, the data on
Q5 is "1"(see Table 4), indicating the erase operation
exceed internal timing limit.
The automatic erase begins on the rising edge of the
last CE pulse in the command sequence and terminates
when the data on Q7 is "1" and the data on Q6 stops
toggling for two consecutive read cycles, at which time
the device returns to the Read mode.
TABLE 3. EXPANDED SILICON ID CODE
Pins
A0
A1
Q15~Q8 Q7 Q6 Q5
Q4 Q3 Q2 Q1 Q0 Code(Hex)
Manufacture code Word VIL
Byte VIL
VIL 00H
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
00C2H
VIL
X
C2H
Device code
Word VIH VIL 22H
Byte VIH VIL
Word VIH VIL 22H
22C4H
for MX29F805T
Device code
X
C4H
224AH
for MX29F805B
Sector Protection
Verification
Byte VIH VIL
X
X
X
4AH
X
X
VIH
VIH
01H (Protected)
00H (Unprotected)
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MX29F805T/B
SECTOR ERASE COMMANDS
The Automatic Sector Erase does not require the de-
vice to be entirely pre-programmed prior to executing
the Automatic Set-up Sector Erase command and Au-
tomatic Sector Erase command. Upon executing the
Automatic Sector Erase command, the device will auto-
matically program and verify the sector(s) memory for
an all-zero data pattern. The system is not required to
provide any control or timing during these operations.
When using the Automatic sector Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array
(no erase verification command is required). Sector
erase is a six-bus cycle operation. There are two "un-
lock" write cycles. These are followed by writing the
set-up command 80H. Two more "unlock" write cycles
are then followed by the sector erase command 30H.
The sector address is latched on the falling edge of CE,
while the command(data) is latched on the rising edge
of CE. Sector addresses selected are loaded into in-
ternal register on the sixth falling edge of CE. Each
successive sector load cycle started by the falling edge
of CE must begin within 80us from the rising edge of
the preceding CE. Otherwise, the loading period ends
and internal auto sector erase cycle starts. (Monitor Q3
to determine if the sector erase timer window is still open,
see section Q3, Sector Erase Timer.) Any command
other than Sector Erase(30H) or Erase Suspend(B0H)
during the time-out period resets the device to read
mode.
When the sector(s) is automatically verified to contain
an all-zero pattern, a self-timed sector erase and verify
begin. The erase and verify operations are complete
when the data on Q7 is "1" and the data on Q6 stops
toggling for two consecutive read cycles, at which time
the device returns to the Read mode. The system is not
required to provide any control or timing during these
operations.
Table 4.Write Operation Status
Status
Q7
Q7
0
Q6
Toggle
Toggle
1
Q5
0
Q3
0
Q2
1
Byte Program in Auto Program Algorithm
Auto Erase Algorithm
0
1
Toggle
Toggle
(Note1)
Erase Suspend Read
1
0
0
In Progress
(Erase Suspended Sector)
Erase Suspend Read
Erase Suspended Mode
Data
Q7
Data
Data Data Data
(Non-Erase Suspended Sector)
Erase Suspend Program
Toggle
(Note2)
Toggle
Toggle
Toggle
0
0
1
(Note3)
1
(Non-Erase Suspended Sector)
Byte Program in Auto Program Algorithm
Program/Erase in Auto Erase Algorithm
Q7
0
1
1
1
0
1
0
Exceeded
N/A
N/A
Time Limits Erase Suspended Mode
Erase Suspend Program
Q7
(Non-Erase Suspended Sector)
Notes:
1.Performing successive read operations from the erase-suspended sector will cause Q2 to toggle.
2.Performing successive read operations from any address will cause Q6 to toggle.
3.Reading the byte address being programmed while in the erase-suspend program mode will indicate logic "1" at the Q2 bit.
However, successive reads from the erase-suspended sector will cause Q2 to toggle.
P/N:PM0614
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9
MX29F805T/B
operation is completed when the data read on Q6 stops
toggling for two consecutive read cycles and the data
on Q7 and Q6 are equivalent to data written to these
two bits, at which time the device returns to the Read
mode(no program verify command is required).
ERASE SUSPEND
This command only has meaning while the state ma-
chine is executing Automatic Block Erase operation, and
therefore will only be responded during Automatic Block
Erase operation. However, When the Erase Suspend
command is written during the sector erase time-out,
the device immediately terminates the time-out period
and suspends the erase operation. After this command
has been executed, the command register will initiate
erase suspend mode. The state machine will return to
read mode automatically after suspend is ready. At this
time, state machine only allows the command register
to respond to the Read Memory Array, Erase Resume
and program commands.
DATA POLLING-Q7
The MX29F805T/B also features Data Polling as a
method to indicate to the host system that the Auto-
matic Program or Erase algorithms are either in progress
or completed.
While the Automatic Programming algorithm is in op-
eration, an attempt to read the device will produce the
complement data of the data last written to Q7. Upon
completion of the Automatic Program Algorithm an at-
tempt to read the device will produce the true data last
written to Q7. The Data Polling feature is valid after the
rising edge of the fourth CE pulse of the four write pulse
sequences for automatic program.
The system can determine the status of the program
operation using the Q7 or Q6 status bits, just as in the
standard program operation. After an erase-suspend
program operation is complete, the system can once
again read array data within non-suspended blocks.
While the Automatic Erase algorithm is in operation, Q7
will read "0" until the erase operation is competed. Upon
completion of the erase operation, the data on Q7 will
read "1". The Data Polling feature is valid after the ris-
ing edge of the sixth CE pulse of six write pulse se-
quences for automatic chip/sector erase.
ERASE RESUME
This command will cause the command register to clear
the suspend state and return back to Sector Erase mode
but only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all
other conditions.Another Erase Suspend command can
be written after the chip has resumed erasing.
The Data Polling feature is active during Automatic Pro-
gram/Erase algorithm or sector erase time-out.(see sec-
tion Q3 Sector Erase Timer)
SET-UP AUTOMATIC PROGRAM COMMANDS
To initiate Automatic Program mode, A three-cycle com-
mand sequence is required. There are two "unlock" write
cycles. These are followed by writing the Automatic Pro-
gram command A0H.
Once the Automatic Program command is initiated, the
next CE pulse causes a transition to an active program-
ming operation. Addresses are latched on the falling
edge, and data are internally latched on the rising
edge of the CE pulse. The rising edge of CE also be-
gins the programming operation. The system is not re-
quired to provide further controls or timings. The device
will automatically provide an adequate internally gener-
ated program pulse and verify margin.
If the program opetation was unsuccessful, the data on
Q5 is "1"(seeTable 4), indicating the program operation
exceed internal timing limit.The automatic programming
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MX29F805T/B
Q2:Toggle Bit II
Q6:Toggle BIT I
The "Toggle Bit II" on Q2, when used with Q6, indicates
whether a particular sector is actively eraseing (that is,
the Automatic Erase alorithm is in process), or whether
that sector is erase-suspended. Toggle Bit I is valid af-
ter the rising edge of the final CE pulse in the command
sequence.
Toggle Bit I on Q6 indicates whether an Automatic Pro-
gram or Erase algorithm is in progress or complete, or
whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final CE pulse in the
command sequence(prior to the program or erase op-
eration), and during the sector time-out.
Q2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The
system may use either OE or CE to control the read
cycles.) But Q2 cannot distinguish whether the sector
is actively erasing or is erase-suspended. Q6, by com-
parison, indicates whether the device is actively eras-
ing, or is in Erase Suspend, but cannot distinguish which
sectors are selected for erasure. Thus, both status bits
are required for sectors and mode information. Refer to
Table 4 to compare outputs for Q2 and Q6.
During an Automatic Program or Erase algorithm op-
eration, successive read cycles to any address cause
Q6 to toggle. The system may use either OE or CE to
control the read cycles.When the operation is complete,
Q6 stops toggling.
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Q6 toggles and
returns to reading array data. If not all selected sectors
are protected, the Automatic Erase algorithm erases the
unprotected sectors, and ignores the selected sectors
that are protected.
Reading Toggle Bits Q6/ Q2
Whenever the system initially begins reading toggle bit
status, it must read Q7-Q0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has com-
pleted the program or erase operation. The system can
read array data on Q7-Q0 on the following read cycle.
The system can use Q6 and Q2 together to determine
whether a sector is actively erasing or is erase sus-
pended.When the device is actively erasing (that is, the
Automatic Erase algorithm is in progress), Q6 toggling.
When the device enters the Erase Suspend mode, Q6
stops toggling. However, the system must also use Q2
to determine which sectors are erasing or erase-sus-
pended. Alternatively, the system can use Q7.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of Q5 is high
(see the section on Q5). If it is, the system should then
determine again whether the toggle bit is toggling, since
the toggle bit may have stopped toggling just as Q5 went
high. If the toggle bit is no longer toggling, the device
has successfuly completed the program or erase op-
eration. If it is still toggling, the device did not complete
the operation successfully, and the system must write
the reset command to return to reading array data.
If a program address falls within a protected sector, Q6
toggles for approximately 2 us after the program com-
mand sequence is written, then returns to reading array
data.
Q6 also toggles during the erase-suspend-program
mode, and stops toggling once the Automatic Program
algorithm is complete.
The remaining scenario is that system initially deter-
mines that the toggle bit is toggling and Q5 has not gone
high. The system may continue to monitor the toggle bit
and Q5 through successive read cycles, determining
the status as described in the previous paragraph. Al-
ternatively, it may choose to perform other system tasks.
In this case, the system must start at the beginning of
the algorithm when it returns to determine the status of
the operation.
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11
MX29F805T/B
Q3
Q5
Sector Erase Timer
Exceeded Timing Limits
After the completion of the initial sector erase command
sequence, the sector erase time-out will begin. Q3 will
remain low until the time-out is complete. Data Polling
andToggle Bit are valid after the initial sector erase com-
mand sequence.
Q5 will indicate if the program or erase time has ex-
ceeded the specified limits(internal pulse count). Un-
der these conditions Q5 will produce a "1". This time-
out condition indicates that the program or erase cycle
was not successfully completed. Data Polling andToggle
Bit are the only operating functions of the device under
this condition.
If Data Polling or theToggle Bit indicates the device has
been written with a valid erase command, Q3 may be
used to determine if the sector erase timer window is
still open. If Q3 is high ("1") the internally controlled
erase cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or
Toggle Bit. If Q3 is low ("0"), the device will accept addi-
tional sector erase commands. To insure the command
has been accepted, the system software should check
the status of Q3 prior to and following each subsequent
sector erase command. If Q3 were high on the second
status check, the command may not have been ac-
cepted.
If this time-out condition occurs during sector erase op-
eration, it specifies that a particular sector is bad and it
may not be reused. However, other sectors are still func-
tional and may be used for the program or erase opera-
tion. The device must be reset to use other sectors.
Write the Reset command sequence to the device, and
then execute program or erase command sequence.
This allows the system to continue to use the other ac-
tive sectors in the device.
If this time-out condition occurs during the chip erase
operation, it specifies that the entire chip is bad or com-
bination of sectors are bad.
WRITE PULSE "GLITCH" PROTECTION
If this time-out condition occurs during the byte program-
ming operation, it specifies that the entire sector con-
taining that byte is bad and this sector maynot be re-
used, (other sectors are still functional and can be re-
used).
Noise pulses of less than 5ns(typical) on CE will not
initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE = VIL, CE
= VIH or BYTE/VPP=VIH/VIL To initiate a write cycle
CE and WE must be a logical zero while OE is a logical
one.
The time-out condition may also appear if a user tries to
program a non blank location without erasing. In this
case the device locks out and never completes the Au-
tomatic Algorithm operation. Hence, the system never
reads a valid data on Q7 bit and Q6 never stops tog-
gling. Once the Device has exceeded timing limits, the
Q5 bit will indicate a "1". Please note that this is not a
device failure condition since the device was incorrectly
used.
POWER SUPPLY DECOUPLING
In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected be-
tween its VCC and GND.
DATA PROTECTION
The MX29F805T/B is designed to offer protection
against accidental erasure or programming caused by
spurious system level signals that may exist during
power transition. During power up the device automati-
cally resets the state machine in the Read mode. In
addition, with its control register architecture, alteration
of the memory contents only occurs after successful
completion of specific command sequences. The de-
vice also incorporates several features to prevent inad-
vertent write cycles resulting from VCC power-up and
power-down transition or system noise.
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12
MX29F805T/B
SECTOR PROTECTION
POWER-UP SEQUENCE
The MX29F805T/B features hardware sector protection.
This feature will disable both program and erase opera-
tions for these sectors protected. To activate this mode,
the programming equipment must forceVID on address
pin A9 and control pin OE, (suggest VID = 12V) A6 =
VIL and CE = VIL.(see Table 2) Programming of the
protection circuitry begins on the falling edge of the CE
pulse and is terminated on the rising edge. Please refer
to sector protect algorithm and waveform.
The MX29F805T/B powers up in the Read only mode.
In addition, the memory contents may only be altered
after successful completion of the predefined command
sequences.
ABSOLUTE MAXIMUM RATINGS
RATING
VALUE
Ambient OperatingTemperature
StorageTemperature
Applied Input Voltage
Applied Output Voltage
VCC to Ground Potential
A9,OE
0oC to 70oC
-65oC to 125oC
-0.5V to 7.0V
-0.5V to 7.0V
-0.5V to 7.0V
-0.5V to 13.5V
-0.5V to 10.5V
To verify programming of the protection circuitry, the pro-
gramming equipment must forceVID on address pin A9
( with CE and OE at VIL and BYTE/VPP at VIH/VIL).
When A1=1, it will produce a logical "1" code at device
output Q0 for a protected sector. Otherwise the device
will produce 00H for the unprotected sector. In this mode,
the addresses,except for A1, are don't care. Address
locations with A1 = VIL are reserved to read manufac-
turer and device codes.(Read Silicon ID)
BYTE/VPP
NOTICE:
It is also possible to determine if the sector is protected
in the system by writing a Read Silicon ID command.
Performing a read operation with A1=VIH, it will pro-
duce a logical "1" at Q0 for the protected sector.
Stresses greater than those listed under ABSOLUTE MAXI-
MUM RATINGS may cause permanent damage to the de-
vice. This is a stress rating only and functional operational
sections of this specification is not implied. Exposure to ab-
solute maximum rating conditions for extended period may
affect reliability.
CHIP UNPROTECT
NOTICE:
The MX29F805T/B also features the chip unprotect
mode, so that all sectors are unprotected after chip
unprotect is completed to incorporate any changes in
thecode.Itisrecommendedtoprotectallsectorsbefore
activating chip unprotect mode.
Specifications contained within the following tables are sub-
ject to change.
To activate this mode, the programming equipment
must force VID on control pin OE and address pin A9.
The CE pins must be set at VIL. Pins A6 must be set to
VIH.(seeTable2) Refertochipunprotect algorithmand
waveform for the chip unprotect algorithm. The
unprotection mechanism begins on the falling edge of
the CE pulse and is terminated on the rising edge.
It is also possible to determine if the chip is unprotected
in the system by writing the Read Silicon ID command.
PerformingareadoperationwithA1=VIH,itwillproduce
00H at data outputs(Q0-Q7) for an unprotected sector.
It is noted that all sectors are unprotected after the chip
unprotect algorithm is completed.
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13
MX29F805T/B
CAPACITANCE TA = 25oC, f = 1.0 MHz
SYMBOL
CIN
PARAMETER
MIN.
TYP
MAX.
8
UNIT
pF
CONDITIONS
VIN = 0V
Input Capacitance
Output Capacitance
COUT
12
pF
VOUT = 0V
READ OPERATION
DC CHARACTERISTICS TA = 0oCTO 70oC, VCC = 5V±10%
SYMBOL
ILI
PARAMETER
MIN.
TYP
MAX.
UNIT
uA
uA
mA
uA
mA
mA
V
CONDITIONS
Input Leakage Current
Output Leakage Current
Standby VCC current
1
VIN = GND to VCC
VOUT = GND to VCC
CE = VIH
ILO
±1
ISB1
ISB2
ICC1
ICC2
VIL
1
0.2
5
CE = VCC + 0.3V
IOUT = 0mA, f=1MHz
IOUT= 0mA, f=10MHz
Operating VCC current
30
50
Input Low Voltage
-0.3(NOTE 1)
2.0
0.8
VIH
Input High Voltage
VCC + 0.3
0.45
V
VOL
Output Low Voltage
Output High Voltage(TTL)
V
IOL = 2.1mA
IOH = -2mA
VOH1
VOH2
2.4
V
Output High Voltage(CMOS) VCC-0.4
V
IOH = -100uA,
VCC=VCC MIN.
NOTES:
1.VIL min. = -1.0V for pulse width is equal to or less than 50 ns.
VIL min. = -2.0V for pulse width is equal to or less than 20 ns.
2.VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns
If VIH is over the specified maximum value, read operation cannot be guaranteed.
AC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V ±10%
29F805T/B-90
29F805T/B-12
SYMBOL PARAMETER
MIN. MAX.
MIN. MAX. UNIT CONDITIONS
tACC
tCE
tOE
tDF
Address to Output Delay
90
90
40
120
120
50
ns
ns
ns
ns
ns
CE=OE=VIL
OE=VIL
CE to Output Delay
OE to Output Delay
CE=VIL
OE High to Output Float (Note1)
Address to Output hold
0
0
20
0
0
30
CE=VIL
tOH
CE=OE=VIL
NOTE:
TEST CONDITIONS:
1. tDF is defined as the time at which the output achieves the
open circuit condition and data is no longer driven.
• Input pulse levels: 0.45V/2.4V
• Input rise and fall times is equal to or less than 10ns
• Outputload:1TTLgate+100pF(Includingscopeand
jig)
• Reference levels for measuring timing: 0.8V, 2.0V
P/N:PM0614
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14
MX29F805T/B
READ TIMING WAVEFORMS
VIH
ADD Valid
Addresses
VIL
tCE
VIH
CE
VIL
VIH/VIL
BYTE/VPP
tDF
tOE
VIH
OE
tACC
VIL
tOH
HIGH Z
HIGH Z
VOH
VOL
Outputs
DATA Valid
COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION
DC CHARACTERISTICSTA = 0oC to 70oC, VCC = 5V ±10%
SYMBOL
ICC1 (Read)
ICC2
PARAMETER
MIN.
TYP
MAX. UNIT CONDITIONS
Operating VCC Current
30
50
50
50
mA
mA
mA
mA
mA
IOUT=0mA, f=1MHz
IOUT=0mA, F=10MHz
In Programming
ICC3 (Program)
ICC4 (Erase)
ICCES
In Erase
VCC Erase Suspend Current
2
CE=VIH, Erase Suspended
NOTES:
1. VIL min. = -0.6V for pulse width is equal to or less than 20ns.
2. If VIH is over the specified maximum value, programming operation cannot be guranteed.
3. ICCES is specified with the device de-selected. If the device is read during erase suspend mode, current draw is the sum of
ICCES and ICC1 or ICC2.
4. All current are in RMS unless otherwise noted.
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MX29F805T/B
AC CHARACTERISTICS WORD/BYTE CONFIGURATION (BYTE/VPP)
Speed Options
SYMBOL
tELFL/tELFH
tFLQZ
Description
90
5
120
5
unit
ns
CE to BYTE/VPP Switching Low or High
MAX
BYTE/VPP Switching Low to Output HIHG Z Max
BYTE/VPP Switching High to Output Active Min
30
90
30
ns
tFHQV
120
ns
Figure 6. BYTE/VPP TIMING WAVEFORMS
CE
OE
VIH
BYTE/VPP
VIL
tELFL
BYTE/VPP
Q0~Q14
Data Output
(Q0~Q14)
Data Output
(Q0~Q7)
Switching
from word
to byte
mode read
Q15/A-1
Q15
Output
Address Input
tFLQZ
tELFL
VIH
BYTE/VPP VIL
Data Output
(Q0~Q7)
Data Output
(Q0~Q14)
BYTE/VPP
Switching
Q0~Q14
from byte
to word
Q15
Output
mode read
Address Input
tFHQV
Q15/A-1
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MX29F805T/B
AC CHARACTERISTICS TA = 0oC to 70oC,VCC = 5V ±10%
29F805T/B-90 29F805T/B-12
SYMBOL PARAMETER
MIN. MAX.
MIN. MAX. UNIT CONDITIONS
tOES
tCWC
tAS
OE setup time
50
50
120
0
ns
ns
ns
ns
us
us
ns
ns
s
Command programming cycle
Address setup time
90
0
tAH
Address hold time
45
50
2
tVPS
tVPH
tCESC
tDF
BYTE/Vpp Setup Time
2
BYTE/Vpp Hold Time
2
2
CE setup time before command write
Output disable time (Note 1)
Total erase time in auto chip erase
Total erase time in auto block erase
Total programming time in auto verify
( word program time)
0
0
20
30
tAETC
tAETB
tAVT
8(TYP.)
1(TYP.)
14(TYP.)
8(TYP.)
1(TYP.)
s
14(TYP.)
us
tBAL
tCH
Block address load time
CE Hold Time
80
0
80
0
us
ns
ns
us
us
tCS
CE setup to WE going low
Voltge Transition Time
0
0
tVLHT
tWPP1
4
4
Write pulse width for sector protect
10
10
tWPP2
tOESP
Write pulse width for sector unprotect
OE Setup Time to BYTE/VPP Active
12
4
12
4
ms
us
NOTES:
1. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.
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MX29F805T/B
SWITCHINGTEST CIRCUITS
DEVICE UNDER
TEST
1.6K ohm
+5V
CL
1.2K ohm
DIODES=IN3064
OR EQUIVALENT
CL=100pF Including jig capacitance
SWITCHING TEST WAVEFORMS
2.4V
2.0V
0.8V
2.0V
TEST POINTS
0.8V
0.45V
INPUT
OUTPUT
AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0".
Input pulse rise and fall times are <20ns.
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18
MX29F805T/B
COMMAND WRITE TIMING WAVEFORM
CE
tOES
OE
tVPH
tVPS
10V
BYTE/VPP
tAS
tAH
ADDRESSES
VALID
tDH
HIGH Z
DIN
DATA
VCC
tDS
tVCS
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MX29F805T/B
AUTOMATIC PROGRAMMING TIMING
WAVEFORM
One byte data is programmed. Verify in fast algorithm
and additional programming by external control are not
required because these operations are executed auto-
matically by internal control circuit. Programming
completion can be verified by DATA polling and toggle
bit checking after automatic verification starts. Device
outputs DATA during programming and DATA after pro-
gramming on Q7.(Q6 is for toggle bit; see toggle bit,
DATA polling, timing waveform)
AUTOMATIC PROGRAMMING TIMING WAVEFORM (WORD MODE)
Vcc 5V
A11~A18
ADD Valid
ADD Valid
2AAH
555H
A0~A10
BYTE/VPP
CE
555H
tAS
10V
tVPH
tVPS
tCESC
tAVT
tCEP
OE
tDS tDH
tDF
Q0,Q1,
DATA
DATA
Command In
Command In
Command In
Data In
DATA polling
Q4(Note 1)
DATA
Command In
Command In
Command In
Data In
Q7
Command #A0H
Command #55H
Command #AAH
(Q0~Q7)
tOE
Notes:
(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit
(2). BYTE/VPP must not be VHH while reading status.
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MX29F805T/B
AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART (WORD MODE)
START
BYTE/VPP=VHH
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data A0H Address 555H
Write Program Data/Address
BYTE/VPP=VIH/VIL
NO
Toggle Bit Checking
Q6 not Toggled
YES
NO
Invalid
Verify Word Ok
Command
YES
NO
Q5 = 1
Reset
Auto Program Completed
YES
Auto Program Exceed
Timing Limit
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MX29F805T/B
AUTOMATIC CHIP ERASE TIMING WAVEFORM
All data in chip are erased. External erase verification
is not required because data is erased automatically
by internal control circuit. Erasure completion can be
verified by DATA polling and toggle bit checking after
automatic erase starts. Device outputs 0 during era-
sure and 1 after erasure on Q7.(Q6 is for toggle bit; see
toggle bit, DATA polling, timing waveform)
AUTOMATIC CHIP ERASE TIMING WAVEFORM (WORD MODE)
Vcc 5V
A11~A18
2AAH
555H
555H
2AAH
A0~A10
BYTE/VPP
CE
555H
555H
tAS
10V
tVPS
tVPH
tCESC
tCEP
OE
tDS tDH
Q0,Q1,
Command In
Command In
Command In
Command In
Command In
Command In
Q4(Note 1)
DATA polling
Command In
Command In
Command In
Command In
Command In
Command In
Q7
Command #80H
Command #AAH
Command #55H
Command #10H
Command #AAH
Command #55H
(Q0~Q7)
Notes:
(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit
(2). BYTE/VPP must not be VHH while reading status.
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MX29F805T/B
AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART (WORD MODE)
START
Byte/VPP=VHH
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 10H Address 555H
BYTE/VPP=VIH/VIL
NO
Toggle Bit Checking
Q6 not Toggled
YES
NO
Invalid
DATA Polling
Command
Q7 = 1
YES
NO
Q5 = 1
Reset
Auto Chip Erase Completed
YES
Auto Chip Erase Exceed
Timing Limit
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23
MX29F805T/B
AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Sector data indicated by A12 to A18 are erased. Exter-
nal erase verify is not required because data are erased
automatically by internal control circuit. Erasure comple-
tion can be verified by DATA polling and toggle bit check-
ing after automatic erase starts. Device outputs 0 dur-
ing erasure and 1 after erasure on Q7.(Q6 is for toggle
bit; see toggle bit, DATA polling, timing waveform)
AUTOMATIC SECTOR ERASE TIMING WAVEFORM (WORD MODE)
Vcc 5V
Sector
Address 1
Sector
Address 0
Sector
Address N
A12~A18
555H
2AAH
555H
A0~A10
555H
tAS
2AAH
BYTE/VPP
tVPS
tVPH
tBAL
tAETB
CE
OE
tCEP
tDS tDH
Command In
Q0,Q1,
Command In
Command In
Command In
Command In
Command In
Command In
Command In
Command In
Command In
Command In
Q4(Note 1)
DATA polling
Command In
Command In
Command In
Command In
Command In
Q7
Command #30H
Command #80H
Command #AAH
Command #55H
Command #30H
Command #30H
Command #AAH
(Q0~Q7)
Command #55H
Notes:
(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit
(2).BYTE/VPP must not be VHH while reading ststus
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MX29F805T/B
AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART (WORD MODE)
START
BYTE/VPP=VHH
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 30H Sector Address
Write Data 30H Sector Address
NO
Toggle Bit Checking
Q6 Toggled ?
Invalid Command
YES
Load Other Sector Addrss If Necessary
(Load Other Sector Address), BYTE/VPP=VHH
NO
Last Sector
to Erase
YES
BYTE/VPP=VIH/VIL
NO
NO
Time-out Bit
Checking Q3=1 ?
YES
Toggle Bit Checking
Q6 not Toggled
YES
NO
Q5 = 1
Reset
DATA Polling
Q7 = 1
YES
Auto Sector Erase Completed
Auto Sector Erase Exceed
Timing Limit
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MX29F805T/B
ERASE SUSPEND/ERASE RESUME FLOWCHART
START
BYTE/VPP=VHH
Write Data B0H
BYTE/VPP=VIH/VIL
NO
Toggle Bit checking Q6
not toggled
YES
Read Array or
Program
Reading or
NO
Programming End
YES
BYTE/VPP=VHH
Write Data 30H
Continue Erase
Another
NO
Erase Suspend ?
YES
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MX29F805T/B
TIMING WAVEFORM FOR SECTOR PROTECTION
A1
A6
12V
5V
A9
tVLHT
Verify
12V
5V
OE
tVLHT
tVLHT
tWPP 1
10V
BYTE/VPP
tOESP
CE
Data
01H
tOE
A18-A12
Sector Address
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MX29F805T/B
TIMING WAVEFORM FOR CHIP UNPROTECTION
A1
12V
5V
A9
tVLHT
A6
Verify
12V
5V
OE
tVLHT
tVLHT
tWPP 2
10V
BYTE/VPP
tOESP
CE
Data
00H
tOE
A18-A12
Sector Address
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MX29F805T/B
SECTOR PROTECTION ALGORITHM
START
Set Up Sector Addr
(A18,A16,A15,A14,A13,A12)
PLSCNT=1
OE=VID,A9=VID,CE=VIL
A6=VIL
BYTE/VPP=VHH
Time Out 10us
BYTE/VPP=VIH/VIL
Set CE=OE=VIL
A9 should remain VID
Read from Sector
Addr=SA, A1=1
No
No
Data=01H?
Yes
PLSCNT=32?
Yes
Device Failed
Yes
Protect Another
Sector?
No
Remove VID from A9
Write Reset Command
Sector Protection
Complete
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MX29F805T/B
CHIP UNPROTECTION ALGORITHM FOR SYSTEM
START
Protect All Sectors
PLSCNT=1
Set OE=A9=VID
CE=VIL,A6=1
BYTE/VPP=VHH
Time Out 12ms
Increment
PLSCNT
BYTE/VPP=VIH/VIL
Set OE=CE=VIL
A9=VID,A1=1
Set Up First Sector Addr
Read Data from Device
No
No
Data=00H?
Yes
PLSCNT=1000?
Increment
Sector Addr
Yes
Device Failed
No
All sectors have
been verified?
Yes
Remove VID from A9
Write Reset Command
Chip Unprotect
Complete
* It is recommended before unprotect whole chip, all sectors should be protected in advance.
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MX29F805T/B
ID CODE READ TIMING WAVEFORM
VCC
5V
VID
ADD
A9
VIH
VIL
VIH
VIL
ADD
A0
tACC
tACC
ADD
A1-A8
VIH
A10-A18 VIL
CE
VIH
VIL
VIH
VIL
tCE
BYTE/VPP
OE
tOE
VIH
VIL
tDF
tOH
tOH
VIH
VIL
DATA
Q0-Q15
DATA OUT
DATA OUT
C4/4A (Byte)
C2H/00C2H
22C4/224A (Word)
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MX29F805T/B
ORDERING INFORMATION
PLASTIC PACKAGE (Top Boot Sector as an sample. For Bottom Boot Sector ones,MX29F805Txx will
change to MX29F805Bxx)
PART NO.
ACCESSTIME OPERATING CURRENT STANDBY CURRENT PACKAGE
(ns)
90
MAX.(mA, at10MHz)
MAX.(uA)
MX29F805TPC-90
MX29F805TPC-12
50
50
5
5
42 Pin PDIP
42 Pin PDIP
120
ERASE AND PROGRAMMING PERFORMANCE
LIMITS
TYP.
PARAMETER
MIN.
MAX.
UNITS
Sector Erase Time
1.3
16
14
7
10.4
128
21
sec
sec
Chip Erase Time
Word Programming Time
Chip Programming Time
Erase/Program Cycles
us
21
sec
100
Cycles
LATCHUP CHARACTERISTICS
MIN.
-1.0V
MAX.
13.5V
Input Voltage with respect to GND on all pins except I/O pins
Input Voltage with respect to GND on all I/O pins
Current
-1.0V
Vcc + 1.0V
+100mA
-100mA
Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time.
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MX29F805T/B
PACKAGE INFORMATION
42-PIN PLASTIC DIP(600 mil)
ITEM
A
MILLIMETERS INCHES
42
22
52.54 max.
0.76 [REF]
2.54 [TP]
.46 [Typ.]
50.76
2.070 max.
.030 [REF]
.100 [TP]
B
C
D
E
.018 [Typ.]
2.000
1
21
F
1.27 [Typ.]
3.30 ±. 25
.51 [REF]
3.94 ±. 25
5.33 max.
15.22 ±.25
13.97± .25
.25 [Typ.]
.050 [Typ.]
.130 ±.010
.020 [REF]
.155 ±.010
.210 max.
.600 ±.010
.550 ±.010
.010 [Typ.]
A
G
H
I
K
L
I
J
J
K
H
G
L
F
B
M
0~15¡
C
M
D
NOTE: Each lead centerline is located within .25
mm[.01 inch] of its true position [TP] at
maximum material condition.
E
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MX29F805T/B
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-8888
FAX:+886-3-578-8887
EUROPE OFFICE:
TEL:+32-2-456-8020
FAX:+32-2-456-8021
JAPAN OFFICE:
TEL:+81-44-246-9100
FAX:+81-44-246-9105
SINGAPORE OFFICE:
TEL:+65-747-2309
FAX:+65-748-4090
TAIPEI OFFICE:
TEL:+886-3-509-3300
FAX:+886-3-509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-453-8088
FAX:+1-408-453-8488
CHICAGO OFFICE:
TEL:+1-847-963-1900
FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice.
34
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