MX29LV002CBQI-55Q [Macronix]
Flash, 256KX8, 55ns, PQCC32;
| 型号： | MX29LV002CBQI-55Q |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | Flash, 256KX8, 55ns, PQCC32 |
| 文件： | 总67页 (文件大小：660K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
CMOS SINGLE VOLTAGE 3V ONLY FLASH MEMORY
FEATURES
GENERAL FEATURES
• Byte mode only:
- 262,411 x8 (MX29LV002C/002NC)
- 524,288 x8 (MX29LV004C)
- 1,048,576 x8 (MX29LV008C)
• Sector Structure
- 16K-Byte x 1, 8K-Byte x 2, 32K-Byte x 1
64K-Byte x 3 (MX29LV002C), 64K-Byte x 7 (MX29LV004C), 64K-Byte x 15 (MX29LV008C)
• Sector Protect
- Provides sector protect function to prevent program or erase operation in the protected sector
- Provides chip unprotect function to allow code changing
- Provides temporary sector unprotect function for code changing in previously protected sector
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 250mA from -1V to Vcc + 1V
• Low Vcc write inhibit : Vcc <= 1.4V
• Compatible with JEDEC standard
- Pinout and software compatible to single power supply Flash
PERFORMANCE
• High Performance
- Fast access time: 45R (MX29LV004C only), 55R(for MX29LV004C and MX29LV008C), 70/90nS
- Fast program time: 9uS/Byte typical utilizing accelerate function
- Fast erase time: 0.7s/sector
• Low Power Consumption
- Low active read current:7mA (typical) at 5MHz
- Low standby current: 200nA (typical)
• Minimum 100,000 erase/program cycle
• 10 years data retention
SOFTWARE FEATURES
• Erase Suspend/ Erase Resume
- Suspends sector erase operation to read data from or program data to another sector which is not being erased
• Status Reply
- Data# Polling &Toggle bits provide detection of program and erase operation completion
• Support Common Flash Interface (CFI) only for 29LV002C/002NC, 29LV004C.
HARDWARE FEATURES
• Ready/Busy# (RY/BY#) Output only for 29LV004C, 29LV008C.
- Provides a hardware method of detecting program and erase operation completion
• Hardware Reset (RESET#) Input
- Provides a hardware method to reset the internal state machine to read mode
PACKAGE
• 32-PinTSOP (for MX29LV002C/002NC)
• 32-Pin PLCC (for MX29LV002C/002NC and MX29LV004C)
• 40-PinTSOP (for MX29LV004C and MX29LV008C)
• All Pb-free devices are RoHS Compliant
P/N:PM1301
REV. 1.1, AUG. 25, 2006
1
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
MX29LV002C/002NC PIN CONFIGURATIONS
32TSOP (TYPE 1)
A11
A9
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CE#
Q7
2
A8
3
A13
A14
A17
WE#
VCC
RESET#
A16
A15
A12
A7
4
5
Q6
6
Q5
7
Q4
MX29LV002C/002NC T/B
8
Q3
9
GND
Q2
10
11
12
13
14
15
16
Q1
Q0
A0
A6
A1
A5
A2
A4
A3
NC on MX29LV002NC
32 PLCC
PIN DESCRIPTION
NC on MX29LV002NC
SYMBOL PIN NAME
A0~A17
Q0~Q7
CE#
Address Input
4
1
32
30
29
5
A7
A6
A5
A4
A3
A2
A1
A0
Q0
A14
A13
A8
DataInput/Output
Chip Enable Input
Write Enable Input
HardwareResetPin/SectorProtect
Unlock
WE#
A9
MX29LV002C/
002NC T/B
9
25
RESET#
A11
OE#
A10
CE#
Q7
OE#
VCC
GND
Output Enable Input
Power Supply Pin (+3V)
GroundPin
13
14
21
17
20
P/N:PM1301
REV. 1.1, AUG. 25, 2006
2
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
MX29LV004C PIN CONFIGURATIONS
40TSOP (StandardType) (10mm x 20mm)
A16
A15
A14
A13
A12
A11
A9
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A17
GND
NC
2
3
4
NC
5
A10
Q7
6
7
Q6
A8
8
Q5
WE#
RESET#
NC
9
Q4
10
11
12
13
14
15
16
17
18
19
20
VCC
VCC
NC
MX29LV004C T/B
RY/BY#
A18
A7
Q3
Q2
A6
Q1
A5
Q0
A4
OE#
VSS
CE#
A0
A3
A2
A1
32 PLCC
PIN DESCRIPTION
SYMBOL PIN NAME
4
1
32
30
29
A0~A18
Q0~Q7
CE#
Address Input
5
9
A7
A6
A5
A4
A3
A2
A1
A0
Q0
A14
A13
A8
Data Input/Output
Chip Enable Input
A9
MX29LV004C T/B 25
WE#
Write Enable Input
A11
OE#
A10
CE#
Q7
RESET#
Hardware Reset Pin/Sector Protect
Unlock (for 40-TSOP)
Output Enable Input
13
14
OE#
21
17
20
RY/BY#
VCC
Ready/Busy# Output (for 40-TSOP)
Power Supply Pin (2.7V~3.6V)
Ground Pin
GND
P/N:PM1301
REV. 1.1, AUG. 25, 2006
3
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
MX29LV008C PIN CONFIGURATIONS
40TSOP (StandardType) (10mm x 20mm)
A16
A15
A14
A13
A12
A11
A9
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A17
GND
NC
2
3
4
A19
A10
Q7
5
6
7
Q6
A8
8
Q5
WE#
RESET#
NC
9
Q4
10
11
12
13
14
15
16
17
18
19
20
VCC
VCC
NC
MX29LV008CT/CB
RY/BY#
A18
A7
Q3
Q2
A6
Q1
A5
Q0
A4
OE#
GND
CE#
A0
A3
A2
A1
PIN DESCRIPTION
SYMBOL PIN NAME
A0~A19
Q0~Q7
CE#
Address Input
Data Input/Output
Chip Enable Input
Write Enable Input
WE#
RESET# Hardware Reset Pin
OE#
Output Enable Input
Ready/Busy Output
Power Supply Pin (2.7V~3.6V)
Ground Pin
RY/BY#
VCC
GND
P/N:PM1301
REV. 1.1, AUG. 25, 2006
4
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
BLOCK DIAGRAM
WRITE
CE#
OE#
CONTROL
INPUT
PROGRAM/ERASE
STATE
HIGH VOLTAGE
MACHINE
WE#
LOGIC
RESET#
(WSM)
STATE
FLASH
ADDRESS
LATCH
REGISTER
ARRAY
ARRAY
A0-AM
AND
SOURCE
HV
BUFFER
Y-PASS GATE
COMMAND
DATA
DECODER
PGM
SENSE
DATA
HV
AMPLIFIER
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
Q0-Q7
I/O BUFFER
AM: MSB address
P/N:PM1301
REV. 1.1, AUG. 25, 2006
5
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Table 1. BLOCK STRUCTURE
MX29LV002CT SECTOR ARCHITECTURE
Sector
Sector Size
Byte Mode
64Kbytes
64Kbytes
64Kbytes
32Kbytes
8Kbytes
Address range
Byte Mode (x8)
00000-0FFFF
10000-1FFFF
20000-2FFFF
30000-37FFF
38000-39FFF
3A000-3BFFF
3C000-3FFFF
Sector Address
A17 A16 A15 A14 A13
SA0
SA1
SA2
SA3
SA4
SA5
SA6
0
0
1
1
0
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
8Kbytes
16Kbytes
MX29LV002CB SECTOR ARCHITECTURE
Sector
Sector Size
Byte Mode
16Kbytes
8Kbytes
Address range
Byte Mode (x8)
00000-03FFF
04000-05FFF
06000-07FFF
08000-0FFFF
10000-1FFFF
20000-2FFFF
30000-3FFFF
Sector Address
A17 A16 A15 A14 A13
SA0
SA1
SA2
SA3
SA4
SA5
SA6
0
0
0
0
0
1
1
0
0
0
0
1
0
1
0
0
0
1
X
0
8Kbytes
0
1
1
32Kbytes
64Kbytes
64Kbytes
64Kbytes
1
X
X
X
X
X
X
X
X
X
X
X
P/N:PM1301
REV. 1.1, AUG. 25, 2006
6
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
MX29LV004CT SECTOR ARCHITECTURE
Sector
Sector Size
Byte Mode
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
32Kbytes
8Kbytes
Address range
Byte Mode (x8)
00000-0FFFF
10000-1FFFF
20000-2FFFF
30000-3FFFF
40000-4FFFF
50000-5FFFF
60000-6FFFF
70000-77FFF
78000-79FFF
7A000-7BFFF
7C000-7FFFF
Sector Address
A18 A17 A16 A15 A14 A13
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
0
1
8Kbytes
1
0
1
16Kbytes
1
1
X
MX29LV004CB SECTOR ARCHITECTURE
Sector
Sector Size
Byte Mode
16Kbytes
8Kbytes
Address range
Byte Mode (x8)
00000-03FFF
04000-05FFF
06000-07FFF
08000-0FFFF
10000-1FFFF
20000-2FFFF
30000-3FFFF
40000-4FFFF
50000-5FFFF
60000-6FFFF
70000-7FFFF
Sector Address
A18 A17 A16 A15 A14 A13
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
0
0
1
X
0
8Kbytes
0
1
1
32Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
P/N:PM1301
REV. 1.1, AUG. 25, 2006
7
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
MX29LV008CT SECTOR ARCHITECTURE
Sector
Sector Size
Address range
Sector Address
A19 A18 A17 A16 A15 A14 A13
SA0
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
32Kbytes
8Kbytes
00000h-0FFFFh
10000h-1FFFFh
20000h-2FFFFh
30000h-3FFFFh
40000h-4FFFFh
50000h-5FFFFh
60000h-6FFFFh
70000h-7FFFFh
80000h-8FFFFh
90000h-9FFFFh
A0000h-AFFFFh
B0000h-BFFFFh
C0000h-CFFFFh
D0000h-DFFFFh
E0000h-EFFFFh
F0000h-F7FFFh
F8000h-F9FFFh
FA000h-FBFFFh
FC000h-FFFFFh
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
1
8Kbytes
1
0
1
16kbytes
1
1
X
P/N:PM1301
REV. 1.1, AUG. 25, 2006
8
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
MX29LV008CB SECTOR ARCHITECTURE
Sector
Sector Size
Address range
Sector Address
A19 A18 A17 A16 A15 A14 A13
SA0
16Kbytes
8Kbytes
00000h-03FFFh
04000h-05FFFh
06000h-07FFFh
08000h-0FFFFh
10000h-1FFFFh
20000h-2FFFFh
30000h-3FFFFh
40000h-4FFFFh
50000h-5FFFFh
60000h-6FFFFh
70000h-7FFFFh
80000h-8FFFFh
90000h-9FFFFh
A0000h-AFFFFh
B0000h-BFFFFh
C0000h-CFFFFh
D0000h-DFFFFh
E0000h-EFFFFh
F0000h-FFFFFh
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
X
0
SA1
SA2
8Kbytes
0
1
1
SA3
32Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64kbytes
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
P/N:PM1301
REV. 1.1, AUG. 25, 2006
9
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Table 2. BUS OPERATION--1
Mode Select
RE-
SET#
L
CE#
WE#
OE#
Address
Q0~Q7
Device Reset
Standby Mode
X
Vcc±
0.3V
L
X
X
X
X
X
X
HighZ
HighZ
Vcc±
0.3V
H
Output
H
H
X
HighZ
Disable
Read Mode
Write
H
H
L
L
X
H
L
L
H
X
AIN
AIN
AIN
DOUT
DIN
Temporary
Sector
Vhv
X
DIN
Unprotect
Sector
Vhv
Vhv
L
L
L
L
H
H
Sector Address,
A6=L, A1=H,
A0=L
DIN
DIN
Protect
Chip
Sector Address,
A6=H, A1=H,
A0=L
Unprotect
Note:
1. Q0~Q7 are input (DIN) or output (DOUT) pins according to the requests of command sequence, sector protection,
or data polling algorithm.
P/N:PM1301
REV. 1.1, AUG. 25, 2006
10
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
BUS OPERATION--2
Item
Control Input
CE# WE# OE# to
A13 A10
AM A12
A8
to
A7
x
A5
to
A2
x
to
A9
Vhv
Vhv
Vhv
Vhv
Vhv
Vhv
Vhv
Vhv
A6
L
A1
H
L
A0
L
Q0~Q7
Sector Protect
Verification
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
SA
x
x
x
x
x
x
x
x
01h or 00h
(Note1)
C2H
Read Silicon ID
Manufacturer Code
Read Silicon ID
MX29LV002CT
Read Silicon ID
MX29LV002CB
Read Silicon ID
MX29LV004CT
Read Silicon ID
MX29LV004CB
Read Silicon ID
MX29LV008CT
Read Silicon ID
MX29LV008CB
x
x
x
x
x
x
x
x
L
x
x
x
x
x
x
x
L
x
L
L
H
H
H
H
H
H
59H
5AH
B5H
B6H
3EH
37H
x
L
L
x
L
L
x
L
L
x
L
L
x
L
L
Notes:
1.Sector unprotected code:00h.Sector protected code:01h.
2. AM: MSB of address.
P/N:PM1301
REV. 1.1, AUG. 25, 2006
11
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
WRITE COMMANDS/COMMAND SEQUENCES
To write a command to the device, system must drive WE# and CE# to Vil, and OE# to Vih. In a command cycle, all
address are latched at the later falling edge of CE# and WE#, and all data are latched at the earlier rising edge of CE#
andWE#.
Figure 1 illustrates the AC timing waveform of a write command, andTable 3 defines all the valid command sets of the
device.System is not allowed to write invalid commands not defined in this datasheet.Writing an invalid command will
bring the device to an undefined state.
REQUIREMENTS FOR READING ARRAY DATA
Read array action is to read the data stored in the array.While the memory device is in powered up or has been reset,
it will automatically enter the status of read array.If the microprocessor wants to read the data stored in array, it has to
drive CE# (device enable control pin) and OE# (Output control pin) asVil, and input the address of the data to be read
into address pin at the same time. After a period of read cycle (Tce or Taa), the data being read out will be displayed
on output pin for microprocessor to access.If CE# or OE# isVih, the output will be in tri-state, and there will be no data
displayed on output pin at all.
After the memory device completes embedded operation (automatic Erase or Program), it will automatically return to
the status of read array, and the device can read the data in any address in the array. In the process of erasing, if the
device receives the Erase suspend command, erase operation will be stopped temporarily after a period of time no
more than Tready1 and the device will return to the status of read array. At this time, the device can read the data
stored in any address except the sector being erased in the array.In the status of erase suspend, if user wants to read
the data in the sectors being erased, the device will output status data onto the output.Similarly, if program command
is issued after erase suspend, after program operation is completed, system can still read array data in any address
except the sectors to be erased
The device needs to issue reset command to enable read array operation again in order to arbitrarily read the data in
the array in the following two situations:
1.In program or erase operation, the programming or erasing failure causes Q5 to go high.
2.The device is in auto select mode or CFI mode.
In the two situations above, if reset command is not issued, the device is not in read array mode and system must
issue reset command before reading array data.
P/N:PM1301
REV. 1.1, AUG. 25, 2006
12
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
RESET# OPERATION
Driving RESET# pin low for a period more thanTrp will reset the device back to read mode. If the device is in program
or erase operation, the reset operation will take at most a period ofTready1 for the device to return to read array mode.
Before the device returns to read array mode, the RY/BY# pin remains low (busy status).
When RESET# pin is held at GND±0.3V, the device consumes standby current(Isb).However, device draws larger
current if RESET# pin is held at Vil but not within GND±0.3V.
It is recommended that the system to tie its reset signal to RESET# pin of flash memory, so that the flash memory will
be reset during system reset and allows system to read boot code from flash memory.
SECTOR PROTECT OPERATION
When a sector is protected, program or erase operation will be disabled on that protected sector. MX29LV002C/
MX29LV004C/MX29LV008CT/B provides two methods for sector protection.
Once the sector is protected, the sector remains protected until next chip unprotect, or is temporarily unprotected by
asserting RESET# pin at Vhv. Refer to temporary sector unprotect operation for further details.
The first method is by applying Vhv on RESET# pin. Refer to Figure 12 for timing diagram and Figure 13 for the
algorithm for this method.
The other method is assertingVhv on A9 and OE# pins, with A6 and CE# atVil.The protection operation begins at the
falling edge of WE# and terminates at the rising edge. Contact Macronix for details.
CHIP UNPROTECT OPERATION
MX29LV002C/MX29LV004C/MX29LV008CT/B provides two methods for chip unprotect.The chip unprotect operation
unprotects all sectors within the device.It is recommended to protect all sectors before activating chip unprotect mode.
All sector are unprotected when shipped from the factory.
The first method is by applyingVhv on RESET# pin.Refer to Figure 12 for timing diagram and Figure 13 for algorithm
of the operation.
The other method is asserting Vhv on A9 and OE# pins, with A6 at Vih and CE# at Vil (see Table 2). The unprotect
operation begins at the falling edge of WE# and terminates at the rising edge. Contact Macronix for details.
TEMPORARY SECTOR UNPROTECT OPERATION
System can apply RESET# pin at Vhv to place the device in temporary unprotect mode. In this mode, previously
protected sectors can be programmed or erased just as it is unprotected.The devices returns to normal operation once
Vhv is removed from RESET# pin and previously protected sectors are again protected.
P/N:PM1301
REV. 1.1, AUG. 25, 2006
13
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
AUTOMATIC SELECT OPERATION
When the device is in Read array mode, erase-suspended read array mode or CFI mode, user can issue read silicon
ID command to enter read silicon ID mode. After entering read silicon ID mode, user can query several silicon IDs
continuously and does not need to issue read silicon ID mode again. When A0 is Low, device will output Macronix
Manufacture ID C2.When A0 is high, device will output Device ID.In read silicon ID mode, issuing reset command will
reset device back to read array mode or erase-suspended read array mode.
Another way to enter read silicon ID is to apply high voltage on A9 pin with CE#, OE#, A6 and A1 atVil.While the high
voltage of A9 pin is discharged, device will automatically leave read silicon ID mode and go back to read array mode
or erase-suspended read array mode.When A0 is Low, device will output Macronix Manufacture ID C2.When A0 is
high, device will output Device ID.
VERIFY SECTOR PROTECT STATUS OPERATION
MX29LV002C/MX29LV004C/MX29LV008CT/B provides hardware sector protection against Program and Erase op-
eration for protected sectors. The sector protect status can be read through Sector Protect Verify command. This
method requiresVhv on A9 pin,Vih onWE# and A1 pins, Vil on CE#, OE#, A6 and A0 pins, and sector address on A13
to AM pins. If the read out data is 01H, the designated sector is protected. Oppositely, if the read out data is 00H, the
designated sector is not protected.
DATA PROTECTION
To avoid accidental erasure or programming of the device, the device is automatically reset to read array mode during
power up. Besides, only after successful completion of the specified command sets will the device begin its erase or
program operation.
Other features to protect the data from accidental alternation are described as followed.
LOWVCCWRITE INHIBIT
The device refuses to accept any write command when Vcc is less than 1.4V. This prevents data from spuriously
altered.The device automatically resets itself when Vcc is lower than 1.4V and write cycles are ignored until Vcc is
greater than 1.4V. System must provide proper signals on control pins after Vcc is larger than 1.4V to avoid uninten-
tional program or erase operation
WRITE PULSE "GLITCH" PROTECTION
CE#, WE#, OE# pulses shorter than 5ns are treated as glitches and will not be regarded as an effective write cycle.
LOGICAL INHIBIT
A valid write cycle requires both CE# and WE# at Vil with OE# at Vih.Write cycle is ignored when either CE# at Vih,
WE# a Vih, or OE# at Vil.
P/N:PM1301
REV. 1.1, AUG. 25, 2006
14
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
POWER-UP SEQUENCE
Upon power up, MX29LV002C/MX29LV004C/MX29LV008CT/B is placed in read array mode.Furthermore, program or
erase operation will begin only after successful completion of specified command sequences.
POWER-UPWRITE INHIBIT
When WE#, CE# is held at Vil and OE# is held at Vih during power up, the device ignores the first command on the
rising edge of WE#.
POWER SUPPLY DECOUPLING
A 0.1uF capacitor should be connected between the Vcc and GND to reduce the noise effect.
P/N:PM1301
REV. 1.1, AUG. 25, 2006
15
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
TABLE 3. MX29LV002C/MX29LV004C/MX29LV008CT/B COMMAND DEFINITIONS
Automatic Select
Manufacturer Device
Read
Mode
Res et
Mode
Chip Sector
Eras e Eras e
Sector Protect
Verify
Command
ID
555
AA
2AA
55
ID
555
AA
2AA
55
Program
555
1s t Bus Cyc
Addr
Data
Addr
Data
XXX
F0
555
AA
555
AA
2AA
55
555
AA
AA
2nd Bus Cyc Addr
Data
2AA
2AA
55
2AA
55
55
3rd Bus Cyc
4th Bus Cyc
5th Bus Cyc
6th Bus Cyc
Addr
Data
Addr
Data
Addr
Data
Addr
Data
555
90
555
90
555
555
555
80
555
80
90
A0
(Sector)X02
X00
C2
X01
ID
Addr
Data
555
AA
2AA
55
555
AA
00/01
2AA
55
555
10
Sector
30
Erase
Eras e Sector
CFI
(Note 4)
Suspend Res ume Protect
Command
XXX
XXX
AA
1s t Bus Cyc
Addr
Data
XXX
60
B0
30
98
2nd Bus Cyc Addr
Data
sector
60
3rd Bus Cyc
4th Bus Cyc
5th Bus Cyc
6th Bus Cyc
Addr
Data
Addr
Data
Addr
Data
Addr
Data
sector
40
sector
00/01
Notes:
1. Device ID :
29LV002C:59H/5AH (Top/Bottom)
29LV004C:B5H/B6H (Top/Bottom)
29LV008C:3EH/37H (Top/Bottom)
2. For sector protect verify result, 00H means sector is not protected, 01H means sector has been protected.
3. Sector Protect command is valid during Vhv at RESET# pin, Vih at A1 pin and Vil at A0, A6 pins.The last Bus cyc
is for protect verify.
4. For MX29LV002C/002NC and MX29LV004C.
P/N:PM1301
REV. 1.1, AUG. 25, 2006
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MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
RESET
In the following situations, executing reset command will reset device back to read array mode:
• Among erase command sequence (before the full command set is completed)
• Sector erase time-out period
• Erase fail (while Q5 is high)
• Among program command sequence (before the full command set is completed, erase-suspended program in-
cluded)
• Program fail (while Q5 is high, and erase-suspended program fail is included)
• Read silicon ID mode
• Sector protect verify
• CFI mode
While device is at the status of program fail or erase fail (Q5 is high), user must issue reset command to reset device
back to read array mode. While the device is in read silicon ID mode, sector protect verify or CFI mode, user must
issue reset command to reset device back to read array mode.
When the device is in the progress of programming (not program fail) or erasing (not erase fail), device will ignore reset
command.
AUTOMATIC SELECT COMMAND SEQUENCE
Automatic Select mode is used to access the manufacturer ID, device ID and to verify whether or not a sector is
protected. The automatic select mode has four command cycles. The first two are unlock cycles, and followed by a
specific command. The fourth cycle is a normal read cycle, and user can read at any address any number of times
without entering another command sequence.The reset command is necessary to exit the Automatic Select mode and
back to read array.The following table shows the identification code with corresponding address.
Address
Data (Hex)
C2
Representation
Manufacturer ID
Device ID
X00
X01
ID
Top/Bottom Boot Sector
Unprotected/protected
Sector Protect Verify
(Sector address) X 02
00/01
There is an alternative method to that shown inTable 2, which is intended for EPROM programmers and requiresVhv
on address bit A9.
Notes:
Device ID : MX29LV002CT:59, MX29LV002CB:5A
MX29LV004CT:B5, MX29LV004CB:B6
MX29LV008CT:3E, MX29LV008CB:37
P/N:PM1301
REV. 1.1, AUG. 25, 2006
17
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
AUTOMATIC PROGRAMMING
The MX29LV002C/MX29LV004C/MX29LV008CT/B can provide the user program function by the form of Byte-Mode or
Word-Mode.As long as the users enter the right cycle defined in theTable.3 (including 2 unlock cycles and A0H), any
data user inputs will automatically be programmed into the array.
Once the program function is executed, the internal write state controller will automatically execute the algorithms and
timings necessary for program and verification, which includes generating suitable program pulse, verifying whether
the threshold voltage of the programmed cell is high enough and repeating the program pulse if any of the cells does not
pass verification.Meanwhile, the internal control will prohibit the programming to cells that pass verification while the
other cells fail in verification in order to avoid over-programming. With the internal write state controller, the device
requires the user to write the program command and data only.
Programming will only change the bit status from "1" to "0".That is to say, it is impossible to convert the bit status from
"0" to "1" by programming. Meanwhile, the internal write verification only detects the errors of the "1" that is not
successfully programmed to "0".
Any command written to the device during programming will be ignored except hardware reset, which will terminate the
program operation after a period of time no more thanTready1.When the embedded program algorithm is complete or
the program operation is terminated by hardware reset, the device will return to the reading array data mode.
When the embedded program operation is on going, user can confirm if the embedded operation is finished or not by the
following methods:
Status
Q7
Q7#
Q7
Q6
Q5
0
RY/BY#*2
In progress*1
Finished
togging
0
1
0
Stop toggling
Toggling
0
Exceed time limit
Q7#
1
*1:The status "in progress" means both program mode and erase-suspended program mode.
*2: RY/BY# is an open drain output pin and should be weakly connected to Vcc through a pull-up resistor.
*3: When an attempt is made to program a protected sector, Q7 will output its complement data or Q6 continues to
toggle for about 1us or less and the device returns to read array state without programing the data in the protected
sector.
P/N:PM1301
REV. 1.1, AUG. 25, 2006
18
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
CHIP ERASE
Chip Erase is to erase all the data with "1" and "0" as all "1". It needs 6 cycles to write the action in, and the first two
cycles are "unlock" cycles, the third one is a configuration cycle, the fourth and fifth are also "unlock" cycles, and the
sixth cycle is the chip erase operation.
During chip erasing, all the commands will not be accepted except hardware reset or the working voltage is too low that
chip erase will be interrupted. After Chip Erase, the chip will return to the state of Read Array.
When the embedded chip erase operation is on going, user can confirm if the embedded operation is finished or not by
the following methods:
Status
Q7
0
Q6
Q5
0
Q2
Toggling
1
RY/BY#
In progress
Finished
Togging
0
1
0
1
Stop toggling
Toggling
0
Exceed time limit
0
1
Toggling
SECTOR ERASE
Sector Erase is to erase all the data in a sector with "1" and "0" as all "1".It requires six command cycles to issue.The
first two cycles are "unlock cycles", the third one is a configuration cycle, the fourth and fifth are also "unlock cycles"
and the sixth cycle is the sector erase command. After the sector erase command sequence is issued, there is a time-
out period of 50us counted internally.During the time-out period, additional sector address and sector erase command
can be written multiply. Once user enters another sector erase command, the time-out period of 50us is recounted.If
user enters any command other than sector eras or erase suspend during time-out period, the erase command would
be aborted and the device is reset to read array condition. The number of sectors could be from one sector to all
sectors. After time-out period passing by, additional erase command is not accepted and erase embedded operation
begins.
During sector erasing, all commands will not be accepted except hardware reset and erase suspend and user can
check the status as chip erase.
When the embedded erase operation is on going, user can confirm if the embedded operation is finished or not by the
following methods:
Status
Q7
0
Q6
Q5
0
Q3
0
Q2
RY/BY#*2
Time-out period
In progress
Finished
Togging
Toggling
Toggling
1
0
0
1
0
0
Togging
0
1
1
Stop toggling
Toggling
0
1
Exceed time limit
0
1
1
Toggling
*1: The status Q3 is the time-out period indicator. When Q3=0, the device is in time-out period and is acceptible to
another sector address to be erased.When Q3=1, the device is in erase operation and only erase suspend is valid.
*2:RY/BY# is open drain output pin and should be weakly connected toVcc through a pull-up resistor.
*3:When an attempt is made to erase a protected sector, Q7 will output its complement data or Q6 continues to toggle
for 100us or less and the device returned to read array status without erasing the data in the protected sector.
P/N:PM1301
REV. 1.1, AUG. 25, 2006
19
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
SECTOR ERASE SUSPEND
During sector erasure, sector erase suspend is the only valid command.If user issue erase suspend command in the
time-out period of sector erasure, device time-out period will be over immediately and the device will go back to erase-
suspended read array mode.If user issue erase suspend command during the sector erase is being operated, device
will suspend the ongoing erase operation, and after theTready1 (<=20uS) suspend finishes and the device will enter
erase-suspended read array mode.User can judge if the device has finished erase suspend through Q6, Q7, and RY/
BY#.
After device has entered erase-suspended read array mode, user can read other sectors not at erase suspend by the
speed of Taa;while reading the sector in erase-suspend mode, device will output its status. User can use Q6 and Q2
to judge the sector is erasing or the erase is suspended.
Status
Q7
1
Q6
No toggle
Data
Q5
Q3
Q2
toggle
Data
N/A
RY/BY#
Erase suspend read in erase suspended sector
Erase suspend read in non-erase suspended sector
Erase suspend program in non-erase suspended sector
0
N/A
1
1
0
Data
Q7#
Data Data
N/A
Toggle
0
When the device has suspended erasing, user can execute the command sets except sector erase and chip erase,
such as read silicon ID, sector protect verify, program, CFI query and erase resume.
SECTOR ERASE RESUME
Sector erase resume command is valid only when the device is in erase suspend state.After erase resume, user can
issue another erase suspend command, but there should be a 400uS interval between erase resume and the next
erase suspend. If user issue infinite suspend-resume loop, or suspend-resume exceeds 1024 times, the time for
erasing will increase.
P/N:PM1301
REV. 1.1, AUG. 25, 2006
20
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
QUERY COMMAND AND COMMON FLASH INTERFACE (CFI) MODE
MX29LV002C/MX29LV004CT/B features CFI mode.Host system can retrieve the operating characteristics, structure
and vendor-specified information such as identifying information, memory size, byte/word configuration, operating
voltages and timing information of this device by CFI mode.The device enters the CFI Query mode when the system
writes the CFI Query command, 98H, to address 55H any time the device is ready to read array data.The system can
read CFI information at the addresses given inTable 4.A reset command is required to exit CFI mode and go back to
ready array mode or erase suspend mode.The system can write the CFI Query command only when the device is in
read mode, erase suspend, standby mode or automatic select mode.
Table 4-1. CFI mode: Identification DataValues (MX29LV002C/002NC and 004C only)
(All values in these tables are in hexadecimal)
Description
Address(h)
Data(h)
0051
0052
0059
0002
0000
0040
0000
0000
0000
0000
0000
Query-unique ASCII string "QRY"
10
11
12
13
14
15
16
17
18
19
1A
Primary vendor command set and control interface ID code
Address for primary algorithm extended query table
Alternate vendor command set and control interface ID code
Address for alternate algorithm extended query table
Table 4-2. CFI Mode: System Interface DataValues
Description
Address(h)
Data(h)
0027
0036
0000
0000
0004
0000
000A
0000
0005
0000
0004
0000
Vcc supply minimum program/erase voltage
Vcc supply maximum program/erase voltage
VPP supply minimum program/erase voltage
VPP supply maximum program/erase voltage
Typical timeout per single word/byte write, 2n uS
Typical timeout for maximum-size buffer write, 2n uS
Typical timeout per individual block erase, 2n mS
Typical timeout for full chip erase, 2n mS
Maximum timeout for word/byte write, 2n times typical
Maximum timeout for buffer write, 2n times typical
Maximum timeout per individual block erase, 2n times typical
Maximum timeout for chip erase, 2n times typical
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
P/N:PM1301
REV. 1.1, AUG. 25, 2006
21
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Table 4-3. CFI Mode:Device Geometry DataValues
Description
Address(h)
Data(h)
0012
0013
0000
0000
0000
0000
0004
0000
0000
0040
0000
0001
0000
0020
0000
0000
0000
0080
0000
0002
0006
0000
0000
0001
Device size = 2n in number of bytes (MX29LV002C)
Device size = 2n in number of bytes (MX29LV004C)
Flash device interface description
27
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
39
3A
3B
3C
Maximum number of bytes in buffer write = 2n (not support)
Number of erase regions within device
Index for Erase Bank Area 1
[2E,2D] = # of same-size sectors in region 1-1
[30, 2F] = sector size in multiples of 256-bytes
Index for Erase Bank Area 2
Index for Erase Bank Area 3
Index for Erase Bank Area 4 (for MX29LV002C)
Index for Erase Bank Area 4 (for MX29LV004C)
P/N:PM1301
REV. 1.1, AUG. 25, 2006
22
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Table 4-4. CFI Mode:PrimaryVendor-Specific Extended Query DataValues
Description
Address(h)
Data(h)
0050
0052
0049
0031
0030
0000
0002
0001
0001
0004
0000
0000
0000
Query - Primary extended table, unique ASCII string, PRI
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
Major version number, ASCII
Minor version number, ASCII
Unlock recognizes address (0= recognize, 1= don't recognize)
Erase suspend (2= to both read and program)
Sector protect (N= # of sectors/group)
Temporarysectorunprotect(1=supported)
Sector protect/Chip unprotect scheme
SimultaneousR/Woperation(0=notsupported)
Burstmode(0=notsupported)
Pagemode(0=notsupported)
P/N:PM1301
REV. 1.1, AUG. 25, 2006
23
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
ABSOLUTE MAXIMUM STRESS RATINGS
Surrounding Temperature with Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . -65oC to +125oC
Storage Temperature . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65oC to +150oC
Voltage Range
Vcc . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V
RESET#, A9 and OE# . .. . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +12.5 V
The other pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 V to Vcc +0.5 V
Output Short Circuit Current (less than one second) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 mA
OPERATING TEMPERATURE AND VOLTAGE
Commercial (C) Grade
Surrounding Temperature (TA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial (I) Grade
Surrounding Temperature (TA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Vcc SupplyVoltages
Full Vcc Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.7 V to 3.6 V
Regulated Vcc Voltage Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.0 V to 3.6 V
P/N:PM1301
REV. 1.1, AUG. 25, 2006
24
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
DC CHARACTERISTICS
Symbol Description
Min
Typ
Max
± 1.0uA
35uA
Remark
Iilk
Input Leak
Iilk9
Iolk
Icr1
A9 Leak
A9=12.5V
Output Leak
Read Current(5MHz)
± 1.0uA
12mA
7mA
2mA
CE#=Vil,
OE#=Vih
Icr2
Icw
Read Current(1MHz)
Write Current
4mA
CE#=Vil,
OE#=Vih
15mA
30mA
CE#=Vil,
OE#=Vih,
WE#=Vil
Isb
Standby Current
Reset Current
0.2uA
0.2uA
5uA
5uA
Vcc=Vcc max,
other pin disable
Vcc=Vccmax,
RESET# enable,
other pin disable
Isbr
Isbs
Vil
Sleep Mode Current
Input LowVoltage
0.2uA
5uA
0.8V
-0.5V
0.7xVcc
11.5V
Vih
Vhv
Input HighVoltage
Vcc+0.3V
12.5V
Very HighVoltage for hardware
Protect/Unprotect/Auto Select/
Temporary Unprotect
Output LowVoltage
Vol
0.45V
Iol=4.0mA
Voh1
Voh2
Ouput HighVoltage
0.85xVcc
Vcc-0.4V
Ioh1=-2mA
Ioh2=-100uA
Ouput HighVoltage
P/N:PM1301
REV. 1.1, AUG. 25, 2006
25
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
SWITCHING TEST CIRCUITS
Vcc
R2
TESTED DEVICE
+3.3V
0.1uF
CL
R1
DIODES=IN3064
OR EQUIVALENT
R1=6.2K ohm
R2=2.7K ohm
Test Condition
Output Load : 1 TTL gate
Output Load Capacitance,CL :30pF(45R/55R/70nS)/100pF(90nS)
Rise/Fall Times : 5nS
In/Out reference levels :1.5V
SWITCHING TEST WAVEFORMS
3.0V
0.0V
1.5V
1.5V
Test Points
INPUT
OUTPUT
P/N:PM1301
REV. 1.1, AUG. 25, 2006
26
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
AC CHARACTERISTICS
MX29LV002C/002NC
Symbol
Taa
Description
Min
Typ
Max
Unit
nS
nS
nS
nS
nS
Valid data output after address
Valid data output after CE# low
Valid data output after OE# low
Data output floating after OE# high
Output hold time from the earliest rising edge of address,
CE#, OE#
70/90
70/90
30/35
25/30
Tce
Toe
Tdf
Toh
0
Trc
Read period time
70/90
70/90
70/90
0
nS
nS
nS
nS
nS
nS
nS
uS
nS
nS
nS
nS
nS
Twc
Tcwc
Tas
Write period time
Command write period time
Address setup time
Tah
Address hold time
45
Tds
Tdh
Tvcs
Tcs
Tch
Toes
Toeh
Toeh
Data setup time
35/45
0
Data hold time
Vcc setup time
50
Chip enable Setup time
Chip enable hold time
Output enable setup time
Read
0
0
0
0
Output enable hold time
Toggle &
10
Data# Polling
Tws
WE# setup time
0
nS
nS
nS
nS
nS
nS
nS
nS
nS
uS
sec
uS
Twh
WE# hold time
0
Tcep
Tceph
Twp
CE# pulse width
35
30
35
30
CE# pulse width high
WE# pulse width
Twph
Tbusy
Tghwl
Tghel
Twhwh1
Twhwh2
Tbal
WE# pulse width high
Program/Erase active time by RY/BY#
Read recover time before write
90
0
0
Read recover time before write (CE# Control)
Byte Program operation
9
300
15
Sector Erase Operation
0.7
Sector Add hold time
50
P/N:PM1301
REV. 1.1, AUG. 25, 2006
27
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
MX29LV004C (Restricated Vcc=3.0V~3.6V for 45R/55R)
Symbol
Taa
Description
Min
Typ
Max
Unit
Valid data output after address
Valid data output after CE# low
Valid data output after OE# low
Data output floating after OE# high
Output hold time from the earliest rising edge of address,
CE#, OE#
45/55/70/90 nS
45/55/70/90 nS
30/30/30/35 nS
25/25/25/30 nS
nS
Tce
Toe
Tdf
Toh
0
Trc
Read period time
45/55/70/90
nS
nS
nS
nS
nS
nS
nS
uS
nS
nS
nS
nS
nS
Twc
Tcwc
Tas
Write period time
45/55/70/90
Command write period time
Address setup time
45/55/70/90
0
Tah
Address hold time
45
Tds
Tdh
Tvcs
Tcs
Tch
Toes
Toeh
Toeh
Data setup time
35/35/35/45
Data hold time
0
50
0
Vcc setup time
Chip enable Setup time
Chip enable hold time
Output enable setup time
Read
0
0
0
Output enable hold time
Toggle &
10
Data# Polling
Tws
WE# setup time
0
nS
nS
nS
nS
nS
nS
Twh
WE# hold time
0
Tcep
Tceph
Twp
CE# pulse width
35
30
35
30
CE# pulse width high
WE# pulse width
Twph
Tbusy
Tghwl
Tghel
Twhwh1
Twhwh2
Tbal
WE# pulse width high
Program/Erase active time by RY/BY#
Read recover time before write
90
nS
nS
nS
uS
sec
uS
0
0
Read recover time before write (CE# Control)
Byte Program operation
9
300
15
Sector Erase Operation
0.7
Sector Add hold time
50
Notes:Only 40-TSOP provide RY/BY# pin.
P/N:PM1301
REV. 1.1, AUG. 25, 2006
28
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
MX29LV008C (Restricated Vcc=3.0V~3.6V for 55R)
Symbol
Taa
Description
Min
Typ
Max
Unit
nS
nS
nS
nS
nS
Valid data output after address
Valid data output after CE# low
Valid data output after OE# low
Data output floating after OE# high
Output hold time from the earliest rising edge of address,
CE#, OE#
55/70/90
55/70/90
30/30/35
25/25/30
Tce
Toe
Tdf
Toh
0
Trc
Read period time
55/70/90
nS
nS
nS
nS
nS
nS
nS
uS
nS
nS
nS
nS
nS
Twc
Tcwc
Tas
Write period time
55/70/90
Command write period time
Address setup time
55/70/90
0
Tah
Address hold time
45
Tds
Tdh
Tvcs
Tcs
Tch
Toes
Toeh
Toeh
Data setup time
35/35/45
Data hold time
0
50
0
Vcc setup time
Chip enable Setup time
Chip enable hold time
Output enable setup time
Read
0
0
0
Output enable hold time
Toggle &
10
Data# Polling
Tws
WE# setup time
0
nS
nS
nS
nS
nS
nS
nS
nS
nS
uS
sec
uS
Twh
WE# hold time
0
Tcep
Tceph
Twp
CE# pulse width
35
30
35
30
CE# pulse width high
WE# pulse width
Twph
Tbusy
Tghwl
Tghel
Twhwh1
Twhwh2
Tbal
WE# pulse width high
Program/Erase active time by RY/BY#
Read recover time before write
90
0
0
Read recover time before write (CE# Control)
Byte Program operation
9
300
15
Sector Erase Operation
0.7
Sector Add hold time
50
P/N:PM1301
REV. 1.1, AUG. 25, 2006
29
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 1. COMMANDWRITE OPERATION
Tcwc
Vih
CE#
Vil
Tch
Tcs
Vih
WE#
Vil
Toes
Twph
Twp
Vih
Vil
OE#
Vih
Vil
Addresses
VA
Tah
Tas
Tdh
Tds
Vih
Vil
Data
DIN
VA: Valid Address
P/N:PM1301
REV. 1.1, AUG. 25, 2006
30
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
READ/RESET OPERATION
Figure 2. READTIMINGWAVEFORMS
Tce
Vih
CE#
Vil
Vih
WE#
Vil
Toeh
Tdf
Toe
Vih
OE#
Vil
Toh
Taa
Trc
Vih
ADD Valid
Addresses
Vil
HIGH Z
HIGH Z
Voh
Vol
Outputs
DATA Valid
P/N:PM1301
REV. 1.1, AUG. 25, 2006
31
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
AC CHARACTERISTICS
Item
Trp1
Trp2
Trh
Description
Setup
MIN
Speed
500
500
50
Unit
nS
nS
nS
nS
nS
uS
RESET# Pulse Width (During Automatic Algorithms)
RESET# Pulse Width (NOT During Automatic Algorithms)
RESET# HighTime Before Read
MIN
MIN
MIN
MIN
MAX
Trb1
Trb2
Tready1
RY/BY# Recovery Time (to CE#, OE# go low)
RY/BY# RecoveryTime (to WE# go low)
RESET# PIN Low (During Automatic Algorithms)
to Read orWrite
0
50
20
Tready2
RESET# PIN Low (NOT During Automatic
Algorithms) to Read or Write
MAX
500
nS
Figure 3. RESET# TIMINGWAVEFORM
Trb1
CE#, OE#
WE#
Trb2
Tready1
RY/BY#
RESET#
Trp1
Reset Timing during Automatic Algorithms
CE#, OE#
RY/BY#
Trh
RESET#
Trp2
Tready2
Reset Timing NOT during Automatic Algorithms
P/N:PM1301
REV. 1.1, AUG. 25, 2006
32
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
ERASE/PROGRAM OPERATION
Figure 4.AUTOMATIC CHIP ERASETIMINGWAVEFORM
CE#
Tch
Twp
WE#
Twph
Tcs
Tghwl
OE#
Last 2 Erase Command Cycle
Read Status
VA
Tah
Twc
Tas
VA
2AAh
SA
Address
Tds
Tdh
In
Progress
Complete
55h
10h
Data
Tbusy
Trb
RY/BY#
SA: 555h for chip erase
P/N:PM1301
REV. 1.1, AUG. 25, 2006
33
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 5.AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 10H Address 555H
Data# Polling Algorithm or
Toggle Bit Algorithm
NO
Data=FFh ?
YES
Auto Chip Erase Completed
P/N:PM1301
REV. 1.1, AUG. 25, 2006
34
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 6. AUTOMATIC SECTOR ERASETIMINGWAVEFORM
Read Status
CE#
Tch
Twhwh2
Twp
WE#
Twph
Tcs
Tghwl
OE#
Tbal
Last 2 Erase Command Cycle
Twc
Tas
Sector
Sector
Sector
VA
VA
2AAh
Address
Address 0
Address 1
Address n
Tah
Tds Tdh
In
Progress
Complete
55h
30h
30h
30h
Data
Tbusy
Trb
RY/BY#
P/N:PM1301
REV. 1.1, AUG. 25, 2006
35
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 7. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 30H Sector Address
NO
Last Sector
to Erase
YES
Data# Polling Algorithm or
Toggle Bit Algorithm
NO
Data=FFh
YES
Auto Sector Erase Completed
P/N:PM1301
REV. 1.1, AUG. 25, 2006
36
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 8. ERASE SUSPEND/RESUME FLOWCHART
START
Write Data B0H
ERASE SUSPEND
NO
Toggle Bit checking Q6
not toggled
YES
Read Array or
Program
Reading or
NO
Programming End
YES
Write Data 30H
ERASE RESUME
Continue Erase
Another
NO
Erase Suspend ?
YES
P/N:PM1301
REV. 1.1, AUG. 25, 2006
37
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 9. AUTOMATIC PROGRAMTIMINGWAVEFORMS
CE#
Tch
Twhwh1
Twp
WE#
Tcs
Twph
Tghwl
OE#
Last 2 Program Command Cycle
Tas
Last 2 Read Status Cycle
VA
Tah
VA
555h
PA
Address
Tdh
Tds
Status
A0h
PD
DOUT
Data
Tbusy
Trb
RY/BY#
P/N:PM1301
REV. 1.1, AUG. 25, 2006
38
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 10. CE# CONTROLLEDWRITETIMINGWAVEFORM
WE#
CE#
OE#
Twhwh1 or Twhwh2
Tcep
Tceph
Tghwl
Tah
Tas
VA
VA
555h
PA
Address
Tdh
Tds
Status
A0h
PD
DOUT
Data
Tbusy
Trb
RY/BY#
P/N:PM1301
REV. 1.1, AUG. 25, 2006
39
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 11. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data A0H Address 555H
Write Program Data/Address
Data# Polling Algorithm or
Toggle Bit Algorithm
next address
No
Read Again Data:
Program Data?
YES
No
Last Word to be
Programed
YES
Auto Program Completed
P/N:PM1301
REV. 1.1, AUG. 25, 2006
40
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
SECTOR PROTECT/CHIP UNPROTECT
Figure 12. Sector Protect/Chip UnprotectWaveform (RESET# Control)
150uS: Sector Protect
1us
15mS: Chip Unprotect
CE#
WE#
OE#
Verification
40h
Status
VA
Data
60h
60h
VA
SA, A6
A1, A0
VA
Vhv
Vih
RESET#
VA: valid address
P/N:PM1301
REV. 1.1, AUG. 25, 2006
41
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 13-1. IN-SYSTEM SECTOR PROTECTWITH RESET#=Vhv
START
Retry count=0
RESET#=Vhv
Wait 1us
Temporary Unprotect Mode
No
First CMD=60h?
Yes
Write Sector Address
with [A6,A1,A0]:[0,1,0]
data: 60h
Wait 150us
Reset
PLSCNT=1
Write Sector Address
with [A6,A1,A0]:[0,1,0]
data: 40h
Retry Count +1
Read at Sector Address
with [A6,A1,A0]:[0,1,0]
No
No
Data=01h?
Yes
Retry Count=25?
Yes
Device fail
Yes
Protect another
sector?
No
Temporary Unprotect Mode
RESET#=Vih
Write RESET CMD
Sector Protect Done
P/N:PM1301
REV. 1.1, AUG. 25, 2006
42
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 13-2. CHIP UNPROTECT ALGORITHMSWITH RESET#=Vhv
START
Retry count=0
RESET#=Vhv
Wait 1us
Temporary Unprotect
No
First CMD=60h?
Yes
No
All sectors
protected?
Protect All Sectors
Yes
Write [A6,A1,A0]:[1,1,0]
data: 60h
Wait 15ms
Write [A6,A1,A0]:[1,1,0]
data: 40h
Retry Count +1
Read [A6,A1,A0]:[1,1,0]
No
No
Retry Count=1000?
Data=00h?
Yes
Yes
Device fail
Temporary Unprotect
Write reset CMD
Chip Unprotect Done
P/N:PM1301
REV. 1.1, AUG. 25, 2006
43
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 14. SECTOR PROTECTTIMINGWAVEFORM (A9, OE# Control)
CE#
Twpp1
WE#
Toesp
Verify
12V
3V
OE#
Tvlht
Tvlht
A1
A6
12V
3V
A9
Tvlht
Sector Address
AM-A13
Data
01H
F0H
Toe
Notes: Tvlht (Voltage transition time)=4uS min.
Twpp1 (Write pulse width for sector protect)=100nS min, 10uS(Typ.)
Twpp2 (Write pulse width for chip unprotected)=100nS min, 12mS(Typ.)
Toesp (OE# setup time to WE# active)=4uS min.
P/N:PM1301
REV. 1.1, AUG. 25, 2006
44
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 15. SECTOR PROTECTION ALGORITHM (A9, OE# Control)
START
Write Sector Addr
Retry Count=0
OE#=Vhv, A9=Vhv, CE#=Vil
A6=Vil
Activate WE# Pulse
Time Out 150us
Retry Count+1
WE#=Vih, CE#=OE#=Vil
A9=Vhv
.
Read at Sector Address
with A1=1
No
No
Data=01H?
PLSCNT=32?
Yes
Device Failed
Yes
Protect Another
Sector?
Remove Vhv from A9
Write Reset Command
Sector Protect
Done
P/N:PM1301
REV. 1.1, AUG. 25, 2006
45
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 16.TIMINGWAVEFORM FOR CHIP UNPROTECTION (A9, OE# Control)
CE#
Twpp2
WE#
Toesp
Verify
12V
VCC
OE#
A1
Tvlht
Tvlht
12V
VCC
A9
A6
Tvlht
AM-A13
Data
Sector Address
00H
F0H
Toe
Notes: Tvlht (Voltage transition time)=4uS min.
Twpp1 (Write pulse width for sector protect)=100nS min, 10uS(Typ.)
Twpp2 (Write pulse width for chip unprotected)=100nS min, 12mS(Typ.)
Toesp (OE# setup time to WE# active)=4uS min.
P/N:PM1301
REV. 1.1, AUG. 25, 2006
46
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 17. CHIP UNPROTECTION ALGORITHM (A9, OE# Control)
START
Protect All Sectors
Retry Count=0
OE#=A9=Vhv
CE#=Vil, A6=Vih
Activate WE# Pulse
Time Out 50ms
Retry Count +1
Sector Protect Verify from
first sector with CE#=OE#=vil,
A9=Vhv, A1=1
No
No
Data=00H?
Yes
PLSCNT=1000?
go to next sector
Yes
Device Failed
No
All sectors have
been verified?
Yes
Remove Vhv from A9
Write Reset Command
Chip Unprotect
Done
* Before chip unprotect, all sectors should be protected.
P/N:PM1301
REV. 1.1, AUG. 25, 2006
47
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Table 5.TEMPORARY SECTOR UNPROTECT
Parameter Alt
Description
Condition Speed
Unit
nS
Trpvhh
Tvhhwl
Tvidr
Trsp
RESET# Rise Time to Vhv and Vhv Fall Time to RESET#
RESET# Vhv to WE# Low
MIN
MIN
500
4
uS
Figure 18.TEMPORARY SECTOR UNPROTECTWAVEFORMS
Program or Erase Command Sequence
CE#
WE#
Tvhhwl
RY/BY#
Vhv 12V
RESET#
0 or Vih
Vil or Vih
Trpvhh
Trpvhh
P/N:PM1301
REV. 1.1, AUG. 25, 2006
48
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 19.TEMPORARY SECTOR UNPROTECT FLOWCHART
Start
Apply Reset# pin Vhv Volt
Enter Program or Erase Mode
Mode Operation Completed
(1) Remove Vhv Volt from Reset#
(2) RESET# = Vih
Completed Temporary Sector
Unprotected Mode
Notes:
1.Temporary unprotect all protected sectorsVhv=11.5~12.5V.
2.The protected conditions of the protected sectors are the same to temporary sector unprotect mode.
P/N:PM1301
REV. 1.1, AUG. 25, 2006
49
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 20. SILICON ID READTIMINGWAVEFORM
Vih
Vil
CE#
WE#
OE#
Tce
Vih
Vil
Toe
Vih
Vil
Tdf
Toh
Toh
Vhv
Vih
Vil
A9
Vih
Vil
A0
A1
Taa
Taa
Vih
Vil
Vih
Vil
ADD
Vih
Vil
DATA
Q0-Q7
DATA OUT
C2H
DATA OUT
Device ID
Notes:
Device ID : MX29LV002CT:59, MX29LV002CB:5A
MX29LV004CT:B5, MX29LV004CB:B6
MX29LV008CT:3E, MX29LV008CB:37
P/N:PM1301
REV. 1.1, AUG. 25, 2006
50
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
WRITE OPERATION STATUS
Figure 21. DATA# POLLINGTIMINGWAVEFORMS (DURING AUTOMATIC ALGORITHMS)
Tce
CE#
Tch
WE#
Toe
OE#
Toeh
Tdf
Trc
VA
VA
Address
Taa
Toh
High Z
High Z
Complement
Status Data
Status Data
True
True
Valid Data
Valid Data
Q7
Q0-Q6
Status Data
Tbusy
RY/BY#
P/N:PM1301
REV. 1.1, AUG. 25, 2006
51
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 22. Data# Polling Algorithm
Start
Read Q7~Q0 at valid address
(Note 1)
No
Q7 = Data# ?
Yes
No
Q5 = 1 ?
Yes
Read Q7~Q0 at valid address
No
Q7 = Data# ?
(Note 2)
Yes
FAIL
Pass
Notes:
1. For programming, valid address meas program address.
For erasing, valid address meas erase sectors address.
2. Q7 should be rechecked even Q5="1" because Q7 may change simultaneously with Q5.
P/N:PM1301
REV. 1.1, AUG. 25, 2006
52
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 23.TOGGLE BIT TIMINGWAVEFORMS (DURING AUTOMATIC ALGORITHMS)
Tce
CE#
Tch
WE#
OE#
Toe
Toeh
Tdf
Trc
VA
VA
VA
VA
Address
Taa
Toh
Valid Status
(second read)
Valid Status
(first read)
Valid Data
Valid Data
Q6/Q2
(stops toggling)
Tbusy
RY/BY#
VA : Valid Address
P/N:PM1301
REV. 1.1, AUG. 25, 2006
53
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 24.Toggle Bit Algorithm
Start
Read Q7-Q0 Twice
(Note 1)
NO
Q6 Toggle ?
YES
NO
Q5 = 1?
YES
Read Q7~Q0 Twice
NO
Q6 Toggle ?
YES
PGM/ERS fail
Write Reset CMD
PGM/ERS Complete
Notes:
1. Read toggle bit twice to determine whether or not it is toggling.
2. Recheck toggle bit because it may stop toggling as Q5 changes to "1".
P/N:PM1301
REV. 1.1, AUG. 25, 2006
54
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
RECOMMENDED OPERATING CONDITIONS
At Device Power-Up
AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up.
If the timing in the figure is ignored, the device may not operate correctly.
Vcc(min)
Vcc
GND
Tvr
Tvcs
Tf
Tce
Tr
Vih
Vil
CE#
WE#
OE#
Vih
Vil
Tf
Toe
Tr
Vih
Vil
Taa
Tr or Tf
Tr or Tf
Vih
Vil
Valid
Address
ADDRESS
Voh
Vol
High Z
Valid
Ouput
DATA
Vih
Vil
WP#/ACC
Figure A. ACTiming at Device Power-Up
Symbol
Parameter
Min.
Max.
Unit
uS/V
uS/V
uS/V
Tvr
Tr
Vcc Rise Time
20
500000
20
Input Signal RiseTime
Input Signal Fall Time
Tf
20
P/N:PM1301
REV. 1.1, AUG. 25, 2006
55
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
ERASE AND PROGRAMMING PERFORMANCE
LIMITS
PARAMETER
MIN.
TYP.
4
MAX.
32
UNITS
sec
Chip Erase Time
MX29LV002C
MX29LV004C
MX29LV008C
4
32
sec
14
sec
Sector Erase Time
0.7
15
sec
Erase/Program Cycles
Chip Programming Time
100,000
Cycles
sec
MX29LV002C
MX29LV004C
MX29LV008C
4.5
4.5
9
13.5
13.5
27
sec
sec
Byte Programming Time
9
300
uS
LATCH-UP CHARACTERISTICS
MIN.
MAX.
12.5V
Input Voltage voltage difference with GND on all pins except I/O pins
Input Voltage voltage difference with GND on all I/O pins
Vcc Current
-1.0V
-1.0V
Vcc + 1.0V
+100mA
-100mA
All pins included except Vcc. Test conditions: Vcc = 3.0V, one pin per testing
TSOP PIN CAPACITANCE
Parameter Symbol
Parameter Description
Control Pin Capacitance
Output Capacitance
Input Capacitance
Test Set
VIN=0
TYP
MAX
12
UNIT
pF
CIN2
COUT
CIN
VOUT=0
VIN=0
12
pF
8
pF
P/N:PM1301
REV. 1.1, AUG. 25, 2006
56
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
ORDERING INFORMATION
MX29LV002C
PART NO.
AccessTime Operating Current Standby Current
PACKAGE
Remark
(nS)
70
70
90
90
70
70
90
90
70
70
70
70
70
70
70
70
70
90
70
90
70
90
70
90
70
90
70
90
70
90
70
90
MAX. (mA)
30
MAX. (uA)
MX29LV002CTTC-70
MX29LV002CBTC-70
MX29LV002CTTC-90
MX29LV002CBTC-90
MX29LV002CTTI-70
MX29LV002CBTI-70
MX29LV002CTTI-90
MX29LV002CBTI-90
MX29LV002CTQC-70
MX29LV002CBQC-70
MX29LV002CTQC-90
MX29LV002CBQC-90
MX29LV002CTQI-70
MX29LV002CBQI-70
MX29LV002CTQI-90
MX29LV002CBQI-90
MX29LV002CTTC-70G
MX29LV002CTTC-90G
MX29LV002CBTC-70G
MX29LV002CBTC-90G
MX29LV002CTTI-70G
MX29LV002CTTI-90G
MX29LV002CBTI-70G
MX29LV002CBTI-90G
MX29LV002CTQC-70G
MX29LV002CTQC-90G
MX29LV002CBQC-70G
MX29LV002CBQC-90G
MX29LV002CTQI-70G
MX29LV002CTQI-90G
MX29LV002CBQI-70G
MX29LV002CBQI-90G
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
32 Pin TSOP
32 Pin TSOP
32 Pin TSOP
32 Pin TSOP
32 Pin TSOP
32 Pin TSOP
32 Pin TSOP
32 Pin TSOP
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin TSOP
32 Pin TSOP
32 Pin TSOP
32 Pin TSOP
32 Pin TSOP
32 Pin TSOP
32 Pin TSOP
32 Pin TSOP
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
PB free
PB free
PB free
PB free
PB free
PB free
PB free
PB free
PB free
PB free
PB free
PB free
PB free
PB free
PB free
PB free
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
P/N:PM1301
REV. 1.1, AUG. 25, 2006
57
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
PART NO.
AccessTime Operating Current Standby Current
PACKAGE
Remark
(nS)
70
70
90
90
70
70
90
90
70
70
70
70
70
70
70
70
70
90
70
90
70
90
70
90
70
90
70
90
70
90
70
90
MAX. (mA)
30
MAX. (uA)
MX29LV002NCTTC-70
MX29LV002NCBTC-70
MX29LV002NCTTC-90
MX29LV002NCBTC-90
MX29LV002NCTTI-70
MX29LV002NCBTI-70
MX29LV002NCTTI-90
MX29LV002NCBTI-90
MX29LV002NCTQC-70
MX29LV002NCBQC-70
MX29LV002NCTQC-90
MX29LV002NCBQC-90
MX29LV002NCTQI-70
MX29LV002NCBQI-70
MX29LV002NCTQI-90
MX29LV002NCBQI-90
MX29LV002NCTTC-70G
MX29LV002NCTTC-90G
MX29LV002NCBTC-70G
MX29LV002NCBTC-90G
MX29LV002NCTTI-70G
MX29LV002NCTTI-90G
MX29LV002NCBTI-70G
MX29LV002NCBTI-90G
MX29LV002NCTQC-70G
MX29LV002NCTQC-90G
MX29LV002NCBQC-70G
MX29LV002NCBQC-90G
MX29LV002NCTQI-70G
MX29LV002NCTQI-90G
MX29LV002NCBQI-70G
MX29LV002NCBQI-90G
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
32 Pin TSOP
32 Pin TSOP
32 Pin TSOP
32 Pin TSOP
32 Pin TSOP
32 Pin TSOP
32 Pin TSOP
32 Pin TSOP
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin TSOP
32 Pin TSOP
32 Pin TSOP
32 Pin TSOP
32 Pin TSOP
32 Pin TSOP
32 Pin TSOP
32 Pin TSOP
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
PB free
PB free
PB free
PB free
PB free
PB free
PB free
PB free
PB free
PB free
PB free
PB free
PB free
PB free
PB free
PB free
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
P/N:PM1301
REV. 1.1, AUG. 25, 2006
58
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
MX29LV004C
PART NO.
AccessTime Operating Current Standby Current
PACKAGE
Remark
(nS)
55
55
70
70
90
90
55
55
70
70
90
90
55
55
70
70
70
70
55
55
70
70
70
70
55
55
70
70
90
90
55
55
70
70
90
90
MAX. (mA)
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
MAX. (uA)
MX29LV004CTTC-55R
MX29LV004CBTC-55R
MX29LV004CTTC-70
MX29LV004CBTC-70
MX29LV004CTTC-90
MX29LV004CBTC-90
MX29LV004CTTI-55R
MX29LV004CBTI-55R
MX29LV004CTTI-70
MX29LV004CBTI-70
MX29LV004CTTI-90
MX29LV004CBTI-90
MX29LV004CTQC-55R
MX29LV004CBQC-55R
MX29LV004CTQC-70
MX29LV004CBQC-70
MX29LV004CTQC-90
MX29LV004CBQC-90
MX29LV004CTQI-55R
MX29LV004CBQI-55R
MX29LV004CTQI-70
MX29LV004CBQI-70
MX29LV004CTQI-90
MX29LV004CBQI-90
MX29LV004CTTC-55Q
MX29LV004CBTC-55Q
MX29LV004CTTC-70G
MX29LV004CBTC-70G
MX29LV004CTTC-90G
MX29LV004CBTC-90G
MX29LV004CTTI-55Q
MX29LV004CBTI-55Q
MX29LV004CTTI-70G
MX29LV004CBTI-70G
MX29LV004CTTI-90G
MX29LV004CBTI-90G
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
PB free
PB free
PB free
PB free
PB free
PB free
PB free
PB free
PB free
PB free
PB free
PB free
P/N:PM1301
REV. 1.1, AUG. 25, 2006
59
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
PART NO.
AccessTime Operating Current Standby Current
PACKAGE
Remark
(nS)
55
55
70
70
90
90
55
55
70
70
90
90
45
45
MAX. (mA)
MAX. (uA)
MX29LV004CTQC-55Q
MX29LV004CBQC-55Q
MX29LV004CTQC-70G
MX29LV004CBQC-70G
MX29LV004CTQC-90G
MX29LV004CBQC-90G
MX29LV004CTQI-55Q
MX29LV004CBQI-55Q
MX29LV004CTQI-70G
MX29LV004CBQI-70G
MX29LV004CTQI-90G
MX29LV004CBQI-90G
MX29LV004CTTI-45Q
MX29LV004CBTI-45Q
30
30
30
30
30
30
30
30
30
30
30
30
30
30
5
5
5
5
5
5
5
5
5
5
5
5
5
5
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
40 Pin TSOP
40 Pin TSOP
PB free
PB free
PB free
PB free
PB free
PB free
PB free
PB free
PB free
PB free
PB free
PB free
PB free
PB free
P/N:PM1301
REV. 1.1, AUG. 25, 2006
60
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
MX29LV008C
PART NO.
ACCESS
OPERATING
STANDBY
PACKAGE
Remark
TIME (nS) Current MAX. (mA) Current MAX. (uA)
MX29LV008CTTC-55R
MX29LV008CTTC-70
MX29LV008CTTC-90
MX29LV008CBTC-55R
MX29LV008CBTC-70
MX29LV008CBTC-90
MX29LV008CTTI-55R
MX29LV008CTTI-70
MX29LV008CTTI-90
MX29LV008CBTI-55R
MX29LV008CBTI-70
MX29LV008CBTI-90
MX29LV008CTTC-55Q
MX29LV008CTTC-70G
MX29LV008CTTC-90G
MX29LV008CBTC-55Q
MX29LV008CBTC-70G
MX29LV008CBTC-90G
MX29LV008CTTI-55Q
MX29LV008CTTI-70G
MX29LV008CTTI-90G
MX29LV008CBTI-55Q
MX29LV008CBTI-70G
MX29LV008CBTI-90G
55
70
90
55
70
90
55
70
90
55
70
90
55
70
90
55
70
90
55
70
90
55
70
90
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
P/N:PM1301
REV. 1.1, AUG. 25, 2006
61
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
PART NAME DESCRIPTION
MX 29 LV 002 C T T C 70 G
OPTION:
G: Lead-free package
R: Restricted Vcc (3.0V~3.6V)
Q: Restricted Vcc (3.0V~3.6V) with Lead-free package
blank: normal
SPEED:
45: 45nS
55: 55nS
70: 70nS
90: 90nS
TEMPERATURE RANGE:
C: Commercial (0˚CC to 70˚ C)
I: Industrial (-40˚aC to 85˚ C)
PACKAGE:
Q: PLCC
T: TSOP
BOOT BLOCK TYPE:
T: Top Boot
B: Bottom Boot
REVISION:
C
DENSITY & MODE:
002/002N: 2Mb, x8 Boot Block
004: 4Mb, x8 Boot Block
008: 8Mb, x8 Boot Block
TYPE:
LV: 3V
DEVICE:
29:Flash
P/N:PM1301
REV. 1.1, AUG. 25, 2006
62
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
PACKAGE INFORMATION
P/N:PM1301
REV. 1.1, AUG. 25, 2006
63
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
P/N:PM1301
REV. 1.1, AUG. 25, 2006
64
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
P/N:PM1301
REV. 1.1, AUG. 25, 2006
65
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
REVISION HISTORY
Revision No. Description
Page
Date
1.1
1. Corrected wrong CFI address data
P21~23
AUG/25/2006
P/N:PM1301
REV. 1.1, AUG. 25, 2006
66
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
MACRONIX INTERNATIONALCO., LTD.
Headquarters:
TEL:+886-3-578-6688
FAX:+886-3-563-2888
Europe Office :
TEL:+32-2-456-8020
FAX:+32-2-456-8021
Hong Kong Office :
TEL:+86-755-834-335-79
FAX:+86-755-834-380-78
Japan Office :
Kawasaki Office :
TEL:+81-44-246-9100
FAX:+81-44-246-9105
Osaka Office :
TEL:+81-6-4807-5460
FAX:+81-6-4807-5461
Singapore Office :
TEL:+65-6346-5505
FAX:+65-6348-8096
Taipei Office :
TEL:+886-2-2509-3300
FAX:+886-2-2509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-262-8887
FAX:+1-408-262-8810
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
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