N02L163WN1AT-70I [NANOAMP]
Standard SRAM, 128KX16, 70ns, CMOS, PDSO44;
| 型号： | N02L163WN1AT-70I |
| 厂家： | 
NANOAMP SOLUTIONS, INC. |
| 描述： | Standard SRAM, 128KX16, 70ns, CMOS, PDSO44 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总10页 (文件大小：91K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NanoAmp Solutions, Inc.
1982 Zanker Road, San Jose, CA 95112
ph: 408-573-8878, FAX: 408-573-8877
www.nanoamp.com
N02L163WN1A
2Mb Ultra-Low Power Asynchronous CMOS SRAM
128Kx16 bit
Overview
Features
The N02L163WN1A is an integrated memory
device containing a 2 Mbit Static Random Access
Memory organized as 131,072 words by 16 bits.
The device is designed and fabricated using
NanoAmp’s advanced CMOS technology to
provide both high-speed performance and ultra-low
power. The base design is the same as
• Single Wide Power Supply Range
2.3 to 3.6 Volts
• Very low standby current
2.0µA at 3.0V (Typical)
• Very low operating current
2.0mA at 3.0V and 1µs (Typical)
NanoAmp’s N02L1618N1A, which is processed to
operate at lower voltages. The device operates
with a single chip enable (CE) control and output
enable (OE) to allow for easy memory expansion.
Byte controls (UB and LB) allow the upper and
lower bytes to be accessed independently. The
N02L163WN1A is optimal for various applications
where low-power is critical such as battery backup
and hand-held devices. The device can operate
• Very low Page Mode operating current
0.8mA at 3.0V and 1µs (Typical)
• Simple memory control
Single Chip Enable (CE)
Byte control for independent byte operation
Output Enable (OE) for memory expansion
• Low voltage data retention
Vcc = 1.8V
over a very wide temperature range of -40oC to
• Very fast output enable access time
30ns OE access time
+85oC and is available in JEDEC standard
packages compatible with other standard 128Kb x
16 SRAMs.
• Automatic power down to standby mode
• TTL compatible three-state output driver
• Compact space saving BGA package avail-
able
Product Family
Standby
Operating
Current (Icc),
Max
Package
Type
Operating
Temperature
Power
Supply (Vcc)
Current (I ),
Part Number
Speed
SB
Max
N02L163WN1AB
48 - BGA
55ns @ 2.7V
70ns @ 2.3V
o
o
2.3V - 3.6V
20 µA
4 mA @ 1MHz
-40 C to +85 C
N02L163WN1AT 44 - TSOP II
Pin Configurations
Pin Descriptions
1
LB
I/O
2
3
4
5
6
NC
I/O
A
A
A
A
A
4
3
2
1
0
1
2
3
4
5
6
7
8
PIN
ONE
A
A
A
OE
UB
5
6
7
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
Pin Name
A -A
Pin Function
A
A
A
OE
A
B
C
D
E
F
0
1
2
Address Inputs
Write Enable Input
Chip Enable Input
Output Enable Input
Lower Byte Enable Input
Upper Byte Enable Input
Data Inputs/Outputs
Not Connected
0
16
A
A
A
A
A
UB
CE
I/O
8
3
5
4
6
7
0
CE
LB
WE
CE
OE
LB
I/O
I/O
I/O
I/O
VCC
VSS
I/O
I/O
I/O
I/O
0
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O
V
I/O
I/O
V
9
10
11
12
13
1
2
1
2
3
9
I/O
I/O
I/O
I/O
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
NC
SS
3
4
5
CC
V
A
A
A
A
V
CC
16
15
13
10
SS
4
5
6
7
UB
I/O
I/O
A
I/O
I/O
14
15
14
6
7
I/O
I/O
NC
9
I/O -I/O
8
0
15
A
WE
NC
WE
G
H
12
A
A
A
A
A
16
15
14
13
12
A
A
A
A
8
NC
9
A
A
9
A
NC
NC
8
11
V
10
11
Power
CC
48 Pin BGA (top)
6 x 8 mm
NC
V
Ground
SS
Stock No. 23116-10 1/02
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
1
NanoAmp Solutions, Inc.
Functional Block Diagram
N02L163WN1A
Word
Address
Inputs
Address
Decode
Logic
A0 - A3
Input/
Output
Mux
and
Buffers
Page
Address
Decode
Logic
8K Page
x 16 word
x 16 bit
Address
Inputs
I/O0 - I/O7
I/O8 - I/O15
A4 - A16
RAM Array
CE
WE
OE
UB
LB
Control
Logic
Functional Description
1
CE
WE
OE
UB
LB
MODE
POWER
I/O - I/O
0
15
2
H
L
L
L
L
X
X
L
X
X
X
H
X
H
High Z
High Z
Standby
Active
Active
Active
Active
Standby
Active
3
1
1
3
Data In
Data Out
High Z
X
L
L
Write
1
1
H
H
L
L
L
Read
H
X
X
Active
1. When UB and LB are in select mode (low), I/O - I/O are affected as shown. When LB only is in the select mode only I/O - I/O7
0
15
0
are affected as shown. When UB is in the select mode only I/O8 - I/O15 are affected as shown.
2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally
isolated from any external influence and disabled from exerting any influence externally.
3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.
Capacitance1
Item
Symbol
Test Condition
Min
Max
8
Unit
pF
o
C
Input Capacitance
I/O Capacitance
V
V
= 0V, f = 1 MHz, T = 25 C
IN
IN
IN
A
o
C
8
pF
= 0V, f = 1 MHz, T = 25 C
I/O
A
1. These parameters are verified in device characterization and are not 100% tested
Stock No. 23116-10 1/02
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
2
NanoAmp Solutions, Inc.
N02L163WN1A
Absolute Maximum Ratings1
Item
Symbol
Rating
Unit
V
Voltage on any pin relative to V
V
–0.3 to V +0.3
SS
IN,OUT
CC
Voltage on V Supply Relative to V
V
–0.3 to 4.5
500
V
CC
SS
CC
P
Power Dissipation
Storage Temperature
mW
D
o
T
–40 to 125
-40 to +85
C
STG
o
T
Operating Temperature
C
A
o
o
T
Soldering Temperature and Time
SOLDER
240 C, 10sec(Lead only)
C
1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operating section of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Operating Characteristics (Over Specified Temperature Range)
1
Item
Symbol
Test Conditions
Min.
Max
Unit
Typ
V
Supply Voltage
Data Retention Voltage
Input High Voltage
2.3
1.8
3.6
V
V
CC
2
V
Chip Disabled
DR
V
V
+0.3
CC
1.8
V
IH
V
Input Low Voltage
–0.3
0.6
V
IL
V
I
= 0.2mA
= -0.2mA
= 0 to V
V
–0.2
CC
Output High Voltage
V
OH
OH
V
I
OL
Output Low Voltage
0.2
0.5
0.5
V
OL
I
V
IN
Input Leakage Current
Output Leakage Current
Read/Write Operating Supply Current
µA
µA
LI
CC
I
OE = V or Chip Disabled
IH
LO
V
=3.6 V, V =V or V
CC
IN
IH
IL
I
2.0
12
4.0
mA
mA
CC1
2
Chip Enabled, I
= 0
@ 1 µs Cycle Time
OUT
V
=3.6 V, V =V or V
Read/Write Operating Supply Current
CC
IN
IH
IL
I
16.0
CC2
2
Chip Enabled, I
= 0
@ 70 ns Cycle Time
OUT
Page Mode Operating Supply Current
2
V
=3.6 V, V =V or V
CC
IN
IH
IL
@ 70ns Cycle Time (Refer to Power
I
4
mA
mA
CC3
Chip Enabled, I
= 0
Savings with Page Mode Operation
diagram)
OUT
V
=3.6 V, V =V or V
CC
IN
IH
IL
Read/Write Quiescent Operating Sup-
I
Chip Enabled, I
f = 0
= 0,
3.0
CC4
OUT
3
ply Current
V
= V or 0V
CC
IN
3
Chip Disabled
I
2.0
20
10
µA
µA
Maximum Standby Current
SB1
o
t = 85 C, VCC = 3.6 V
A
V
= 1.8V, V = V or 0
IN CC
CC
3
I
Maximum Data Retention Current
DR
o
Chip Disabled, t = 85 C
A
1. Typical values are measured at Vcc=Vcc Typ., T =25°C and are not 100% tested.
A
2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive
output capacitance expected in the actual system.
3. This device assumes a standby mode if the chip is disabled (CE high). In order to achieve low standby current all inputs must be
within 0.2 volts of either VCC or VSS
Stock No. 23116-10 1/02
3
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
N02L163WN1A
Power Savings with Page Mode Operation (WE = VIH)
Page Address (A4 - A16 )
Word Address (A0 - A3)
CE
Open page
...
Word 16
Word 1
Word 2
OE
LB, UB
Note: Page mode operation is a method of addressing the SRAM to save operating current. The internal
organization of the SRAM is optimized to allow this unique operating mode to be used as a valuable power
saving feature.
The only thing that needs to be done is to address the SRAM in a manner that the internal page is left open
and 16-bit words of data are read from the open page. By treating addresses A0-A3 as the least significant
bits and addressing the 16 words within the open page, power is reduced to the page mode value which is
considerably lower than standard operating currents for low power SRAMs.
Stock No. 23116-10 1/02
4
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
Timing Test Conditions
N02L163WN1A
Item
0.1V to 0.9 V
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
CC
CC
5ns
0.5 V
CC
CL = 30pF
o
Operating Temperature
-40 to +85 C
Timing
2.3 - 3.6 V
2.7 - 3.6 V
Item
Symbol
Units
Min.
Max.
Min.
Max.
t
Read Cycle Time
70
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
t
Address Access Time
70
70
35
35
55
55
30
30
AA
t
Chip Enable to Valid Output
Output Enable to Valid Output
Byte Select to Valid Output
Chip Enable to Low-Z output
Output Enable to Low-Z Output
Byte Select to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Byte Select Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
CO
t
OE
t
, t
LB UB
t
10
5
10
5
LZ
t
OLZ
t
, t
10
0
10
0
LBZ UBZ
t
20
20
20
20
20
20
HZ
t
0
0
OHZ
t
, t
0
0
LBHZ UBHZ
t
10
70
50
50
50
40
0
10
55
40
40
40
40
0
OH
t
WC
t
Chip Enable to End of Write
Address Valid to End of Write
Byte Select to End of Write
Write Pulse Width
CW
t
AW
t
, t
LBW UBW
t
WP
t
Address Setup Time
AS
t
Write Recovery Time
0
0
WR
t
Write to High-Z Output
20
20
WHZ
t
Data to Write Time Overlap
Data Hold from Write Time
End Write to Low-Z Output
40
0
35
0
DW
t
DH
t
10
10
ns
OW
Stock No. 23116-10 1/02
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
5
NanoAmp Solutions, Inc.
N02L163WN1A
Timing of Read Cycle (CE = OE = VIL, WE = VIH)
tRC
Address
tAA
tOH
Previous Data Valid
Data Out
Data Valid
Timing Waveform of Read Cycle (WE= VIH)
tRC
Address
tAA
tHZ
tCO
CE
tLZ
tOHZ
tOE
OE
tOLZ
tLB, UB
t
LB, UB
tLBLZ, UBLZ
t
tLBHZ, UBHZ
t
High-Z
Data Valid
Data Out
Stock No. 23116-10 1/02
6
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
N02L163WN1A
Timing Waveform of Write Cycle (WE control)
tWC
Address
tWR
tAW
tCW
CE
tLBW, tUBW
LB, UB
tWP
tAS
WE
tDW
tDH
High-Z
Data Valid
Data In
Data Out
tWHZ
tOW
High-Z
Timing Waveform of Write Cycle (CE Control)
tWC
Address
CE
tAW
tCW
tWR
tAS
tLBW, tUBW
LB, UB
WE
tWP
tDW
tDH
Data Valid
High-Z
Data In
tLZ
tWHZ
Data Out
Stock No. 23116-10 1/02
7
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
N02L163WN1A
44-Lead TSOP II Package (T44)
18.41±0.13
11.76±0.20
10.16±0.13
0.80mm REF
0.45
0.30
SEE DETAIL B
DETAIL B
1.10±0.15
0o-8o
0.20
0.00
0.80mm REF
Note:
1. All dimensions in inches (Millimeters)
2. Package dimensions exclude molding flash
Stock No. 23116-10 1/02
8
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
Ball Grid Array Package
N02L163WN1A
0.28±0.05
1.24±0.10
D
A1 BALL PAD
CORNER (3)
1. 0.35±0.05 DIA.
E
2. SEATING PLANE - Z
0.15
0.05
Z
Z
TOP VIEW
SIDE VIEW
1. DIMENSION IS MEASURED AT THE
MAXIMUM SOLDER BALL DIAMETER.
PARALLEL TO PRIMARY Z.
A1 BALL PAD
CORNER
SD
2. PRIMARY DATUM Z AND SEATING
PLANE ARE DEFINED BY THE
SPHERICAL CROWNS OF THE
SOLDER BALLS.
e
SE
3. A1 BALL PAD CORNER I.D. TO BE
MARKED BY INK.
K TYP
J TYP
e
BOTTOM VIEW
Dimensions (mm)
e = 0.75
BALL
D
E
MATRIX
TYPE
SD
SE
J
K
6±0.10
8±0.10
0.375
0.375
1.125
1.375
FULL
Stock No. 23116-10 1/02
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
9
NanoAmp Solutions, Inc.
Ordering Information
N02L163WN1A
N02L163WN1AX-XX X
I = Industrial, -40°C to 85°C
Temperature
55 = 55ns
Performance
T = 44-pin TSOP II
B = 48-ball BGA
Package Type
Note: Add -T&R following the part number for Tape and Reel. Orders will be
considered in tray if not noted.
Revision History
Revision #
Date
Change Description
01
02
03
04
05
06
07
08
09
Dec. 1999
Sept. 2000
Oct. 2000
Oct. 2000
Jan. 2001
Mar. 2001
May 2001
June 2001
Sept. 2001
Initial Preliminary Release
Modified Voltage Range and Standby Current Limits.
Added Missing Tas Parameter Specification.
Modified Standby Current Specifications.
Extensive Modification to use voltage regulator design
Modified BGA pinout, access time 70ns @ 2.7V, misc. errata
Changed access time to 55ns, modified 44-Lead TSOP Package diagram
Revised voltage range in Timing table, revised Dimensions table
Minor parametric modifications, full production release
Part number change from EM128L16, modified Overview and Features, added
Page Mode Operation diagram, revised Operating Characteristics table, Package
diagram, Functional Description table and Ordering Information diagram
10
Dec. 2001
© 2001 - 2002 Nanoamp Solutions, Inc. All rights reserved.
NanoAmp Solutions, Inc. ("NanoAmp") reserves the right to change or modify the information contained in this data sheet and the products described therein, without prior notice.
NanoAmp does not convey any license under its patent rights nor the rights of others. Charts, drawings and schedules contained in this data sheet are provided for illustration pur-
poses only and they vary depending upon specific applications.
NanoAmp makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does NanoAmp assume any liability arising out of the application
or use of any product or circuit described herein. NanoAmp does not authorize use of its products as critical components in any application in which the failure of the NanoAmp
product may be expected to result in significant injury or death, including life support systems and critical medical instruments.
Stock No. 23116-10 1/02
10
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
相关型号：
©2020 ICPDF网 联系我们和版权申明