NP34N055ILE-AZ [NEC]

Power Field-Effect Transistor, 34A I(D), 55V, 0.024ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252, MP-3Z, 3 PIN;
NP34N055ILE-AZ
型号: NP34N055ILE-AZ
厂家: NEC    NEC
描述:

Power Field-Effect Transistor, 34A I(D), 55V, 0.024ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252, MP-3Z, 3 PIN

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DATA SHEET  
MOS FIELD EFFECT TRANSISTOR  
NP34N055HLE, NP34N055ILE, NP34N055SLE  
SWITCHING  
N-CHANNEL POWER MOSFET  
DESCRIPTION  
These products are N-Channel MOS Field Effect Tran-  
sistors designed for high current switching applications.  
ORDERING INFORMATION  
PART NUMBER  
PACKAGE  
NP34N055HLE  
TO-251 (JEITA) / MP-3  
TO-252 (JEITA) / MP-3Z  
TO-252 (JEDEC) / MP-3ZK  
Note  
NP34N055ILE  
FEATURES  
Channel temperature 175 degree rated  
Super low on-state resistance  
RDS(on)1 = 18 mMAX. (VGS = 10 V, ID = 17 A)  
RDS(on)2 = 22 mMAX. (VGS = 5 V, ID = 17 A)  
Low Ciss : Ciss = 2000 pF TYP.  
Built-in gate protection diode  
NP34N055SLE  
Note Not for new design.  
(TO-251)  
(TO-252)  
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)  
Drain to Source Voltage  
VDSS  
VGSS  
ID(DC)  
ID(pulse)  
PT  
55  
V
V
A
Gate to Source Voltage  
±20  
±34  
Drain Current (DC)  
Drain Current (Pulse) Note1  
Total Power Dissipation (TA = 25°C)  
Total Power Dissipation (TC = 25°C)  
Single Avalanche Current Note2  
Single Avalanche Energy Note2  
Channel Temperature  
±136  
1.2  
A
W
W
A
PT  
88  
IAS  
34 / 27 / 10  
EAS  
11 / 72 / 100 mJ  
175 °C  
–55 to + 175 °C  
Tch  
Storage Temperature  
Tstg  
Notes 1. PW 10 µ s, Duty Cycle 1%  
2. Starting Tch = 25°C, RG = 25 Ω, VGS = 20 0 V (See Figure 4.)  
THERMAL RESISTANCE  
Channel to Case Thermal Resistance  
Channel to Ambient Thermal Resistance  
Rth(ch-C)  
1.70  
125  
°C/W  
°C/W  
Rth(ch-A)  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all products and/or types are available in every country. Please check with an NEC Electronics  
sales representative for availability and additional information.  
Document No.  
D14154EJ4V0DS00 (4th edition)  
The mark  
shows major revised points.  
Date Published July 2005 NS CP(K)  
Printed in Japan  
1999, 2005  
NP34N055HLE, NP34N055ILE, NP34N055SLE  
ELECTRICAL CHARACTERISTICS (TA = 25°C)  
CHARACTERISTICS  
Zero Gate Voltage Drain Current  
Gate Leakage Current  
SYMBOL  
TEST CONDITIONS  
MIN.  
TYP.  
MAX.  
10  
UNIT  
µA  
µA  
V
VDS = 55 V, VGS = 0 V  
IDSS  
VGS = ±20 V, VDS = 0 V  
VDS = VGS, ID = 250 µA  
VDS = 10 V, ID = 17 A  
VGS = 10 V, ID = 17 A  
VGS = 5 V, ID = 17 A  
VGS = 4.5 V, ID = 17 A  
VDS = 25 V  
±10  
2.5  
IGSS  
1.5  
9
2
19  
14  
17  
18  
2000  
250  
130  
17  
11  
57  
9
Gate to Source Threshold Voltage  
VGS(th)  
| yfs |  
RDS(on)1  
RDS(on)2  
RDS(on)3  
Ciss  
Note  
Forward Transfer Admittance  
S
Note  
18  
22  
mΩ  
mΩ  
mΩ  
pF  
pF  
pF  
ns  
Drain to Source On-state Resistance  
24  
3000  
380  
230  
37  
Input Capacitance  
Output Capacitance  
Reverse Transfer Capacitance  
Turn-on Delay Time  
Rise Time  
VGS = 0 V  
Coss  
f = 1 MHz  
Crss  
VDD = 28 V, ID = 17 A  
VGS = 10 V  
td(on)  
tr  
28  
ns  
RG = 1 Ω  
110  
23  
Turn-off Delay Time  
Fall Time  
td(off)  
tf  
ns  
ns  
VDD = 44 V, VGS = 10 V, ID = 34 A  
VDD = 44 V  
41  
23  
7
72  
Total Gate Charge  
QG1  
nC  
nC  
nC  
nC  
V
35  
QG2  
VGS = 5 V  
Gate to Source Charge  
Gate to Drain Charge  
QGS  
ID = 34 A  
12  
1.0  
42  
58  
QGD  
VF(S-D)  
trr  
Note  
IF = 34 A, VGS = 0 V  
IF = 34 A, VGS = 0 V  
di/dt = 100 A/µs  
Body Diode Forward Voltage  
Reverse Recovery Time  
Reverse Recovery Charge  
Note Pulsed  
ns  
Qrr  
nC  
TEST CIRCUIT 1 AVALANCHE CAPABILITY  
TEST CIRCUIT 2 SWITCHING TIME  
D.U.T.  
L
D.U.T.  
V
V
GS  
R
G
= 25 Ω  
50 Ω  
R
L
90%  
V
GS  
Wave Form  
V
GS  
10%  
0
R
G
PG.  
V
DD  
PG.  
GS = 20 0 V  
V
DD  
V
DS  
90%  
d(on)  
90%  
V
DS  
V
0
GS  
BVDSS  
10% 10%  
V
DS  
Wave Form  
0
I
AS  
V
DS  
ID  
τ
t
tr  
t
d(off)  
t
f
V
DD  
t
on  
t
off  
τ = 1  
µs  
Duty Cycle 1%  
Starting Tch  
TEST CIRCUIT 3 GATE CHARGE  
D.U.T.  
= 2 mA  
IG  
RL  
50 Ω  
PG.  
V
DD  
2
Data Sheet D14154EJ4V0DS  
NP34N055HLE, NP34N055ILE, NP34N055SLE  
TYPICAL CHARACTERISTICS (TA = 25°C)  
Figure2. TOTAL POWER DISSIPATION vs.  
CASE TEMPERATURE  
Figure1. DERATING FACTOR OF FORWARD BIAS  
SAFE OPERATING AREA  
140  
120  
100  
80  
100  
80  
60  
40  
20  
0
60  
40  
20  
0
0
25 50 75 100 125 150 175 200  
0
25 50 75 100 125 150 175 200  
- Case Temperature - ˚C  
T
C
TC - Case Temperature - ˚C  
Figure4. SINGLE AVALANCHE ENERGY  
DERATING FACTOR  
Figure3. FORWARD BIAS SAFE OPERATING AREA  
120  
100  
80  
60  
40  
20  
0
1000  
100  
10  
100 mJ  
72 mJ  
I
D(pulse)  
I
D(DC)  
DC  
IAS = 10 A  
27 A  
34 A  
1
11 mJ  
T
C
= 25˚C  
Single Pulse  
0.1  
0.1  
1
10  
100  
25  
50  
75  
100  
125  
150  
175  
V
DS - Drain to Source Voltage - V  
Starting Tch - Starting Channel Temperature - ˚C  
Figure5. TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH  
1000  
R
th(ch-A) = 125 ˚C/W  
th(ch-C) = 1.70 ˚C/W  
100  
10  
R
1
0.1  
0.01  
Single Pulse  
= 25˚C  
T
C
10 µ  
1 m  
10 m  
100 m  
1
10  
100  
1000  
100 µ  
PW - Pulse Width - s  
3
Data Sheet D14154EJ4V0DS  
NP34N055HLE, NP34N055ILE, NP34N055SLE  
Figure6. FORWARD TRANSFER CHARACTERISTICS  
Figure7. DRAIN CURRENT vs.  
DRAIN TO SOURCE VOLTAGE  
100  
Pulsed  
Pulsed  
200  
160  
120  
10  
T
A
= 55˚C  
25˚C  
V
GS = 10 V  
5 V  
75˚C  
150˚C  
175˚C  
1
0.1  
80  
40  
0
4.5 V  
2
0.01  
5
6
1
2
3
4
4
8
6
0
VGS - Gate to Source Voltage - V  
VDS - Drain to Source Voltage - V  
Figure9. DRAIN TO SOURCE ON-STATE RESISTANCE vs.  
GATE TO SOURCE VOLTAGE  
Figure8. FORWARD TRANSFER ADMITTANCE vs.  
DRAIN CURRENT  
100  
40  
VDS=10V  
Pulsed  
Pulsed  
35  
10  
30  
25  
20  
TA  
= 175˚C  
75˚C  
25˚C  
1
0.1  
ID = 17 A  
55˚C  
15  
10  
5
0.01  
0.01  
0
0.1  
1
10  
100  
0
5
10  
15  
20  
ID - Drain Current - A  
V
GS - Gate to Source Voltage - V  
Figure10. DRAIN TO SOURCE ON-STATE  
Figure11. GATE TO SOURCE THRESHOLD VOLTAGE vs.  
CHANNEL TEMPERATURE  
RESISTANCE vs. DRAIN CURRENT  
Pulsed  
40  
35  
30  
25  
20  
15  
10  
5
3.0  
V
GµS  
I
D
D=S =25V0  
A
2.5  
V
GS = 10 V  
5 V  
2.0  
1.5  
1.0  
4.5 V  
0.5  
0
0
1
10  
100  
1000  
50  
0
50  
100  
150  
I
D
- Drain Current - A  
Tch - Channel Temperature - ˚C  
4
Data Sheet D14154EJ4V0DS  
NP34N055HLE, NP34N055ILE, NP34N055SLE  
Figure12. DRAIN TO SOURCE ON-STATE RESISTANCE vs.  
CHANNEL TEMPERATURE  
Figure13. SOURCE TO DRAIN DIODE  
FORWARD VOLTAGE  
45  
40  
35  
30  
25  
20  
15  
10  
5
1000  
100  
Pulsed  
Pulsed  
V
GS = 10 V  
V
GS = 10 V  
5 V  
4.5 V  
10  
1
V
GS = 0 V  
I
D
= 17 A  
0.1  
0
0
1.5  
1.0  
- Source to Drain Voltage - V  
0.5  
100  
150  
0
50  
50  
V
SD  
Tch - Channel Temperature - ˚C  
Figure14. CAPACITANCE vs. DRAIN TO  
SOURCE VOLTAGE  
Figure15. SWITCHING CHARACTERISTICS  
1000  
100  
10000  
1000  
100  
V
GS = 0 V  
f = 1 MHz  
tf  
C
iss  
td(off)  
td(on)  
C
oss  
rss  
10  
1
C
tr  
0.1  
1
10  
100  
10  
0.1  
1
10  
100  
ID - Drain Current - A  
VDS - Drain to Source Voltage - V  
Figure17. DYNAMIC INPUT/OUTPUT CHARACTERISTICS  
Figure16. REVERSE RECOVERY TIME vs.  
DRAIN CURRENT  
16  
14  
12  
10  
8
80  
70  
60  
50  
40  
30  
20  
10  
0
1000  
100  
di/dt = 100 A/µs  
VGS = 0 V  
V
GS  
V
DD = 44 V  
28 V  
11 V  
6
10  
1
4
2
V
DS  
I
D
= 34 A  
35  
0
40  
0
5
10 15 20  
25 30  
0.1  
1
10  
100  
QG  
- Gate Charge - nC  
IF  
- Drain Current - A  
5
Data Sheet D14154EJ4V0DS  
NP34N055HLE, NP34N055ILE, NP34N055SLE  
PACKAGE DRAWINGS (Unit: mm)  
1) TO-251 (JEITA) / MP-3  
2) TO-252 (JEITA) / MP-3Z  
2.3 0.2  
6.5 0.2  
2.3 0.2  
6.5 0.2  
5.0 0.2  
4
0.5 0.1  
5.0 0.2  
0.5 0.1  
4
1
2
3
DESIGN  
1
2
3
1.1 0.2  
NEW  
1.1 0.2  
0.9 MAX.  
0.8 MAX.  
+0.2  
0.1  
+0.2  
0.5  
0.5  
0.1  
2.3 TYP.  
2.3 TYP.  
0.8 TYP.  
2.3 TYP.  
2.3 TYP.  
FOR  
1. Gate  
2. Drain  
3. Source  
1. Gate  
2. Drain  
3. Source  
4. Fin (Drain)  
NOT  
4. Fin (Drain)  
3) TO-252 (JEDEC) / MP-3ZK  
2.3 0.1  
6.5 0.2  
5.1 TYP.  
4.3 MIN.  
0.5 0.1  
No Plating  
EQUIVALENT CIRCUIT  
4
Drain  
1
2
3
Body  
Diode  
Gate  
No Plating  
0.76 0.12  
1.14 MAX.  
0 to 0.25  
0.5 0.1  
2.3 2.3  
Gate  
Protection  
Diode  
1.0  
Source  
1. Gate  
2. Drain  
3. Source  
4. Fin (Drain)  
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When  
this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated  
voltage may be applied to this device.  
6
Data Sheet D14154EJ4V0DS  
NP34N055HLE, NP34N055ILE, NP34N055SLE  
The information in this document is current as of July, 2005. The information is subject to change  
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or  
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all  
products and/or types are available in every country. Please check with an NEC Electronics sales  
representative for availability and additional information.  
No part of this document may be copied or reproduced in any form or by any means without the prior  
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may  
appear in this document.  
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(1)  
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M8E 02. 11-1  

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