UPA1818GR-9JG [NEC]
P-CHANNEL MOS FIELD EFFECT TRANSISTOR FOR SWITCHING; P沟道MOS场效应晶体管切换型号: | UPA1818GR-9JG |
厂家: | NEC |
描述: | P-CHANNEL MOS FIELD EFFECT TRANSISTOR FOR SWITCHING |
文件: | 总8页 (文件大小:77K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µPA1818
P-CHANNEL MOS FIELD EFFECT TRANSISTOR
FOR SWITCHING
DESCRIPTION
The µ PA1818 is a switching device which can be
PACKAGE DRAWING (Unit: mm)
driven directly by a 2.5 V power source.
8
5
This device features a low on-state resistance and
excellent switching characteristics, and is suitable for
applications such as power management of notebook
computers and so on.
1, 2, 3 :Source
:Gate
5, 6, 7, 8:Drain
1.2 MAX.
1.0±0.05
4
0.25
FEATURES
+5°
–3°
• 2.5 V drive available
3°
0.5
• Low on-state resistance
0.1±0.05
+0.15
–0.1
0.6
RDS(on)1 = 15.2 mΩ MAX. (VGS = −4.5 V, ID = −5.0 A)
RDS(on)2 = 16 mΩ MAX. (VGS = −4.0 V, ID = −5.0 A)
RDS(on)3 = 25 mΩ MAX. (VGS = −2.5 V, ID = −5.0 A)
• Built-in G-S protection diode against ESD
1
4
6.4 ±0.2
4.4 ±0.1
3.15 ±0.15
3.0 ±0.1
1.0 ±0.2
ORDERING INFORMATION
PART NUMBER
PACKAGE
µPA1818GR-9JG
Power TSSOP8
0.65
0.8 MAX.
0.1
+0.03
–0.08
0.27
0.10 M
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
EQUIVALENT CIRCUIT
Drain to Source Voltage (VGS = 0 V)
Gate to Source Voltage (VDS = 0 V)
Drain Current (DC) (TA = 25°C)
Drain Current (pulse) Note1
VDSS
VGSS
ID(DC)
ID(pulse)
PT
−20
V
V
m 12
m 10
Drain
A
Body
40
A
m
Diode
Gate
Total Power Dissipation Note2
2.0
W
°C
°C
Gate
Channel Temperature
Tch
150
Protection
Diode
Storage Temperature
Tstg
−55 to +150
Source
Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1%
2. Mounted on ceramic substrate of 5000 mm2 x 1.1 mm
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage
exceeding the rated voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
2002
Document No.
Date Published September 2002 NS CP(K)
Printed in Japan
G16254EJ1V0DS00 (1st edition)
©
µPA1818
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate Leakage Current
SYMBOL
IDSS
TEST CONDITIONS
MIN. TYP. MAX. UNIT
VDS = −20 V, VGS = 0 V
VGS = 12 V, VDS = 0 V
−1.0
µ A
µ A
V
10
IGSS
m
m
Gate Cut-off Voltage
VGS(off)
| yfs |
RDS(on)1
RDS(on)2
RDS(on)3
Ciss
VDS = −10 V, ID = −1.0 mA
VDS = −10 V, ID = −5.0 A
VGS = −4.5 V, ID = −5.0 A
VGS = −4.0 V, ID = −5.0 A
VGS = −2.5 V, ID = −5.0 A
VDS = −10 V
−0.5 −1.1 −1.5
Forward Transfer Admittance
Drain to Source On-state Resistance
12
24
12.1
12.7
18.8
2200
510
310
23
S
15.2
16
mΩ
mΩ
mΩ
pF
pF
pF
ns
25
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Coss
VGS = 0 V
Crss
f = 1.0 MHz
td(on)
tr
td(off)
tf
VDD = −10 V, ID = −5.0 A
VGS = −4.0 V
207
139
193
20
ns
Turn-off Delay Time
Fall Time
RG = 10 Ω
ns
ns
Total Gate Charge
QG
VDD = −16 V
nC
nC
nC
V
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
QGS
VGS = −4.0 V
5.0
QGD
VF(S-D)
trr
ID = −10 A
6.0
IF = 10 A, VGS = 0 V
IF = 10 A, VGS = 0 V
di/dt = 100 A / µ s
0.82
44
ns
Qrr
28
nC
TEST CIRCUIT 1 SWITCHING TIME
TEST CIRCUIT 2 GATE CHARGE
V
V
GS(−)
D.U.T.
D.U.T.
90%
VGS
V
GS
Wave Form
10%
I
G
= −2 mA
R
L
0
R
L
DS(−)
RG
PG.
V
DD
50 Ω
PG.
V
DD
90%
90%
VDS
0
10% 10%
V
DS
Wave Form
VGS (−)
0
td(on)
t
r
td(off)
tf
τ
ton
toff
τ = 1
µs
Duty Cycle ≤ 1%
2
Data Sheet G16254EJ1V0DS
µPA1818
TYPICAL CHARACTERISTICS (TA = 25°C)
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
TOTAL POWER DISSIPATION vs.
AMBIENT TEMPERATURE
120
100
80
60
40
20
0
2.5
2
Mounted on ceramic
substrate of 5000 mm2 x 1.1 mm
1.5
1
0.5
0
Mounted on FR-4 board
of 2500 mm2 x 1.6 mm
0
25
50
75
100
125
150
175
0
25
50
75
100
125
150
175
TA - Ambient Temperature - °C
TA - Ambient Temperature - °C
FORWARD BIAS SAFE OPERATING AREA
-100
D(pulse)
I
PW = 1 ms
D(DC)
I
-10
-1
10 ms
DS(on)
R
Limited
100 ms
GS
(V
−
4.5 V)
=
DC
-0.1
-0.01
Single pulse
Mounted on ceramic
substrate of 5000 mm2 x 1.1 mm
-0.1
-1
-10
-100
VDS - Drain to Source Voltage - V
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
1000
100
10
Single pulse
Mounted on FR-4 board
of 2500 mm2 x 1.6 mm
125°C/W
Mounted on ceramic
substrate of 5000 mm2 x 1.1 mm
62.5°C/W
1
0.1
1 m
10 m
100 m
1
10
100
1000
PW - Pulse Width - s
3
Data Sheet G16254EJ1V0DS
µPA1818
DRAIN CURRENT vs.
FORWARD TRANSFER CHARACTERISTICS
DRAIN TO SOURCE VOLTAGE
- 40
- 30
- 20
- 10
0
- 100
- 10
DS
−
10 V
V
=
Pulsed
GS
V
−
4.5 V
=
Pulsed
−
4.0 V
- 1
A
°
= 125 C
T
−
2.5 V
°
75 C
- 0.1
°
25 C
−
°
25 C
- 0.01
- 0.001
- 0.0001
- 0.5
- 1
- 1.5
- 2
- 2.5
0
- 0.2
- 0.4
- 0.6
- 0.8
VDS - Drain to Source Voltage - V
VGS - Gate to Source Voltage - V
GATE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
- 1.4
- 1.2
- 1
100
DS
−
10 V
V
=
DS
−
10 V
−
1.0 mA
V
=
Pulsed
D
I
=
10
1
A
T
− °
= 25 C
°
25 C
°
75 C
°
125 C
- 0.8
- 0.6
- 0.4
0.1
-50
0
50
100
150
- 0.01
- 0.1
- 1
- 10
- 100
Tch - Channel Temperature - °C
ID - Drain Current - A
DRAIN TO SOURCE ON-STATE RESISTANCE
vs. CHANNEL TEMPERATURE
DRAIN TO SOURCE ON-STATE RESISTANCE
vs.GATE TO SOURCE VOLTAGE
30
20
10
0
30
D
−
I
=
5.0 A
D
−
I
=
5.0 A
Pulsed
Pulsed
GS
V
−
2.5 V
=
20
10
0
−
4.0 V
−
4.5 V
-50
0
50
100
150
0
-2
-4
-6
-8
-10
-12
Tch – Channel Temperrature - °C
VGS - Gate to Source Voltage - V
4
Data Sheet G16254EJ1V0DS
µPA1818
DRAIN TO SOURCE ON-STATE RESISTANCE
vs. DRAIN CURRENT
DRAIN TO SOURCE ON-STATE RESISTANCE
vs. DRAIN CURRENT
30
20
10
0
30
20
10
0
GS
−
4.0 V
GS
−
= 4.5 V
V
=
V
Pulsed
Pulsed
A
T
°
= 125 C
A
T
°
= 125 C
°
75 C
75°C
25°C
-25°C
°
25 C
−
25°C
- 0.01
- 0.1
- 1
- 10
- 100
- 0.01
- 0.1
- 1
- 10
- 100
ID - Drain Current - A
ID - Drain Current - A
DRAIN TO SOURCE ON-STATE RESISTANCE
vs. DRAIN CURRENT
CAPACITANCE vs.
DRAIN TO SOURCE VOLTAGE
30
20
10
0
10000
1000
100
GS
−
2.5 V
V
=
GS
V
= 0 V
Pulsed
f = 1.0 MHz
iss
C
A
T
°
= 125 C
°
75 C
°
25 C
oss
C
−
°
25 C
rss
C
- 0.01
- 0.1
- 1
- 10
- 100
- 0.1
- 1
- 10
- 100
ID - Drain Current - A
VDS - Drain to Source Voltage - V
SWITCHING CHARACTERISTICS
SOURCE TO DRAIN DIODE FORWARD VOLTAGE
10000
1000
100
100
DD
GS
−
−
V
V
R
=
=
10 V
4.0 V
Ω
GS
V
= 0 V
Pulsed
G
= 10
10
1
f
t
d(off)
t
0.1
0.01
d(on)
t
r
t
10
- 0.01
- 0.1
- 1
- 10
0.4
0.6
0.8
1
1.2
ID - Drain Current - A
VF(S-D) - Source to Drain Voltage - V
5
Data Sheet G16254EJ1V0DS
µPA1818
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
- 5
- 4
- 3
- 2
- 1
0
D
I
−
10 A
=
DD
V
−
4.0 V
=
−
10 V
−
16 V
0
5
10
15
20
25
QG - Gate Charge - nC
6
Data Sheet G16254EJ1V0DS
µPA1818
[MEMO]
7
Data Sheet G16254EJ1V0DS
µPA1818
•
The information in this document is current as of September, 2002. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
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M8E 00. 4
相关型号:
UPA1818GR-9JG-A
Small Signal Field-Effect Transistor, 10A I(D), 20V, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, POWER, TSSOP-8
NEC
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