UPD160062N_技术文档

DATA SHEET

MOS INTEGRATED CIRCUIT

µ PD160062

420-OUTPUT TFT-LCD SOURCE DRIVER

(COMPATIBLE WITH 64-GRAY SCALE)

DESCRIPTION

The µ PD160062 is a source driver for TFT-LCDs capable of dealing with displays with 64-gray scale. Data input is

based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors

by output of 64 values γ -corrected by an internal D/A converter and 5-by-2 external power modules.

Because the output dynamic range is as large as V^SS2+0.1 V to VDD2 –0.1 V, level inversion operation of the LCD’s

common electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and

column line inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit D/A converter

circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity.

Assuring a clock frequency of 45 MHz when driving at 2.3 V, this driver is applicable to SXGA+ standard TFT-LCD

panels.

FEATURES

• CMOS level input (2.3 to 3.6 V)

• 420 outputs

• Input of 6 bits (gray scale data) by 6 dots

• Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter (R-DAC)

• Logic power supply voltage (V^DD1) : 2.3 to 3.6 V

• Driver power supply voltage (V^DD2) : 8.0 to 9.0 V

• High-speed data transfer: fCLK = 45 MHz (internal data transfer speed when operating at VDD1 = 2.3 V)

• Output dynamic range V^SS2+0.1 V to VDD2 –0.1 V

• Apply for dot-line inversion, n-line inversion and column line inversion

• Output voltage polarity inversion function (POL)

• Input data inversion function (capable of controlling by each input port) (POL21, POL22)

• Current consumption control function (LPC, HPC, Bcont)

• Slim chip

ORDERING INFORMATION

Part Number

Package

µ PD160062N-×××

TCP (TAB package)

Remark The TCP’s external shape is customized. To order the required shape, please contact one of our sales

representatives.

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with an NEC Electronics

sales representative for availability and additional information.

Document No. S16449EJ1V0DS00 (1st edition)

Date Published July 2003 NS CP(K)

Printed in Japan

2002

µ PD160062

1. BLOCK DIAGRAM

STHR

R,/L

CLK

STB

STHL

V^DD1

70-bit bidirectional shift register

VSS1

C1

C2

C69

C70

D00 to D05

D¹⁰to D15

D20 to D25

D30 to D35

Data register

D40 to D45

D50 to D55

POL21, POL22

POL

Latch

VDD2

VSS2

Level shifter

V0 to V9

D/A converter

HPC

LPC

Voltage follower output

Bcont

S1

S2

S3

S420

Remark /xxx indicates active low signal.

2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER

S

1

S

2

S

419

S

420

5

V

0

V

4

Multi-

plexer

6-bit D/A converter

V

5

V

9

POL

Data Sheet S16449EJ1V0DS

2

µ PD160062

3. PIN CONFIGURATION (µ PD160062N-xxx: TCP) (Copper Foil Surface, Face-up)

S

420

S

419

S

418

S

417

STHL

D

55

54

53

52

51

50

45

44

43

42

41

40

35

34

33

32

31

30

V

DD1

R,/L

V

9

8

7

6

5

V

DD2

SS2

Copper Foil

Surface

V

Bcont

V

4

3

2

1

0

HPC

V

SS1

LPC

CLK

STB

POL

POL21

POL22

D

25

24

23

22

21

20

15

14

13

12

11

10

05

04

03

02

01

00

S

4

3

2

1

S

STHR

Remark This figure does not specify the TCP package.

Data Sheet S16449EJ1V0DS

3

µ PD160062

4. PIN FUNCTIONS

(1/2)

Pin Symbol

S1 to S420

D00 to D05

D10 to D15

D20 to D25

D30 to D35

D40 to D45

D50 to D55

R,/L

Pin Name

I/O

Description

Driver

Output

Input

The D/A converted 64-gray-scale analog voltage is output.

Display data

The display data is input with a width of 36 bits, viz., the gray scale data (6 bits) by

6 dots (2 pixels).

D^X0: LSB, DX5: MSB

Shift direction

control

Input

The shift direction control pin of shift register. The shift directions of the shift

registers are as follows.

R,/L = H (right shift) : STHR input, S¹→ S420, STHL output

R,/L = L (left shift) : STHL input, S⁴²⁰→ S1, STHR output

STHR

STHL

CLK

Right shift start

pulse

I/O

These refer to the start pulse I/O pins when driver ICs are connected in cascade.

Fetching of display data starts when H is read at the rising edge of CLK.

R,/L = H (right shift) : STHR input, STHL output

R,/L = L (left shift) : STHL input, STHR output

Left shift start

pulse

A H level should be input as the pulse of one cycle of the clock signal.

If the start pulse input is more than 2 CLK, the first 1 CLK of the H level input is

valid.

Shift clock

Input

Refers to the shift register’s shift clock input. The display data is incorporated into

the data register at the rising edge. At the rising edge of the 70th clock after the

start pulse input, the start pulse output reaches the high level, thus becoming the

start pulse of the next-level driver. If 72 clock pulses are input after input of the

start pulse, input of display data is halted automatically. The contents of the shift

register are cleared at the STB’s rising edge.

STB

POL

Latch

Input

The contents of the data register are transferred to the latch circuit at the rising

edge. And, at the falling edge, the gray scale voltage is supplied to the driver. It is

necessary to ensure input of one pulse per horizontal period.

POL = L: The S2n–1 output uses V0 to V4 as the reference supply. The S2n output

uses V⁵to V9 as the reference supply.

Polarity input

POL = H: The S^2n–1output uses V5 to V9 as the reference supply. The S2n output

uses V⁰to V4 as the reference supply.

S²ⁿ⁻¹indicates the odd output and S2n indicates the even output. Input of the POL

signal is allowed the setup time (t^POL-STB) with respect to STB’s rising edge.

Data inversion can invert when display data is loaded.

POL21,

POL22

Data inversion

Input

POL21: Invert/not invert of display data D⁰⁰to D05, D10 to D15, D20 to D25

POL22: Invert/not invert of display data D³⁰to D35, D40 to D45, D50 to D55

POL21, POL22 = H: Data inversion loads display data after inverting it.

POL21, POL22 = L: Data inversion does not invert input data.

Controls the write function of the driver section by digitally controlling the bypass

current of the output amplifier. Refer to 9. CURRENT CONSUMPTION

CONTROL FUNCTION for details.

LPC

HPC

Bcont

Low power control

High power control

Bias control

Input

This pin is pulled up to the V^DD1power supply inside the IC.

This pin can be used to finely control the bias current inside the output amplifier.

Refer to 9. CURRENT CONSUMPTION CONTROL FUNCTION for details.

When this fine-control function is not required, leave this pin open.

Data Sheet S16449EJ1V0DS

4

µ PD160062

(2/2)

Pin Symbol

V0 to V9

Pin Name

I/O

Description

γ -corrected power

−

Input the γ -corrected power supplies from outside by using operational amplifier.

supplies

Make sure to maintain the following relationships. During the gray scale voltage

output, be sure to keep the gray scale level power supply at a constant level.

V^DD2−0.1 V ≥ V0 > V1 > V2 > V3 > V4 ≥ 0.5 VDD2

0.5 V^DD2≥ V5 > V6 > V7 > V8 > V9 ≥ VSS2 +0.1 V

VDD1

VDD2

VSS1

VSS2

Logic power supply

Driver power supply

Logic ground

−

2.3 to 3.6 V

8.0 to 9.0 V

Grounding

Driver ground

Cautions 1. The power start sequence must be V^DD1, logic input, and VDD2 & V0 to V9 in that order. Reverse

this sequence to shut down.

2. To stabilize the supply voltage, please be sure to insert a 0.1 µF bypass capacitor between

V

DD1-VSS1 and VDD2-VSS2. Furthermore, for increased precision of the D/A converter, insertion of a

bypass capacitor of about 0.01 µF is also recommended between the γ -corrected power supply

terminals (V , V , V , ···, V

0

1

2

9) and VSS2.

Data Sheet S16449EJ1V0DS

5

µ PD160062

5. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE

The µ PD160062 incorporates a 6-bit D/A converter whose odd output pins and even output pins output respectively

gray scale voltages of differing polarity with respect to the LCD’s counter electrode (common electrode) voltage. The

D/A converter consists of ladder resistors and switches.

The ladder resistors (r0 to r62) are designed so that the ratio of LCD panel γ -compensated voltages to V0’ to V63’

and V⁰” to V63” is almost equivalent. For the 2 sets of five γ -compensated power supplies, V0 to V4 and V5 to V9,

respectively, input gray scale voltages of the same polarity with respect to the common voltage. When fine gray scale

voltage precision is not necessary, there is no need to connect a voltage follower circuit to the γ -compensated power

supplies V¹to V3 and V6 to V8.

Figure 5−1 shows the relationship between the driving voltages such as liquid-crystal driving voltages VDD2 and VSS2,

common electrode potential V^COM, and γ -corrected voltages V0 to V9 and the input data. Be sure to maintain the

voltage relationships of

V^DD2−0.1 V ≥ V0 > V1 > V2 > V3 > V4 ≥ 0.5 VDD2

0.5 V^DD2≥ V5 > V6 > V7 > V8 > V9 ≥ VSS2 +0.1 V

Figures 5−2 shows γ -corrected power supply voltage and ladder resistors ratio and figure 5−3 shows the relationship

between the input data and the output voltage.

Figure 5−1. Relationship between Input Data and γ -corrected Power Supplies

VDD2

0.1 V

Split interval

16

V0

V1

16

15

V

2

3

V

V4

V

COM

0.5 V^DD2

V5

15

V

6

16

V

7

V8

16

V9

0.1 V

VSS2

00

10

20

30

3F

Input data (HEX)

Data Sheet S16449EJ1V0DS

6

µ PD160062

Figure 5−2. γ -corrected Voltages and Ladder Resistors Ratio

V

5

V

63’’

V

0

V

0

’

rn

Ratio 1

8.00

7.50

7.00

6.50

6.00

5.50

5.00

4.00

3.50

3.00

2.50

2.00

1.50

1.00

1.50

2.00

2.50

3.00

5.00

8.00

Ratio 2

0.0505

0.0473

0.0442

0.0410

0.0379

0.0347

0.0315

0.0252

0.0221

0.0189

0.0158

0.0126

0.0095

0.0063

0.0095

0.0126

0.0158

0.0189

0.0315

0.0505

Value (

Ω

)

r0

544

510

476

442

408

374

340

272

238

204

170

136

102

68

r0

r1

r2

r3

r62

r61

r60

r59

r1

V1

V62’’

V61’’

V60’’

r2

r3

r4

V

2

3

’

r5

r6

V

r7

r8

r9

r10

r11

r12

r13

r14

r15

r16

r17

r18

r19

r20

r21

r22

r23

r24

r25

r26

r27

r28

r29

r30

r31

r32

r33

r34

r35

r36

r37

r38

r39

r40

r41

r42

r43

r44

r45

r46

r47

r48

r49

r50

r51

r52

r53

r54

r55

r56

r57

r58

r59

r60

r61

r62

r49

r48

r47

r46

r14

r15

r16

r17

V15

V16

V17

’

V

49’’

48’’

47’’

V1

V6

68

r46

r47

r48

r49

r17

r16

r15

r14

68

V47

’

V

17’’

16’’

68

V48

’

V

3

V8

68

V49

’

V15’’

68

102

136

170

204

340

544

10778

68

r60

r2

r1

r0

V2

’’

V

61

’

r61

r62

62

’

V1

V9

V4

63

V0’’

Total resistance

Minimum resistance value

Remark The resistance ratio1 is a relative ratio in the case of setting the minimum resistance value to 1.

The resistance ratio2 is a relative ratio in the case of setting the total resistance to 1.

Caution There is no connection between V4 and V5 terminal in the chip.

Data Sheet S16449EJ1V0DS

7

µ PD160062

Figure 5−3. Relationship between Input Data and Output Voltage (POL21, POL22 = L)

(Output Voltage 1) VDD2 −0.1 V ≥ V0 > V1 > V2 > V3 > V4 ≥ 0.5 VDD2

(Output Voltage 2) 0.5 V^DD2≥ V5 > V6 > V7 > V8 > V9 ≥ VSS2 +0.1 V

Input Data

00H

01H

02H

03H

04H

05H

06H

07H

08H

09H

0AH

0BH

0CH

0DH

0EH

0FH

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H

1AH

1BH

1CH

1DH

1EH

1FH

20H

21H

22H

23H

24H

25H

26H

27H

28H

29H

2AH

2BH

2CH

2DH

2EH

2FH

30H

31H

32H

33H

34H

35H

36H

37H

38H

39H

3AH

3BH

3CH

3DH

3EH

3FH

Output Voltage 1

Output Voltage 2

V_0'

V_1'

V_2'

V_3'

V_4'

V_5'

V_6'

V_7'

V_8'

V_9'

V

V_0''

V

V⁰+(V -V )×

V¹+(V⁰-V¹)×

4930

4420

3944

3502

3094

2720

2346

2006

1666

1394

1122

884

/

5474 V_1''V⁹+(V -V )×

5474 V_2''V⁹+(V⁸-V⁹)×

5474 V_3''V⁹+(V⁸-V⁹)×

5474 V_4''V⁹+(V⁸-V⁹)×

544

1054

1530

1972

2380

2754

3128

3468

3808

4080

4352

4590

4828

5066

5270

/

5474

V¹

1

+(V⁰

0

-V¹

1

)×

5474 V_5''V⁹

9

+(V⁸

8

-V⁹

9

)×

V

1+(V

0

-V

1

)×

5474 V_6''

5474 V_7''

V

9+(V

8

-V

9

)×

+(V -V )×

V¹+(V⁰-V¹)×

5474 V_8''V⁹+(V⁸-V⁹)×

5474 V_9''V⁹+(V⁸-V⁹)×

5474 V_10''V⁹+(V⁸-V⁹)×

V¹+(V⁰-V¹)×

V_10'V¹+(V⁰-V¹)×

V_11'V¹

1

+(V⁰

0

-V¹

1

)×

5474 V_11''V⁹

9

+(V⁸

8

-V⁹

9

)×

V_12'

V_13'

V

1+(V

0-V

1

)×

5474 V_12''

5474 V_13''

V

9+(V

8-V

9

)×

+(V -V )×

V_14'V¹+(V⁰-V¹)×

646

+(V -V )×

5474 V_14''V⁹+(V⁸-V⁹)×

408

V_15'V¹+(V⁰

0

-V¹

1

)×

204

5474 V_15''V⁹+(V⁸

8

-V⁹

9

)×

V_16'V¹

V_16''V⁹

V_17'V¹

2

+(V

1

-V

2

)×

1666

1496

1326

1156

1020

884

748

646

544

442

340

272

204

136

68

/

1870 V_17''V⁸

8

+(V

7

-V

8

)×

204

374

/

1870

V_18'

V_19'

V

2+(V

1

2)×

1870 V_18''

1870 V_19''

V

8+(V

7

8)×

+(V -V )×

544

V_20'V²+(V¹-V²)×

V_21'V²+(V¹-V²)×

V_22'V²+(V¹-V²)×

V_23'V²+(V¹-V²)×

1870 V_20''V⁸+(V⁷-V⁸)×

1870 V_21''V⁸+(V⁷-V⁸)×

1870 V_22''V⁸+(V⁷-V⁸)×

1870 V_23''V⁸+(V⁷-V⁸)×

714

850

986

1122

1224

1326

1428

1530

1598

1666

1734

1802

V_24'V²

2

+(V¹

1

-V²

2

)×

1870 V_24''V⁸

8

+(V⁷

7

-V⁸

8

)×

V_25'

V

+(V -V )×

1870 V_25''

V

+(V -V )×

V_26'V²+(V¹-V²)×

V_27'V²+(V¹-V²)×

V_28'V²+(V¹-V²)×

V_29'V²+(V¹-V²)×

1870 V_26''V⁸+(V⁷-V⁸)×

1870 V_27''V⁸+(V⁷-V⁸)×

1870 V_28''V⁸+(V⁷-V⁸)×

1870 V_29''V⁸+(V⁷-V⁸)×

V_30'V²

2

+(V¹

1

-V²

2

)×

1870 V_30''V⁸

8

+(V⁷

7

-V⁸

8

)×

V_31'

V

+(V

1

-V

2

)×

1870 V_31''

V

+(V

7

-V

8

)×

V_32'V²

V_32''V⁸

V_33'V²+(V -V )×

V_34'V³+(V²-V³)×

V_35'V³+(V²-V³)×

1020

952

884

816

748

680

612

544

476

408

340

272

204

136

68

/

1088 V_33''V⁷+(V -V )×

1088 V_34''V⁷+(V⁶-V⁷)×

1088 V_35''V⁷+(V⁶-V⁷)×

68

136

204

272

340

408

476

544

612

680

748

816

884

952

1020

/

1088

V_36'V³

3

+(V²

2

-V³

3

)×

1088 V_36''V⁷

7

+(V⁶

6

-V⁷

7

)×

V_37'

V

+(V -V )×

1088 V_37''

V

+(V -V )×

V_38'V³+(V²-V³)×

V_39'V³+(V²-V³)×

V_40'V³+(V²-V³)×

V_41'V³+(V²-V³)×

1088 V_38''V⁷+(V⁶-V⁷)×

1088 V_39''V⁷+(V⁶-V⁷)×

1088 V_40''V⁷+(V⁶-V⁷)×

1088 V_41''V⁷+(V⁶-V⁷)×

V_42'V³

3

+(V²

2

-V³

3

)×

1088 V_42''V⁷

7

+(V⁶

6

-V⁷

7

)×

V_43'

V_44'

V

3+(V

2-V

3)×

1088 V_43''

1088 V_44''

V

7+(V

6-V

7)×

+(V -V )×

V_45'V³+(V²-V³)×

1088 V_45''V⁷+(V⁶-V⁷)×

V_46'V³+(V²-V³)×

1088 V_46''V⁷+(V⁶-V⁷)×

V_47'V³+(V²

2

-V³

3

)×

1088 V_47''V⁷+(V⁶

6

-V⁷

7

)×

V_48'V³

3

V_48''V⁷

6

V_49'

V_50'

V

4+(V

3

-V

4

)×

2278

2210

2142

2074

2006

1904

1802

1700

1564

1428

1258

1088

884

/

2346 V_49''

2346 V_50''

V

6+(V

5

-V

6

)×

68

136

/

2346

+(V -V )×

V_51'V⁴+(V³-V⁴)×

V_52'V⁴+(V³-V⁴)×

V_53'V⁴+(V³-V⁴)×

2346 V_51''V⁶+(V⁵-V⁶)×

2346 V_52''V⁶+(V⁵-V⁶)×

2346 V_53''V⁶+(V⁵-V⁶)×

204

272

340

V_54'V⁴

4

+(V³

3

-V⁴

4

)×

2346 V_54''V⁶

6

+(V⁵

5

-V⁶

6

)×

442

V_55'

V_56'

V

4+(V

3-V

4)×

2346 V_55''

2346 V_56''

V

6+(V

5-V

6)×

544

+(V -V )×

646

V_57'V⁴+(V³-V⁴)×

V_58'V⁴+(V³-V⁴)×

V_59'V⁴+(V³-V⁴)×

V_60'V⁴+(V³-V⁴)×

2346 V_57''V⁶+(V⁵-V⁶)×

2346 V_58''V⁶+(V⁵-V⁶)×

2346 V_59''V⁶+(V⁵-V⁶)×

2346 V_60''V⁶+(V⁵-V⁶)×

782

918

1088

1258

1462

1802

V_61'V⁴

4

+(V³

3

-V⁴

4

)×

2346 V_61''V⁶

6

+(V⁵

5

-V⁶

6

)×

V_62'

V

+(V

3

-V

4

)×

544

2346 V_62''

V

+(V

5

-V

6

)×

V_63'V⁴

4

V_63''V⁶

5

Data Sheet S16449EJ1V0DS

8

µ PD160062

6. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN

Data format: 6 bits × 2 RGBs (6 dots)

Input width: 36 bits (2-pixel data)

(1) R,/L = H (right shift)

Output

Data

S1

S2

S3

S4

xxx

S419

S420

D00 to D05

D10 to D15

D20 to D25

D30 to D35

D40 to D45

D50 to D55

(2) R,/L = L (left shift)

Output

Data

S1

S2

S3

S4

xxx

S419

S420

D00 to D05

D10 to D15

D20 to D25

D30 to D35

D40 to D45

D50 to D55

Note

S²ⁿ⁻¹

S2n

POL

L

V0 to V4

V5 to V9

V0 to V4

H

Note S2n−1 (odd output), S2n (even output)

7. RELATIONSHIP BETWEEN STB, POL AND OUTPUT WAVEFORM

The output voltage is written to the LCD panel synchronized with the STB falling edge.

STB

POL

S

2n-1

Selected voltage V

0

to V

4

Selected voltage V

5

to V

9

Selected voltage V

0

to V

4

S

2n

Selected voltage V

0

to V

4

Selected voltage V

5

to V

9

Selected voltage V

5

to V

9

Hi-Z

Remark Hi-Z: High impedance

Data Sheet S16449EJ1V0DS

9

µ PD160062

8. RELATIONSHIP BETWEEN STB, CLK AND OUTPUT WAVEFORM

The output voltage is written to the LCD panel synchronized with the STB falling edge.

Figure 8−1. Output Circuit Block Diagram

Output Amp.

−

DAC

+

S

n

SW1

(V

X)

V

AMP(IN)

Figure 8−2. Output Circuit Timing Waveform

[1] [2]

CLK

(External input)

STB

(External input)

SW1: ON

SW1: OFF

SW1: ON

VAMP(IN)

S

n

(VOUT: External output)

Output

Hi-Z

Remarks 1. STB = L: SW1 = ON, STB = H: SW1 = OFF

2. STB = H is acknowledged at timing [1] .

3. The display data latch is completed at timing [2] and the input voltage (V^AMP(IN): gray-scale level

voltage) of the output amplifier changes.

Data Sheet S16449EJ1V0DS

10

µ PD160062

9. CURRENT CONSUMPTION CONTROL FUNCTION

The µ PD160062 has a power control function which can switch the bias current of the output amplifier between four

levels and a bias control function (Bcont) which can be used to finely control the bias current.

< Power control function (LPC, HPC) >

The bias current of the output amplifier can be switched between four levels using LPC (Low Power Control) pins

and HPC (High Power Control) pins (show in below table).

Power Mode

LPC

HPC

High

L

Middle

Normal

Low

H or open

L

H or open

Following graph shows the relationship between each power modes and bias current.

High

Middle

Normal

Low

6.00

7.00

8.00

9.00

VDD2

Remark This relationship is founded on results of simulation and don’t assuring a characteristics of this product.

Data Sheet S16449EJ1V0DS

11

µ PD160062

< Bias Current Control Function (Bcont) >

It is possible to fine-control the current consumption by using the bias current control function (Bcont pin). When

using this function, connect this pin to the stabilized ground potential (V^SS2) via an external resistor (REXT). When not

using this function, leave this pin open.

Figure 9−1. Bias Current Control Function (Bcont)

HPC

LPC

H/L

µ

PD160062

B

cont

R^EXT

VSS2

Refer to the table below for the percentage of current regulation when using the bias current control function.

Table 9−1. Current Consumption Regulation Percentage Compared to Normal Mode (V^DD1= 3.3 V, VDD2 = 8.7 V)

Current Consumption Regulation Percentage (%)

REXT (kΩ)

LPC = L

100

LPC = H/open

∞ (Open)

65

70

80

85

50

20

10

110

115

120

Remark The above current consumption regulation percentages are founded on

results of simulation and don’t assuring a characteristics of this product.

Caution Because the power and bias-current control functions control the bias current in the output amplifier

and regulate the over-all current consumption of the driver IC, when this occurs, the characteristics

of the output amplifier will simultaneously change. Therefore, when using these functions, be sure

to sufficiently evaluate the picture quality.

Data Sheet S16449EJ1V0DS

12

µ PD160062

10. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (T^A= 25°C, VSS1 = VSS2 = 0 V)

Parameter

Symbol

Rating

Unit

V

−0.5 to +4.0

Logic Part Supply Voltage

Driver Part Supply Voltage

Logic Part Input Voltage

Driver Part Input Voltage

Logic Part Output Voltage

Driver Part Output Voltage

Operating Ambient Temperature

Storage Temperature

VDD1

−0.5 to +10.0

−0.5 to V^DD1+0.5

−0.5 to V^DD2+0.5

−0.5 to V^DD1+0.5

−0.5 to V^DD2+0.5

−10 to +75

VDD2

VI1

V

VI2

V

VO1

VO2

TA

V

°C

−55 to +125

Tstg

Caution Product qualify may suffer if the absolute maximum rating is exceeded even momentarily for any

parameter/ That is, the absolute maximum ratings are rated values at which the product is on the

verge of suffering physical damage, and therefore the product must be used under conditions that

ensure that the absolute maximum ratings are not exceeded.

Recommended Operating Range (T^A= −10 to +75°C, VSS1 = VSS2 = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

8.5

MAX.

Unit

V

Logic Part Supply Voltage

Driver Part Supply Voltage

High-Level Input Voltage

Low-Level Input Voltage

γ -corrected Voltage

VDD1

2.3

8.0

3.6

9.0

VDD2

VIH

V

0.7 VDD1

0

VDD1

V

VIL

0.3 VDD1

V^DD2−0.1

V

V0 to V4

V⁵to V9

VO

0.5 VDD2

VSS2 +0.1

V

0.5 VDD2

V

V^DD2−0.1

Driver Part Output Voltage

Maximum Clock Frequency

V

V^DD1= 2.3 V

fCLK

45

MHz

Data Sheet S16449EJ1V0DS

13

µ PD160062

Electrical Characteristics (TA = −10 to +75°C, VDD1 = 2.3 to 3.6 V, VDD2 = 8.0 to 9.0 V, VSS1 = VSS2 = 0 V,

unless otherwise specified, power mode = normal, Bcont = open.)

Parameter

Symbol

IIL

Conditions

MIN.

V^DD1−0.1

5.4

TYP.

MAX.

1.0

Unit

µA

V

Input Leak Current

High-Level Output Voltage

Low-Level Output Voltage

γ -corrected Resistance

VOH

VOL

STHR (STHL), IOH = 0 mA

STHR (STHL), IOL = 0 mA

VDD2 = 8.5 V, V0 to V4 = V5 to V9 =

4.0 V

0.1

V

kΩ

Rγ

10.8

21.6

Note

−30

µA

V^X= 7.0 V, VOUT = 6.5 V

Driver Output Current

IVOH

I^VOL

∆V^O

Note

V^X= 1.0 V, VOUT = 1.5 V

30

7

2

20

15

Output Voltage Deviation

TA = 25°C, VDD1 = 3.3 V,

VDD2 = 8.5 V,

mV

∆V^P–P

IDD1

Output swing difference

deviation

mV

mA

VOUT = 2.0 V, 4.25 V, 6.5 V

Logic Part Dynamic Current

Consumption

VDD1

1.0

3.0

6.5

Driver Part Dynamic

Current Consumption

IDD2

VDD2, with no load

Note VX refers to the output voltage of analog output pins S1 to S420. VOUT refers to the voltage applied to analog

output pins S¹to S420.

Cautions 1. fSTB = 64 kHz, fCLK = 40 MHz

2. The TYP. values refer to an all black or all white input pattern. The MAX. value refers to the

measured values in the dot checkerboard input pattern.

3. Refers to the current consumption per driver when cascades are connected under the

assumption of SXGA+ single-sided mounting (10 units).

Switching Characteristics (TA = −10 to +75°C, VDD1 = 2.3 to 3.6 V, VDD2 = 8.0 to 9.0 V, VSS1 = VSS2 = 0 V,

unless otherwise specified, power mode = normal, Bcont = open.)

Parameter

Symbol

Conditions

CL = 10 pF

MIN.

TYP.

10

2.5

5

MAX.

Unit

Start Pulse Delay Time

Driver Output Delay Time

tPLH1

20

5

ns

µs

pF

C^L= 75 pF, RL = 5 kΩ

tPLH2

tPLH3

tPHL2

tPHL3

CI1

8

2.5

5

8

Input Capacitance

STHR (STHL) excluded,

TA = 25°C

10

C^I2

STHR (STHL), TA = 25°C

10

pF

Data Sheet S16449EJ1V0DS

14

µ PD160062

Timing Requirement (TA = −10 to +75°C, VDD1 = 2.3 to 3.6 V, VSS1 = 0 V, tr = tf = 5.0 ns)

Parameter

Clock Pulse Width

Symbol

Conditions

MIN.

22

4

TYP.

MAX.

Unit

ns

PWCLK

Clock Pulse High Period

Clock Pulse Low Period

Data Setup Time

PWCLK(H)

PWCLK(L)

tSETUP1

tHOLD1

ns

4

ns

4

ns

Data Hold Time

0

ns

Start Pulse Setup Time

Start Pulse Hold Time

POL21, POL22 Setup Time

POL21, POL22 Hold Time

STB Pulse Width

tSETUP2

tHOLD2

4

ns

0

ns

tSETUP3

tHOLD3

4

ns

0

ns

PWSTB

tLDT

2

CLK

ns

Last Data Timing

2

CLK ↑ → STB ↑

CLK-STB Time

tCLK-STB

tSTB-CLK

tSTB-STH

tPOL-STB

tSTB-POL

6

STB ↑ → CLK ↑

STB-CLK Time

9

ns

STB ↑ → STHR(STHL) ↑

POL ↑ or ↓ → STB ↑

STB ↓ → POL ↓ or ↑

Time Between STB and Start Pulse

POL-STB Time

2

CLK

ns

–5

6

STB-POL Time

ns

Remark Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1.

Data Sheet S16449EJ1V0DS

15

µ PD160062

11. RECOMMENDED MOUNTING CONDITIONS

The following conditions must be met for soldering conditions of the µ PD160062.

For more details, refer to the Semiconductor Device Mount Manual

(http://www.necel.com/pkg/en/mount/index.html).

Please consult with our sales offices in case other soldering process is used, or in case the soldering is done under

different conditions.

µ PD160062N-×××: TCP (TAB package)

Mounting Condition

Thermocompression

Mounting Method

Soldering

Condition

Heating tool 300 to 350°C, heating for 2 to 3 seconds, pressure 100g (per

solder)

ACF

Temporary bonding 70 to 100°C, pressure 3 to 8 kg/cm², time 3 to 5 seconds.

Real bonding 165 to 180°C, pressure 25 to 45 kg/cm², time 30 to 40 seconds.

(When using the anisotropy conductive film SUMIZAC1003 of Sumitomo

Bakelite, Ltd.)

(Adhesive Conductive

Film)

Caution To find out the detailed conditions for packaging the ACF part, please contact the ACF

manufacturing company. Be sure to avoid using two or more packaging methods at a time.

Data Sheet S16449EJ1V0DS

17

µ PD160062

NOTES FOR CMOS DEVICES

1

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

2

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V^DDor GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

3

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

Data Sheet S16449EJ1V0DS

18


型号：	UPD160062N
厂家：	NEC
描述：	420-OUTPUT TFT-LCD SOURCE DRIVER 420输出TFT -LCD源极驱动器驱动器输出元件 CD
文件：	总18页 (文件大小：212K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UPD160062N [NEC]

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