UPD160081 [ETC]
UPD160081 Data Sheet | Data Sheet[06/2003] ; UPD160081数据表|数据表[ 06/2003 ]\n型号: | UPD160081 |
厂家: | ETC |
描述: | UPD160081 Data Sheet | Data Sheet[06/2003]
|
文件: | 总24页 (文件大小:236K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD160081
384-OUTPUT TFT-LCD SOURCE DRIVER
(COMPATIBLE WITH 64-GRAY SCALES)
DESCRIPTION
The µ PD160081 is a source driver for TFT-LCDs capable of dealing with displays with 64-gray scales. Data input is
based on digital input configured as 6 bits by 3 dots (1 pixel) with double clock edge, which can realize a full-color
display of 260,000 colors by output of 64 values γ -corrected by an internal D/A converter and 7-by-2 external power
modules. Because the output dynamic range is as large as VSS2 + 0.1 V to VDD2 – 0.1 V, level inversion operation of the
LCD’s common electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and
column line inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit D/A converter
circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. Assuring
a clock frequency of 83 MHz when driving at 3.0 V, this driver is applicable to XGA-standard (1024 x 768), SXGA-
standard (1280 x 1024) TFT-LCD panels.
FEATURES
• RSDSTM (Reduced Swing Differential Signaling) interface
• 384 outputs
• Input of 6 bits (gradation data) by 3 dots with double clock edge sampling
• Capable of outputting 64 values by means of 7-by-2 external power modules (14 units) and a D/A converter
• Logic power supply voltage (VDD1): 2.7 to 3.6 V
• Driver power supply voltage (VDD2): 10.0 to 12.5 V
• Output dynamic range: VSS2 + 0.1 V to VDD2 – 0.1 V
• High-speed data transfer: fCLK = 83MHz MAX. (Internal data transfer speed when operating at VDD1 = 3.0 V)
• Apply for dot-line inversion, n-line inversion and column line inversion
• Output Voltage polarity inversion function (POL)
• Input data inversion function (INV)
Remark RSDSTM is a trademark of National Semiconductor Corporation.
★
ORDERING INFORMATION
Part Number
Package
Chip
★
µPD160081P
★
Remark Purchasing the above chip entail the exchange of documents such as a separate memorandum or product
quality, so please contact one of our sales representatives.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
The mark ★ shows major revised points.
Document No. S15923EJ2V0DS00 (2nd edition)
Date Published June 2003 CP(K)
Printed in Japan
2003
µ PD160081
★
1. BLOCK DIAGRAM
STHR
STHL
R,/L
CLKP, CLKN
STB
128-bit bidirectional shift register
C127 C128
VDD1
VSS1
C1 C2 C3
D
00P
10P
20P
-
D
02P
12P
22P
,
D
00N
10N
20N
-
D
02N
D
-
D
,
D
-
D
12N
D
-D
,
D
-D
22N
Data register
INV
Latch
POL
V
V
DD2
SS2
Level shifter
V0-
V
13
D/A converter
Voltage follower output
S
1
S
2
S
3
S
384
TEST
SHIELDING
PASS1, PASS3,
PASS4
DUMMY (140, 141)
RPI1
RPI2
RPO1
RPO2
Line repair Amp.
Remark /xxx indicates active low signal.
2
Data Sheet S15923EJ2V0DS
µ PD160081
2. PIN CONFIGURATION
Chip size: (1.43 ± 0.02) x (17.31 ± 0.02) mm2
1
561
171
Output side
Input side
Y
X
2
170
3
Data Sheet S15923EJ2V0DS
µ PD160081
Table 2−1. Pad Coordinate (1/7)
Pad No.
1
Pin Name
DUMMY42
DUMMY41
DUMMY40
PASS4
PASS3
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
RPI2
X Position
-8517.0
-8517.0
-8447.0
-8135.0
-8055.0
-7975.0
-7895.0
-7815.0
-7735.0
-7655.0
-7575.0
-7495.0
-7415.0
-7335.0
-7225.0
-7175.0
-7095.0
-7015.0
-6935.0
-6855.0
-6775.0
-6695.0
-6615.0
-6535.0
-6455.0
-6375.0
-6295.0
-6145.0
-6075.0
-5925.0
-5855.0
-5705.0
-5555.0
-5485.0
-5335.0
-5185.0
-5115.0
-4965.0
-4895.0
-4745.0
-4675.0
-4525.0
-4455.0
-4305.0
-4235.0
-4085.0
-4015.0
-3865.0
-3795.0
-3645.0
-3575.0
-3425.0
-3355.0
-3205.0
-3135.0
-2985.0
-2915.0
-2765.0
-2695.0
-2545.0
-2475.0
-2405.0
-2335.0
-2265.0
-2115.0
-2045.0
-1895.0
-1825.0
-1675.0
-1605.0
-1455.0
-1385.0
-1235.0
-1165.0
-1015.0
-945.0
Y Position
600.0
X Pitch
Y Pitch
X Size
Y Size
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
43
43
43
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
2
3
4
5
6
7
8
9
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
0.0
1200.0
70.0
312.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
150.0
70.0
150.0
70.0
150.0
150.0
70.0
150.0
150.0
70.0
150.0
70.0
150.0
70.0
150.0
70.0
150.0
70.0
150.0
70.0
150.0
70.0
150.0
70.0
150.0
70.0
150.0
70.0
150.0
70.0
150.0
70.0
150.0
70.0
70.0
70.0
70.0
150.0
70.0
150.0
70.0
150.0
70.0
150.0
70.0
150.0
70.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
RPI2
RPO2
RPO2
SHIELDING
STHL
STHL
SHIELDING
D22P
D22P
D22N
D22N
D21P
D21P
D21N
D21N
D20P
D20P
D20N
D20N
D12P
D12P
D12N
D12N
D11P
D11P
D11N
D11N
D10P
D10P
D10N
D10N
VDD1
VDD1
VDD1
VDD1
VDD1
R,/L
R,/L
V13
V13
V12
V12
V11
V11
V10
V10
V9
V9
V8
150.0
70.0
150.0
70.0
-795.0
-725.0
-575.0
V8
V7
150.0
80
V7
-505.0
-600.0
70.0
0.0
50
50
4
Data Sheet S15923EJ2V0DS
µ PD160081
Table 2−1. Pad Coordinate (2/7)
Pad No.
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
Pin Name
VDD2
VDD2
VDD2
VDD2
VDD2
VSS2
VSS2
VSS2
VSS2
VSS2
V6
X Position
-355.0
-285.0
-215.0
-145.0
-75.0
Y Position
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
X Pitch
150.0
Y Pitch
0.0
X Size
Y Size
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
70.0
70.0
70.0
70.0
150.0
70.0
70.0
70.0
70.0
150.0
70.0
150.0
70.0
150.0
70.0
150.0
70.0
150.0
70.0
150.0
70.0
150.0
70.0
150.0
70.0
70.0
70.0
70.0
150.0
70.0
150.0
70.0
150.0
70.0
150.0
70.0
150.0
70.0
150.0
70.0
150.0
70.0
150.0
70.0
150.0
70.0
150.0
70.0
150.0
70.0
150.0
150.0
70.0
150.0
150.0
70.0
150.0
70.0
150.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
75.0
145.0
215.0
285.0
355.0
505.0
575.0
725.0
V6
V5
V5
V4
V4
V3
V3
V2
V2
V1
V1
V0
795.0
945.0
1015.0
1165.0
1235.0
1385.0
1455.0
1605.0
1675.0
1825.0
1895.0
2045.0
2115.0
2185.0
2255.0
2325.0
2475.0
2545.0
2695.0
2765.0
2915.0
2985.0
3135.0
3205.0
3355.0
3425.0
3575.0
3645.0
3795.0
3865.0
4015.0
4085.0
4235.0
4305.0
4455.0
4525.0
4675.0
4745.0
4895.0
5045.0
5115.0
5265.0
5415.0
5485.0
5635.0
5705.0
5855.0
5935.0
6015.0
6095.0
6175.0
6255.0
6335.0
6415.0
6495.0
6575.0
6655.0
6735.0
6815.0
6895.0
6975.0
7055.0
7135.0
7215.0
7295.0
7375.0
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
V0
VSS1
VSS1
VSS1
VSS1
VSS1
CLKP
CLKP
CLKN
CLKN
STB
STB
POL
POL
INV
INV
D02P
D02P
D02N
D02N
D01P
D01P
D01N
D01N
D00P
D00P
D00N
D00N
SHIELDING
STHR
STHR
SHIELDING
RPO1
RPO1
TEST
TEST
DUMMY*
DUMMY*
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
160
DUMMY
7455.0
-600.0
80.0
0.0
50
50
5
Data Sheet S15923EJ2V0DS
µ PD160081
Table 2−1. Pad Coordinate (3/7)
Pad No.
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
Pin Name
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
PASS1
DUMMY4
DUMMY3
DUMMY2
DUMMY1
PASS1
RPI1
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
X Position
7535.0
7615.0
7695.0
7775.0
7855.0
7935.0
8015.0
8095.0
8447.0
8517.0
8517.0
8447.0
8320.5
8277.5
8234.5
8191.5
8148.5
8105.5
8062.5
8019.5
7976.5
7933.5
7890.5
7847.5
7804.5
7761.5
7718.5
7675.5
7632.5
7589.5
7546.5
7503.5
7460.5
7417.5
7374.5
7331.5
7288.5
7245.5
7202.5
7159.5
7116.5
7073.5
7030.5
6987.5
6944.5
6901.5
6858.5
6815.5
6772.5
6729.5
6686.5
6643.5
6600.5
6557.5
6514.5
6471.5
6428.5
6385.5
6342.5
6299.5
6256.5
6213.5
6170.5
6127.5
6084.5
6041.5
5998.5
5955.5
5912.5
5869.5
5826.5
5783.5
5740.5
5697.5
5654.5
5611.5
5568.5
5525.5
5482.5
Y Position
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
-600.0
600.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
X Pitch
80.0
Y Pitch
0.0
X Size
Y Size
50
50
50
50
50
50
50
50
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
80.0
80.0
80.0
80.0
80.0
80.0
80.0
352.0
70.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
1200.0
0.0
70.0
126.5
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
S50
S51
S52
S53
S54
S55
S56
S57
S58
S59
S60
S61
S62
S63
S64
S65
240
S66
5439.5
600.0
43.0
80.0
43
50
6
Data Sheet S15923EJ2V0DS
µ PD160081
Table 2−1. Pad Coordinate (4/7)
Pad No.
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
Pin Name
S67
S68
S69
S70
S71
S72
S73
S74
S75
S76
S77
S78
S79
S80
S81
S82
S83
S84
S85
S86
S87
S88
S89
S90
S91
S92
S93
S94
S95
S96
S97
S98
X Position
5396.5
5353.5
5310.0
5267.5
5224.5
5181.5
5138.5
5095.5
5052.5
5009.5
4966.5
4923.5
4880.5
4837.5
4794.5
4751.5
4708.5
4665.5
4622.5
4579.5
4536.5
4493.5
4450.5
4407.5
4364.5
4321.5
4278.5
4235.5
4192.5
4149.5
4106.5
4063.5
4020.5
3977.5
3934.5
3891.5
3848.5
3805.5
3762.5
3719.5
3676.5
3633.5
3590.5
3547.5
3504.5
3461.5
3418.5
3375.5
3332.5
3289.5
3246.5
3203.5
3160.5
3117.5
3074.5
3031.5
2988.5
2945.5
2902.5
2859.5
2816.5
2773.5
2730.5
2687.5
2644.5
2601.5
2558.5
2515.5
2472.5
2429.5
2386.5
2343.5
2300.5
2257.5
2214.5
2171.5
2128.5
2085.5
2042.5
Y Position
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
X Pitch
43.0
Y Pitch
80.0
X Size
Y Size
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
S99
S100
S101
S102
S103
S104
S105
S106
S107
S108
S109
S110
S111
S112
S113
S114
S115
S116
S117
S118
S119
S120
S121
S122
S123
S124
S125
S126
S127
S128
S129
S130
S131
S132
S133
S134
S135
S136
S137
S138
S139
S140
S141
S142
S143
S144
S145
320
S146
1999.5
600.0
43.0
80.0
43
50
7
Data Sheet S15923EJ2V0DS
µ PD160081
Table 2−1. Pad Coordinate (5/7)
Pad No.
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
Pin Name
S147
S148
S149
S150
S151
S152
S153
S154
S155
S156
S157
S158
S159
S160
S161
S162
S163
S164
S165
S166
S167
S168
S169
S170
S171
S172
S173
S174
S175
S176
S177
S178
S179
S180
S181
S182
S183
S184
S185
S186
S187
S188
S189
S190
S191
S192
S193
S194
S195
S196
S197
S198
S199
S200
S201
S202
S203
S204
S205
S206
S207
S208
S209
S210
S211
S212
S213
S214
S215
S216
S217
S218
S219
S220
S221
S222
S223
S224
S225
X Position
1956.5
1913.5
1870.5
1827.5
1784.5
1741.5
1698.5
1655.5
1612.5
1569.5
1526.5
1483.5
1440.5
1397.5
1354.5
1311.5
1268.5
1225.5
1182.5
1139.5
1096.5
1053.5
1010.5
967.5
Y Position
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
X Pitch
43.0
Y Pitch
80.0
X Size
Y Size
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
924.5
881.5
838.5
795.5
752.5
709.5
666.5
623.5
580.5
537.5
494.5
451.5
408.5
365.5
322.2
279.5
236.5
193.5
150.5
107.5
64.5
21.5
-21.5
-64.5
-107.5
-150.5
-193.5
-236.5
-279.5
-322.5
-365.5
-408.5
-451.5
-494.5
-537.5
-580.5
-623.5
-666.5
-709.5
-752.5
-795.5
-838.5
-881.5
-924.5
-967.5
-1010.5
-1053.5
-1096.5
-1139.5
-1182.5
-1225.5
-1268.5
-1311.5
-1354.5
-1397.5
400
S226
-1440.5
600.0
43.0
80.0
43
50
8
Data Sheet S15923EJ2V0DS
µ PD160081
Table 2−1. Pad Coordinate (6/7)
Pad No.
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
549
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
Pin Name
S227
S228
S229
S230
S231
S232
S233
S234
S235
S236
S237
S238
S239
S240
S241
S242
S243
S244
S245
S246
S247
S248
S249
S250
S251
S252
S253
S254
S255
S256
S257
S258
S259
S260
S261
S262
S263
S264
S265
S266
S267
S268
S269
S270
S271
S272
S273
S274
S275
S276
S277
S278
S279
S280
S281
S282
S283
S284
S285
S286
S287
S288
S289
S290
S291
S292
S293
S294
S295
S296
S297
S298
S299
S300
S301
S302
S303
S304
S305
X Position
-1483.5
-1526.5
-1569.5
-1612.5
-1655.5
-1698.5
-1741.5
-1784.5
-1827.5
-1870.5
-1913.5
-1956.5
-1999.5
-2042.5
-2085.5
-2128.5
-2171.5
-2214.5
-2257.5
-2300.5
-2343.5
-2386.5
-2429.5
-2472.5
-2515.5
-2558.5
-2601.5
-2644.5
-2687.5
-2730.5
-2773.5
-2816.5
-2859.5
-2902.5
-2945.5
-2988.5
3031.5
Y Position
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
X Pitch
43.0
Y Pitch
80.0
X Size
Y Size
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
-3074.5
-3117.5
-3160.5
-3203.5
-3246.5
-3289.5
-3332.5
-3375.5
-3418.5
-3461.5
-3504.5
-3547.5
-3590.5
-3633.5
-3676.5
-3719.5
-3762.5
-3805.5
-3848.5
-3891.5
-3934.5
-3977.5
-4020.5
-4063.5
-4106.5
-4149.5
-4192.5
-4235.5
-4278.5
-4321.5
-4364.5
-4407.5
-4450.5
-4493.5
-4536.5
-4579.5
-4622.5
-4665.5
-4708.5
-4751.5
-4794.5
-4837.5
480
S306
-4880.5
600.0
43.0
80.0
43
50
9
Data Sheet S15923EJ2V0DS
µ PD160081
Table 2−1. Pad Coordinate (7/7)
Pad No.
Pin Name
X Position
Y Position
X Pitch
43.0
Y Pitch
80.0
X Size
Y Size
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
S307
S308
S309
S310
S311
S312
S313
S314
S315
S316
S317
S318
S319
S320
S321
S322
S323
S324
S325
S326
S327
S328
S329
S330
S331
S332
S333
S334
S335
S336
S337
S338
S339
S340
S341
S342
S343
S344
S345
S346
S347
S348
S349
S350
S351
S352
S353
S354
S355
S356
S357
S358
S359
S360
S361
S362
S363
S364
S365
S366
S367
S368
S369
S370
S371
S372
S373
S374
S375
S376
S377
S378
S379
S380
S381
S382
S383
S384
PASS3
PASS4
DUMMY43
-4923.5
-4966.5
-5009.5
-5052.5
-5095.5
-5138.5
-5181.5
-5224.5
-5267.5
-5310.5
-5353.5
-5396.5
-5439.5
-5482.5
-5525.5
-5568.5
-5611.5
-5654.5
-5697.5
-5740.5
-5783.5
-5826.5
-5869.5
-5912.5
-5955.5
-5998.5
-6041.5
-6084.5
-6127.5
-6170.5
-6213.5
-6256.5
-6299.5
-6342.5
-6385.5
-6428.5
-6471.5
-6514.5
-6557.5
-6600.5
-6643.5
-6686.5
-6729.5
-6772.5
-6815.5
-6858.5
-6901.5
-6944.5
-6987.5
-7030.5
-7073.5
-7116.5
-7159.5
-7202.5
-7245.5
-7288.5
-7331.5
-7374.5
-7417.5
-7460.5
-7503.5
-7546.5
-7589.5
-7632.5
-7675.5
-7718.5
-7761.5
-7804.5
-7847.5
-7890.5
-7933.5
-7976.5
-8019.5
-8062.5
-8105.5
-8148.5
-8191.5
-8234.5
-8277.5
-8320.5
-8447.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
520.0
600.0
600.0
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
126.5
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
0.0
8312.0
-324.0
-324.0
Alignment mark 1
Alignment mark 2
-8312.0
10
Data Sheet S15923EJ2V0DS
µ PD160081
★
3. PIN FUNCTIONS
(1/2)
Pin Symbol
Pin Name
Pad No.
175 to 558
120 to 131
I/O
Description
S1 to S384
Driver
Output The D/A converted 64-gray-scale analog voltage is output.
D00P to D02P,
D00N to D02N
D10P to D12P,
D10N to D12N
D20P to D22P,
D20N to D22N
R,/L
Display data
Input The display data is input with a width of 9 bits by double edge, viz., the gray
(RSDS) scale data (6 bits) by 3 dots (1 pixel).
48 to 59
36 to 47
65, 66
Shift direction
control
Input These refer to the start pulse input/output pins when driver ICs are
(CMOS) connected in cascade. The shift directions of the shift registers are as
follows.
R,/L = H (VDD1 level): STHR input, S1 → S384, STHL output
R,/L = L (VSS1 level): STHL input, S384→ S1, STHR output
STHR
STHL
Right shift start
pulse
133, 134
33, 34
I/O
(CMOS) R,/L = L (VSS1 level): Becomes the start pulse output pin.
I/O R,/L = H (VDD1 level): Becomes the start pulse output pin.
R,/L = H (VDD1 level): Becomes the start pulse input pin.
Left shift start
pulse
(CMOS) R,/L = L (VSS1 level): Becomes the start pulse input pin.
CLKP,
CLKN
Shift clock
110 to 113
Input Refers to the shift register’s shift clock input. The display data is
(RSDS) incorporated into the data register at both of rising and falling edge.
At the falling edge of the 128th clock after the start pulse input, the start pulse
output reaches the high level, thus becoming the start pulse of the next-level
driver.
STB
POL
Latch
114, 115
116, 117
Input The contents of the data register are transferred to the latch circuit at the
(CMOS) rising edge. The gray scale voltage is supplied to the driver at the falling
edge of STB.
It is necessary to ensure input of one pulse per horizontal period.
Input POL = H (VDD1 level): The S2n–1 output uses V0-V6 as the reference supply.
Polarity
(CMOS)
The S2n output uses V7-V13 as the reference supply.
POL = L (VSS1 level): The S2n–1 output uses V7-V13 as the reference supply.
The S2n output uses V0-V6 as the reference supply.
S2n-1 indicates the odd output: and S2n indicates the even output. Input of the
POL signal is allowed the setup time (tPOL-STB) with respect to STB’s rising
edge.
INV
Data inversion
118, 119
Input Data inversion can invert when display data is loaded.
(CMOS) INV = H (VDD1 level): Data inversion loads display data after inverting it.
INV = L (VSS1 level): Data inversion does not invert input data.
Please input DC signal. For details, refer to 6. DATA INVERSION.
Input The structure of the line-repair amplifier is the same as that of the analog
output.
RPI1, RPI2
RPO1, RPO2
TEST
Line-repair Amp. 28, 29, 174
RPI1 (RPI2) → impedance changed → RPO1 (RPO2)
Output
30, 31, 136,
137
Test
138, 139
Input TEST = H or open: Normal operation mode
TEST = L: Test mode
This pin is pulled up to power supply VDD1 inside IC.
I/O Input and output short-circuit inside IC.
PASS1,
PASS3,
PASS4
Pass
168, 173,
5, 559,
4, 560
SHIELDING Shielding
32, 35, 132,
135
Input This pin is pulled down to power supply VSS2 inside IC.
11
Data Sheet S15923EJ2V0DS
µ PD160081
(2/2)
Pin Symbol
Pin Name
Pad No.
I/O
Description
DUMMY*
(140, 141)
Driving ability 140, 141
control
Input DUMMY = H or open: Normal mode
DUMMY = L: Higher driving ability mode
This pin is pulled up to power supply VDD1 inside IC.
V0-V13
γ -corrected
67 to 80,
−
Input the γ -corrected power supplies from outside by using operational
amplifier. Make sure to maintain the following relationships. During the
gray scale voltage output, be sure to keep the gray scale level power
supply at a constant level.
power supplies 91 to 104
VDD2 – 0.1 V ≥ V0 > V1 > V2 > V3 > V4 > V5 > V6 ≥ 0.5 VDD2
0.5 VDD2 ≥ V7 > V8 > V9 > V10 > V11 >V12 > V13 ≥ VSS2 + 0.1 V
2.7 to 3.6 V
VDD1D/A
VDD2
Logic power
Supply
60 to 64
−
−
Driver power 81 to 85
supply
10.0 to 12.5 V
VSS1D/A
VSS2
Logic ground 105 to 109
Driver ground 86 to 90
−
−
−
Grounding
Grounding
Dummy pin
DUMMY
Dummy
6 to 27,
142 to 167
169 to 172
DUMMY1 to
DUMMY4
DUMMY40 to
DUMMY42
DUMMY43
1 to 3
561
Cautions 1. The power on sequence must be VDD1, logic input, and VDD2 and V0-V13 in that order. Reverse this
sequence to shut down (Simultaneous power application to VDD2 and V0-V13 is possible.).
2. To stabilize the supply voltage, please be sure to insert a 0.1 µ F bypass capacitor between
VDD1-VSS1 and VDD2-VSS2. Furthermore, for increased precision of the D/A converter, insertion of
a bypass capacitor of about 0.01 µF is also advised between the γ -corrected power supply pins
(V0, V1, V2, ···,V13) and VSS2.
12
Data Sheet S15923EJ2V0DS
µ PD160081
4. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE
The µPD160081 incorporates a 6-bit D/A converter whose odd output pins and even output pins output respectively
gray scale voltages of differing polarity with respect to the LCD’s counter electrode (common electrode) voltage. The
D/A converter consists of ladder resistors and switches.
The ladder resistors (r0 to r62) are designed so that the ratio of LCD panel γ -compensated voltages to V0’-V63’ and
V0”-V63” is almost equivalent, therefore, each resistance value indicates figure 4−2. For the 2 sets of 7 γ -
compensated power supplies, V0-V6 and V7-V13, respectively, input gray scale voltages of the same polarity with
respect to the common voltage.
Figure 4−1 shows the relationship between the driving voltages such as liquid-crystal driving voltages VDD2, VSS2 and
0.5 VDD2, and γ -corrected voltages V0-V13 and the input data. Be sure to maintain the voltage relationships below.
VDD2 – 0.1 V ≥ V
0
>V
1
>V
2
>V
3
>V
4
>V5
>V
6
≥ 0.5 VDD2
0.5 VDD2 ≥ V
7
>V
8
> V
9
>V10 >V11 >V12 >V13 ≥ VSS2 + 0.1 V
Figures 4−2 shows γ -corrected voltages and ladder resistors ratio and figure 4−3 shows relationship between the
input data (DxxP) and the output voltage (INV = L).
Figure 4−1. Relationship Between Input Data and γ -corrected Power Supply
V
DD2
0.1 V
Split interval
V
0
V
1
16
V
2
16
16
15
V
V
3
4
V
5
6
V
0.5 VDD2
V
7
V
8
15
V
9
16
16
V
V
10
11
16
V
12
V
13
0.1 V
V
SS2
01
3E
3F
00
10
20
30
Input data (HEX)
13
Data Sheet S15923EJ2V0DS
µ PD160081
★
Figure 4−2. γ -corrected Voltages and Ladder Resistors Ratio
rn
Ratio (1) Ratio (2) Resistance Value
V
7
V
63’’
V
0
1
V
V
0
’
’
r0
8.00
7.50
7.00
6.50
6.00
5.50
5.50
5.00
5.00
4.00
4.00
3.50
3.50
3.50
3.00
3.00
3.00
2.50
2.50
2.50
2.00
2.00
2.00
1.50
1.50
1.50
1.50
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.50
1.50
1.50
2.00
2.00
2.50
2.50
3.00
5.00
8.00
0.0505
0.0473
0.0442
0.0410
0.0379
0.0347
0.0347
0.0315
0.0315
0.0252
0.0252
0.0221
0.0221
0.0221
0.0189
0.0189
0.0189
0.0158
0.0158
0.0158
0.0126
0.0126
0.0126
0.0095
0.0095
0.0095
0.0095
0.0063
0.0063
0.0063
0.0063
0.0063
0.0063
0.0063
0.0063
0.0063
0.0063
0.0063
0.0063
0.0063
0.0063
0.0063
0.0063
0.0063
0.0063
0.0063
0.0063
0.0063
0.0063
0.0063
0.0063
0.0063
0.0063
0.0095
0.0095
0.0095
0.0126
0.0126
0.0158
0.0158
0.0189
0.0315
0.0505
800
750
700
650
600
550
550
500
500
400
400
350
350
350
300
300
300
250
250
250
200
200
200
150
150
150
150
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
150
150
150
200
200
250
250
300
500
800
r1
r2
r0
r1
r2
r3
r62
r61
r60
r59
V
1
V
8
V62’’
V61’’
V60’’
r3
r4
r5
V
V
2
’
’
r6
r7
3
r8
r9
r10
r11
r12
r13
r14
r15
r16
r17
r18
r19
r20
r21
r22
r23
r24
r25
r26
r27
r28
r29
r30
r31
r32
r33
r34
r35
r36
r37
r38
r39
r40
r41
r42
r43
r44
r45
r46
r47
r48
r49
r50
r51
r52
r53
r54
r55
r56
r57
r58
r59
r60
r61
r62
r49
r48
r47
r14
r15
r16
r17
V
V
V
15
16
17
’
’
’
V
V
V
49’’
48’’
47’’
V
2
V
9
r46
r46
r47
r48
r49
r17
r16
r15
r14
V
47
’
V
17’’
16’’
V
48
’
V
V
4
V11
V49
’
V15’’
r60
r2
r1
r0
V
2
’’
V
V
V
61
’
r61
r62
Total resistance
Minimum resistance value
15850
100
62
’
’
V
5
V
12
13
V1
’’
V
V
6
63
V0’’
Remark The resistance ratio 1 is a relative ratio in the case of setting the minimum resistance value to 1.
The resistance ratio 2 is a relative ratio in the case of setting the total resistance to 1.
Caution There is no connection between V4 and V5 pin inside the IC.
14
Data Sheet S15923EJ2V0DS
µ PD160081
★
Figure 4−3. Relationship between Input Data (DxxP) and Output Voltage (INV = L)
(Output voltage 1) VDD2 – 0.1 V ≥ V0 > V1 > V2 > V3 > V4 > V5 > V6 ≥ 0.5 VDD2
(Output voltage 2) 0.5 VDD2 ≥ V7 > V8 > V9 > V10 > V11 > V12 > V13 ≥ VSS2 + 0.1 V
Input Data
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
Output Voltage 1
Output Voltage 2
V1' V1
V1'' V12
V2' V2+(V1-V2)× 6500 /
V3' V2+(V1-V2)× 5800 /
V4' V2+(V1-V2)× 5150 /
V5' V2+(V1-V2)× 4550 /
V6' V2+(V1-V2)× 4000 /
V7' V2+(V1-V2)× 3450 /
V8' V2+(V1-V2)× 2950 /
V9' V2+(V1-V2)× 2450 /
V10' V2+(V1-V2)× 2050 /
V11' V2+(V1-V2)× 1650 /
V12' V2+(V1-V2)× 1300 /
7250 V2'' V12+(V11-V12)× 750
7250 V3'' V12+(V11-V12)× 1450
7250 V4'' V12+(V11-V12)× 2100
7250 V5'' V12+(V11-V12)× 2700
7250 V6'' V12+(V11-V12)× 3250
7250 V7'' V12+(V11-V12)× 3800
7250 V8'' V12+(V11-V12)× 4300
7250 V9'' V12+(V11-V12)× 4800
7250 V10'' V12+(V11-V12)× 5200
7250 V11'' V12+(V11-V12)× 5600
7250 V12'' V12+(V11-V12)× 5950
7250 V13'' V12+(V11-V12)× 6300
7250 V14'' V12+(V11-V12)× 6650
7250 V15'' V12+(V11-V12)× 6950
V16'' V11
2750 V17'' V11+(V10-V11)× 300
2750 V18'' V11+(V10-V11)× 550
2750 V19'' V11+(V10-V11)× 800
2750 V20'' V11+(V10-V11)× 1050
2750 V21'' V11+(V10-V11)× 1250
2750 V22'' V11+(V10-V11)× 1450
2750 V23'' V11+(V10-V11)× 1650
2750 V24'' V11+(V10-V11)× 1800
2750 V25'' V11+(V10-V11)× 1950
2750 V26'' V11+(V10-V11)× 2100
2750 V27'' V11+(V10-V11)× 2250
2750 V28'' V11+(V10-V11)× 2350
2750 V29'' V11+(V10-V11)× 2450
2750 V30'' V11+(V10-V11)× 2550
2750 V31'' V11+(V10-V11)× 2650
V32'' V10
/
/
/
/
/
/
/
/
/
/
/
/
/
/
7250
7250
7250
7250
7250
7250
7250
7250
7250
7250
7250
7250
7250
7250
V13' V2+(V1-V2)×
V14' V2+(V1-V2)×
V15' V2+(V1-V2)×
V16' V2
950 /
600 /
300 /
V17' V3+(V2-V3)× 2450 /
V18' V3+(V2-V3)× 2200 /
V19' V3+(V2-V3)× 1950 /
V20' V3+(V2-V3)× 1700 /
V21' V3+(V2-V3)× 1500 /
V22' V3+(V2-V3)× 1300 /
V23' V3+(V2-V3)× 1100 /
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
2750
2750
2750
2750
2750
2750
2750
2750
2750
2750
2750
2750
2750
2750
2750
V24' V3+(V2-V3)×
V25' V3+(V2-V3)×
V26' V3+(V2-V3)×
V27' V3+(V2-V3)×
V28' V3+(V2-V3)×
V29' V3+(V2-V3)×
V30' V3+(V2-V3)×
V31' V3+(V2-V3)×
V32' V3
950 /
800 /
650 /
500 /
400 /
300 /
200 /
100 /
V33' V4+(V3-V4)× 1500 /
V34' V4+(V3-V4)× 1400 /
V35' V4+(V3-V4)× 1300 /
V36' V4+(V3-V4)× 1200 /
V37' V4+(V3-V4)× 1100 /
V38' V4+(V3-V4)× 1000 /
1600 V33'' V10+(V9-V10)×
1600 V34'' V10+(V9-V10)×
1600 V35'' V10+(V9-V10)×
1600 V36'' V10+(V9-V10)×
1600 V37'' V10+(V9-V10)×
1600 V38'' V10+(V9-V10)×
1600 V39'' V10+(V9-V10)×
1600 V40'' V10+(V9-V10)×
1600 V41'' V10+(V9-V10)×
1600 V42'' V10+(V9-V10)×
1600 V43'' V10+(V9-V10)×
1600 V44'' V10+(V9-V10)×
1600 V45'' V10+(V9-V10)×
1600 V46'' V10+(V9-V10)×
1600 V47'' V10+(V9-V10)×
V48'' V9
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
1400
1500
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
1600
1600
1600
1600
1600
1600
1600
1600
1600
1600
1600
1600
1600
1600
1600
V39' V4+(V3-V4)×
V40' V4+(V3-V4)×
V41' V4+(V3-V4)×
V42' V4+(V3-V4)×
V43' V4+(V3-V4)×
V44' V4+(V3-V4)×
V45' V4+(V3-V4)×
V46' V4+(V3-V4)×
V47' V4+(V3-V4)×
V48' V4
900 /
800 /
700 /
600 /
500 /
400 /
300 /
200 /
100 /
V49' V5+(V4-V5)× 2550 /
V50' V5+(V4-V5)× 2450 /
V51' V5+(V4-V5)× 2350 /
V52' V5+(V4-V5)× 2250 /
V53' V5+(V4-V5)× 2150 /
V54' V5+(V4-V5)× 2000 /
V55' V5+(V4-V5)× 1850 /
V56' V5+(V4-V5)× 1700 /
V57' V5+(V4-V5)× 1500 /
V58' V5+(V4-V5)× 1300 /
V59' V5+(V4-V5)× 1050 /
2650 V49'' V9+(V8-V9)×
2650 V50'' V9+(V8-V9)×
2650 V51'' V9+(V8-V9)×
2650 V52'' V9+(V8-V9)×
2650 V53'' V9+(V8-V9)×
2650 V54'' V9+(V8-V9)×
2650 V55'' V9+(V8-V9)×
2650 V56'' V9+(V8-V9)×
2650 V57'' V9+(V8-V9)×
2650 V58'' V9+(V8-V9)×
2650 V59'' V9+(V8-V9)×
2650 V60'' V9+(V8-V9)×
2650 V61'' V9+(V8-V9)×
V62'' V8
100
200
300
400
500
650
800
950
1150
1350
1600
1850
2150
/
/
/
/
/
/
/
/
/
/
/
/
/
2650
2650
2650
2650
2650
2650
2650
2650
2650
2650
2650
2650
2650
V60' V5+(V4-V5)×
V61' V5+(V4-V5)×
V62' V5
800 /
500 /
3FH
V63' V6
V63'' V7
15
Data Sheet S15923EJ2V0DS
µ PD160081
5. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN
Data format: 6 bits × 1 RGB (3 dots)
Input width: 9 bits x double edge (1-pixel data)
(1) R,/L = H (Right shift)
Output
Data
S1
S2
S3
S4
!!!
!!!
S383
S384
D00P-D02P,
D00N-D02N
D10P-D12P,
D10N-D12N
D20P-D22P,
D20N-D22N
D00P-D02P,
D00N-D02N
D10P-D12P,
D10N-D12N
D20P-D22P,
D20N-D22N
(2) R,/L = L (Left shift)
Output
Data
S1
S2
S3
S4
!!!
!!!
S383
S384
D00P-D02P,
D00N-D02N
D10P-D12P,
D10N-D12N
D20P-D22P,
D20N-D22N
D00P-D02P,
D00N-D02N
D10P-D12P,
D10N-D12N
D20P-D22P,
D20N-D22N
Note
Note
S2n
POL
L
S2n–1
V0-V6
V7-V13
V0-V6
H
V7-V13
Note S2n-1 (Odd output), S2n (Even output)
6. DATA INVERSION (INV)
INV controls the internal data inversion. When INV = H, the internal data is inverted and CLK is not inverted (See the
figure as below). Using the INV pin, the RSDS data bus interface can be changed.
µPD160081
µPD160081
D00N
D00N
D00P
D00N
D00P
D00N
D00P
D22N
D00P
D22N
D22P
D22N
D22P
D22N
D22P
D22P
CLKP
CLKN
CLKP
CLKN
INV = H
INV = L
16
Data Sheet S15923EJ2V0DS
µ PD160081
7. TIMING CHART AND RELATIONSHIP BETWEEN 6-BIT DATA AND DATA BUS LINE
tHOLD2
tHOLD1
tHOLD1
tSETUP2
tSETUP1
tSETUP1
CLK
(Differential)
STHR
D00
S1
S1
S4
S4
S7
S7
(Differential)
(0)
(1)
(0)
(1)
(0)
(1)
D01
S1
S1
S4
S4
S7
S7
(Differential)
(2)
(3)
(2)
(3)
(2)
(3)
D02
S1
S1
S4
S4
S7
S7
(4)
(5)
(4)
(5)
(4)
(5)
(Differential)
D10
S2
S2
S5
S5
S8
S8
(0)
(1)
(0)
(1)
(0)
(1)
(Differential)
D11
S2
S2
S5
S5
S8
S8
(2)
(3)
(2)
(3)
(2)
(3)
(Differential)
S2
S2
S5
S5
S8
S8
D12
(4)
(5)
(4)
(5)
(4)
(5)
(Differential)
D20
S3
S3
S6
S6
S9
S9
(Differential)
(0)
(1)
(0)
(1)
(0)
(1)
D21
S3
S3
S6
S6
S9
S9
(2)
(3)
(2)
(3)
(2)
(3)
(Differential)
D22
S3
S3
S6
S6
S9
S9
(4)
(5)
(4)
(5)
(4)
(5)
(Differential)
Remark Sn(0): LSB, Sn(5): MSB
17
Data Sheet S15923EJ2V0DS
µ PD160081
8. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = +25 °C, VSS1 = VSS2 = 0 V)
Parameter
Symbol
Ratings
Unit
V
Logic Part Supply Voltage
Driver Part Supply Voltage
Logic Part Input Voltage
Driver Part Input Voltage
Logic Part Output Voltage
Driver Part Output Voltage
Operating Ambient Temperature
Storage Temperature
VDD1
–0.5 to +4.0
VDD2
VI1
–0.5 to +14.0
–0.5 to VDD1 + 0.5
–0.3 to VDD2 + 0.3
–0.5 to VDD1 + 0.5
–0.5 to VDD2 + 0.5
–10 to +75
V
V
VI2
V
VO1
VO2
TA
V
V
°C
°C
Tstg
–55 to +125
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Range (TA = –10 to +75 °C, VSS1 = VSS2 = 0 V, DUMMY (140, 141) = H or open)
Parameter
Symbol
Conditions
MIN.
2.7
TYP.
3.3
MAX.
3.6
Unit
V
Logic Part Supply Voltage
Driver Part Supply Voltage
High-Level Input Voltage 1
Low-Level Input Voltage 1
High-Level Input Voltage 2
(Differential :VRSDSP-VRSDSN)
Low-Level Input Voltage 2
(Differential :VRSDSP-VRSDSN)
Common Mode Input
VDD1
VDD2
VIH1
VIL1
10.0
0.7 VDD1
0
11.0
12.5
V
VDD1
V
0.3 VDD1
V
VCM = 1.2 V Note
VIH2
CLK, Dxx
+100
+200
mV
(x = 0 to 2)
VIL2
–200
–100
mV
V
Note
VOFF = 200 mVp-p
VCM
0.5
1.4
Voltage
Driver Part Output Voltage
γ -Corrected Voltage
VO
0.1
0.5 VDD2
0.1
VDD2 − 0.1
VDD2 – 0.1
0.5 VDD2
65
V
V
VNv
V0-V6
V7-V13
V
Clock Frequency
fCLK
VDD1 = 2.7 V
VDD1 = 3.0 V
MHz
MHz
83
Note
V
RSDSN
(CLKN, DxxN)
VCMRSDS
VRSDSP
(CLKP, DxxP)
VIH2 = +100 mV MIN.
0 V
IL2 = −100 mV MAX.
V
RSDSP-VRSDSN
(Differential CLK, DATA)
V
Internal Logic
L
H
L
H
VCM = (VCLKP + VCLKN) /2 or = (VDxxP + VDxxN) /2 (x = 0 to 2)
Remark
VDIFF = (VCLKP − VCLKN) or = (VDxxP − VDxxN) (x = 0 to 2)
18
Data Sheet S15923EJ2V0DS
µ PD160081
Electrical Characteristics (TA = –10 to +75 °C, VDD1 = 2.7 to 3.6 V, VDD2 = 10.0 to 12.0 V , VSS1 = VSS2 = 0 V,
DUMMY (140, 141) = H or open)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
± 1.0
Unit
µA
V
Input Leak Current
IIL
High-Level Output Voltage VOH
Low-Level Output Voltage VOL
STHR (STHL), IOH = 0 mA
STHR (STHL), IOL = 0 mA
VDD2 = 11.0 V, TA = 25°C,
V0-V6 = V7-V13 = 5.0 V
VDD1 − 0.4
VSS1
VDD1
VSS1 + 0.4
20.605
V
γ -Corrected Resistance
Rγ
11.095
15.850
kΩ
Driver Output Current
IVOH
IVOL
∆VO
S1 to S384,
VX = 9.0 V, VOUT = 8.5 VNote1
VX = 1.0 V, VOUT = 1.5 VNote1
−140
130
± 9
−90
µA
µA
RPO1, RPO2
80
Output Voltage Deviation
VO = 1.5 V to VDD2 – 1.5 V.
VO = 0.1 to 1.5 V,
± 20
± 45
mV
mV
± 25
VO = VDD2 – 1.5 V to VDD2 – 0.1 V
VO = 1.5 V to VDD2 – 1.5 V
VO = 0.1 to 1.5 V,
Output Swing Voltage
Difference Deviation
∆Vp–p1
∆Vp–p2
± 4
± 15
± 40
mV
mV
± 20
VO = VDD2 – 1.5 V to VDD2 – 0.1 V
Output Swing Voltage
Average Deviation
AVO
IDD11
IDD12
IDD2
Input data: 20H
± 3
± 7.5
mV
mA
mA
mA
Note2, 3
VDD1
3.0 Note2
2.5 Note4
8.5 Note6
5.0 Note3
4.5 Note5
17.0 Note7
Logic Part Dynamic
Current Consumption 1
Logic Part Dynamic
Current Consumption 2
Driver Part Dynamic
Current Consumption
Note2, 3
VDD1,
VDD2 , with no load,
RPI1, RPI2 are not floating
Notes 1. VX refers to the otuput voltage of analog output pins S1 to S384.
VOUT refers to the voltage applied to analog output pins S1 to S384
.
2. fCLKP, fCLKN = 83 MHz, fSTB = 1/15 µs, test pattern = dot inversion, TA = 25°C, VDD1 = 3.0 V
3. fCLKP, fCLKN = 83 MHz, fSTB = 1/15 µs, test pattern = dot inversion, VDD1 = 3.6 V
4. fCLKP, fCLKN = 65 MHz, fSTB = 1/20 µs, test pattern = dot inversion, TA = 25°C, VDD1 = 3.0V
5. fCLKP, fCLKN = 65 MHz, fSTB = 1/20 µs, test pattern = dot inversion, VDD1 = 3.6 V
6. fCLKP, fCLKN = 83 MHz, fSTB = 1/15 µs, test pattern = dot inversion, TA = 25°C, VDD2 = 11.0 V
7. fCLKP, fCLKN = 83 MHz, fSTB = 1/15 µs, test pattern = dot inversion, VDD2 = 12.0 V
19
Data Sheet S15923EJ2V0DS
µ PD160081
Switching Characteristics (TA = –10 to +75 °C, VDD1 = 2.7 to 3.6V, VDD2 = 10.0 to 12.0 V, VSS1 = VSS2 = 0 V,)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
ns
µs
µs
µs
µs
µs
µs
µs
µs
pF
Start Pulse Delay Time
Driver Output Delay Time
tPLH1
CL = 15 pF
10
6
Note1
Note2
Note1
Note2
Note1
Note2
Note1
Note2
tPLH2
tPLH3
tPHL2
tPHL3
tPLH4
tPLH5
tPHL4
tPHL5
CI1
VDD2 = 11.0 V, RPO1, RPO2,
4
5
S1 to S384, RL = 16.5 kΩ, CL = 45 pF
8
2.5
4.5
5
4
8
7
6
9
3
5
6
9
Input Capacitance
Logic input besides STHR (STHL),
TA = 25°C
10
CI2
STHR (STHL),TA = 25°C
15
pF
Notes 1. The value is specified when the drive voltage valuw reaches the target output voltage level of 10% or 90%.
2. The value is specified when the drive voltage valuw reaches the target output voltage level of 6-bit accuracy.
<Test condition>
Measurement
point
RL3
RL2
RL1
RLn = 5.5 kΩ
Output
CLn = 15 pF
CL2
CL1
CL3
V
COM = 0.5 VDD2
20
Data Sheet S15923EJ2V0DS
µ PD160081
Timing Requirement (TA = –10 to +75°C, VDD1 = 2.7 to 3.6V, VSS1 = 0 V, tr = tf = 3.0 ns (CMOS),
tr = tf = 1.0 ns (RSDS))
Parameter
Clock Period
Symbol
Condition
MIN.
15
12
6
TYP.
MAX.
Unit
ns
PWCLK
VDD1 = 2.7 V
VDD1 = 3.0 V
ns
Clock Pulse High Period
Clock Pulse Low Period
Data Setup Time
PWCLK(H)
PWCLK(L)
tSETUP1
tHOLD1
ns
6
ns
3
ns
Data Hold Time
1
ns
Start Pulse Setup Time
Start Pulse Hold Time
Start Pulse “H” Width
STB Pulse “H” Width
Last Data Timing
tSETUP2
tHOLD2
2
ns
4
ns
PWSTH
PWSTB
tLDT
1
2
CLKP
CLKP
CLKP
ns
5
1
STB-CLK Time
tSTB-CLK
tSTB-STH
STB ↑ → CLKP, CLKN ↓
STB ↑ → STHR (STHL) ↑
4
Time Between STB and Start
Pulse
5
CLKP
POL-STB Time
tPOL-STB
tSTB-POL
POL ↑ or ↓ → STB ↑
STB ↓ → POL ↓ or ↑
14
10
ns
ns
STB-POL Time
Remark tr, tf are defined 10 to 90% of each signal amplitude.
21
Data Sheet S15923EJ2V0DS
tr
tf
CLK(L)
0 V
CLK(H)
CLK
PW
PW
PW
CLK
(Differential)
90%
10%
0 V
2
0 V
0 V
0 V
0 V
0 V
0 V
0 V
10%
1
1
t
3
128
129
2
SETUP2
HOLD2
t
tr
tf
V
DD1
0.7 VDD1
0.7 VDD1
90%
0.3 VDD1
STHR
(1st Dr.)
10%
10%
V
SS1
PWSTH
Invalid
STB-CLK
t
STB-STH
t
tSETUP1 tHOLD1
<D376 to D378
>
<D379 to D381
>
D
n0 to Dn2
Last
Data
Even
Odd
Even
Odd
Even
0 V
Odd
0 V
Invalid
(Differential)
<D1 to D3 >
PLH1
t
PHL1
t
V
DD1
0.7 VDD1
0.7 VDD1
STHL
(1st Dr.)
VSS1
PWSTB
V
DD1
tLDT
0.7 VDD1
0.3 VDD1
0.7 VDD1
0.3 VDD1
STB
POL
VSS1
tPOL-STB
tSTB- POL
V
DD1
0.7 VDD1
0.3 VDD1
0.7 VDD1
0.3 VDD1
V
SS1
tPLH3
tPLH2
Hi-Z
S1 toS384
tPHL2
tPHL3
tPLH5
tPLH4
RPO1,
RPO2
tPHL4
tPHL5
µ PD160081
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
23
Data Sheet S15923EJ2V0DS
µ PD160081
Reference Documents
NEC Semiconductor Device Reliability/Quality Control System (C10983E)
Quality Grades On NEC Semiconductor Devices (C11531E)
•
The information in this document is current as of June, 2003. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
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or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
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customers or third parties arising from the use of these circuits, software and information.
•
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
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• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
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The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
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"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
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The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
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(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
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(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
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