UPD703003AGC-25_技术文档

DATA SHEET

MOS INTEGRATED CIRCUIT

µPD703003A,703004A,703025A

V853^TM

32-/16-BIT SINGLE-CHIP MICROCONTROLLERS

The µPD703003A, 703004A, and703025AaremembersoftheV850Family^TMof32-bitsingle-chipmicrocontrollers

designed for real-time control operations. These microcontrollers provide on-chip features including a 32-bit CPU

core, ROM, RAM, an interrupt controller, a real-time pulse unit, a serial interface, an A/D converter, a D/A converter,

and PWM.

Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before

designing.

V853 User’s Manual Hardware:

U10913E

V850 Family User’s Manual Architecture: U10243E

FEATURES

•

Number of instructions: 74

Minimum instruction execution time: 30 ns (@ 33 MHz operation)

General-purpose registers: 32 bits × 32 registers

Instruction set optimized for control applications

On-chip memory

ROM: 256 KB (µPD703025A)

128 KB (µPD703003A)

96 KB (µPD703004A)

RAM: 8 KB (µPD703025A)

4 KB (µPD703003A, 703004A)

•

Advanced on-chip interrupt controller

Real-time pulse unit suitable for control operations

Powerful serial interface (on-chip dedicated baud rate generator)

On-chip clock generator

10-bit resolution A/D converter: 8 channels

8-bit resolution D/A converter: 2 channels

8-/9-/10-/12-bit resolution PWM: 2 channels

Power saving functions

APPLICATIONS

•

AV: Camcorders, VCRs, etc.

Office equipment: PPCs, LBPs, printers, etc.

Industrial equipment: Motor controllers, NC machine tools, etc.

Communications equipment: Mobile telephones, etc.

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for availability

and additional information.

Document No. U13188EJ4V0DS00 (4th edition)

Date Published July 2000 N CP(K)

Printed in Japan

The mark

shows major revised points.

1998

©

µPD703003A, 703004A, 703025A

ORDERING INFORMATION

Part Number

Package

Maximum

Operating

Internal Internal

ROM RAM

Frequency (MHz) (Bytes) (Bytes)

µPD703003AGC-25-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 × 14 mm)

µPD703003AGC-33-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 × 14 mm)

µPD703004AGC-25-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 × 14 mm)

µPD703004AGC-33-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 × 14 mm)

µPD703025AGC-25-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 × 14 mm)

µPD703025AGC-33-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 × 14 mm)

25

33

25

33

25

33

128 K

96 K

4 K

8 K

96 K

256 K

Remark xxx indicates ROM code suffix.

PIN CONFIGURATION

•

100-pin plastic LQFP (fine pitch) (14 × 14 mm)

µPD703003AGC-25-xxx-8EU

µPD703003AGC-33-xxx-8EU

µPD703004AGC-25-xxx-8EU

µPD703004AGC-33-xxx-8EU

µPD703025AGC-25-xxx-8EU

µPD703025AGC-33-xxx-8EU

P31/TO131

P32/TCLR13

P33/TI13

1

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

P75/ANI5

2

P74/ANI4

P73/ANI3

P72/ANI2

P71/ANI1

P70/ANI0

ANO0

3

P34/INTP130

P35/INTP131/SO3

P36/INTP132/SI3

P37/INTP133/SCK3

P63/A19

4

5

6

7

8

ANO1

P62/A18

9

AV^REF2

P61/A17

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

AVREF3

P60/A16

P07/INTP113/ADTRG

P06/INTP112

P05/INTP111

P04/INTP110

P03/TI11

V

SS

V

DD

P57/AD15

P56/AD14

P55/AD13

P54/AD12

P53/AD11

P52/AD10

P51/AD9

P50/AD8

P47/AD7

P46/AD6

P45/AD5

P44/AD4

P02/TCLR11

P01/TO111

P00/TO110

P117/INTP143

P116/INTP142

P115/INTP141

P114/INTP140

P113/TI14

P112/TCLR14

P111/TO141

Caution Connect the IC (Internally Connected) pin directly to V^SS.

2

Data Sheet U13188EJ4V0DS00

µPD703003A, 703004A, 703025A

PIN NAMES

A16 to A19:

AD0 to AD15:

ADTRG:

ANI0 to ANI7:

ANO0, ANO1:

ASTB:

Address Bus

P30 to P37:

P40 to P47:

P50 to P57:

P60 to P63:

P70 to P77:

P90 to P96:

P110 to P117:

PWM0, PWM1:

RESET:

Port 3

Address/Data Bus

AD Trigger Input

Analog Input

Port 4

Port 5

Port 6

Analog Output

Port 7

Address Strobe

Port 9

AV^DD:

Analog Power Supply

Analog Reference Voltage

Analog Ground

Port 11

AVREF1 to AVREF3:

AV^SS:

Pulse Width Modulation

Reset

CV^DD:

Power Supply for Clock Generator

Ground for Clock Generator

Clock Select

R/W:

Read/Write Status

Receive Data

Serial Clock

Serial Input

Serial Output

Timer Output

CVSS:

RXD0, RXD1:

SCK0 to SCK3:

SI0 to SI3:

CKSEL:

CLKOUT:

DSTB:

Clock Output

Data Strobe

SO0 to SO3:

TO110, TO111,:

TO120, TO121,

TO130, TO131,

TO140, TO141

HLDAK:

Hold Acknowledge

Hold Request

HLDRQ:

IC:

Internally Connected

INTP110 to INTP113,: Interrupt Request from Peripherals

INTP120 to INTP123,

TCLR11 to TCLR14: Timer Clear

INTP130 to INTP133,

TI11 to TI14:

TXD0, TXD1:

UBEN:

Timer Input

Transmit Data

Upper Byte Enable

Wait

INTP140 to INTP143

LBEN:

Lower Byte Enable

MODE:

Mode

WAIT:

NMI:

Non-maskable Interrupt Request

X1, X2:

V^DD:

Crystal

P00 to P07:

P10 to P17:

P20 to P27:

Port 0

Port 1

Port 2

Power Supply

Ground

V^SS:

Data Sheet U13188EJ4V0DS00

3

µPD703003A, 703004A, 703025A

INTERNAL BLOCK DIAGRAM

Mask ROM

CPU

ASTB

NMI

Instruction

DSTB

queue

PC

INTC

RPU

INTP110 to INTP113

INTP120 to INTP123

INTP130 to INTP133

INTP140 to INTP143

R/W

UBEN

LBEN

Note 1

32-bit

barrel shifter

Multiplier

WAIT

16 × 16 → 32

A16 to A19

BCU

System

registers

AD0 to AD15

TO110, TO111

TO120, TO121

TO130, TO131

TO140, TO141

HLDRQ

HLDAK

RAM

General-purpose

registers

32 bits × 32

ALU

TCLR11 to TCLR14

TI11 to TI14

Note 2

SIO

SO0/TXD0

SI0/RXD0

SCK0

UART0/CSI0

BRG0

UART1/CSI1

BRG1

SO1/TXD1

SI1/RXD1

SCK1

CKSEL

Port

A/D

D/A

CG

CLKOUT

converter converter

X1

X2

SO2

SI2

SCK2

MODE

RESET

CSI2

BRG2

V

DD

SS

SO3

SI3

SCK3

CVDD

CVSS

CSI3

PWM0, PWM1

PWM

Notes 1. µPD703003A:

µPD703004A:

128 KB

96 KB

µPD703025A:

256 KB

2. µPD703003A, 703004A: 4 KB

µPD703025A:

8 KB

4

Data Sheet U13188EJ4V0DS00

µPD703003A, 703004A, 703025A

CONTENTS

1. DIFFERENCES AMONG PRODUCTS ............................................................................................

6

2. PIN FUNCTIONS..............................................................................................................................

2.1 Port Pins ................................................................................................................................

2.2 Non-Port Pins ........................................................................................................................

7

9

2.3 Pin I/O Circuits and Recommended Connection of Unused Pins .................................... 11

3. ELECTRICAL SPECIFICATIONS.................................................................................................... 14

4. PACKAGE DRAWING ..................................................................................................................... 36

5. RECOMMENDED SOLDERING CONDITIONS............................................................................... 37

Data Sheet U13188EJ4V0DS00

5

µPD703003A, 703004A, 703025A

1. DIFFERENCES AMONG PRODUCTS

Item

µPD703003 µPD703003A µPD703004A µPD703025A µPD70F3003 µPD70F3003A µPD70F3025A

Internal ROM

Internal RAM

Mask ROM

128 KB

Flash memory

128 KB

96 KB

256 KB

8 KB

256 KB

8 KB

4 KB

Operation Normal

Single-chip Implemented

mode

operation mode

mode

ROM-less Implemented Not implemented

mode

Implemented Not implemented

Implemented

Flash memory

Not implemented

programming mode

VPP pin

Not implemented

Implemented

Value of CKC register after reset 00H

MODE = 0: 03H

MODE = 1: 00H

00H

MODE = 0: 03H

MODE = 1: 00H

Electrical specifications

Other

Power consumption levels vary (see specific product’s data sheet).

Depending on the products, noise tolerance and noise emission will vary due to the

differences in circuit scale and mask layout.

6

Data Sheet U13188EJ4V0DS00

µPD703003A, 703004A, 703025A

2. PIN FUNCTIONS

2.1 Port Pins

(1/2)

Pin Name

P00

I/O

Function

Alternate Function

TO110

Port 0

8-bit I/O port

P01

P02

P03

P04

P05

P06

P07

P10

P11

P12

P13

P14

P15

P16

P17

P20

P21

P22

P23

P24

P25

P26

P27

P30

P31

P32

P33

P34

P35

P36

P37

P40 to P47

TO111

Input/output can be specified in 1-bit units.

TCLR11

TI11

INTP110

INTP111

INTP112

INTP113/ADTRG

TO120

I/O

Port 1

8-bit I/O port

TO121

Input/output can be specified in 1-bit units.

TCLR12

TI12

INTP120

INTP121/SO2

INTP122/SI2

INTP123/SCK2

PWM0

Port 2

8-bit I/O port

PWM1

Input/output can be specified in 1-bit units.

TXD0/SO0

RXD0/SI0

SCK0

TXD1/SO1

RXD1/SI1

SCK1

Port 3

TO130

8-bit I/O port

TO131

Input/output can be specified in 1-bit units.

TCLR13

TI13

INTP130

INTP131/SO3

INTP132/SI3

INTP133/SCK3

AD0 to AD7

I/O

Port 4

8-bit I/O port

Input/output can be specified in 1-bit units.

P50 to P57

Port 5

AD8 to AD15

8-bit I/O port

Input/output can be specified in 1-bit units.

Data Sheet U13188EJ4V0DS00

7

µPD703003A, 703004A, 703025A

(2/2)

Alternate Function

A16 to A19

Pin Name

I/O

Function

P60 to P63

Port 6

4-bit I/O port

Input/output can be specified in 1-bit units.

P70 to P77

Input

I/O

Port 7

ANI0 to ANI7

8-bit input port

P90

Port 9

LBEN

7-bit I/O port

P91

UBEN

Input/output can be specified in 1-bit units.

P92

R/W

P93

DSTB

P94

ASTB

P95

HLDAK

HLDRQ

TO140

TO141

TCLR14

TI14

P96

P110

P111

P112

P113

P114

P115

P116

P117

I/O

Port 11

8-bit I/O port

Input/output can be specified in 1-bit units.

INTP140

INTP141

INTP142

INTP143

8

Data Sheet U13188EJ4V0DS00

µPD703003A, 703004A, 703025A

2.2 Non-Port Pins

(1/2)

Pin Name

TO110

I/O

Function

Alternate Function

P00

Output

Pulse signal output from timers 11 to 14

TO111

TO120

TO121

TO130

TO131

TO140

TO141

TCLR11

TCLR12

TCLR13

TCLR14

TI11

P01

P10

P11

P30

P31

P110

P111

Input

Output

Input

External clear signal input for timers 11 to 14

External count clock input for timers 11 to 14

P02

P12

P32

P112

P03

TI12

P13

TI13

P33

TI14

P113

INTP110

INTP111

INTP112

INTP113

INTP120

INTP121

INTP122

INTP123

INTP130

INTP131

INTP132

INTP133

INTP140

INTP141

INTP142

INTP143

SO0

External maskable interrupt request input, also used as external capture

trigger input for timer 11

P04

P05

P06

P07/ADTRG

P14

External maskable interrupt request input, also used as external capture

trigger input for timer 12

P15/SO2

P16/SI2

P17/SCK2

P34

External maskable interrupt request input, also used as external capture

trigger input for timer 13

P35/SO3

P36/SI3

P37/SCK3

P114

External maskable interrupt request input, also used as external capture

trigger input for timer 14

P115

P116

P117

Serial transmit data output (3-wire) for CSI0 to CSI3

Serial receive data input (3-wire) for CSI0 to CSI3

P22/TXD0

P25/TXD1

P15/INTP121

P35/INTP131

P23/RXD0

P26/RXD1

P16/INTP122

P36/INTP132

SO1

SO2

SO3

SI0

SI1

SI2

SI3

Data Sheet U13188EJ4V0DS00

9

µPD703003A, 703004A, 703025A

(2/2)

Alternate Function

P24

Pin Name

SCK0

I/O

Function

Serial clock I/O (3-wire) for CSI0 to CSI3

SCK1

P27

SCK2

P17/INTP123

P37/INTP133

SCK3

TXD0

Output

Input

Output

I/O

Serial transmit data output for UART0 and UART1

Serial receive data input for UART0 and UART1

PWM pulse signal output

P22/SO0

TXD1

P25/SO1

RXD0

P23/SI0

RXD1

P26/SI1

PWM0

PWM1

AD0 to AD7

AD8 to AD15

A16 to A19

LBEN

P20

P21

16-bit multiplexed address/data bus for external memory expansion

P40 to P47

P50 to P57

Output

Higher address bus used for external memory expansion

External data bus’s lower byte enable signal output

External data bus’s higher byte enable signal output

External read/write status output

P60 to P63

P90

UBEN

R/W

P91

Output

P92

DSTB

External data strobe signal output

External address strobe signal output

Bus hold acknowledge output

P93

ASTB

P94

HLDAK

HLDRQ

ANI0 to ANI7

ANO0, ANO1

NMI

Output

Input

Output

Input

Output

Input

—

P95

Bus hold request input

P96

Analog input to A/D converter

P70 to P77

Analog output from D/A converter

Non-maskable interrupt request input

System clock output

—

CLKOUT

CKSEL

WAIT

—

Input for specifying clock generator’s operation mode

Control signal input for inserting wait in bus cycle

Operation mode specification

CVDD

—

MODE

RESET

X1

—

System reset input

—

Resonator connection for system clock. Input is via X1 when using an

external clock.

—

X2

—

ADTRG

AVREF1

AVREF2

AVREF3

AVDD

Input

A/D converter external trigger input

P07/INTP113

Reference voltage input for A/D converter

Reference voltage input for D/A converter

—

Positive power supply for A/D converter

Ground potential for A/D converter

Positive power supply for on-chip clock generator

Ground potential for on-chip clock generator

Positive power supply

—

AVSS

—

CVDD

CKSEL

—

CVSS

VDD

—

VSS

Ground potential

—

IC

Internally connected pin (Connect directly to VSS)

—

10

Data Sheet U13188EJ4V0DS00

µPD703003A, 703004A, 703025A

2.3 Pin I/O Circuits and Recommended Connection of Unused Pins

The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 2-1.

Figure 2-1 illustrates the various circuit types using partially abridged diagrams.

When connecting to V^DDor VSS via a resistor, a resistance value in the range of 1 to 10 kΩ is recommended.

Table 2-1. Types of Pin Input/Output Circuits (1/2)

Pin Name

Input/Output Circuit Type

Recommended Connection of Unused Pins

P00/TO110, P01/TO111

5

8

Input: Independently connect to VDD or VSS via a resistor.

Output: Leave open.

P02/TCLR11, P03/TI11,

P04/INTP110 to P07/INTP113/ADTRG

P10/TO120, P11/TO121

5

8

P12/TCLR12, P13/TI12

P14/INTP120

P15/INTP121/SO2

P16/INTP122/SI2

P17/INTP123/SCK2

P20/PWM0, P21/PWM1

P22/TXD0/SO0

5

P23/RXD0/SI0, P24/SCK0

P25/TXD1/SO1

8

5

8

5

8

P26/RXD1/SI1, P27/SCK1

P30/TO130, P31/TO131

P32/TCLR13, P33/TI13

P34/INTP130

P35/INTP131/SO3

P36/INTP132/SI3

P37/INTP133/SCK3

10-A

5

P40/AD0 to P47/AD7

P50/AD8 to P57/AD15

P60/A16 to P63/A19

P70/ANI0 to P77/ANI7

P90/LBEN

9

5

Connect directly to VSS.

Input: Independently connect to VDD or VSS via a resistor.

Output: Leave open.

P91/UBEN

P92/R/W

P93/DSTB

P94/ASTB

P95/HLDAK

P96/HLDRQ

P110/TO140, P111/TO141

P112/TCLR14, P113/TI14

8

P114/INTP140 to P117/INTP143

ANO0, ANO1

NMI

12

2

Leave open.

Connect directly to VSS.

Data Sheet U13188EJ4V0DS00

11

µPD703003A, 703004A, 703025A

Table 2-1. Types of Pin Input/Output Circuits (2/2)

Pin Name

Input/Output Circuit Type

Recommended Connection of Unused Pins

Leave open.

CLKOUT

WAIT

3

1

2

Connect directly to VDD.

MODE

—

RESET

CVDD/CKSEL

AVREF1 to AVREF3, AVSS

—

Connect directly to VSS.

Connect directly to VDD.

Connect directly to VSS.

AVDD

IC

12

Data Sheet U13188EJ4V0DS00

µPD703003A, 703004A, 703025A

Figure 2-1. Pin Input/Output Circuits

Type 1

Type 8

V^DD

P-ch

V^DD

Data

IN/OUT

P-ch

Output

disable

IN

N-ch

Type 2

Type 9

P-ch

N-ch

Comparator

+

–

IN

VREF (threshold voltage)

Input enable

Schmitt-triggered input with hysteresis characteristics

Type 3

Type 10-A

VDD

V^DD

Pull-up

P-ch

enable

VDD

P-ch

OUT

Data

P-ch

IN/OUT

N-ch

Open drain

N-ch

Output disable

Type 5

Type 12

V^DD

P-ch

Data

IN/OUT

P-ch

N-ch

Analog output voltage

Output

disable

OUT

N-ch

Input

enable

Data Sheet U13188EJ4V0DS00

13

µPD703003A, 703004A, 703025A

3. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (TA = 25°C)

Parameter

Symbol

VDD

Conditions

Ratings

–0.5 to +7.0

–0.5 to VDD + 0.3

–0.5 to +0.5

–0.5 to VDD + 0.3

–0.5 to +0.5

–0.5 to VDD + 0.3

–0.5 to VDD + 1.0

4.0

Unit

V

Power supply voltage

VDD pin

CVDD

CVSS

AVDD

AVSS

VI1

CVDD pin

CVSS pin

AVDD pin

AVSS pin

V

Input voltage

Note, VDD = 5.0 V ±10%

X1 pin, VDD = 5.0 V ±10%

Per pin

V

Clock input voltage

Output current, low

VK

V

IOL

mA

V

Total for all pins

Per pin

100

Output current, high

IOH

–4.0

Total for all pins

VDD = 5.0 V ±10%

P70/ANI0 to P77/ANI7

–100

Output voltage

VO

–0.5 to VDD + 0.3

–0.5 to AVDD + 0.3

–0.5 to VDD + 0.3

–0.5 to AVDD + 0.3

–40 to +85

Analog input voltage

VIAN

AVDD > VDD

VDD ≥ AVDD

AVDD > VDD

VDD ≥ AVDD

V

Analog reference input voltage

AVREF

AVREF1 to AVREF3

V

Operating ambient temperature

Storage temperature

TA

°C

Tstg

–65 to +150

Note X1, P70/ANI0 to P77/ANI7, and AVREF1 to AVREF3 are excluded.

Cautions 1. Be sure to avoid direct connections among the IC device output (or I/O) pins and between

V^DDor VCC and GND. However, open-drain pins and open collector pins can be directly

connected. A direct connection to an external circuit can be made to avoid conflicting output

from high-impedance pins if the external circuit is designed for the correct timing.

2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for

any parameter. That is, the absolute maximum ratings are rated values at which the product

is on the verge of suffering physical damage, and therefore the product must be used under

conditions that ensure that the absolute maximum ratings are not exceeded.

The ratings and conditions shown below for DC characteristics and AC characteristics are

within the range for normal operation and quality assurance.

Capacitance (T^A= 25°C, VDD = VSS = 0 V)

Parameter

Input capacitance

Symbol

CI

Condition

MIN.

TYP. MAX.

Unit

pF

fC = 1 MHz

Unmeasured pins returned to 0 V.

15

I/O capacitance

CIO

pF

Output capacitance

C^O

pF

14

Data Sheet U13188EJ4V0DS00

µPD703003A, 703004A, 703025A

Operating Conditions

Operation Mode

Internal Operating

Operating Ambient

Temperature (TA)

Power Supply

Voltage (VDD)

Clock Frequency (φ)

Note 1

Direct mode, PLL mode

2 to 33 MHz

–40 to +85°C

5.0 V ±10%

Note 2

5 to 33 MHz

Notes 1. When not using A/D converter

2. When using A/D converter

Recommended Oscillator

(1) Ceramic resonator connection (T^A= –40 to +85°C)

(a) µPD703003A, 703004A

X1

X2

Rd

C2

C1

Manufacturer

Part Number

Oscillation

Frequency

fXX (MHz)

Recommended

Circuit Constant

Oscillation

Voltage Range

Stabilization Time

(MAX.) TOST (ms)

C1 (pF) C2 (pF)

33 33

Rd (Ω) MIN. (V) MAX. (V)

Kyocera

KBR-5.0MSA/MSB

KBR-5.0MKC

KBR-5.0MKD

KBR-5.0MKS

PBRC5.00A

5.0

6.6

5.0

6.6

5.0

6.6

680

—

4.5

5.5

0.14

0.10

0.18

0.16

0.17

0.31

0.30

Corporation

On-chip On-chip

33

On-chip On-chip

33 33

33

PBRC5.00B

KBR-6.6MSA/MSB

KBR-6.6MKC

KBR-6.6MKD

KBR-6.6MKS

PBRC6.60A

On-chip On-chip

—

33

—

PBRC6.60B

On-chip On-chip

—

TDK

CCR5.0MC3

—

FCR5.0MC5

—

CCR6.6MC3

—

Murata Mfg.

Co., Ltd.

CSA5.00MG040

CST5.00MGW040

CSA6.60MTZ040

CST6.60MTW040

100

On-chip On-chip

100 100

On-chip On-chip

100

—

Cautions 1. Put the oscillator as close to the X1 and X2 pins as possible.

2. Do not cross the wiring with the other signal lines in the area enclosed by the broken lines.

3. Sufficiently evaluate the matching between the µPD703003A or 703004A and the resonator.

Data Sheet U13188EJ4V0DS00

15

µPD703003A, 703004A, 703025A

(b) µPD703025A

X1

X2

Rd

C2

C1

Manufacturer

Part Number

Oscillation

Frequency

fXX (MHz)

Recommended

Circuit Constant

Oscillation

Voltage Range

Stabilization Time

(MAX.) TOST (ms)

C1 (pF) C2 (pF)

On-chip On-chip

Rd (Ω) MIN. (V) MAX. (V)

TDK

CCR4.0MC3

4.0

5.0

4.0

6.6

—

4.5

5.5

0.28

0.20

0.16

0.20

0.09

CCR5.0MC3

Murata Mfg.

Co., Ltd.

CSA4.00MG040

CST4.00MGW040

CSTS0400MG06

CSA6.60MTZ040

CST6.60MTW040

CSTS0660MG06

100

On-chip On-chip

100

On-chip On-chip

Cautions 1. Put the oscillator as close to the X1 and X2 pins as possible.

2. Do not cross the wiring with the other signal lines in the area enclosed by the broken lines.

3. Sufficiently evaluate the matching between µPD703025A and the resonator.

(2) External clock input

X1

X2

Open

High-speed CMOS inverter

External clock

Cautions 1. Put the high-speed CMOS inverter as close to the X1 pin as possible.

2. Sufficiently evaluate the matching between the µPD703003A, 703004A, or 703025A

and the high-speed CMOS inverter.

16

Data Sheet U13188EJ4V0DS00

µPD703003A, 703004A, 703025A

DC Characteristics (TA = –40 to +85°C, VDD = 5.0 V ±10%, VSS = 0 V)

(1/2)

Parameter

Input voltage, high

Symbol

Conditions

MIN.

2.2

TYP.

MAX.

VDD + 0.3

+0.8

Unit

V

VIH

Except for X1 and pins listed in Note

Note

0.8VDD

–0.5

V

Input voltage, low

VIL

Except for X1 and pins listed in Note

V

Note

–0.5

0.2VDD

VDD + 0.5

+0.6

V

Clock input voltage, high

Clock input voltage, low

VXH

VXL

X1

0.8VDD

–0.5

V

X1

V

+

Schmitt-triggered input

Threshold voltage

VT

Note, rising edge

Note, falling edge

Note

3.0

2.0

V

–

V^T

V

+

–

Schmitt-triggered input hysteresis width VT – VT

0.5

V

Output voltage, high

VOH

IOH = –2.5 mA

IOH = –100 µA

IOL = 2.5 mA

VI = VDD

0.7VDD

V

VDD – 0.4

V

Output voltage, low

VOL

ILIH

ILIL

0.45

10

V

Input leakage current, high

Input leakage current, low

Output leakage current, high

Output leakage current, low

Software pull-up resistor

µA

kΩ

VI = 0 V

–10

10

ILOH

ILOL

R

VO = VDD

VO = 0 V

–10

90

P35/INTP131/SO3,

P36/INTP132/SI3,

P37/INTP133/SCK3

15

40

Note P02/TCLR11, P03/TI11, P04/INTP110 to P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/

INTP121/SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/

SCK1, P32/TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/SCK3,

P112/TCLR14, P113/TI14, P114/INTP140 to P117/INTP143, RESET, NMI, MODE

Remarks 1. TYP. values are reference values for when T^A= 25°C and VDD = 5.0 V.

2. φ = Internal system clock frequency

Data Sheet U13188EJ4V0DS00

17

µPD703003A, 703004A, 703025A

DC Characteristics (TA = –40 to +85°C, VDD = 5.0 V ±10%, VSS = 0 V)

(2/2)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Note

Power µPD703003A, When

IDD1

Direct mode

1.9 × φ + 5 2.1 × φ + 17 mA

2.0 × φ + 7 2.2 × φ + 20 mA

1.2 × φ + 5 1.3 × φ + 13 mA

1.3 × φ + 7 1.4 × φ + 15 mA

703004A

operating

Note

supply

current

PLL mode

Note

In

IDD2

IDD3

IDD4

IDD1

IDD2

IDD3

I^DD4

Direct mode

HALT mode

Note

PLL mode

Note

In

Direct mode

8 × φ + 300 10 × φ + 500

0.1 × φ + 2 0.2 × φ + 3

µA

mA

µA

IDLE mode

Note

PLL mode

In

2

50

STOP mode

Note

µPD703025A When

operating

Direct mode

2.5 × φ + 2 2.8 × φ + 16.5 mA

2.6 × φ + 4 2.9 × φ +19.5 mA

1.3 × φ + 5 1.4 × φ + 13 mA

1.3 × φ + 10 1.4 × φ + 18 mA

8 × φ + 300 10 × φ + 500 µA

Note

PLL mode

In

Direct mode

HALT mode

Note

PLL mode

In

Direct mode

IDLE mode

Note

PLL mode

0.1 × φ + 2 0.2 × φ + 3

mA

In

2

50

µA

STOP mode

Note When using A/D converter: φ = 5 to 33 MHz

When not using A/D converter: φ = 2 to 33 MHz

Remarks 1. TYP. values are reference values for when T^A= 25°C and VDD = 5.0 V. The power supply current

does not include AVREF1 to AVREF3 or the current that flows across a software pull-up resistor.

2. φ = Internal system clock frequency

18

Data Sheet U13188EJ4V0DS00

µPD703003A, 703004A, 703025A

Data Retention Characteristics (TA = –40 to +85°C)

Parameter

Data retention voltage

Data retention current

Symbol

VDDDR

IDDDR

Conditions

MIN.

1.5

TYP.

MAX.

5.5

Unit

V

STOP mode

VDD = VDDDR

–40°C ≤ TA ≤ +50°C

50°C < TA ≤ 85°C

0.2VDDDR

50

µA

µs

200

Power supply voltage rise time

Power supply voltage fall time

tRVD

tFVD

tHVD

200

0

µs

Power supply voltage hold time

(vs. STOP mode setting)

ms

STOP mode release signal input time tDREL

Data retention high-level input voltage

Data retention low-level input voltage VILDR

Note

0

0.9VDDDR

0

ns

V

VIHDR

VDDDR

0.1VDDDR

V

Note P02/TCLR11, P03/TI11, P04/INTP110 to P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/

INTP121/SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/

SCK1, P32/TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/SCK3,

P112/TCLR14, P113/TI14, P114/INTP140 to P117/INTP143, RESET, NMI, MODE, X1

Remark TYP. values are reference values for when T^A= 25°C and VDD = 5.0 V.

STOP mode setting (fifth clock after PSC register is set)

V

DD

V

DD

V

DD

V

DDDR

t

DREL

t

HVD

t

FVD

t

RVD

RESET (input)

V

IHDR

NMI (input)

(Released at falling edge)

IHDR

NMI (input)

(Released at rising edge)

V

ILDR

Data Sheet U13188EJ4V0DS00

19

µPD703003A, 703004A, 703025A

AC Characteristics (TA = –40 to +85°C, VDD = 5.0 V ±10%, VSS = 0 V)

AC test input waveform

(a) P02/TCLR11, P03/TI11, P04/INTP110toP07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/INTP121/

SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, P32/

TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/SCK3, P112/TCLR14,

P113/TI14, P114/INTP140 to P117/INTP143, RESET, NMI, MODE, X1

V

DD

0.8VDD

0.2VDD

0.8VDD

0.2VDD

Point of

mesurement

0 V

(b) Pins other than those listed in (a) above

2.4 V

2.2 V

0.8 V

Point of

mesurement

0.8 V

0.4 V

AC test output measurement points

2.2 V

0.8 V

2.2 V

0.8 V

Point of

mesurement

Load condition

DUT

(Device under testing)

CL = 50 pF

Caution In cases where the load capacitance is greater than 50 pF due to the circuit configuration, insert

a buffer or other element to reduce the device’s load capacitance to below 50 pF.

20

Data Sheet U13188EJ4V0DS00

µPD703003A, 703004A, 703025A

(1) Clock timing

Parameter

Symbol

Conditions

25 MHz Version

33 MHz Version

Unit

MIN.

20

MAX.

Note 1

MIN.

15

MAX.

Note 1

X1 input cycle

<1> tCYX

Direct mode

ns

PLL mode (PLL locked)

200

151

X1 input high-level width

X1 input low-level width

<2> tWXH

<3> tWXL

Direct mode

PLL mode

7

6

ns

80

60

Direct mode

PLL mode

7

6

ns

80

60

X1 input rise time

X1 input fall time

<4> tXR

<5> tXF

Direct mode

7

PLL mode

15

10

ns

Direct mode

PLL mode

7

15

7

10

ns

CPU operating frequency

CLKOUT output cycle

–

φ

Note 2

40

25

Note 2

30

33

MHz

ns

<6> tCYK

<7> tWKH

<8> tWKL

<9> tKR

<10> tKF

Note 3

CLKOUT input high-level width

CLKOUT input low-level width

CLKOUT input rise time

CLKOUT input fall time

0.5T – 5

ns

5

ns

Delay time from X1↓ to CLKOUT <11> tDXK

Direct mode

3

17

3

17

ns

Notes 1. When using A/D converter: 100 ns

When not using A/D converter: 250 ns

2. When using A/D converter: 5 MHz

When not using A/D converter: 2 MHz

3. When using A/D converter: 200 ns

When not using A/D converter: 500 ns

Remark T = t^CYK

<1>

<2>

<3>

X1 (input)

<4>

<11>

<5>

<6>

<11>

<7>

<8>

CLKOUT (output)

<9>

<10>

Data Sheet U13188EJ4V0DS00

21

µPD703003A, 703004A, 703025A

(2) Input waveform

(a) P02/TCLR11, P03/TI11, P04/INTP110 to P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/

INTP121/SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/

SCK1, P32/TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/

SCK3, P112/TCLR14, P113/TI14, P114/INTP140 to P117/INTP143, RESET, NMI, MODE

Parameter

Symbol

Conditions

25 MHz Version

33 MHz Version

Unit

MIN.

MAX.

20

MIN.

MAX.

20

Input rise time

Input fall time

<12> tIR2

<13> tIF2

ns

20

V

DD

0.8VDD

<12>

Input signal

0.2VDD

<13>

0.2VDD

0 V

(b) Pins other than those listed in (a) above

Parameter

Symbol

Conditions

25 MHz Version

33 MHz Version

Unit

MIN.

MAX.

10

MIN.

MAX.

10

Input rise time

Input fall time

<14> tIR1

<15> t^IF1

ns

10

2.4 V

0.4 V

2.2 V

<14>

Input signal

0.8 V

<15>

0.8 V

(3) Output waveform (other than CLKOUT)

Parameter

Symbol

Conditions

25 MHz Version

33 MHz Version

Unit

MIN.

MAX.

10

MIN.

MAX.

10

Output rise time

Output fall time

<16> tOR

<17> tOF

ns

10

2.2 V

Output signal

0.8 V

<17>

<16>

22

Data Sheet U13188EJ4V0DS00

µPD703003A, 703004A, 703025A

(4) Reset timing

Parameter

Symbol

Conditions

25 MHz Version

33 MHz Version

Unit

MIN.

500

MAX.

MIN.

500

MAX.

RESET high-level width

RESET low-level width

<18> tWRSH

<19> tWRSL

ns

When power supply is ON

and STOP mode has been

released

500 + TOST

Other than when power

supply is ON and STOP

mode has been released

500

ns

Remark TOST: Oscillation stabilization time

<18>

<19>

RESET (input)

Data Sheet U13188EJ4V0DS00

23

µPD703003A, 703004A, 703025A

(5) Read timing (1/2)

Parameter

Symbol

Conditions

25 MHz Version

33 MHz Version

Unit

ns

MIN.

3

MAX.

20

MIN.

3

MAX.

20

Delay time from CLKOUT

to R/W, UBEN, LBEN <78> tDKA2

Delay time from CLKOUT to address float <21> tFKA

to ASTB <22> tDKST

↑ to address <20> tDKA

Delay time from CLKOUT

↑

–2

3

+13

15

–2

3

+13

15

ns

↑

Delay time from CLKOUT

↓

3

15

3

15

ns

Delay time from CLKOUT↑ to DSTB <23> tDKD

Data input setup time (to CLKOUT↑) <24> tSIDK

Data input hold time (from CLKOUT↑) <25> tHKID

WAIT setup time (to CLKOUT↓) <26> tSWTK

WAIT hold time (from CLKOUT↓) <27> tHKWT

Address hold time (from CLKOUT↑) <28> tHKA

Address setup time (to ASTB↓) <29> tSAST

3

5

0

–40°C ≤ TA ≤ +70°C

70°C < TA ≤ 85°C

0.5T – 10

0.5T – 12

0.5T – 10

0.5T – 12

0.5T – 10

Address hold time (from ASTB↓) <30> tHSTA

Delay time from DSTB

↓

to address float <31> tFDA

0

Data input setup time (to address) <32> tSAID

–40°C ≤ TA ≤ +70°C

70°C < TA ≤ 85°C

–40°C ≤ TA ≤ +70°C

70°C < TA ≤ 85°C

(2 + n)T – 22

(2 + n)T – 25

(1 + n)T – 20

(1 + n)T – 24

(2 + n)T – 22

(2 + n)T – 25

(1 + n)T – 20

(1 + n)T – 24

Data input setup time (to DSTB↓) <33> tSDID

Delay time from ASTB↓ to DSTB↓ <34> tDSTD

Data input hold time (from DSTB↑) <35> tHDID

Delay time from DSTB↑ to address output <36> tDDA

Delay time from DSTB↑ to ASTB↑ <37> tDDSTH

Delay time from DSTB↑ to ASTB↓ <38> tDDSTL

0.5T – 10

0

0.5T – 10

0

(1 + i)T

0.5T – 10

(1.5 + i)T – 10

(1 + n)T – 10

(1 + n)T – 13

T – 10

(1 + i)T

0.5T – 10

(1.5 + i)T – 10

(1 + n)T – 10

(1 + n)T – 13

T – 10

DSTB low-level width

<39> tWDL

–40°C ≤ TA ≤ +70°C

70°C < TA ≤ 85°C

ASTB high-level width

<40> tWSTH

<41> tSAWT1

WAIT setup time (to address)

n ≥ 1, –40°C ≤ TA ≤ +70°C

n ≥ 1, 70°C < TA ≤ 85°C

n ≥ 1, –40°C ≤ TA ≤ +70°C

n ≥ 1, 70°C < TA ≤ 85°C

n ≥ 1

1.5T – 20

1.5T – 24

(1.5 + n)T – 20

(1.5 + n)T – 24

1.5T – 20

1.5T – 24

(1.5 + n)T – 20

(1.5 + n)T – 24

<42> tSAWT2

WAIT hold time (from address) <43> tHAWT1

<44> tHAWT2

(0.5 + n)T

(1.5 + n)T

(0.5 + n)T

(1.5 + n)T

n ≥ 1

WAIT setup time (to ASTB↓)

<45> tSSTWT1

n ≥ 1, –40°C ≤ TA ≤ +70°C

n ≥ 1, 70°C < TA ≤ 85°C

n ≥ 1

T – 18

T – 20

T – 18

T – 20

<46> tSSTWT2

<47> tHSTWT1

<48> tHSTWT2

(1 + n)T – 15

WAIT hold time (from ASTB↓)

Remarks 1. T = tCYK

n ≥ 1

nT

n ≥ 1

(1 + n)T

2. n indicates the number of wait clocks that are inserted during a bus cycle. The sampling timing may

vary when using the programmable wait insertion function.

3. i indicates the number of idle states (0 or 1) that are inserted after a read cycle.

4. Maintain at least one of the two data input hold times, either t^HKID(<25>) or tHDID (<35>).

24

Data Sheet U13188EJ4V0DS00

µPD703003A, 703004A, 703025A

(5) Read timing (2/2): 1 wait

T1

T2

TW

T3

CLKOUT (output)

<20>

<28>

A16 to A19 (output)

<78>

R/W (output)

UBEN (output)

LBEN (output)

<32>

<21>

<24>

<25>

AD0 to AD15 (I/O)

A0 to A15 (output)

D0 to D15 (input)

<35>

<22>

<29>

<30>

<22>

ASTB (output)

DSTB (output)

<37>

<36>

<40>

<31>

<23>

<34>

<23>

<33>

<38>

<39>

<45> <26>

<47>

<46>

<48>

<27>

<26>

<27>

WAIT (input)

<41>

<43>

<42>

<44>

Remark Broken lines indicate high impedance.

Data Sheet U13188EJ4V0DS00

25

µPD703003A, 703004A, 703025A

(6) Write timing (1/2)

Parameter

Symbol

Conditions

25 MHz Version

33 MHz Version

Unit

MIN.

MAX.

20

MIN.

MAX.

20

Delay time from CLKOUT

↑

to address <20> tDKA

3

–2

3

–2

ns

Delay time from CLKOUT

↑

to R/W, UBEN, LBEN <78> tDKA2

+13

15

+13

15

Delay time from CLKOUT↓ to ASTB <22> tDKST

Delay time from CLKOUT↑ to DSTB <23> tDKD

WAIT setup time (to CLKOUT↓) <26> tSWTK

WAIT hold time (from CLKOUT↓) <27> tHKWT

Address hold time (from CLKOUT↑) <28> tHKA

Address setup time (to ASTB↓) <29> tSAST

3

15

3

15

5

0

–40°C ≤ TA ≤ +70°C

70°C < TA ≤ 85°C

0.5T – 10

0.5T – 12

0.5T – 10

(1 + n)T – 10

(1 + n)T – 13

T – 10

0.5T – 10

0.5T – 12

0.5T – 10

(1 + n)T – 10

(1 + n)T – 13

T – 10

Address hold time (from ASTB↓) <30> tHSTA

Delay time from ASTB↓ to DSTB↓ <34> tDSTD

Delay time from DSTB↓ to ASTB↓ <37> tDDSTH

DSTB low-level width

<39> tWDL

–40°C ≤ TA ≤ +70°C

70°C < TA ≤ 85°C

ASTB high-level width

<40> tWSTH

<41> tSAWT1

WAIT setup time (to address)

n ≥ 1, –40°C ≤ TA ≤ +70°C

n ≥ 1, 70°C < TA ≤ 85°C

n ≥ 1, –40°C ≤ TA ≤ +70°C

n ≥ 1, 70°C < TA ≤ 85°C

n ≥ 1

1.5T – 20

1.5T – 24

(1.5 + n)T – 20

(1.5 + n)T – 24

1.5T – 20

1.5T – 24

(1.5 + n)T – 20

(1.5 + n)T – 24

<42> tSAWT2

WAIT hold time (from address) <43> tHAWT1

<44> tHAWT2

(0.5 + n)T

(1.5 + n)T

(0.5 + n)T

(1.5 + n)T

n ≥ 1

WAIT setup time (to ASTB↓)

<45> tSSTWT1

n ≥ 1, –40°C ≤ TA ≤ +70°C

n ≥ 1, 70°C < TA ≤ 85°C

n ≥ 1

T – 18

T – 20

T – 18

T – 20

<46> tSSTWT2

<47> tHSTWT1

<48> tHSTWT2

<49> tDKOD

(1 + n)T – 15

WAIT hold time (from ASTB↓)

n ≥ 1

nT

n ≥ 1

(1 + n)T

Delay time from

–40°C ≤ TA ≤ +70°C

70°C < TA ≤ 85°C

20

23

10

20

23

10

CLKOUT↑ to data output

Delay time from DSTB↓ to data output <50> tDDOD

Data output hold time (from CLKOUT↑) <51> tHKOD

Data output setup time (to DSTB↑) <52> tSODD

Data output hold time (from DSTB↑) <53> tHDOD

0

(1 + n)T – 15

T – 10

(1 + n)T – 15

T – 10

Remarks 1. T = tCYK

2. n indicates the number of wait clocks that are inserted during a bus cycle. The sampling timing may

vary when using the programmable wait insertion function.

26

Data Sheet U13188EJ4V0DS00

µPD703003A, 703004A, 703025A

(6) Write timing (2/2): 1 wait

T1

T2

TW

T3

CLKOUT (output)

<20>

<28>

A16 to A19 (output)

<78>

R/W (output)

UBEN (output)

LBEN (output)

<49>

<51>

AD0 to AD15 (I/O)

A0 to A15 (output)

D0 to D15 (output)

<22>

<29>

<30>

<22>

ASTB (output)

<23>

<37>

<53>

<23>

<50>

<40>

<34>

<52>

DSTB (output)

<39>

<45> <26>

<47>

<46>

<48>

<27>

<26>

<27>

WAIT (input)

<41>

<43>

<42>

<44>

Remark Broken lines indicate high impedance.

Data Sheet U13188EJ4V0DS00

27

µPD703003A, 703004A, 703025A

(7) Bus hold timing (1/2)

Parameter

Symbol

Conditions

25 MHz Version

33 MHz Version

Units

MIN.

MAX.

MIN.

MAX.

HLDRQ setup time (to CLKOUT↓) <54> tSHQK

HLDRQ hold time (from CLKOUT↓) <55> tHKHQ

HLDAK delay time from CLKOUT↑ <56> tDKHA

5

ns

20

HLDRQ high-level width

HLDAK low-level width

<57> tWHQH

<58> tWHAL

T + 10

T – 10

T – 12

T + 10

T – 10

T – 12

–40°C ≤ TA ≤ +70°C

70°C < TA ≤ 85°C

Delay time from CLKOUT↑ to bus float <59> tDKF

Delay time from HLDAK↑ to bus output <60> tDHAC

Delay time from HLDRQ↓ to HLDAK↓ <61> tDHQHA1

Delay time from HLDRQ↑ to HLDAK↑ <62> tDHQHA2

20

–3

(2n + 7.5)T + 20

0.5T 1.5T + 20 0.5T 1.5T + 20

Remarks 1. T = tCYK

2. n indicates the number of wait clocks that are inserted during a bus cycle. The sampling timing may

vary when using the programmable wait insertion function.

28

Data Sheet U13188EJ4V0DS00

µPD703003A, 703004A, 703025A

(7) Bus hold timing (2/2)

TH

TI

CLKOUT (output)

<54>

<54><55>

<57>

HLDRQ (input)

<56>

<61>

<62>

HLDAK (output)

<58>

<60>

<59>

A16 to A19 (output),

Note

D0 to D15

(input or output)

AD0 to AD15 (I/O)

ASTB (output)

DSTB (output)

R/W (output)

Note UBEN (output), LBEN (output)

Remark Broken lines indicate high impedance.

Data Sheet U13188EJ4V0DS00

29

µPD703003A, 703004A, 703025A

(8) Interrupt timing

Parameter

Symbol

Conditions

25 MHz Version

33 MHz Version

Unit

MIN.

500

MAX.

MIN.

500

MAX.

NMI high-level width

NMI low-level width

INTPn high-level width

<63> tWNIH

<64> tWNIL

<65> tWITH

ns

500

n = 110 to 113, 120 to 123, 3T + 10

130 to 133, 140 to 143

3T + 10

INTPn low-level width

<66> tWITL

n = 110 to 113, 120 to 123, 3T + 10

130 to 133, 140 to 143

3T + 10

ns

Remark T = tCYK

<63>

<64>

NMI (input)

<65>

<66>

INTPn (input)

Remark n = 110 to 113, 120 to 123, 130 to 133, 140 to 143

30

Data Sheet U13188EJ4V0DS00

µPD703003A, 703004A, 703025A

(9) CSI timing (1/2)

(a) Master mode

(i) Timing of CSI0 to CSI2

Parameter

Symbol

Conditions

25 MHz Version

33 MHz Version

Unit

MIN.

160

MAX.

MIN.

120

MAX.

SCKn cycle

<67> tCYSK1

<68> tWSKH1

<69> tWSKL1

<70> tSSISK1

<71> tHSKSI1

Output

ns

SCKn high-level width

0.5tCYSK1 – 20

30

0.5tCYSK1 – 20

30

SCKn low-level width

SIn setup time (to SCKn↑)

SIn hold time (from SCKn↑)

0

SOn output delay time (from SCKn↓) <72> tDSKSO1

SOn output hold time (from SCKn↑) <73> tHSKSO1

18

0.5tCYSK1 – 5

Remark n = 0 to 2

(ii) Timing of CSI3

Parameter

Symbol

Conditions

25 MHz Version

33 MHz Version

Unit

MIN.

500

MAX.

MIN.

500

MAX.

SCK3 cycle

<67> tCYSK3

<68> tWSKH3

<69> tWSKL3

<70> tSSISK3

<71> tHSKSI3

Output

RL = 1.5 kΩ

CL = 50 pF

ns

SCK3 high-level width

0.5tCYSK3 – 70

100

0.5tCYSK3 – 70

100

SCK3 low-level width

SI3 setup time (to SCK3↑)

SI3 hold time (from SCK3↑)

50

SO3 output delay time (from SCK3↓) <72> tDSKSO3

SO3 output hold time (from SCK3↑) <73> tHSKSO3

RL = 1.5 kΩ

150

CL = 50 pF

0.5tCYSK3 – 5

Remark RL and CL are the load resistance and load capacitance of the SCK3 and SO3 output lines.

(b) Slave mode

(i) Timing of CSI0 to CSI2

Parameter

Symbol

Conditions

25 MHz Version

33 MHz Version

Unit

MIN.

160

50

MAX.

MIN.

120

30

MAX.

SCKn cycle

<67> tCYSK2

<68> tWSKH2

<69> tWSKL2

<70> tSSISK2

<71> tHSKSI2

Input

ns

SCKn high-level width

SCKn low-level width

50

30

SIn setup time (to SCKn↑)

SIn hold time (from SCKn↑)

10

SOn output delay time (from SCKn↓) <72> tDSKSO2

SOn output hold time (from SCKn↑) <73> tHSKSO2

30

tWSKH2

Remark n = 0 to 2

Data Sheet U13188EJ4V0DS00

31

µPD703003A, 703004A, 703025A

(9) CSI timing (2/2)

(ii) Timing of CSI3

Parameter

Symbol

Conditions

25 MHz Version

33 MHz Version

Unit

MIN.

500

180

100

50

MAX.

MIN.

500

180

100

50

MAX.

SCK3 cycle

<67> tCYSK4

<68> tWSKH4

<69> tWSKL4

<70> tSSISK4

<71> tHSKSI4

Input

ns

SCK3 high-level width

SCK3 low-level width

SI3 setup time (to SCK3↑)

SI3 hold time (from SCK3↑)

SO3 output delay time (from SCK3↓) <72> tDSKSO4

SO3 output hold time (from SCK3↑) <73> tHSKSO4

RL = 1.5 kΩ

150

CL = 50 pF

tWSKH4

Remark RL and CL are the load resistance and load capacitance of the SCK3 and SO3 output lines.

<67>

<69>

<68>

SCKn (I/O)

<70>

<71>

SIn (Input)

Input data

<72>

<73>

SOn (output)

Output data

Remarks 1. Broken lines indicate high impedance.

2. n = 0 to 3

32

Data Sheet U13188EJ4V0DS00

µPD703003A, 703004A, 703025A

(10) RPU timing

Parameter

Symbol

Conditions

25 MHz Version

33 MHz Version

Unit

MIN.

MAX.

MIN.

MAX.

TI1n high-level width

TI1n low-level width

<74> tWTIH

<75> tWTIL

<76> tWTCH

<77> tWTCL

3T + 10

ns

TCLR1n high-level width

TCLR1n low-level width

Remark T = tCYK

<74>

<75>

TI1n (input)

<76>

<77>

TCLR1n (input)

Remark n = 1 to 4

Data Sheet U13188EJ4V0DS00

33

µPD703003A, 703004A, 703025A

A/D Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = 5 V ±10%, VSS = AVSS = 0 V)

Parameter

Symbol

Conditions

25 MHz Version

33 MHz Version

Unit

bit

MIN.

TYP.

10

MAX.

MIN.

TYP.

10

MAX.

10

Resolution

Overall error

—

10

Note 1

4.5 V ≤ AVREF1 ≤ AVDD

3.5 V ≤ AVREF1 ≤ AVDD

±0.4

±0.7

±1/2

±0.4 %FSR

±0.7 %FSR

—

Quantization error

Conversion time

—

±1/2

LSB

tCYK

LSB

V

tCONV

4.5 V ≤ AVREF1 ≤ AVDD

3.5 V ≤ AVREF1 ≤ AVDD

4.5 V ≤ AVREF1 ≤ AVDD

3.5 V ≤ AVREF1 ≤ AVDD

4.5 V ≤ AVREF1 ≤ AVDD

3.5 V ≤ AVREF1 ≤ AVDD

4.5 V ≤ AVREF1 ≤ AVDD

3.5 V ≤ AVREF1 ≤ AVDD

4.5 V ≤ AVREF1 ≤ AVDD

3.5 V ≤ AVREF1 ≤ AVDD

48

8

60

10

Sampling time

tSAMP

8

Note 1

Zero-scale error

—

±1.5

±3.5

±4.5

±2.5

±4.5

±2.5

±4.5

±1.5

±3.5

±4.5

±2.5

±4.5

±2.5

±4.5

Note 1

Full-scale error

Non-linearity error

Analog input

—

Note 1

—

VIAN

–0.3

3.5

AVDD

–0.3

3.5

AVDD

Note 2

voltage

+ 0.3

Reference voltage

AVREF1 current

AVREF1

AIREF1

AIDD

AVDD

3.0

AVDD

3.0

V

1.2

2.3

1.2

2.3

mA

AVDD power supply

current

6.0

Notes 1. Excludes quantization error.

2. When V^IAN= 0, the conversion result becomes 000H.

When 0 < VIAN < AVREF1, conversion has 10-bit resolution.

When AVREF1 ≤ VIAN ≤ AVDD, the conversion result becomes 3FFH.

34

Data Sheet U13188EJ4V0DS00

µPD703003A, 703004A, 703025A

D/A Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = 5 V ±10%, VSS = AVSS = 0 V)

Parameter

Symbol

Conditions

25 MHz Version

33 MHz Version

Unit

MIN.

TYP.

8

MAX.

MIN.

TYP.

8

MAX.

Resolution

—

8

bit

%

Overall error

Load condition: 2 MΩ, 30 pF

AVREF2 = VDD

0.8

AVREF3 = 0

—

Load condition: 2 MΩ, 30 pF

AVREF2 = 0.75VDD

1.0

0.6

0.8

10

1.0

0.6

0.8

10

%

AVREF3 = 0.25VDD

Load condition: 4 MΩ, 30 pF

AVREF2 = VDD

AVREF3 = 0

Load condition: 4 MΩ, 30 pF

AVREF2 = 0.75VDD

AVREF3 = 0.25VDD

Settling time

—

Load condition: 2 MΩ, 30 pF

µs

kΩ

V

Output resistance

AVREF2 input voltage

AVREF3 input voltage

RO

8

4

8

4

AVREF2

AVREF3

0.75VDD

VDD

0.75VDD

VDD

0

2

0.25VDD

0

2

0.25VDD

V

Resistance between

AVREF2 and AVREF3

RAIREF DACS0, DACS1 = 55H

kΩ

Data Sheet U13188EJ4V0DS00

35

µPD703003A, 703004A, 703025A

4. PACKAGE DRAWING

100-PIN PLASTIC LQFP (FINE PITCH) (14x14)

A

B

75

76

51

50

detail of lead end

S

C

D

R

Q

100

1

26

25

F

M

G

J

H

I

K

P

S

N

S

L

M

NOTE

Each lead centerline is located within 0.08 mm of

its true position (T.P.) at maximum material condition.

ITEM MILLIMETERS

A

B

C

D

F

16.00±0.20

14.00±0.20

16.00±0.20

1.00

G

1.00

+0.05

0.22

H

−0.04

I

J

0.08

0.50 (T.P.)

1.00±0.20

0.50±0.20

K

L

+0.03

0.17

M

−0.07

N

P

Q

0.08

1.40±0.05

0.10±0.05

+7°

3°

R

−3°

S

1.60 MAX.

S100GC-50-8EU, 8EA-2

36

Data Sheet U13188EJ4V0DS00

µPD703003A, 703004A, 703025A

5. RECOMMENDED SOLDERING CONDITIONS

The µPD703003A, 703004A, and 703025A should be soldered and mounted under the following recommended

conditions.

For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting

Technology Manual (C10535E).

For soldering methods and conditions other than those recommended below, contact your NEC sales represen-

tatives.

Table 5-1. Soldering Conditions

µPD703003AGC-25-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14 mm)

µPD703003AGC-33-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14 mm)

µPD703004AGC-25-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14 mm)

µPD703004AGC-33-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14 mm)

µPD703025AGC-25-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14 mm)

µPD703025AGC-33-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14 mm)

Soldering Method

Infrared reflow

Soldering Conditions

Recommended

Condition Symbol

IR35-107-2

VP15-107-2

—

Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or

Note

higher), Count: Two times or less, Exposure limit: 7 days

(after that,

prebake at 125°C for 10 hours)

VPS

Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or

Note

higher), Count: Two times or less, Exposure limit: 7 days

(after that,

prebake at 125°C for 10 hours)

Partial heating

Pin temperature: 300°C max., Time 3 seconds max. (per pin row)

Note After opening a dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.

Caution Do not use different soldering methods together (except for partial heating).

Data Sheet U13188EJ4V0DS00

37

µPD703003A, 703004A, 703025A

NOTES FOR CMOS DEVICES

1

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

2

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V^DDor GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

3

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

RELATED DOCUMENTS µPD703003 Data Sheet (U12261E)

µPD70F3003 Data Sheet (U12036E)

µPD70F3003A, 70F3025A Data Sheet (U13189E)

The related documents indicated in this publication may include preliminary versions. However, preliminary versions

are not marked as such.

V850 Family and V853 are trademarks of NEC Corporation.

38

Data Sheet U13188EJ4V0DS00

µPD703003A, 703004A, 703025A

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC

product in your application, please contact the NEC office in your country to obtain a list of authorized

representatives and distributors. They will verify:

• Device availability

• Ordering information

• Product release schedule

• Availability of related technical literature

• Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

• Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary

from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California

Tel: 408-588-6000

800-366-9782

NEC Electronics Hong Kong Ltd.

Hong Kong

Tel: 2886-9318

NEC Electronics (Germany) GmbH

Benelux Office

Eindhoven, The Netherlands

Tel: 040-2445845

Fax: 2886-9022/9044

Fax: 408-588-6130

800-729-9288

Fax: 040-2444580

NEC Electronics Hong Kong Ltd.

Seoul Branch

Seoul, Korea

Tel: 02-528-0303

Fax: 02-528-4411

NEC Electronics (France) S.A.

Velizy-Villacoublay, France

Tel: 01-30-67 58 00

NEC Electronics (Germany) GmbH

Duesseldorf, Germany

Tel: 0211-65 03 02

Fax: 01-30-67 58 99

Fax: 0211-65 03 490

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130

Tel: 65-253-8311

NEC Electronics (France) S.A.

Spain Office

Madrid, Spain

NEC Electronics (UK) Ltd.

Milton Keynes, UK

Tel: 01908-691-133

Fax: 65-250-3583

Tel: 91-504-2787

Fax: 01908-670-290

Fax: 91-504-2860

NEC Electronics Taiwan Ltd.

Taipei, Taiwan

Tel: 02-2719-2377

NEC Electronics Italiana s.r.l.

Milano, Italy

NEC Electronics (Germany) GmbH

Scandinavia Office

Tel: 02-66 75 41

Fax: 02-2719-5951

Taeby, Sweden

Fax: 02-66 75 42 99

Tel: 08-63 80 820

NEC do Brasil S.A.

Fax: 08-63 80 388

Electron Devices Division

Rodovia Presidente Dutra, Km 214

07210-902-Guarulhos-SP Brasil

Tel: 55-11-6465-6810

Fax: 55-11-6465-6829

J99.1

Data Sheet U13188EJ4V0DS00

39

µPD703003A, 703004A, 703025A

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited

without governmental license, the need for which must be judged by the customer. The export or re-export of this product

from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales

representative.

•

The information in this document is current as of March, 2000. The information is subject to change

without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data

books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products

and/or types are available in every country. Please check with an NEC sales representative for

availability and additional information.

•

No part of this document may be copied or reproduced in any form or by any means without prior

written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.

NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of

third parties by or arising from the use of NEC semiconductor products listed in this document or any other

liability arising from the use of such products. No license, express, implied or otherwise, is granted under any

patents, copyrights or other intellectual property rights of NEC or others.

•

Descriptions of circuits, software and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these

circuits, software and information in the design of customer's equipment shall be done under the full

responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third

parties arising from the use of these circuits, software and information.

While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers

agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize

risks of damage to property or injury (including death) to persons arising from defects in NEC

semiconductor products, customers must incorporate sufficient safety measures in their design, such as

redundancy, fire-containment, and anti-failure features.

NEC semiconductor products are classified into the following three quality grades:

"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products

developed based on a customer-designated "quality assurance program" for a specific application. The

recommended applications of a semiconductor product depend on its quality grade, as indicated below.

Customers must check the quality grade of each semiconductor product before using it in a particular

application.

"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment

and industrial robots

"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support)

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's

data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not

intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness

to support a given application.

(Note)

(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.

(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for

NEC (as defined above).

M8E 00. 4


型号：	UPD703003AGC-25
厂家：	NEC
描述：	V853TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLERS V853TM 32位/ 16位单芯片微控制器微控制器
文件：	总40页 (文件大小：228K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UPD703003AGC-25 [NEC]

相关型号：

UPD703003AGC-25-8EU

UPD703003AGC-25-XXX-8E

UPD703003AGC-25-XXX-8EU

UPD703003AGC-33

UPD703003AGC-33-XXX-8E

UPD703003AGC-33-XXX-8EU

UPD703003AGC-33-XXX-8EU-A

UPD703003AGC-33-XXX-8EU-A

UPD703003GC

UPD703003GC-25

UPD703003GC-25-XXX-7EA

UPD703003GC-33