UPD78F4225YGK-BE9 [NEC]
Microcontroller, 16-Bit, FLASH, MOS, PQFP80, 12 X 12 MM, FINE PITCH, PLASTIC, TQFP-80;
| 型号： | UPD78F4225YGK-BE9 |
| 厂家： | 
NEC |
| 描述： | Microcontroller, 16-Bit, FLASH, MOS, PQFP80, 12 X 12 MM, FINE PITCH, PLASTIC, TQFP-80 时钟 微控制器 外围集成电路 |
| 文件： | 总30页 (文件大小：205K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY PRODUCT INFORMATION
MOS INTEGRATED CIRCUIT
µPD78F4225Y
16/8-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
The µPD78F4225Y is a product in the µPD784225Y subseries in the 78K/IV series.
The µPD78F4225Y has a flash memory in the place of the internal ROM of the µPD784225Y. Data can be written
to or erased from the flash memory of the µPD78F4225F with the microcontroller mounted on a printed wiring board.
The µPD78F4225Y is based on the µPD78F4225 with an I2C bus control function appended, and is ideal for
applications in audio visual.
The functions are explained in detail in the following user’s manuals. Be sure to read this manual when
designing your system.
µPD784225, 784225Y Subseries User’s Manual - Hardware : Planned
78K/IV Series User’s Manual - Instruction
: U10905E
FEATURES
•
•
•
•
•
I2C bus serial interface supporting multi task
Pin-compatible with mask ROM model (except VPP pin)
Flash memory: 128K bytes
Internal RAM : 4352 bytes
Same operating voltage as mask ROM model: VDD = 1.8 to 5.5 V
ORDERING INFORMATION
Part Number
Package
µPD78F4225YGC-8BT
µPD78F4225YGK-BE9
80-pin plastic QFP (14 × 14 mm)
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
Document No. U12377EJ1V0PM00 (1st edition)
Date Published May 1997 N
Printed in Japan
1997
©
µPD78F4225Y
78K/IV Series Product Development
: Under mass production
: Under development
I2C bus compatible model
µ
PD784038Y
µ
PD784038
Enhanced internal memory capacity,
µ
pin-compatible with PD784026
µ
PD784026
Multi-master I2C bus
compatible model
Multi-master I2C bus
compatible model
Enhaced A/D, 16-bit timer,
power management
µ
PD784216Y
µ
PD784225Y
µ
µ
PD784216
PD784225
100 pins, enhanced I/O
80 pins
and internal memory capacity
µ
PD784054
µ
PD784928Y
µ
PD784046
µ
PD784928
With 10-bit A/D
Enhanced functions of
PD784915
µ
µ
PD784908
With IEBusTM controller
µ
PD784915
With software servo control,
analog circuit for VCRs,
enhanced timer
µ
PD78F4943
For CD-ROM,
Flash memory: 56 KB
2
µPD78F4225Y
FUNCTIONS
Item
Function
Number of basic instructions
(mnemonics)
113
General-purpose register
8 bits × 16 registers × 8 banks, or 16 bits × 8 registers × 8 banks (memory mapping)
Minimum instruction execution
time
• 160 ns/320 ns/640 ns/1280 ns/2560 ns (main system clock: fXX = 12.5 MHz)
• 61 µs (subsystem clock: fXX = 32.768 KHz)
Internal
memory
Flash memory
RAM
128 KBytes
4352 Bytes
Memory space
I/O port
1 MB with program and data spaces combined
Total
67
8
CMOS Input
CMOS I/O
59
57
Pins with pull-up
resistor
Pins with
ancillary
LEDs direct
drive output
16
Note
functions
Real-time output port
Timer/counter
4 bits × 2, or 8 bits × 1
16-bit timer/counter : timer register × 1
Capture/compare register × 2
Pulse output
• PWM/PPG output
• Square wave output
• One-shot pulse output
8-bit timer/counter 1 : timer register × 1
Compare register × 1
Pulse output
• PWM output
• Square wave output
8-bit timer/counter 2 : timer register × 1
Compare register × 1
Pulse output
• PWM output
• Square wave output
8-bit timer/counter 5 : timer register × 1
Compare register × 1
8-bit timer/counter 6 : timer register × 1
Compare register × 1
Serial interface
UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator
)
2
CSI (3-wire serial I/O, I C bus supporting multi master): 1 channel
A/D converter
D/A converter
Clock output
Buzzer output
Watch timer
Watchdog timer
Standby
8-bit resolution × 8 channels
8-bit resolution × 2 channels
2
3
4
5
6
7
Selectable from fXX, fXX/2, fXX/2 , fXX/2 , fXX/2 , fXX/2 , fXX/2 , fXX/2 , fXT
10
11
12
13
Selectable from fXX/2 , fXX/2 , fXX/2 , fXX/2
1 channel
1 channel
• HALT/STOP/IDLE mode
• In power-saving mode (with subsystem clock): HALT/IDLE mode
25 (internal: 18, external: 7)
Interrupt
Hardware
Software
BRK instruction, BRKCS instruction, operand error
Internal: 1, external: 1
Non-maskable
Maskable
Internal: 17, external: 6
• 4 programmable priority levels
• 3 service modes: vectored interrupt/macro service/context switching
Supply voltage
Package
VDD = 1.8 to 5.5 V
• 80-pin plastic QFP (14 × 14 mm)
• 80-pin plastic TQFP (fine pitch) (12 × 12 mm)
Note The pins with ancillary functions are included in the I/O pins.
3
µPD78F4225Y
CONTENTS
1. DIFFERENCES AMONG MODELS IN µPD784225Y SUBSERIES............................................. 5
2. PIN CONFIGURATION (Top View) ............................................................................................... 6
3. BLOCK DIAGRAM ......................................................................................................................... 8
4. PIN FUNCTION ............................................................................................................................... 9
4.1 Port Pins ................................................................................................................................................
9
4.2 Pins Other Than Port Pins .................................................................................................................. 11
4.3 I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins ........... 13
5. INTERNAL MEMORY SIZE SELECT REGISTER (IMS).............................................................. 16
6. FLASH MEMORY PROGRAMMING ............................................................................................. 17
6.1 Selecting Communication Mode ........................................................................................................ 17
6.2 Flash Memory Programming Function ............................................................................................. 18
6.3 Connecting Flashpro II ........................................................................................................................ 18
7. PACKAGE DRAWINGS ................................................................................................................. 20
APPENDIX A. DEVELOPMENT TOOLS............................................................................................. 22
APPENDIX B. RELATED DOCUMENTS ............................................................................................ 24
4
µPD78F4225Y
1. DIFFERENCES AMONG MODELS IN µPD784225Y SUBSERIES
The only difference among the µPD784224Y and 784225Y lies in the internal memory capacity.
The µPD78P4225Y is provided with a 128-KB flash memory instead of the mask ROM of the above models. These
differences are summarized in Table 1-1.
Table 1-1. Differences among Models in µPD784225Y Subseries
Part Number
µPD784224Y
96 KBytes
µPD784225Y
128 KBytes
µPD78F4225Y
128 KBytes
Item
Internal ROM
(mask ROM)
3584 Bytes
None
(mask ROM)
(flash memory)
Internal RAM
4352 Bytes
Internal memory size
Provided
Provided
switching register (IMS)
VPP pin
None
5
µPD78F4225Y
2. PIN CONFIGURATION (Top View)
• 80-pin plastic QFP (14 × 14 mm)
µPD78F4225YGC-8BT
• 80-pin plastic TQFP (fine pitch) (12 × 12 mm)
µPD78F4225YGK-BE9
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
P15/ANI5
P16/ANI6
1
RESET
2
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P127/RTP7
P126/RTP6
P125/RTP5
P124/RTP4
P123/RTP3
P122/RTP2
P121/RTP1
P120/RTP0
P37/EXA
P36/TI01
P35/TI00
P34/TI2
P17/ANI7
3
AVSS
4
P130/ANO0
P131/ANO1
AVREF1
5
6
7
P70/SI2/RxD2
P71/SO2/TxD2
P72/SCK2/ASCK2
P20/SI1/RxD1
P21/SO1/TxD1
P22/SCK1/ASCK1
P23/PCL
8
9
10
11
12
13
14
15
16
17
18
19
20
P33/TI1
P24/BUZ
P32/TO2
P25/SI0/SDA0
P26/SO0
P31/TO1
P30/TO0
P27/SCK0/SCL0
P40/AD0
P67/ASTB
P66/WAIT
P65/WR
P41/AD1
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Notes 1. Directly connect the TEST/VPP pin to VSS0 in normal operation mode.
2. Connect the AVSS pin to VSS0.
Remark When using in applications where noise from inside the microcomputer has to be reduced, it is
recommended to take countermeasures against noise such as supplying power to VDD0 and VDD1
independently, and connecting VSS0 and VSS1 to different ground lines.
6
µPD78F4225Y
A8-A19
: Address Bus
P130, P131
PCL
: Port13
AD0-AD7
ANI0-ANI7
ANO0, ANO1
ASCK1, ASCK2
ASTB
: Address/Data Bus
: Analog Input
: Programmable Clock
: Read Strobe
: Reset
RD
: Analog Output
RESET
: Asynchronous Serial Clock
: Address Strobe
RTP0-RTP7
RxD1, RxD2
SCK0-SCK2
SCL0
: Real-time Output Port
: Receive Data
: Serial Clock
: Serial Clock
: Serial Data
AVDD
: Analog Power Supply
: Analog Reference Voltage
: Analog Ground
AVREF1
AVSS
SDA0
BUZ
: Buzzer Clock
SI0-SI2
: Serial Input
: Serial Output
: Test
EXA
: External Access Status Output SO0-SO2
INTP0-INTP5
NMI
: Interrupt from Peripherals
TEST
: Non-maskable Interrupt
: Port0
TI00, TI01, TI1-TI2 : Timer Input
P00-P05
P10-P17
P20-P27
P30-P37
P40-P47
P50-P57
P60-P67
P70-P72
P120-P127
TO0-TO2
TxD1, TxD2
VDD0, VDD1
VPP
: Timer Output
: Port1
: Transmit Data
: Port2
: Power Supply
: Port3
: Programming Power Supply
: Ground
: Port4
VSS0, VSS1
WAIT
: Port5
: Wait
: Port6
WR
: Write Strobe
: Port7
X1, X2
: Crystal (Main System Clock)
: Crystal (Subsystem Clock)
: Port12
XT1, XT2
7
µPD78F4225Y
3. BLOCK DIAGRAM
RxD1/SI1
TxD1/SO1
INTP2/NMI
PROGRAMMABLE
INTERRUPT
CONTROLLER
UART/IOE1
BAUD-RATE
GENERATOR
INTP0, INTP1,
INTP3-INTP6
ASCK1/SCK1
RxD2/SI2
TxD2/SO2
UART/IOE2
BAUD-RATE
GENERATOR
TI00
TI01
TO0
TIMER/COUNTER
(16 BITS)
ASCK2/SCK2
SI0/SDA0
SO0
SCK0/SCL0
CLOCKED
SERIAL
INTERFACE
TIMER/COUNTER1
TI1
TO1
(8 BITS)
AD0-AD7
TIMER/COUNTER2
TI2
(8 BITS)
TO2
A8-A15
A16-A19
TIMER/COUNTER5
BUS I/F
RD
WR
(8 BITS)
WAIT
ASTB
EXA
TIMER/COUNTER6
78K/IV
CPU CORE MEMORY
FLASH
(8 BITS)
PORT0
PORT1
PORT2
PORT3
PORT4
PORT5
PORT6
PORT7
PORT12
PORT13
P00-P05
P10-P17
P20-P27
P30-P37
P40-P47
P50-P57
P60-P67
P70-P72
P120-P127
P130,P131
WATCH TIMER
WATCHDOG TIMER
RAM
REAL-TIME
OUTPUT PORT
RTP0-RTP7
ANO0
ANO1
AVREF1
AVSS
D/A
CONVERTER
ANI0-ANI7
A/D
AVDD
AVSS
CONVERTER
RESET
X1
CLOCK OUTPUT
CONTROL
PCL
BUZ
SYSTEM CONTROL
X2
XT1
XT2
BUZZER OUTPUT
V
V
DD0, VDD1
SS0, VSS1
TEST/VPP
8
µPD78F4225Y
4. PIN FUNCTION
4.1 Port Pins (1/2)
Pin Name
P00
I/O
I/O
Alternate Function
INTP0
Function
Port 0 (P0):
• 6-bit I/O port
P01
INTP1
• Can be set in input or output mode bit-wise.
• Pins set in input mode can be connected to internal pull-up
resistors by software bit-wise.
P02
INTP2/NMI
INTP3
P03
P04
INTP4
P05
INTP5
P10-P17
Input
I/O
ANI0-ANI7
Port 1 (P1):
• 8-bit input port
P20
P21
P22
P23
P24
P25
P26
P27
P30
P31
P32
P33
P34
P35
P36
P37
P40-P47
RxD1/SI1
TxD1/SO1
ASCK1/SCK1
PCL
Port 2 (P2):
• 8-bit I/O port
• Can be set in input or output mode bit-wise.
• Pins set in input mode can be connected to internal pull-up
resistors by software bit-wise.
BUZ
SI0/SDA0
SO0
SCK0/SCL0
TO0
I/O
Port 3 (P3):
• 8-bit I/O port
TO1
• Can be set in input or output mode bit-wise.
• Pins set in input mode can be connected to internal pull-up
resistors by software bit-wise.
TO2
TI1
TI2
TI00
TI01
EXA
I/O
I/O
AD0-AD7
Port 4 (P4):
• 8-bit I/O port
• Can be set in input or output mode bit-wise.
• All pins set in input mode can be connected to internal pull-up
resistors by software.
• Can drive LEDs.
P50-P57
A8-A15
Port 5 (P5):
• 8-bit I/O port
• Can be set in input or output mode bit-wise.
• All pins set in input mode can be connected to internal pull-up
resistors by software.
• Can drive LEDs.
9
µPD78F4225Y
4.1 Port Pins (2/2)
Pin Name
P60
I/O
I/O
Alternate Function
A16
Function
Port 6 (P6):
• 8-bit I/O port
P61
P62
P64
P65
P66
P67
P70
A17
• Can be set in input or output mode bit-wise.
A18
• All pins set in input mode can be connected to internal pull-up
resistors by software.
RD
WR
WAIT
ASTB
RxD2/SI2
I/O
Port 7 (P7):
• 3-bit I/O port
• Can be set in input or output mode bit-wise.
• Pins set in input mode can be connected to internal pull-up resistor
by software bit-wise.
P71
TxD2/SO2
P72
ASCK2/SCK2
RTP0-RTP7
P120-P127
I/O
I/O
Port 12 (P12):
• 8-bit I/O port
• Can be set in input or output mode bit-wise.
• Pins set in input mode can be connected to internal pull-up resistor
by software bit-wise.
P130, P131
ANO0, ANO1
Port 13 (P13):
• 2-bit I/O port
• Can be set in input or output mode bit-wise.
10
µPD78F4225Y
4.2 Pins Other Than Port Pins (1/2)
Pin Name
TI00
I/O
Alternate Function
P35
Function
Input
External count clock input to 16-bit timer register
Capture trigger signal input to capture/compare register 00
External count clock input to 8-bit timer register 1
External count clock input to 8-bit timer register 2
16-bit timer output (shared by 14-bit PWM output)
8-bit timer output (shared by 8-bit PWM output)
TI01
P36
TI1
P33
TI2
P34
TO0
Output
P30
TO1
P31
TO2
P32
RxD1
RxD2
TxD1
TxD2
ASCK1
ASCK2
SI0
Input
Output
Intput
Input
P20/SI1
P70/SI2
P21/SO1
P71/SO2
P22/SCK1
P72/SCK2
P25/SDA0
P20/RxD1
P70/RxD2
P26
Serial data input (UART1)
Serial data input (UART2)
Serial data output (UART1)
Serial data output (UART2)
Baud rate clock input (UART1)
Baud rate clock input (UART2)
Serial data input (3-wire serial clock I/O0)
Serial data input (3-wire serial clock I/O1)
Serial data input (3-wire serial clock I/O2)
Serial data output (3-wire serial I/O0)
Serial data output (3-wire serial I/O1)
Serial data output (3-wire serial I/O2)
SI1
SI2
SO0
Output
SO1
P21/TxD1
P71/TxD2
P25/SI0
P27/SCL0
P22/ASCK1
P72/ASCK2
P27/SCK0
P02/INTP2
P00
SO2
2
SDA0
SCK0
SCK1
SCK2
SCL0
NMI
I/O
I/O
Serial data input/output (I C bus)
Serial clock input/output (3-wire serial I/O0)
Serial clock input/output (3-wire serial I/O1)
Serial clock input/output (3-wire serial I/O2)
2
Serial clock input/output (I C bus)
Input
Non-maskable interrupt request input
External interrupt request input
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
PCL
P01
P02/NMI
P03
P04
P05
Output
Output
Output
P23
Clock output (for trimming main system clock and subsystem clock)
Buzzer output
BUZ
P24
RTP0-RTP7
P120-P127
Real-time output port that outputs data in synchronization with
trigger
AD0-AD7
A8-A15
A16-A19
RD
I/O
P40-P47
P50-P57
P60-P63
P64
Low-order address/data bus when external memory is connected
Middle-order address bus when external memory is connected
High-order address bus when external memory is connected
Strobe signal output for read operation of external memory
Strobe signal output for write operation of external memory
Output
Output
WR
P65
11
µPD78F4225Y
4.2 Pins Other Than Port Pins (2/2)
Pin Name
WAIT
I/O
Alternate Function
P66
Function
Input
To insert wait state(s) when external memory is accessed
ASTB
Output
P67
Strobe output to externally latch address information output to ports
4 through 6 to access external memory
EXA
Output
Input
Input
—
P37
External access status output
System reset input
RESET
X1
—
—
To connect main system clock oscillation crystal
X2
XT1
Input
—
—
To connect subsystem clock oscillation crystal
XT2
ANI0-ANI7
ANO0, ANO1
AVREF1
AVDD
AVSS
Input
Output
—
P10-P17
Analog voltage input for A/D converter
P130, P131
Analog voltage output for D/A converter
—
To apply reference voltage for D/A converter
Positive power supply for A/D converter. Connected to VDD0.
GND for A/D converter and D/A converter. Connected to VSS0.
Positive power supply for port block
VDD0
VSS0
GND potential for port block
VDD1
Positive power supply (except port block)
GND potential (except port block)
VSS1
TEST
VPP
VPP
Directly connect this pin to VSS (this pin is for IC test).
TEST
Sets flash memory programming mode.
To apply a high voltage when program is written or verified.
12
µPD78F4225Y
4.3 I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins
Table 4-1 shows symbols indicating the I/O circuit types of the respective pins and the recommended connection
of unused pins.
For the circuit diagram of each type of I/O circuit, refer to Figure 4-1.
Table 4-1. I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins (1/2)
Pin Name
P00/INTP0
I/O Circuit Type
8-C
I/O
I/O
Recommended Connections of Unused Pins
Input : Individually connected to VSS0 via resistor
Output: Open
P01/INTP1
P02/INTP2/NMI
P03/INTP3-P05/INTP5
P10/ANI0-P17/ANI7
P20/RxD1/SI1
P21/TxD1/SO1
P22/ASCK1/SCK1
P23/PCL
9
Input
I/O
Connected to VSS0 or VDD0
10-B
Input : Individually connected to VSS0 via resistor
Output: Open
P24/BUZ
P25/SDA0/SI0
P26/SO0
P27/SCL0/SCK0
P30/TO0-P32/TO2
P33/TI1, P34/TI2
P35/TI00, P36/TI01
P37/EXA
8-C
5-H
P40/AD0-P47/AD7
P50/A8-P57/A15
P60/A16-P63/A19
P64/RD
P65/WR
P66/WAIT
P67/ASTB
P70/RxD2/SI2
P71/TxD2/SO2
P72/ASCK2/SCK2
P120/RTP0-P127/RTP7
P130/ANO0, P131/ANO1
8-C
12-C
13
µPD78F4225Y
Table 4-1. I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins (2/2)
Pin Name
I/O Circuit Type
I/O
Recommended Connections of Unused Pins
RESET
XT1
2
Input
—
16
Connected to VSS0
Open
XT2
—
AVREF1
AVDD
—
Connected to VDD0
AVSS
Connected to VSS0
TEST/VPP
Directly connected to VSS0
Remark Because the circuit type numbers are standardized among the 78K series products, they are not
sequential in some models (i.e., some circuits are not provided).
14
µPD78F4225Y
Figure 4-1. Types of Pin I/O Circuits
Type 2
Type 10-B
V
DD0
pullup
enable
P-ch
IN
VDD0
data
P-ch
IN/OUT
Schmitt trigger input with hysteresis characteristics
open drain
output disable
N-ch
V
SS0
VDD0
Type 12-C
Type 5-H
VDD0
pullup
enable
pullup
enable
P-ch
P-ch
V
DD0
data
V
DD0
P-ch
IN/OUT
data
P-ch
output
disable
N-ch
IN/OUT
VSS0
output
disable
N-ch
P-ch
V
SS0
input
enable
Analog output
voltage
input
enable
N-ch
VSS0
Type 16
Type 8-C
VDD0
feedback
cut-off
pullup
enable
P-ch
P-ch
V
DD0
data
P-ch
IN/OUT
output
disable
N-ch
V
SS0
XT1
XT2
Type 9
Comparator
P-ch
N-ch
+
IN
–
VREF
(threshold voltage)
input
enable
15
µPD78F4225Y
5. INTERNAL MEMORY SIZE SELECT REGISTER (IMS)
The IMS is a register that prevents by software a part of the internal memory from being used. By using this
register, the memory of the µPD78F4225Y can be mapped in the same manner as a mask ROM model with different
internal memory (ROM and RAM) capacity.
This register is set by using an 8-bit memory manipulation instruction.
Its value is set to FFH by RESET input.
Figure 5-1. Format of Internal Memory Size Select Register (IMS)
Address: 0FFFCH
7
At reset: FFH
W
6
1
5
4
3
1
2
1
1
0
IMS
1
ROM1
ROM0
RAM1
RAM0
ROM1
ROM0
Selects internal ROM capacity
0
0
1
1
0
1
0
1
48K bytes
64K bytes
96K bytes
128K bytes
RAM1
RAM0
Selects peripheral RAM capacity
0
0
1
1
0
1
0
1
1536 bytes
2304 bytes
3072 bytes
3840 bytes
Caution IMS is not provided on the mask ROM models (µPD784224Y and 784225Y).
The value to be set to the IMS to map the memory of the µPD78F4225Y in the same manner as the mask ROM
model is shown in Table 5-1.
Table 5-1. Set Value of Internal Memory Size Select Register (IMS)
Mask ROM Model
µPD784225Y
µPD784226Y
Set Value of IMS
EEH
FFH
16
µPD78F4225Y
6. PROGRAMMING FLASH MEMORY
The flash memory can be written with the µPD78F4225Y mounted on the target board (on-board). To do so,
connect a dedicated flash writer (Flashpro II) to the host machine and target system.
Remark Flashpro II is a product of Naito Densei Machida Mfg. Co., Ltd.
6.1 Selecting Communication Mode
To write the flash memory, use Flashpro II and serial communication. Select a serial communication mode from
those listed in Table 6-1 in the format shown in Figure 6-1. Each communication mode is selected by the number
of VPP pulses shown in Table 6-1.
Table 6-1. Communication Modes
Communication Mode
3-wire serial I/O
Number of Channels
Pins Used
Number of VPP Pulses
3
SCK0/SCL0/P27
SO0/P26
0
SI0/SDA0/P25
SCK1/ASCK1/P22
SO1/TxD1/P21
SI1/RxD1/P20
1
2
SCK2/ASCK2/P72
SO2/TxD2/P71
SI2/RxD2/P70
I2C bus
UART
1
2
SCL0/SCK0/P27
SDA0/SI0/P25
4
TxD1/SO1/P21
RxD1/SI1/P20
8
TxD2/SO2/P71
RxD2/SI2/P70
9
Psendo-3-wire serial
I/ONote
1
P32/TO2
12
(serial clock I/O)
P31/TO1
(serial data output)
P30/TO0
(serial data output)
Note Performs serial transfer by controlling port by software.
Caution Be sure to select a communication mode with the number of VPP pulses shown in Table 6-1.
Figure 6-1. Communication Mode Selecting Format
10 V
V
PP
V
DD
1
2
n
V
SS
V
DD
SS
RESET
V
17
µPD78F4225Y
6.2 Flash Memory Programming Function
The flash memory is written by transferring or receiving commands and data in a selected communication mode.
The major functions of flush memory programming are listed in Table 6-2.
Table 6-2. Major Functions of Flash Memory Programming
Function
Batch erasure
Block erasure
Batch blank check
Block blank check
Data write
Description
Erases all contents of memory.
Erases contents of specified memory block.
Checks erased status of entire memory.
Checks erased status of specified block
Writes flash memory based on write start address and number of data to be
written (in bytes).
Batch verify
Block verify
Compares all contents of memory with input data.
Compares contents of specified memory block with input data.
6.3 Connecting Flashpro II
The Flashpro II and µPD78F4225Y are connected differently depending on the selected communication mode.
Figures 6-2 through 6-5 show the connections in the respective communication modes.
Figure 6-2. Connection of Flashpro II in 3-Wire Serial I/O Mode (When Using 3-Wire Serial I/O 0)
Flashpro II
µ PD78F4225Y
V
PPnNote
V
V
PP
VDD
DD0, VDD1
RESET
SCK
SO
RESET
SCK0
SI0
SI
SO0
VSS
V
SS0, VSS1
Note n = 1, 2
18
µPD78F4225Y
Figure 6-3. Connection of Flashpro II in I2C Bus Mode
Flashpro II
µ PD78F4225Y
V
PPnNote
VPP
VDD
VDD0, VDD1
RESET
SCK
SI
RESET
SCL0
SDA0
VSS
VSS0, VSS1
Note n = 1, 2
Figure 6-4. Connection of Flashpro II in UART Mode (When Using UART1)
Flashpro II
µ PD78F4225Y
V
PPnNote
VPP
VDD
VDD0, VDD1
RESET
SO
RESET
D1
R
X
T
XD1
SI
VSS
VSS0, VSS1
Note n = 1, 2
Figure 6-5. Connection of Flashpro II in Pseudo-3-Wire Serial I/O Mode
Flashpro II
µ PD78F4225Y
V
PPnNote
VPP
VDD
VDD0, VDD1
RESET
SCK
SO
RESET
P32 (serial clock)
P30 (serial input)
P31 (serial output)
SI
VSS
VSS0, VSS1
Note n = 1, 2
19
µPD78F4225Y
7. PACKAGE DRAWINGS
80 PIN PLASTIC QFP (14×14)
A
B
60
61
41
40
detail of lead end
S
C
D
R
Q
80
1
21
20
F
J
M
G
P
H
I
K
L
M
N
NOTE
ITEM MILLIMETERS
INCHES
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
A
B
17.20±0.20
14.00±0.20
0.677±0.008
+0.009
0.551
–0.008
+0.009
0.551
C
D
14.00±0.20
17.20±0.20
–0.008
0.677±0.008
F
0.825
0.825
0.032
0.032
G
+0.002
0.013
H
0.32±0.06
–0.003
I
0.13
0.005
J
K
0.65 (T.P.)
1.60±0.20
0.026 (T.P.)
0.063±0.008
+0.009
0.031
L
0.80±0.20
–0.008
+0.03
0.17
+0.001
0.007
M
–0.07
–0.003
N
P
Q
0.10
0.004
1.40±0.10
0.125±0.075
0.055±0.004
0.005±0.003
+7°
3°
+7°
3°
R
S
–3°
–3°
1.70 MAX.
0.067 MAX.
P80GC-65-8BT
20
µPD78F4225Y
80 PIN PLASTIC TQFP (FINE PITCH) ( 12)
A
B
60
41
61
40
detail of lead end
80
21
1
20
G
M
I
J
H
K
N
L
NOTE
ITEM MILLIMETERS
INCHES
Each lead centerline is located within 0.10 mm (0.004 inch) of
its true position (T.P.) at maximum material condition.
+0.009
A
B
C
D
14.0±0.2
12.0±0.2
12.0±0.2
14.0±0.2
0.551
0.472
0.472
0.551
–0.008
+0.009
–0.008
+0.009
–0.008
+0.009
–0.008
F
1.25
1.25
0.049
0.049
G
+0.05
0.22
H
0.009±0.002
–0.04
I
0.10
0.004
J
0.5 (T.P.)
0.020 (T.P.)
+0.009
0.039
K
L
1.0±0.2
0.5±0.2
–0.008
+0.008
0.020
–0.009
+0.055
M
0.145
0.006±0.002
–0.045
N
P
Q
R
S
0.10
1.05
0.004
0.041
0.05±0.05
5°±5°
0.002±0.002
5°±5°
1.27 MAX.
0.050 MAX.
P80GK-50-BE9-4
21
µPD78F4225Y
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for supporting development of a system using the µPD78F4225Y.
Language processor software
Note 1
RA78K4
CC78K4
Assembler package common to 78K/IV series
C compiler package common to 78K/IV series
C compiler library source file common to 78K/IV series
Note 1
Note 1
CC78K4-L
Flash memory writing tool
Flashpro II
Dedicated flash writer.
Flashpro is the product of Naito Densei Machida Mfg. Co., Ltd.
Product name pending
Adapter for flash memory writing.
Debugging tool
IE-784000-R
In-circuit emulator common to 78K/IV series
Break board common to 78K/IV series
IE-784000-R-BK
IE-784218-R-EM1
IE-784000-R-EM
Emulation board for evaluation of µPD784225Y subseries
IE-70000-98-IF-B
IE-70000-98N-IF
IE-70000-PC-IF-B
IE-78000-R-SV3
Interface adapter when PC-9800 series (except notebook type) is used as host machine
Interface adapter and cable when notebook type PC-9800 series is used as host machine
Interface adapter when IBM PC/ATTM is used as host machine
Interface adapter and cable when EWS is used as host machine
Emulation probe common to µPD784225Y subseries
Product name pending
Note 2
SM78K4
System simulator common to 78K/IV series
Note 2
ID78K4
Integrated debugger for IE-784000-R
Note 3
DF784225 (Pending)
Device file for µPD784225Y subseries
Real-time OS
Note 3
RX78K/IV
Real-time OS for 78K/IV series
OS for 78K/IV series
Note 4
MX78K4
Remark RA78K4, CC78K4, SM78K4, and ID78K4 are used in combination with DF784225.
22
µPD78F4225Y
Notes 1. • PC-9800 series (MS-DOSTM) base
• IBM PC/AT and compatible machine (PC DOSTM, WindowsTM, MS-DOS, IBM DOSTM) base
• HP9000 series 700TM (HP-UXTM) base
• SPARCstationTM (SunOSTM) base
• NEWSTM (NEWS-OSTM) base
2. • PC-9800 series (MS-DOS+Windows) base
• IBM PC/AT and compatible machine (PC DOS, Windows, MS-DOS, IBM DOS) base
• HP9000 series 700 (HP-UX) base
• SPARCstation (SunOS) base
3. • PC-9800 series (MS-DOS) base
• IBM PC/AT and compatible machine (PC DOS, Windows, MS-DOS, IBM DOS) base
• HP9000 series 700 (HP-UX) base
• SPARCstation (SunOS) base
4. • PC-9800 series (MS-DOS) base
• IMB PC/AT and compatible machine (PC DOS, Windows, MS-DOS, IBM DOS) base
23
µPD78F4225Y
APPENDIX B. RELATED DOCUMENTS
Documents related to device
Document Name
Document No.
Japanese
U12376J
U11824J
Planned
Planned
U10905J
U10594J
U10595J
U10095J
English
µPD784224Y, 784225Y Preliminary Product Information
µPD78F4225Y Preliminary Product Information
µPD784225, 784225Y Subseries User’s Manual - Hardware
µPD784225Y Subseries Special Function Register Table
78K/IV Series User’s Manual - Instruction
Planned
This document
Planned
–
U10905E
78K/IV Series Instruction Table
–
–
–
78K/IV Series Instruction Set
78K/IV Series Application Note - Software Basics
Documents related to development tools (User’s Manuals)
Document Name
Document No.
Japanese
U11334J
U11162J
EEU-817
EEU-960
EEU-961
U12322J
EEU-5004
U12155J
U10093J
U10092J
English
U11334E
–
RA78K4 Assembler Package
Operation
Language
RA78K Series Structured Assembler Preprocessor
CC78K4 Series
EEU-1402
–
Operation
Language
–
CC78K Series Library Source File
IE-784000-R
–
EEU-1534
U12155E
U10093E
U10092E
IE-784218-R-EM1
SM78K4 System Simulator - Windows Base
SM78K Series System Simulator
Reference
External component
user open interface
specification
ID78K4 Integrated Debugger - Windows based
Reference
U10440J
U10440E
Caution The contents of the above related documents are subject to change without notice. Be sure to
use the latest edition of a document for designing.
24
µPD78F4225Y
Documents related to embedded software (User’s Manual)
Document Name
Document No.
Japanese
U10603J
U10604J
U10364J
U11779J
English
78K/IV Series Real-Time OS
Basics
–
–
–
–
Installation
Debugger
Basics
78K/IV Series OS MX78K4
Other documents
Document Name
Document No.
Japanese
C10943X
C10535J
C11531J
C10983J
MEM-539
C11893J
U11416J
English
IC Package Manual
Semiconductor Device Mounting Technology Manual
Quality Grades on NEC Semiconductor Devices
C10535E
C11531E
C10983E
–
NEC Semiconductor Device Reliability/Quality Control System
Electrostatic Discharge (ESD) Test
Guide to Quality Assurance for Semiconductor Devices
Guide to Microcomputer-Related Products by Third Parties
MEI-1202
–
Caution The contents of the above related documents are subject to change without notice. Be sure to
use the latest edition of a document for designing.
25
µPD78F4225Y
[MEMO]
26
µPD78F4225Y
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to VDD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Produc-
tion process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed imme-
diately after power-on for devices having reset function.
27
µPD78F4225Y
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 800-366-9782
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 800-729-9288
Fax: 2886-9022/9044
Fax: 040-2444580
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 0211-65 03 490
Tel: 02-528-0303
Fax: 02-528-4411
Fax: 01-30-67 58 99
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel: 253-8311
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
Fax: 01908-670-290
Fax: 250-3583
Tel: 01-504-2787
NEC Electronics Italiana s.r.1.
Milano, Italy
Tel: 02-66 75 41
Fax: 01-504-2860
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-719-2377
NEC Electronics (Germany) GmbH
Scandinavia Office
Fax: 02-66 75 42 99
Fax: 02-719-5951
Taeby, Sweden
Tel: 08-63 80 820
NEC do Brasil S.A.
Sao Paulo-SP, Brasil
Tel: 011-889-1680
Fax: 011-889-1689
Fax: 08-63 80 388
J96. 8
28
µPD78F4225Y
Caution Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use
these components in an I2C system, provided that the system conforms to the I2C Standard
Specification as defined by Philips.
IEBus is a trademark of NEC Corp.
MS-DOS and Windows are trademarks of Microsoft Corp.
IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corp.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Co.
SPARCstation is a trademark of SPARC International, Inc.
SunOS is a trademark of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corp.
29
µPD78F4225Y
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
相关型号：
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