UPD78F9801GB-8ES-A_技术文档

User’s Manual

µPD789800 Subseries

8-Bit Single-Chip Microcontrollers

µPD789800

µPD78F9801

Document No. U12978EJ3V3UD00 (3rd edition)

Date Published August 2005 N CP (K)

1998, 2003

Printed in Japan

[MEMO]

User’s Manual U12978EJ3V3UD

2

NOTES FOR CMOS DEVICES

VOLTAGE APPLICATION WAVEFORM AT INPUT PIN

1

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the

CMOS device stays in the area between V^IL(MAX) and VIH (MIN) due to noise, etc., the device may

malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,

and also in the transition period when the input level passes through the area between V^IL(MAX) and

V

IH (MIN).

HANDLING OF UNUSED INPUT PINS

2

Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is

possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS

devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed

high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V^DDor GND

via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must

be judged separately for each device and according to related specifications governing the device.

3

PRECAUTION AGAINST ESD

A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as

much as possible, and quickly dissipate it when it has occurred. Environmental control must be

adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that

easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static

container, static shielding bag or conductive material. All test and measurement tools including work

benches and floors should be grounded. The operator should be grounded using a wrist strap.

Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for

PW boards with mounted semiconductor devices.

4

STATUS BEFORE INITIALIZATION

Power-on does not necessarily define the initial status of a MOS device. Immediately after the power

source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does

not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the

reset signal is received. A reset operation must be executed immediately after power-on for devices

with reset functions.

5

POWER ON/OFF SEQUENCE

In the case of a device that uses different power supplies for the internal operation and external

interface, as a rule, switch on the external power supply after switching on the internal power supply.

When switching the power supply off, as a rule, switch off the external power supply and then the

internal power supply. Use of the reverse power on/off sequences may result in the application of an

overvoltage to the internal elements of the device, causing malfunction and degradation of internal

elements due to the passage of an abnormal current.

The correct power on/off sequence must be judged separately for each device and according to related

specifications governing the device.

6

INPUT OF SIGNAL DURING POWER OFF STATE

Do not input signals or an I/O pull-up power supply while the device is not powered. The current

injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and

the abnormal current that passes in the device at this time may cause degradation of internal elements.

Input of signals during the power off state must be judged separately for each device and according to

related specifications governing the device.

User’s Manual U12978EJ3V3UD

3

FIP and EEPROM are trademarks of NEC Electronics Corporation.

Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the

United States and/or other countries.

PC/AT is a trademark of International Business Machines Corporation.

HP9000 Series 700 and HP-UX are trademarks of Hewlett-Packard Company.

SPARCstation is a trademark of SPARC International, Inc.

Solaris and SunOS are trademarks of Sun Microsystems, Inc.

User’s Manual U12978EJ3V3UD

4

These commodities, technology or software, must be exported in accordance

with the export administration regulations of the exporting country.

Diversion contrary to the law of that country is prohibited.

•

The information in this document is current as of August, 2005. The information is subject to

change without notice. For actual design-in, refer to the latest publications of NEC Electronics data

sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not

all products and/or types are available in every country. Please check with an NEC Electronics sales

representative for availability and additional information.

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Descriptions of circuits, software and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these

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•

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The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC

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(Note)

(1)

"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its

majority-owned subsidiaries.

(2)

"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as

defined above).

M8E 02. 11-1

User’s Manual U12978EJ3V3UD

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Regional Information

Some information contained in this document may vary from country to country. Before using any NEC

Electronics product in your application, pIease contact the NEC Electronics office in your country to

obtain a list of authorized representatives and distributors. They will verify:

•

Device availability

Ordering information

Product release schedule

Availability of related technical literature

Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

•

Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary

from country to country.

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J05.6

User’s Manual U12978EJ3V3UD

6

Major Revisions in This Edition (1/2)

Page

Contents

Throughout

Deletion of CU-type and GB-3BS type packages

Deletion of indication “under development” for µPD78F9801

Modification of operating ambient temperature when flash memory is written in 1.1 Features

Addition of outline of timer in 1.7 Functions

p. 21

p. 27

pp. 29, 31 to 33

pp. 35, 36

Modification of handling of REGC and VPP pins

Correction of address values in Figure 3-1 Memory Map (µPD789800) and Figure 3-2 Memory Map

(µPD78F9801)

p. 75

Modification of Figure 5-3 External Circuit of System Clock Oscillator (b) External clock

pp. 98, 103, 105, CHAPTER 8 USB FUNCTION

106,

• Modification of chapter composition

108 to 112,

• Standardization of buffer name indications as receive token bank, receive data bank, and transmit data

115 to 117, 120,

125, 127 to 130

banks 0 and 1

• Addition of image diagrams for reception and transmission

• Addition of register value for SETUP reception

• Modification of description on data handshake packet receive mode register (URXMOD)

• Addition of description on packet receive status register (RXSTAT) and modification of read-only bit

• Addition of Note for token packet receive result store register (TRXRSL)

• Addition of Caution for data packet transmit reservation register (DTXRSV)

• Modification of description of bit 1 (DNAEN) of handshake packet transmit reservation register (HTXRSV)

• Change of contents of 8.5.2 Remote wakeup control operation

• Addition of Table 8-4 List of Sources of Interrupts from USB Function

• Correction of incorrect flag name in 8.6 Interrupt Request from USB Function

• Addition of description on USB reset/Resume detection interrupt (INTUSBRE)

• Addition of 8.7 USB Function Control

p. 162

p. 164

p. 167

Modification of Figure 10-1 Block Diagram of Regulator and USB Driver/Receiver and Cautions

Addition of Remark in Table 11-1 Interrupt Source List

Addition of Caution 3 on watchdog timer interrupt to Figure 11-2 Format of Interrupt Request Flag

Register

p. 184

Addition of 12.2.2 STOP mode (3) Cautions on STOP instruction execution

Revision of contents of flash memory programming as 14.1 Flash Memory Characteristics

Addition of CHAPTER 16 ELECTRICAL SPECIFICATIONS

pp. 191 to 199

pp. 210 to 218

p. 219

Addition of CHAPTER 17 PACKAGE DRAWING

p. 220

Addition of CHAPTER 18 RECOMMENDED SOLDERING CONDITIONS

pp. 221 to 228

Revision of APPENDIX A DEVELOPMENT TOOLS

Deletion of embedded software and addition of notes on target system design

pp. 233, 234

Addition of the revision contents in 3rd edition in APPENDIX C REVISION HISTORY

Major revisions in modification version (U12978EJ3V2UD00)

p. 88

Modification of Figure 6-8. Timing of External Event Counter Operation (with Rising Edge Specified)

Modification of conditions of VIL2 and VOL2 in CHAPTER 16 ELECTRICAL SPECIFICATIONS

p. 213

The mark shows major revised points.

User’s Manual U12978EJ3V3UD

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Major Revisions in This Edition (2/2)

Page

Contents

Major revisions in modification version (U12978EJ3V3UD00)

Addition of lead-free products in CHAPTER 1 GENERAL

pp. 22, 23

p. 221

Addition of soldering conditions of lead-free products in Table 18-1 Surface Mounting Type Soldering

Conditions

The mark shows major revised points.

User’s Manual U12978EJ3V3UD

8

INTRODUCTION

Readers

This manual is intended for users who wish to understand the functions of the

µPD789800 Subseries and who design and develop its application systems and

programs.

Target products:

• µPD789800 Subseries: µPD789800 and µPD78F9801

Purpose

This manual is intended to give users an understanding of the functions described in

the Organization below.

Organization

Two manuals are available for the µPD789800 Subseries:

This manual and the Instruction Manual (common to the 78K/0S Series).

78K/0S Series

µPD789800 Subseries

User’s Manual

Instruction

• Pin functions

• CPU function

• Internal block functions

• Interrupts

• Instruction set

• Instruction description

• Other internal peripheral functions

• Electrical specifications

How to Read This Manual

It is assumed that the readers of this manual have general knowledge in the fields of

electrical engineering, logic circuits, and microcontrollers.

• To understand the overall functions of the µPD789800 Subseries

→ Read this manual in the order of the CONTENTS.

• How to read register formats

→ The name of a bit whose number is enclosed in angle brackets (< >) is reserved in

the assembler and is defined in the C compiler by the header file sfrbit.h.

• To learn the detailed functions of a register whose register name is known

→ See APPENDIX B REGISTER INDEX.

• To learn details of the instruction functions of the 78K/0S Series

→ Refer to 78K/0S Series Instruction User’s Manual (U11047E) separately

available.

• To know the electrical specifications of the µPD789800 Subseries

→ Refer to CHAPTER 16 ELECTRICAL SPECIFICATIONS.

Conventions

Data significance:

Active low representation:

Note:

Higher digits on the left and lower digits on the right

xxx (overscore over pin or signal name)

Footnote for item marked with Note in the text

Information requiring particular attention

Supplementary information

Caution:

Remark:

Numerical representation:

Binary ... xxxx or xxxxB

Decimal ... xxxx

Hexadecimal ... xxxxH

User’s Manual U12978EJ3V3UD

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Other Related Documents

Document Name

SEMICONDUCTOR SELECTION GUIDE - Products and Packages - (CD-ROM)

Semiconductor Device Mounting Technology Manual

Document No.

X13769X

C10535E

Quality Grades on NEC Semiconductor Devices

C11531E

NEC Semiconductor Device Reliability/Quality Control System

Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)

C10983E

C11892E

Caution The related documents listed above are subject to change without notice. Be sure to use the

latest version of each document for designing.

User’s Manual U12978EJ3V3UD

10

TABLE OF CONTENTS

CHAPTER 1 GENERAL......................................................................................................................... 22

1.1 Features...................................................................................................................................... 22

1.2 Applications............................................................................................................................... 22

1.3 Ordering Information ................................................................................................................ 22

1.4 Pin Configuration (Top View)................................................................................................... 23

1.5 78K/0S Series Lineup................................................................................................................ 24

1.6 Block Diagram ........................................................................................................................... 27

1.7 Functions ................................................................................................................................... 28

CHAPTER 2 PIN FUNCTIONS ............................................................................................................. 29

2.1 List of Pin Functions................................................................................................................. 29

2.2 Pin Functions............................................................................................................................. 31

2.2.1

2.2.2

2.2.3

2.2.4

2.2.5

2.2.6

2.2.7

2.2.8

2.2.9

P00 to P07 (Port 0)........................................................................................................................31

P10 to P17 (Port 1)........................................................................................................................31

P20 to P26 (Port 2)........................................................................................................................31

P40 to P47 (Port 4)........................................................................................................................32

RESET ..........................................................................................................................................32

X1, X2............................................................................................................................................32

REGC............................................................................................................................................32

USBDM .........................................................................................................................................32

USBDP..........................................................................................................................................32

2.2.10 V^DD0, VDD1 .....................................................................................................................................32

2.2.11 V^SS0, VSS1 .....................................................................................................................................32

2.2.12 VPP (µPD78F9801 only).................................................................................................................33

2.2.13 IC (mask ROM version only) .........................................................................................................33

2.3 Pin I/O Circuits and Recommended Connection of Unused Pins........................................ 34

CHAPTER 3 CPU ARCHITECTURE .................................................................................................... 36

3.1 Memory Space........................................................................................................................... 36

3.1.1

3.1.2

3.1.3

3.1.4

Internal program memory space....................................................................................................38

Internal data memory (internal high-speed RAM) space................................................................38

Special function register (SFR) area..............................................................................................38

Data memory addressing ..............................................................................................................39

3.2 Processor Registers ................................................................................................................. 41

3.2.1

3.2.2

3.2.3

Control registers ............................................................................................................................41

General-purpose registers.............................................................................................................44

Special function registers (SFRs) ..................................................................................................45

3.3 Instruction Address Addressing ............................................................................................. 49

3.3.1

3.3.2

3.3.3

Relative addressing.......................................................................................................................49

Immediate addressing ...................................................................................................................50

Table indirect addressing ..............................................................................................................51

User’s Manual U12978EJ3V3UD

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3.3.4

Register addressing...................................................................................................................... 51

3.4 Operand Address Addressing..................................................................................................52

3.4.1

3.4.2

3.4.3

3.4.4

3.4.5

3.4.6

3.4.7

Direct addressing.......................................................................................................................... 52

Short direct addressing................................................................................................................. 53

Special function register (SFR) addressing................................................................................... 54

Register addressing...................................................................................................................... 55

Register indirect addressing.......................................................................................................... 56

Based addressing ......................................................................................................................... 57

Stack addressing .......................................................................................................................... 57

CHAPTER 4 PORT FUNCTIONS..........................................................................................................58

4.1 Port Functions............................................................................................................................58

4.2 Port Configuration .....................................................................................................................60

4.2.1

4.2.2

4.2.3

4.2.4

Port 0 ............................................................................................................................................ 61

Port 1 ............................................................................................................................................ 62

Port 2 ............................................................................................................................................ 63

Port 4 ............................................................................................................................................ 69

4.3 Registers Controlling Port Function........................................................................................70

4.4 Port Function Operation............................................................................................................73

4.4.1

4.4.2

4.4.3

Writing to I/O port.......................................................................................................................... 73

Reading from I/O port ................................................................................................................... 73

Arithmetic operation of I/O port ..................................................................................................... 73

CHAPTER 5 CLOCK GENERATOR.....................................................................................................74

5.1 Clock Generator Functions.......................................................................................................74

5.2 Clock Generator Configuration ................................................................................................74

5.3 Register Controlling Clock Generator .....................................................................................75

5.4 System Clock Oscillators..........................................................................................................76

5.4.1

5.4.2

5.4.3

System clock oscillator.................................................................................................................. 76

Examples of incorrect resonator connection ................................................................................. 77

Frequency divider ......................................................................................................................... 78

5.5 Clock Generator Operation.......................................................................................................78

5.6 Changing Setting of CPU Clock ...............................................................................................79

5.6.1

5.6.2

Time required for switching CPU clock ......................................................................................... 79

Switching CPU clock..................................................................................................................... 79

CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01 ...........................................................80

6.1 Functions of 8-Bit Timer/Event Counters 00 and 01 ..............................................................80

6.2 Configuration of 8-Bit Timer/Event Counters 00 and 01........................................................81

6.3 Registers Controlling 8-Bit Timer/Event Counters 00 and 01...............................................83

6.4 Operation of 8-Bit Timer/Event Counters 00 and 01 ..............................................................86

6.4.1

6.4.2

6.4.3

Operation as interval timer............................................................................................................ 86

Operation as external event counter (timer 01 only) ..................................................................... 88

Operation as square-wave output (timer 01 only) ......................................................................... 89

6.5 Notes on Using 8-Bit Timer/Event Counters 00 and 01 .........................................................91

User’s Manual U12978EJ3V3UD

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CHAPTER 7 WATCHDOG TIMER ....................................................................................................... 92

7.1 Watchdog Timer Functions...................................................................................................... 92

7.2 Watchdog Timer Configuration ............................................................................................... 93

7.3 Registers Controlling Watchdog Timer .................................................................................. 94

7.4 Watchdog Timer Operation ...................................................................................................... 96

7.4.1

7.4.2

Operation as watchdog timer.........................................................................................................96

Operation as interval timer ............................................................................................................97

CHAPTER 8 USB FUNCTION.............................................................................................................. 98

8.1 USB Overview............................................................................................................................ 98

8.2 USB Function Features............................................................................................................. 99

8.3 USB Function Configuration.................................................................................................... 99

8.4 Registers Controlling USB Function..................................................................................... 110

8.5 USB Function Operation......................................................................................................... 123

8.5.1

8.5.2

USB timer operation ....................................................................................................................123

Remote wakeup control operation...............................................................................................126

8.6 Interrupt Request from USB Function .................................................................................. 128

8.6.1

8.6.2

Interrupt sources..........................................................................................................................128

Cautions when using interrupts ...................................................................................................130

8.7 USB Function Control............................................................................................................. 131

8.7.1

8.7.2

Relationship between packets and operation modes...................................................................131

Interrupt servicing flow.................................................................................................................137

8.8 USB Function Internal Circuit Operations............................................................................ 141

8.8.1

8.8.2

8.8.3

8.8.4

8.8.5

Operation of transmit/receive pointer...........................................................................................141

Receive bank switching ID detection buffer operation.................................................................148

Sync detection/USBCLK detector operation................................................................................149

NRZI encoder operation ..............................................................................................................151

Bit stuffing/strip controller operation ............................................................................................152

CHAPTER 9 SERIAL INTERFACE 10 .............................................................................................. 155

9.1 Functions of Serial Interface 10............................................................................................. 155

9.2 Configuration of Serial Interface 10 ...................................................................................... 156

9.3 Register Controlling Serial Interface 10................................................................................ 158

9.4 Operation of Serial Interface 10............................................................................................. 160

9.4.1

9.4.2

Operation stop mode...................................................................................................................160

3-wire serial I/O mode .................................................................................................................161

CHAPTER 10 REGULATOR ............................................................................................................... 163

CHAPTER 11 INTERRUPT FUNCTIONS........................................................................................... 164

11.1 Interrupt Function Types........................................................................................................ 164

11.2 Interrupt Sources and Configuration .................................................................................... 164

11.3 Registers Controlling Interrupt Function.............................................................................. 167

11.4 Interrupt Servicing Operation ................................................................................................ 172

11.4.1 Non-maskable interrupt acknowledgment operation....................................................................172

User’s Manual U12978EJ3V3UD

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11.4.2 Maskable interrupt acknowledgment operation........................................................................... 174

11.4.3 Multiplexed interrupt servicing..................................................................................................... 176

11.4.4 Interrupt request hold.................................................................................................................. 178

CHAPTER 12 STANDBY FUNCTION.................................................................................................179

12.1 Standby Function and Configuration ....................................................................................179

12.1.1 Standby function ......................................................................................................................... 179

12.1.2 Register controlling standby function .......................................................................................... 180

12.2 Standby Function Operation...................................................................................................181

12.2.1 HALT mode................................................................................................................................. 181

12.2.2 STOP mode................................................................................................................................ 184

CHAPTER 13 RESET FUNCTION ......................................................................................................187

CHAPTER 14 µPD78F9801..................................................................................................................191

14.1 Flash Memory Characteristics................................................................................................192

14.1.1 Programming environment.......................................................................................................... 192

14.1.2 Communication mode................................................................................................................. 193

14.1.3 On-board pin processing............................................................................................................. 196

14.1.4 Connection of adapter for flash writing........................................................................................ 199

CHAPTER 15 INSTRUCTION SET .....................................................................................................201

15.1 Operation ..................................................................................................................................201

15.1.1 Operand identifiers and description methods.............................................................................. 201

15.1.2 Description of “operation” column ............................................................................................... 202

15.1.3 Description of “flag operation” column ........................................................................................ 202

15.2 Operation List...........................................................................................................................203

15.3 Instructions Listed by Addressing Type ...............................................................................208

CHAPTER 16 ELECTRICAL SPECIFICATIONS................................................................................211

CHAPTER 17 PACKAGE DRAWINGS...............................................................................................220

CHAPTER 18 RECOMMENDED SOLDERING CONDITIONS .........................................................221

APPENDIX A DEVELOPMENT TOOLS .............................................................................................222

A.1 Software Package ....................................................................................................................224

A.2 Language Processing Software .............................................................................................224

A.3 Control Software......................................................................................................................225

A.4 Flash Memory Writing Tools...................................................................................................225

A.5 Debugging Tools (Hardware)..................................................................................................226

A.6 Debugging Tools (Software)...................................................................................................227

A.7 Notes on Target System Design.............................................................................................228

APPENDIX B REGISTER INDEX........................................................................................................230

User’s Manual U12978EJ3V3UD

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B.1 Register Index (Alphabetic Order of Register Name).......................................................... 230

B.2 Register Index (Alphabetic Order of Register Symbol)....................................................... 232

APPENDIX C REVISION HISTORY ................................................................................................... 234

User’s Manual U12978EJ3V3UD

15

LIST OF FIGURES (1/4)

Figure No.

2-1

Title

Page

Pin I/O Circuits..........................................................................................................................................35

3-1

3-2

3-3

3-4

3-5

3-6

3-7

3-8

3-9

3-10

Memory Map (µPD789800).......................................................................................................................36

Memory Map (µPD78F9801) ....................................................................................................................37

Data Memory Addressing (µPD789800) ...................................................................................................39

Data Memory Addressing (µPD78F9801).................................................................................................40

Configuration of Program Counter ............................................................................................................41

Configuration of Program Status Word .....................................................................................................41

Configuration of Stack Pointer ..................................................................................................................43

Data to Be Saved to Stack Memory..........................................................................................................43

Data to Be Restored from Stack Memory .................................................................................................43

Configuration of General-Purpose Registers ............................................................................................44

4-1

Port Types ................................................................................................................................................58

Block Diagram of P00 to P07....................................................................................................................61

Block Diagram of P10 to P17....................................................................................................................62

Block Diagram of P20 ...............................................................................................................................63

Block Diagram of P21 ...............................................................................................................................64

Block Diagram of P22 ...............................................................................................................................65

Block Diagram of P23 and P24.................................................................................................................66

Block Diagram of P25 ...............................................................................................................................67

Block Diagram of P26 ...............................................................................................................................68

Block Diagram of P40 to P47....................................................................................................................69

Format of Port Mode Register...................................................................................................................70

Format of Pull-up Resistor Option Register 0 ...........................................................................................71

Format of Port Output Mode Register 0....................................................................................................72

Format of Port Output Mode Register 1....................................................................................................72

4-2

4-3

4-4

4-5

4-6

4-7

4-8

4-9

4-10

4-11

4-12

4-13

4-14

5-1

5-2

5-3

5-4

5-5

Block Diagram of Clock Generator............................................................................................................74

Format of Processor Clock Control Register.............................................................................................75

External Circuit of System Clock Oscillator...............................................................................................76

Examples of Incorrect Resonator Connection...........................................................................................77

Switching of CPU Clock............................................................................................................................79

6-1

6-2

6-3

6-4

6-5

6-6

Block Diagram of 8-Bit Timer 00...............................................................................................................81

Block Diagram of 8-Bit Timer/Event Counter 01 .......................................................................................82

Format of 8-Bit Timer Mode Control Register 00 ......................................................................................83

Format of 8-Bit Timer Mode Control Register 01 ......................................................................................84

Format of Port Mode Register 2................................................................................................................85

Interval Timer Operation Timing of 8-Bit Timer 00....................................................................................87

User’s Manual U12978EJ3V3UD

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LIST OF FIGURES (2/4)

Figure No.

Title

Page

6-7

Interval Timer Operation Timing of 8-Bit Timer/Event Counter 01............................................................ 87

Timing of External Event Counter Operation (with Rising Edge Specified) .............................................. 88

Timing of Square-Wave Output................................................................................................................ 90

Start Timing of 8-Bit Timer Counter.......................................................................................................... 91

Timing of External Event Counter Operation............................................................................................ 91

6-8

6-9

6-10

6-11

7-1

7-2

7-3

Block Diagram of Watchdog Timer........................................................................................................... 93

Format of Timer Clock Select Register 2.................................................................................................. 94

Format of Watchdog Timer Mode Register............................................................................................... 95

8-1

USB Bus Topology (Desktop Type PC).................................................................................................... 98

Block Diagram of USB Function............................................................................................................. 100

Block Diagram of USB Timer.................................................................................................................. 101

Configuration of Receive Token Bank .................................................................................................... 103

Configuration of Receive Data Bank....................................................................................................... 104

Configuration of Transmit Data Bank 0 (Buffer 0)................................................................................... 105

Configuration of Transmit Data Bank 1 (Buffer 1)................................................................................... 106

Configuration of TIDCMP and ADRCMP................................................................................................ 108

Configuration of DIDCMP....................................................................................................................... 109

Format of USB Receiver Enable Register .............................................................................................. 110

Format of Data/Handshake Packet Receive Mode Register .................................................................. 111

Format of Packet Receive Status Register............................................................................................. 113

Format of Data/Handshake Packet Receive Result Store Register........................................................ 114

Format of Token Packet Receive Result Store Register ........................................................................ 115

Format of Data Packet Transmit Reservation Register .......................................................................... 116

Format of Handshake Packet Transmit Reservation Register................................................................ 117

Configuration of Handshake Packet Transmit Reservation Register...................................................... 120

Format of USB Timer Start Reservation Control Register ...................................................................... 121

Format of Remote Wakeup Control Register.......................................................................................... 122

Flowchart of USB Timer Operation......................................................................................................... 124

Flow Chart of Remote Wakeup Control Operation ................................................................................. 126

Configuration of Remote Wakeup Control.............................................................................................. 127

Timing of Data/Handshake Packet Receive Interrupt Request Generation............................................ 128

Timing of INTUSBRE Generation........................................................................................................... 129

Flowchart of Transmit/Receive Pointer Operation.................................................................................. 141

Flowchart of Receive Bank Switching ID Detection Buffer Operation..................................................... 148

Timing of Sync Detection/USBCLK Detector Operation ......................................................................... 149

Timing of Sync Detection/USBCLK Generation Operation..................................................................... 149

Flowchart of Sync Detection/USBCLK Detector Operation .................................................................... 150

Timing of NRZI Encoder Operation ........................................................................................................ 151

8-2

8-3

8-4

8-5

8-6

8-7

8-8

8-9

8-10

8-11

8-12

8-13

8-14

8-15

8-16

8-17

8-18

8-19

8-20

8-21

8-22

8-23

8-24

8-25

8-26

8-27

8-28

8-29

8-30

User’s Manual U12978EJ3V3UD

17

LIST OF FIGURES (3/4)

Figure No.

Title

Page

8-31

8-32

8-33

8-34

Flow Chart of NRZI Encoder Operation ..................................................................................................151

Timing of Bit Stuffing/Strip Controller Operation .....................................................................................152

Flow Chart of Bit Stuffing Control Operation...........................................................................................153

Flow Chart of Bit Strip Control Operation................................................................................................154

9-1

9-2

9-3

Block Diagram of Serial Interface 10.......................................................................................................157

Format of Serial Operation Mode Register 10 ........................................................................................158

3-Wire Serial I/O Mode Timing................................................................................................................162

10-1

Block Diagram of Regulator and USB Driver/Receiver ...........................................................................163

11-1

11-2

11-3

11-4

11-5

11-6

11-7

11-8

11-9

Basic Configuration of Interrupt Function................................................................................................166

Format of Interrupt Request Flag Register..............................................................................................168

Format of Interrupt Mask Flag Register ..................................................................................................169

Format of External Interrupt Mode Register 0.........................................................................................169

Configuration of Program Status Word ...................................................................................................170

Format of Key Return Mode Register 00 ................................................................................................171

Block Diagram of Falling Edge Detector .................................................................................................171

Flowchart of Non-Maskable Interrupt Request Acknowledgment............................................................173

Timing of Non-Maskable Interrupt Request Acknowledgment ................................................................173

11-10 Acknowledging Non-Maskable Interrupt Request ...................................................................................173

11-11 Interrupt Acknowledgment Program Algorithm .......................................................................................174

11-12 Timing of Interrupt Request Acknowledgment (Example of MOV A,r) ....................................................175

11-13 Timing of Interrupt Request Acknowledgment

(When Interrupt Request Flag Is Generated at Last Clock of Instruction Execution) ..............................175

11-14 Example of Multiplexed Interrupt Servicing.............................................................................................177

12-1

12-2

12-3

12-4

12-5

Format of Oscillation Stabilization Time Select Register.........................................................................180

Releasing HALT Mode by Interrupt.........................................................................................................182

Releasing HALT Mode by RESET Input .................................................................................................183

Releasing STOP Mode by Interrupt ........................................................................................................185

Releasing STOP Mode by RESET Input.................................................................................................186

13-1

13-2

13-3

13-4

Block Diagram of Reset Function ...........................................................................................................187

Reset Timing by RESET Input................................................................................................................188

Reset Timing by Overflow in Watchdog Timer........................................................................................188

Reset Timing by RESET Input in STOP Mode........................................................................................188

14-1

14-2

Environment for Writing Program to Flash Memory ................................................................................192

Communication Mode Selection Format.................................................................................................193

User’s Manual U12978EJ3V3UD

18

LIST OF FIGURES (4/4)

Figure No.

Title

Page

14-3

14-4

14-5

14-6

14-7

14-8

14-9

Example of Connection with Dedicated Flash Programmer ................................................................... 194

V^PPPin Connection Example.................................................................................................................. 196

Signal Conflict (Input Pin of Serial Interface).......................................................................................... 197

Abnormal Operation of Other Device...................................................................................................... 197

Signal Conflict (RESET Pin)................................................................................................................... 198

Wiring Example for Flash Writing Adapter with 3-Wire Serial I/O........................................................... 199

Wiring Example for Flash Writing Adapter with Pseudo-3-Wire Method................................................. 200

A-1

A-2

A-3

Development Tools ................................................................................................................................ 223

Distance Between In-Circuit Emulator and Conversion Adapter............................................................. 228

Connection Condition of Target System (NP-H44GB-TQ)...................................................................... 229

User’s Manual U12978EJ3V3UD

19

LIST OF TABLES (1/2)

Table No.

2-1

Title

Page

Type of Pin I/O Circuit Recommended Connection of Unused Pins .........................................................34

3-1

3-2

Vector Table .............................................................................................................................................38

Special Function Register List ..................................................................................................................46

4-1

4-2

4-3

Functions of Ports.....................................................................................................................................59

Configuration of Port.................................................................................................................................60

Port Mode Register and Output Latch Settings When Using Alternate Functions.....................................71

5-1

5-2

Configuration of Clock Generator..............................................................................................................74

Maximum Time Required for Switching CPU Clock..................................................................................79

6-1

6-2

6-3

6-4

6-5

6-6

6-7

Interval Time of 8-Bit Timer 00..................................................................................................................80

Interval Time of 8-Bit Timer/Event Counter 01..........................................................................................80

Square Wave Output Range of 8-Bit Timer/Event Counter 01..................................................................81

Configuration of 8-Bit Timer/Event Counters 00 and 01............................................................................81

Interval Time of 8-Bit Timer 00..................................................................................................................86

Interval Time of 8-Bit Timer/Event Counter 01..........................................................................................86

Square-Wave Output Range of 8-Bit Timer/Event Counter 01 .................................................................89

7-1

7-2

7-3

7-4

7-5

Inadvertent Loop Detection Time of Watchdog Timer...............................................................................92

Interval Time.............................................................................................................................................92

Configuration of Watchdog Timer .............................................................................................................93

Inadvertent Loop Detection Time of Watchdog Timer...............................................................................96

Interval Time of Interval Timer ..................................................................................................................97

8-1

8-2

8-3

8-4

Configuration of USB Function .................................................................................................................99

Flag of RXSTAT After Reception of USB Reset Signal and Resume Signal ..........................................114

Conditions in Transmit Reservation ........................................................................................................118

List of Sources of Interrupts from USB Function.....................................................................................128

9-1

9-2

Configuration of Serial Interface 10.........................................................................................................156

Operating Mode Settings of Serial Interface 10 ......................................................................................159

11-1

11-2

11-3

Interrupt Source List ...............................................................................................................................165

Flags Corresponding to Interrupt Request Signals .................................................................................167

Time from Generation of Maskable Interrupt Request to Servicing.........................................................174

12-1

12-2

HALT Mode Operation Status.................................................................................................................181

Operation After Release of HALT Mode .................................................................................................183

User’s Manual U12978EJ3V3UD

20

LIST OF TABLES (2/2)

Table No.

Title

Page

12-3

12-4

STOP Mode Operation Status................................................................................................................ 184

Operation After Release of STOP Mode ................................................................................................ 186

13-1

Hardware Status After Reset.................................................................................................................. 189

14-1

14-2

14-3

Differences Between µPD78F9801 and Mask ROM Versions................................................................ 191

Communication Mode List...................................................................................................................... 193

Pin Connection List ................................................................................................................................ 195

15-1

18-1

Operand Identifiers and Description Methods ........................................................................................ 201

Surface Mounting Type Soldering Conditions ........................................................................................ 221

User’s Manual U12978EJ3V3UD

21

CHAPTER 1 GENERAL

1.1 Features

• On-chip USB functions

• Implements a USB (Universal Serial Bus) by connecting to Hub and Host.

• Transfer speed: 1.5 Mbps (at 6.0 MHz operation with system clock)

• On-chip regulator

• Controls the USB port voltage by using a bus power supply (VREG = 3.3 0.3 V) dedicated to the USB

driver/receiver.

• On-chip ROM and RAM

• Internal ROM:

8 KB

Flash memory (for µPD78F9801 only): 16 KB

• Internal high-speed RAM:

256 bytes

• Variable minimum instruction execution time: From high-speed (0.33 µs) to low speed (1.33 µs) with the system

clock operating at 6.0 MHz

• 31 I/O ports

• Two serial interface channels

• USB function

• 3-wire serial I/O mode

• Three timers:

• 8-bit timer

• 8-bit timer/event counter

• Watchdog timer

• On-chip key return signal detector

• 12 vectored interrupt sources

• Power supply voltage: V^DD= 4.0 to 5.5 V

• Operating ambient temperature: T^A= –40 to +85°C (when the USB is not operating)

T^A= 0 to +70°C (when the USB is operating)

T^A= 10 to 40°C (when the flash memory is written)

1.2 Applications

USB keyboards, etc.

1.3 Ordering Information

Part Number

µPD789800GB-×××-8ES

µPD78F9801GB-8ES

Package

44-pin plastic LQFP (10 × 10)

Internal ROM

Mask ROM

44-pin plastic LQFP (10 × 10)

Flash memory

Mask ROM

µPD789800GB-×××-8ES-A

µPD78F9801GB-8ES-A

Flash memory

Remarks 1. Products that have the part numbers suffixed by "-A" are lead-free products.

2. ××× indicates ROM code suffix.

User’s Manual U12978EJ3V3UD

22

CHAPTER 1 GENERAL

1.4 Pin Configuration (Top View)

• 44-pin plastic LQFP (10 × 10)

µPD789800GB-×××-8ES

µPD78F9801GB-8ES

µPD789800GB-×××-8ES-A

µPD78F9801GB-8ES-A

44 43 42 41 40 39 38 37 36 35 34

P04

P03

P02

P01

P00

1

33

USBDP

USBDM

2

32

31

30

29

28

27

26

25

24

23

3

IC (V^PP

REGC

)

4

5

VDD0

V

DD1

6

V

SS0

V

SS1

7

X1

X2

P17

P16

P15

P14

8

9

RESET

10

P40/KR00

P41/KR01

11

12 13 14 15 16 17 18 19 20 21 22

Cautions 1. Connect the IC pin directly to the V^SS0pin.

2. Directly connect the V^PPpin to the VSS0 pin in the normal operation mode.

Remark The parenthesized values apply to the µPD78F9801.

IC:

Internally connected

SI10:

SO10:

TI01:

Serial data input

Serial data output

Timer input

INTP0:

Interrupt from peripherals

KR00 to KR07 :

Key return

NC:

No connection

TO01:

Timer output

P00 to P07:

P10 to P17:

P20 to P26:

P40 to P47:

RESET :

REGC:

Port 0

USBDM, USBDP: Universal serial bus data

Port 1

V^DD0:

V^DD1:

V^PP:

Port power supply

Power supply

Programming power supply

Port ground

Port 2

Port 4

Reset

V^SS0:

V^SS1:

X1, X2:

Voltage regulator for USB function

Serial clock input/output

Ground

SCK10 :

Crystal

User’s Manual U12978EJ3V3UD

23

CHAPTER 1 GENERAL

1.5 78K/0S Series Lineup

The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.

Products in mass

production

Products under

development

Y subseries supports SMB.

Small-scale package, general-purpose applications

µ

44-pin

PD789074 with subsystem clock added

µ

PD789046

PD789026

PD789088

PD789074

PD789014

PD789062

PD789052

42-/44-pin

PD789014 with enhanced timer function and expanded ROM and RAM

30-pin

28-pin

PD789074 with enhanced timer function and expanded ROM and RAM

PD789026 with enhanced timer function

µ

On-chip UART and capable of low-voltage (1.8 V) operation

20-pin

RC oscillation version of PD789052

µ

PD789860 without EEPROM^TM, POC, and LVI

Small-scale package, general-purpose applications and A/D function

PD789177Y

µ

PD789167 with 10-bit A/D

44-pin

30-pin

µ

PD789177

PD789167

PD789156

PD789146

PD789134A

PD789124A

PD789114A

PD789104A

µ

PD789104A with enhanced timer

PD789146 with 10-bit A/D

PD789167Y

µ

PD789104A with EEPROM^TMadded

PD789124A with 10-bit A/D

µ

RC oscillation version of PD789104A

µ

PD789104A with 10-bit A/D

PD789026 with 8-bit A/D and multiplier added

µ

LCD drive

144-pin

88-pin

80-pin

µ

PD789835

UART + 8-bit A/D + dot LCD (total display outputs: 96)

UART + dot LCD (40 × 16)

SIO + 10-bit A/D + internal voltage boosting method LCD (28 × 4)

SIO + 8-bit A/D + resistance division method LCD (28 × 4)

PD789830

PD789489

PD789479

PD789417A

PD789407A

PD789456

PD789446

PD789436

PD789426

PD789316

PD789306

PD789467

PD789327

80-pin

µ

PD789407A with 10-bit A/D

SIO + 8-bit A/D + resistance division method LCD (28 × 4)

PD789446 with 10-bit A/D

SIO + 8-bit A/D + internal voltage boosting method LCD (15 × 4)

78K/0S

Series

80-pin

64-pin

µ

PD789426 with 10-bit A/D

SIO + 8-bit A/D + internal voltage boosting method LCD (5 × 4)

RC oscillation version of PD789306

µ

SIO + internal voltage boosting method LCD (24 × 4)

8-bit A/D + internal voltage boosting method LCD (23 × 4)

SIO + resistance division method LCD (24 × 4)

64-pin

52-pin

µ

USB

44-pin

µ

PD789800

For PC keyboard. On-chip USB function

Inverter control

µ

PD789842

44-pin

30-pin

On-chip inverter controller and UART

On-chip CAN controller

On-chip bus controller

PD789850

µ

Keyless entry

30-pin

20-pin

µ

PD789860 with enhanced timer function, SIO, and expanded ROM and RAM

RC oscillation version of PD789860

PD789862

PD789861

PD789860

µ

On-chip POC and key return circuit

VFD drive

µ

PD789871

52-pin

On-chip VFD controller (total display outputs: 25)

Meter control

µ

PD789881

64-pin

UART + resistance division method LCD (26 × 4)

Remark VFD (Vacuum Fluorescent Display) is referred to as FIP^TM(Fluorescent Indicator Panel) in some

documents, but the functions of the two are same.

User’s Manual U12978EJ3V3UD

24

CHAPTER 1 GENERAL

The major differences between subseries are shown below.

Series for General-Purpose and LCD Drive

Function

ROM

Capacity

(Bytes)

Timer

8-Bit 10-Bit

Serial Interface

I/O

VDD

Remarks

A/D

Subseries

8-Bit 16-Bit Watch WDT

MIN.Value

Small-

scale

µPD789046

16 K

1 ch 1 ch 1 ch 1 ch

−

1 ch (UART: 1ch)

34

24

1.8 V

−

µPD789026

µPD789088

µPD789074

µPD789014

µPD789062

4Kto16K

−

package,

general-

purpose

applica-

tions

16 K to 32 K 3 ch

2 K to 8 K 1 ch

2 K to 4 K 2 ch

4 K

−

22

14

−

RC-oscillation

version

µPD789052

µPD789177

µPD789167

µPD789156

µPD789146

−

Small-

scale

16 K to 24 K 3 ch 1 ch 1 ch

1ch

−

8 ch

−

8 ch 1 ch (UART: 1ch)

31

20

1.8 V

−

4 ch

−

package,

general-

purpose

applica-

tions +

A/D

8 K to 16 K 1 ch

−

On-chip

EEPROM

4 ch

−

µPD789134A 2 K to 8 K

µPD789124A

4 ch

−

RC-oscillation

version

4 ch

−

converter

µPD789114A

4 ch

−

µPD789104A

4 ch

LCD

drive

µPD789835

µPD789830

µPD789489

µPD789479

24 K to 60 K 6 ch

−

1 ch 1 ch 3 ch

−

1 ch (UART: 1ch)

37 1.8 V^NoteDot LCD

supported

24 K

1 ch 1 ch

−

30 2.7 V

32 K to 48 K 3 ch

24 K to 48 K

8 ch 2 ch (UART: 1ch)

45 1.8 V

−

8 ch

−

µPD789417A 12 K to 24 K

µPD789407A

7 ch 1 ch (UART: 1ch)

43

30

40

23

7 ch

−

µPD789456

µPD789446

µPD789436

µPD789426

µPD789316

12 K to 16 K 2 ch

6 ch

−

6 ch

−

8 K to 16 K

4 K to 24 K

2 ch (UART: 1ch)

RC-oscillation

version

µPD789306

µPD789467

µPD789327

−

1 ch

−

18

21

−

1 ch

Note Flash memory version: 3.0 V

User’s Manual U12978EJ3V3UD

25

CHAPTER 1 GENERAL

Series for ASSP

Function

ROM

Capacity

(Bytes)

Timer

8-Bit 16-Bit Watch WDT

8-Bit 10-Bit

Serial Interface

I/O

VDD

Remarks

A/D

Subseries

USB

MIN.Value

µPD789800

µPD789842

8 K

2 ch

−

1 ch

−

2 ch (USB: 1ch)

1 ch (UART: 1ch)

31 4.0 V

30 4.0 V

−

Inverter

control

8 K to 16 K 3 ch Note 1 1 ch 1 ch 8 ch

On-chip

bus

µPD789850

16 K

4 K

1 ch 1 ch

−

1 ch 4 ch

−

2 ch (UART: 1ch) 18 4.0 V

−

controller

Keyless µPD789861

entry

2 ch

−

1 ch

−

14 1.8 V

RC-oscillation

version,

on-chip

EEPROM

µPD789860

µPD789862

On-chip

EEPROM

16 K

1 ch 2 ch

1 ch (UART: 1ch) 22

VFD

drive

µPD789871

4 K to 8 K 3 ch

−

1 ch 1 ch

1 ch

−

1 ch

33 2.7 V

−

Meter

µPD789881

16 K 2 ch 1 ch

−

1 ch (UART: 1 ch) 28 2.7 V^{Note 2}

control

Notes 1. 10-bit timer: 1 channel

2. Flash memory version: 3.0 V

User’s Manual U12978EJ3V3UD

26

CHAPTER 1 GENERAL

1.6 Block Diagram

KR00 to KR07

Key return 0

8-bit timer 00

Port 0

Port 1

Port 2

Port 4

P00 to P07

P10 to P17

P20 to P26

P40 to P47

ROM

Flash

memory

78K/0S

CPU

core

8-bit timer/event

counter 01

TI01/TO01/P26/INTP0

Watchdog timer

REGC

Regulator

VREG

RAM

USBDM

USBDP

USB

function 0

RESET

X1

X2

System control

SCK10/P20

SO10/P21

SI10/P22

Serial

interface 1

VDD0

VDD1

VSS0

V

SS1 IC

Interrupt

control

INTP0/P26

(V^PP

)

Remark The parenthesized values apply to the µPD78F9801.

User’s Manual U12978EJ3V3UD

27

CHAPTER 1 GENERAL

1.7 Functions

µPD789800

µPD78F9801

Product

Item

Internal memory

ROM

Mask ROM

Flash memory

16 KB

8 KB

High-speed RAM

256 bytes

0.33 µs/1.33 µs (at 6.0 MHz operation with system clock)

Minimum instruction execution time

Instruction set

• 16-bit operation

• Bit manipulation (set, reset, and test) etc.

I/O ports

CMOS I/O

31

(Of the above COMS I/O ports, 18 ports can be switched to N-ch open-drain

I/O ports.)

Serial interface

Timer

• USB (Universal Serial Bus) function: 1 channel

• Three-wired serial I/O mode:

1 channel

• 8-bit timer:

1 channel

• 8-bit timer/event counter:1 channel

• Watchdog timer:

1 channel

Incorporated (V^REG= 3.3 0.3 V)

Internal: 9, external: 2

Regulator

Vector interrupt

sources

Maskable

Non-maskable

Internal: 1

Power supply voltage

VDD = 4.0 to 5.5 V

• T^A= –40 to +85°C (when the USB is not operating)

• T^A= 0 to +70°C (when the USB is operating)

• T^A= 10 to 40°C (when a flash memory is written)

Operating ambient temperature

44-pin plastic LQFP (10 × 10)

Package

An outline of the timer is shown below.

8-Bit Timer 00

8-Bit Timer/

Watchdog Timer

Event Counter 01

Operation mode

Function

Interval timer

1 channel

1 output

−

1 channel^Note

−

1

−

2

External event counter

Timer outputs

Square-wave outputs

Capture

Interrupt sources

1

Note The watchdog timer has watchdog timer and interval timer functions. However, use the watchdog timer by

selecting either the watchdog timer function or interval timer function.

User’s Manual U12978EJ3V3UD

28

CHAPTER 2 PIN FUNCTIONS

2.1 List of Pin Functions

(1) Port pins

Pin Name

I/O

Function

After Reset

Input

Alternate

Function

P00 to P07

I/O

Port 0

—

8-bit I/O port

Input/output can be specified in 1-bit units.

When used as an input port, use of on-chip pull-up resistors can be

specified by pull-up resistor option register 0 (PU0).

When used as an output port, CMOS output or N-ch open-drain

output can be specified in 8-bit units by port output mode register 0

(POM0).

P10 to P17

I/O

Port 1

Input

—

8-bit I/O port

Input/output can be specified in 1-bit units.

When used as an input port, use of on-chip pull-up resistors can be

specified by pull-up resistor option register 0 (PU0).

When used as an output port, CMOS output or N-ch open-drain

output can be specified in 8-bit units by port output mode register 0

(POM0).

P20

I/O

Port 2

Input

SCK10

7-bit I/O port

P21

SO10

SI10

Input/output can be specified in 1-bit units.

P22

When used as an input port, use of on-chip pull-up resistors can be

specified by pull-up resistor option register 0 (PU0).

P23 to P25

P26

—

When P25 or P26 is used as an output port, CMOS output or N-ch

open-drain output can be specified in 1-bit units by port output mode

register 1 (POM1).

INTP0/TI01/TO01

KR00 to KR07

P40 to P47

I/O

Port 4

Input

8-bit I/O port

Input/output can be specified in 1-bit units.

When used as an input port, use of on-chip pull-up resistors can be

specified by pull-up resistor option register 0 (PU0).

User’s Manual U12978EJ3V3UD

29

CHAPTER 2 PIN FUNCTIONS

(2) Non-port pins

Pin Name

I/O

Function

After Reset

Input

Alternate

Function

INTP0

Input

External interrupt request input for which valid edge (rising

and/or falling edge) can be specified

P26/TI01/TO01

KR00 to

KR07

Input

Input for detecting key return signals

Input

P40 to P47

NC

—

No connection. Can be left open.

—

REGC

Internally generated power supply for driving USB

driver/receiver. Connect this pin to V^SSvia a 22 µF capacitor.

RESET

SCK10

SI10

Input

System reset input

Input

—

I/O

Serial clock input/output for serial interface

Serial data input for serial interface

Serial data output for serial interface

External count clock input to 8-bit timer TM01

Output from 8-bit timer TM01

P20

Input

Output

Input

Output

I/O

P22

SO10

TI01

P21

P26/INTP0/TO01

P26/INTP0/TI01

—

TO01

USBDM

Serial data input/output (negative side) for USB function. The

pull-up resistor (1.5 kΩ) for the USBDM pin must be connected

to the REGC pin.

USBDP

VDD0

VDD1

VSS0

VSS1

X1

I/O

—

Serial data input/output (positive side) for USB function

Positive power supply for ports

Input

—

Positive power supply for circuits other than ports

Ground potential for ports

—

Ground potential for circuits other than ports

Crystal resonator connection to for system clock oscillator

—

Input

—

Input

—

X2

—

IC

—

Internally connected directly to VSS0

—

VPP

—

Sets flash memory programming mode. Apply high voltage

when a program is written or verified.

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CHAPTER 2 PIN FUNCTIONS

2.2 Pin Functions

2.2.1 P00 to P07 (Port 0)

These pins constitute an 8-bit I/O port and can be set to the input or output port mode in 1-bit units by using port

mode register 0 (PM0). When these pins are used as an input port, an on-chip pull-up resistor can be used by setting

pull-up resistor option register 0 (PU0). When these pins are used as an output port, CMOS output or N-ch open-

drain output can be specified in 8-bit units by setting port output mode register 0 (POM0).

2.2.2 P10 to P17 (Port 1)

These pins constitute an 8-bit I/O port. Port 1 can be set to the input or output mode in 1-bit units by using port

mode register 1 (PM1). When the port is used as an input port, an on-chip pull-up resistor can be used by setting

pull-up resistor option register 0 (PU0). When these pins are used as an output port, CMOS output or N-ch open-

drain output can be specified in 8-bit units by setting port output mode register 0 (POM0).

2.2.3 P20 to P26 (Port 2)

These pins constitute a 7-bit I/O port. In addition, these pins function as data I/O, and clock I/O to and from the

serial interface, external interrupt input, and timer I/O.

Port 2 can be specified in the following operation modes in 1-bit units.

(1) Port mode

In the port mode, P20 to P26 function as a 7-bit I/O port. Port 2 can be set to the input or output mode in 1-bit

units by using port mode register 2 (PM2). When the port is used as an input port, an on-chip pull-up resistor can

be used by setting pull-up resistor option register 0 (PU0). When P25 or P26 is used as an output port, CMOS

output or N-ch open-drain output can be specified by setting in 1-bit units port output mode register 1 (POM1).

(2) Control mode

In this mode, P20 to P26 function as the data I/O and the clock I/O to and from the serial interface.

(a) SI10, SO10

These are the serial data I/O pins of the serial interface.

(b) SCK10

This is the serial clock I/O pin of the serial interface.

(c) TI01

This is the external clock input pin for the 8-bit timer/event counter.

(d) TO01

This is the output pin of the 8-bit timer.

(e) INTP0

This is an external interrupt input pin for which the valid edge (rising edge, falling edge, or both rising and

falling edges) can be specified.

Caution

When using P20 to P26 as serial interface pins, the I/O mode and output latch must be set

according to the functions to be used. For setting details, see Table 9-2.

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CHAPTER 2 PIN FUNCTIONS

2.2.4 P40 to P47 (Port 4)

These pins constitute an 8-bit I/O port. In addition, they also function as key return signal detection pins.

The following operation modes can be specified in 1-bit units.

(1) Port mode

In this mode, port 4 functions as an 8-bit I/O port. Port 4 can be set to the input or output mode in 1-bit units by

using port mode register 4 (PM4). When used as an input port an on-chip pull-up resistor can be used by setting

pull-up resistor option register 0 (PU0).

(2) Control mode

In this mode, the pins function as key return signal detection pins (KR00 to KR07).

2.2.5 RESET

This pin inputs an active-low system reset signal.

2.2.6 X1, X2

These pins are used to connect a crystal resonator for system clock oscillation.

To supply an external clock, input the clock to X1 and input the inverted signal to X2.

2.2.7 REGC

This pin is a power supply pin for driving a USB driver/receiver generated internally. Connect this pin to the V^SS

pin via 22 µF capacitor.

2.2.8 USBDM

This pin (negative side) inputs or outputs serial data for the USB function.

2.2.9 USBDP

This pin (positive side) inputs or outputs serial data for the USB function.

2.2.10 V^DD0, VDD1

These pins are positive power supply pins.

2.2.11 V^SS0, VSS1

These pins are ground pins.

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CHAPTER 2 PIN FUNCTIONS

2.2.12 VPP (µPD78F9801 only)

A high voltage should be applied to this pin when the flash memory programming mode is set and when the

program is written or verified.

Handle this pin in either of the following ways.

• Independently connect a 10 kΩ pull-down resistor.

• Switch this pin to be directly connected to the dedicated flash programmer in programming mode or to V^SS0in

normal operation mode using a jumper on the board.

2.2.13 IC (mask ROM version only)

The IC (Internally Connected) pin is used to set the µPD789800 Subseries in the test mode before shipment. In

the normal operation mode, directly connect this pin to the VSS0 pin with as short a wiring length as possible.

If a potential difference is generated between the IC pin and V^SS0pin due to a long wiring length between the IC pin

and V^SS0pin or an external noise superimposed on the IC pin, a user program may not run correctly.

• Directly connect the IC pin to the V^SS0pin.

V

^SS0IC

Keep short

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CHAPTER 2 PIN FUNCTIONS

2.3 Pin I/O Circuits and Recommended Connection of Unused Pins

Table 2-1 lists the types of I/O circuits for each pin and explains how unused pins are handled.

Figure 2-1 shows the configuration of each type of I/O circuit.

Table 2-1. Type of Pin I/O Circuit Recommended Connection of Unused Pins

Pin Name

P00 to P07

I/O Circuit Type

5-R

I/O

Recommended Connection of Unused Pins

Input:

Independently connect to V^DD0, VDD1, VSS0, or VSS1 via a

resistor.

P10 to P17

P20/ SCK10

Output: Leave open.

8-C

P21/SO10

P22/SI10

P23, P24

P25

8-F

P26/INTP0/TI01/TO01

P40/ KR00 to

P47/ KR07

8-C

USBDM

USBDP

RESET

24-A

Connect to the REGC pin.

Independently connect to VSS0 or VSS1 via a resistor.

—

2

Input

—

NC

—

Leave open.

REGC

—

Connect to USBDM pin.

Connect directly to VSS0.

IC

—

Independently connect a 10 kΩ pull-down resistor, or connect directly to

VPP

V^SS0.

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CHAPTER 2 PIN FUNCTIONS

Figure 2-1. Pin I/O Circuits

Type 2

Type 8-F

V

DD0

Pull-up

enable

P-ch

cut

V

DD0

IN

Output

data

P-ch

IN/OUT

Schmitt-triggered input with hysteresis characteristics

Output

disable

N-ch

V

SS0

Type 5-R

Type 24-A

V

DD0

Pull-up

enable

P-ch

V

REG

P-ch

cut

V

DD0

TXDXP

RXDX

P-ch

Output

data

P-ch

IN/OUT

N-ch

TXDXN

Output

disable

N-ch

V

SS0

V

SS0

Input

enable

Type 8-C

V

DD0

Pull-up

enable

P-ch

VDD0

Output

data

P-ch

IN/OUT

Output

disable

N-ch

VSS0

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CHAPTER 3 CPU ARCHITECTURE

3.1 Memory Space

The µPD789800 Subseries can access 64 KB of memory space.

Figures 3-1 and 3-2 show the memory maps.

Figure 3-1. Memory Map (µPD789800)

F F F F H

Special function register

256 × 8 bits

F F 0 0 H

F E F F H

Internal high-speed RAM

256 × 8 bits

F E 0 0 H

F D F F H

Data memory

space

Reserved

1 F F F H

2 0 0 0 H

1 F F F H

Program area

0 0 8 0 H

0 0 7 F H

Internal ROM

8,192 × 8 bits

Program memory

space

CALLT table area

Program area

0 0 4 0 H

0 0 3 F H

0 0 1 A H

0 0 1 9 H

Vector table area

0 0 0 0 H

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CHAPTER 3 CPU ARCHITECTURE

Figure 3-2. Memory Map (µPD78F9801)

F F F F H

Special function register

256 × 8 bits

F F 0 0 H

F E F F H

Internal high-speed RAM

256 × 8 bits

F E 0 0 H

F D F F H

Data memory

space

Reserved

3 F F F H

4 0 0 0 H

3 F F F H

Program area

0 0 8 0 H

0 0 7 F H

Flash memory

16,384 × 8 bits

Program memory

space

CALLT table area

Program area

0 0 4 0 H

0 0 3 F H

0 0 1 A H

0 0 1 9 H

Vector table area

0 0 0 0 H

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CHAPTER 3 CPU ARCHITECTURE

3.1.1 Internal program memory space

The internal program memory space stores programs and table data. This space is usually addressed by the

program counter (PC).

The following areas are allocated to the internal program memory space.

(1) Vector table area

A 26-byte area of addresses 0000H to 0019H is reserved as a vector table area. This area stores program start

addresses to be used when branching by RESET input or interrupt request generation. Of a 16-bit program

address, the lower 8 bits are stored in an even address, and the higher 8 bits are stored in an odd address.

Table 3-1. Vector Table

Vector Table Address

0000H

Interrupt Request

RESET input

Vector Table Address

000EH

Interrupt Request

INTUSBRE

0004H

0006H

0008H

000AH

000CH

INTWDT

0010H

0012H

0014H

0016H

0018H

INTP0

INTUSBTM

INTUSBRT

INTUSBRD

INTUSBST

INTCSI10

INTTM00

INTTM01

INTKR00

(2) CALLT instruction table area

The subroutine entry address of a 1-byte call instruction (CALLT) can be stored in a 64-byte area of addresses

0040H to 007FH.

3.1.2 Internal data memory (internal high-speed RAM) space

An internal high-speed RAM is incorporated in the area between FE00H and FEFFH.

The internal high-speed RAM is also used as a stack.

3.1.3 Special function register (SFR) area

Special function registers (SFRs) of on-chip peripheral hardware are allocated to an area of FF00H to FFFFH (see

Table 3-2).

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CHAPTER 3 CPU ARCHITECTURE

3.1.4 Data memory addressing

The µPD789800 Subseries provides a variety of addressing modes which take account of memory manipulability,

etc. Especially at addresses corresponding to data memory area (FE00H to FFFFH), particular addressing modes are

possible to meet the functions of the special function registers (SFR) and general-purpose registers. Figures 3-3 and

3-4 show the data memory addressing modes.

Figure 3-3. Data Memory Addressing (µPD789800)

FFFFH

Special function registers (SFR)

SFR addressing

256 × 8 bits

FF20H

FF1FH

FF00H

FEFFH

Short direct

Internal high-speed RAM

addressing

256 × 8 bits

FE20H

FE1FH

FE00H

FDFFH

Direct addressing

Register indirect

addressing

Reserved

Based addressing

2000H

1FFFH

Internal ROM

8,192 × 8 bits

0000H

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CHAPTER 3 CPU ARCHITECTURE

Figure 3-4. Data Memory Addressing (µPD78F9801)

FFFFH

Special function registers (SFR)

SFR addressing

256 × 8 bits

FF20H

FF1FH

FF00H

FEFFH

Short direct

addressing

Internal high-speed RAM

256 × 8 bits

FE20H

FE1FH

FE00H

FDFFH

Direct addressing

Register indirect

addressing

Based addressing

Reserved

4000H

3FFFH

Flash memory

16,384 × 8 bits

0000H

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CHAPTER 3 CPU ARCHITECTURE

3.2 Processor Registers

The µPD789800 Subseries provides the following on-chip processor registers.

3.2.1 Control registers

The control registers contain special functions to control the program sequence, statuses and stack memory. A

program counter, a program status word, and a stack pointer are the control registers.

(1) Program counter (PC)

The program counter is a 16-bit register which holds the address information of the next program to be executed.

In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to

be fetched. When a branch instruction is executed, immediate data or register contents are set.

RESET input sets the program counter to the reset vector table values at addresses 0000H and 0001H.

Figure 3-5. Configuration of Program Counter

15

0

PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

(2) Program status word (PSW)

The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution.

Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW

instruction execution and are automatically restored upon execution of the RETI and POP PSW instructions.

RESET input sets the PSW to 02H.

Figure 3-6. Configuration of Program Status Word

7

0

IE

Z

0

AC

0

1

CY

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CHAPTER 3 CPU ARCHITECTURE

(a) Interrupt enable flag (IE)

This flag controls interrupt request acknowledgment operations of the CPU.

When 0, the IE flag is set to the interrupt disabled status (DI), and interrupt requests other than non-

maskable interrupts are all disabled.

When 1, the IE flag is set to the interrupt enabled status (EI). Interrupt request acknowledgment enable is

controlled by the interrupt mask flag corresponding to each interrupt source.

The IE flag is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI

instruction execution.

(b) Zero flag (Z)

When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.

(c) Auxiliary carry flag (AC)

If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other

cases.

(d) Carry flag (CY)

This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value

upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction

execution.

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CHAPTER 3 CPU ARCHITECTURE

(3) Stack pointer (SP)

This is a 16-bit register that holds the start address of the memory stack area. Only the internal high-speed RAM

area can be set as the stack area.

Figure 3-7. Configuration of Stack Pointer

15

0

SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0

The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restore) from

the stack memory.

Each stack operation saves/restores data as shown in Figures 3-8 and 3-9.

Caution

Since RESET input makes the SP contents undefined, be sure to initialize the SP before

instruction execution.

Figure 3-8. Data to Be Saved to Stack Memory

Interrupt

PUSH rp

instruction

CALL, CALLT

instructions

_

SP SP

SP

3

2

1

_

SP SP

2

SP SP

SP

2

1

PC7 to PC0

PC15 to PC8

PSW

Lower half

register pairs

_

SP

2

1

SP

PC7 to PC0

Upper half

register pairs

SP

PC15 to PC8

SP

Figure 3-9. Data to Be Restored from Stack Memory

POP rp

RET instruction

RETI instruction

instruction

Lower half

register pairs

SP

SP + 1

PC7 to PC0

SP

SP + 1

PC7 to PC0

PC15 to PC8

PSW

Upper half

register pairs

PC15 to PC8

SP + 1

SP SP + 2

SP + 2

SP SP + 3

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CHAPTER 3 CPU ARCHITECTURE

3.2.2 General-purpose registers

The general-purpose registers consist of eight 8-bit registers (X, A, C, B, E, D, L, and H).

In addition that each register can be used as an 8-bit register, two 8-bit registers in pairs can be used as a 16-bit

register (AX, BC, DE, and HL).

They can be described in terms of functional names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute

names (R0 to R7 and RP0 to RP3).

Figure 3-10. Configuration of General-Purpose Registers

(a) Absolute names

16-bit processing

RP3

8-bit processing

R7

R6

R5

R4

RP2

RP1

RP0

R3

R2

R1

R0

15

0

7

0

(b) Functional names

16-bit processing

HL

8-bit processing

H

L

D

E

DE

BC

AX

B

C

A

X

15

0

7

0

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CHAPTER 3 CPU ARCHITECTURE

3.2.3 Special function registers (SFRs)

Unlike general-purpose registers, each special function register has a special function.

The special function registers are allocated in the 256-byte area FF00H to FFFFH.

The special function registers can be manipulated, like the general-purpose registers, with operation, transfer, and

bit manipulation instructions. Manipulatable bit units (1, 8, and 16) differ depending on the special function register

type.

Each manipulation bit can be specified as follows.

• 1-bit manipulation

Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). This

manipulation can also be specified using address.

• 8-bit manipulation

Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). This

manipulation can also be specified using an address.

• 16-bit manipulation

Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand. When

specifying an address, describe an even address.

Table 3-2 lists the special function registers. The meanings of the symbols in this table are as follows.

• Symbol

Indicates the address of the implemented special function register. The symbols shown in this column are

reserved words in the assembler, and have already been defined in the header file “sfrbit.h” in the C compiler.

Therefore, these symbols can be used as instruction operands if an assembler or integrated debugger is used.

• R/W

Indicates whether the special function register in question can be read or written.

R/W: Read/write

R:

Read only

Write only

W:

• Bit units for manipulation

Indicates the bit units (1, 8, 16) in which the special function register in question can be manipulated.

• After reset

Indicates the status of the special function register when the RESET signal is input.

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CHAPTER 3 CPU ARCHITECTURE

Table 3-2. Special Function Register List (1/3)

Address

Special Function Register (SFR) Name

Symbol

R/W

Manipulatable Bit Unit

After Reset

00H

1 Bit

8 Bits

16 Bits

√

FF00H

FF01H

FF02H

FF04H

FF07H

FF08H

FF09H

FF0AH

FF0BH

FF0CH

FF0DH

FF0EH

FF0FH

FF10H

FF14H

Port 0

P0

P1

P2

P4

—

√

Port 1

√

Port 2

√

Port 4

Receive data PID

USBRD

R

—

√

Note

Undefined

Receive data address 0

Receive data address 1

Receive data address 2

Receive data address 3

Receive data address 4

Receive data address 5

Receive data address 6

Receive data address 7

Transmit/receive shift register 10

USBR0 USBR10

USBR1

Note

√

USBR2 USBR32

USBR3

USBR4 USBR54

USBR5

USBR6 USBR76

USBR7

SIO10

R/W

—

Note

√

Handshake packet transmit reservation

register

HTX

RSV

USB

CON

00H

√

FF15H

Data packet transmit reservation register

DTX

RSV

√

FF20H

FF21H

FF22H

FF24H

FF30H

FF31H

FF42H

FF50H

FF51H

FF53H

FF54H

FF55H

FF57H

FF60H

FF61H

Port mode register 0

PM0

—

FFH

00H

Port mode register 1

PM1

√

Port mode register 2

PM2

√

Port mode register 4

PM4

√

Port output mode register 0

Port output mode register 1

Timer clock select register 2

8-bit compare register 00

8-bit timer counter 00

POM0

POM1

TCL2

CR00

TM00

TMC00

CR01

TM01

TMC01

√

—

√

W

R

Undefined

00H

8-bit timer mode control register 00

8-bit compare register 01

8-bit timer counter 01

R/W

W

—

√

Undefined

00H

R

8-bit timer mode control register 01

Token PID compare register

Token address compare register

R/W

W

TIDCMP

—

ADRCMP

Note 16-bit access is possible only in short direct addressing.

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CHAPTER 3 CPU ARCHITECTURE

Table 3-2. Special Function Register List (2/3)

Address

Special Function Register (SFR) Name

Symbol

R/W

Manipulatable Bit Unit

After Reset

1 Bit

8 Bits

16 Bits

√

FF62H

FF63H

FF64H

Token packet receive result store register

Data/handshake PID compare register

TRXRSL

DIDCMP

DRXCON

R/W

W

—

00H

C3H

18H

—

Data/handshake packet receive byte

number counter

√

FF65H

FF66H

Data/handshake packet receive result store

register

DRXRSL

URXMOD

R/W

—

00H

Data/handshake packet receive mode

register

√

FF67H

FF68H

FF69H

FF6AH

FF6BH

FF6CH

FF6DH

FF72H

FFA1H

FFA2H

FFA3H

FFA4H

FFA5H

FFA6H

FFA7H

FFA8H

FFA9H

FFABH

FFACH

FFADH

FFAEH

FFAFH

FFB0H

FFB1H

FFB2H

FFB3H

FFB5H

FFB6H

FFB7H

FFE0H

FFE1H

FFE4H

FFE5H

Packet receive status register

Data packet transmit byte number counter 0

Data packet transmit byte number counter 1

Remote wakeup control register

Transmit/receive pointer

RXSTAT

DTXCO0

DTXCO1

REMWUP

USBPOW

USBTCL

USBMOD

CSIM10

USBTD0

USBT00

USBT01

USBT02

USBT03

USBT04

USBT05

USBT06

USBT07

USBTD1

USBT10

USBT11

USBT12

USBT13

USBT14

USBT15

USBT16

USBT17

USBRTP

USBRAL

USBRAH

IF0

—

√

—

W

20H

30H

08H

00H

01H

00H

R/W

R

—

√

USB timer start reservation control register

USB receiver enable register

Serial operation mode register 10

Transmit data PID bank 0

R/W

√

W

—

√

Undefined

Transmit data bank 0 address 00

Transmit data bank 0 address 01

Transmit data bank 0 address 02

Transmit data bank 0 address 03

Transmit data bank 0 address 04

Transmit data bank 0 address 05

Transmit data bank 0 address 06

Transmit data bank 0 address 07

Transmit data PID bank 1

Transmit data bank 1 address 10

Transmit data bank 1 address 11

Transmit data bank 1 address 12

Transmit data bank 1 address 13

Transmit data bank 1 address 14

Transmit data bank 1 address 15

Transmit data bank 1 address 16

Transmit data bank 1 address 17

Receive token PID

R

00H

FFH

Receive token address L

Receive token address H

Interrupt request flag register 0

Interrupt request flag register 1

Interrupt mask flag register 0

R/W

√

IF1

√

MK0

√

Interrupt mask flag register 1

MK1

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CHAPTER 3 CPU ARCHITECTURE

Table 3-2. Special Function Register List (3/3)

Address

Special Function Register (SFR) Name

Symbol

R/W

Manipulatable Bit Unit

After Reset

00H

1 Bit

8 Bits

16 Bits

√

FFECH

FFF5H

FFF7H

FFF9H

FFFAH

FFFBH

External interrupt mode register 0

Key return mode register 00

INTM0

—

√

—

KRM00

PU0

√

Pull-up resistor option register 0

Watchdog timer mode register

Oscillation stabilization time select register

Processor clock control register

√

WDTM

OSTS

PCC

—

√

04H

02H

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CHAPTER 3 CPU ARCHITECTURE

3.3 Instruction Address Addressing

An instruction address is determined by program counter (PC) contents. PC contents are normally incremented

(+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another

instruction is executed. When a branch instruction is executed, the branch destination information is set to the PC

and branched by the following addressing (for details of each instruction, refer to 78K/0S Series Instruction User’s

Manual (U11047E)).

3.3.1 Relative addressing

[Function]

The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start

address of the following instruction is transferred to the program counter (PC) and branched. The displacement

value is treated as signed two’s complement data (−128 to +127) and bit 7 becomes a sign bit.

This means that information is relatively branched to a location between −128 and +127, from the start address

of the next instruction when relative addressing is used.

This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.

[Illustration]

15

0

...

PC is the start address of

the next instruction of

a BR instruction.

PC

+

8

7

6

α

S

jdisp8

15

0

PC

When S = 0, α indicates all bits 0.

When S = 1, α indicates all bits 1.

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CHAPTER 3 CPU ARCHITECTURE

3.3.2 Immediate addressing

[Function]

Immediate data in the instruction word is transferred to the program counter (PC) and branched.

This function is carried out when the CALL !addr16 or BR !addr16 instruction is executed.

The CALL !addr16 and BR !addr16 instructions can be branched to any location in the memory space.

[Illustration]

In case of CALL !addr16 and BR !addr16 instructions

7

0

CALL or BR

Low Addr.

High Addr.

15

8 7

0

PC

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CHAPTER 3 CPU ARCHITECTURE

3.3.3 Table indirect addressing

[Function]

Table contents (branch destination address) of the particular location to be addressed by the lower-5-bit

immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and

branched.

This function is carried out when the CALLT [addr5] instruction is executed. The instruction enables a branch

to any location in the memory space by referring to the addresses stored in the memory table at 40H to 7FH.

[Illustration]

7

6

1

5

1

0

Instruction code

Effective address

0

ta4–0

15

8

0

7

0

6

1

5

1

0

7

Memory (Table)

Low Addr.

0

High Addr.

Effective address + 1

15

8

7

0

PC

3.3.4 Register addressing

[Function]

Register pair (AX) contents to be specified with an instruction word are transferred to the program counter

(PC) and branched.

This function is carried out when the BR AX instruction is executed.

[Illustration]

7

0

8

7

0

rp

A

X

15

PC

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CHAPTER 3 CPU ARCHITECTURE

3.4 Operand Address Addressing

The following methods are available to specify the register and memory (addressing) to undergo manipulation

during instruction execution.

3.4.1 Direct addressing

[Function]

The memory indicated by immediate data in an instruction word is directly addressed.

[Operand format]

Identifier

addr16

Description

Label or 16-bit immediate data

[Description example]

MOV A, !FE00H; When setting !addr16 to FE00H

Instruction code

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Opcode

00H

FEH

[Illustration]

7

0

Opcode

addr16 (Low)

addr16 (High)

Memory

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CHAPTER 3 CPU ARCHITECTURE

3.4.2 Short direct addressing

[Function]

The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.

The fixed space is the 256-byte space FE20H to FF1FH where the addressing is applied. An internal high-

speed RAM and special function registers (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH,

respectively.

The SFR area (FF00H to FF1FH), where short direct addressing is applied, is a part of the whole SFR area.

In this area, ports which are frequently accessed in a program and a compare register of the timer/event

counter are mapped, and these SFRs can be manipulated with a small number of bytes and clocks.

When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH,

bit 8 is set to 1. See [Illustration] below.

[Operand format]

Identifier

saddr

Description

Label or FE20H to FF1FH immediate data

saddrp

Label or FE20H to FF1FH immediate data (even address only)

[Description example]

MOV FE30H, #50H; When setting saddr to FE30H and the immediate data to 50H

Instruction code

1

0

1

0

1

0

1

0

1

0

1

0

Opcode

30H (saddr-offset)

50H (Immediate data)

[Illustration]

7

0

Opcode

saddr-offset

Short direct memory

15

1

8

0

Effective

address

1

α

When 8-bit immediate data is 20H to FFH, α = 0.

When 8-bit immediate data is 00H to 1FH, α = 1.

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CHAPTER 3 CPU ARCHITECTURE

3.4.3 Special function register (SFR) addressing

[Function]

The memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction

word.

This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the

SFR mapped at FF00H to FF1FH can be accessed with short direct addressing.

[Operand format]

Identifier

sfr

Description

Special function register name

[Description example]

MOV PM0, A; When selecting PM0 for sfr

Instruction code

1

0

1

0

1

0

1

0

1

0

1

0

[Illustration]

7

0

Opcode

sfr-offset

SFR

15

1

8 7

0

Effective

Address

1

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CHAPTER 3 CPU ARCHITECTURE

3.4.4 Register addressing

[Function]

In the register addressing mode, general-purpose registers are accessed as operands. The general-purpose

register to be accessed is specified by the register specification code or function name in the instruction code.

Register addressing is carried out when an instruction with the following operand format is executed. When an

8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code.

[Operand format]

Identifier

Description

r

X, A, C, B, E, D, L, H

AX, BC, DE, HL

rp

r and rp can be described by absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C,

B, E, D, L, H, AX, BC, DE, and HL).

[Description example]

MOV A, C; When selecting the C register for r

Instruction code

0

1

0

1

0

1

0

1

Register specification code

INCW DE; When selecting the DE register pair for rp

Instruction code

1

0

1

0

Register specification code

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CHAPTER 3 CPU ARCHITECTURE

3.4.5 Register indirect addressing

[Function]

In the register indirect addressing mode, memory is manipulated according to the contents of a register pair

specified as an operand. The register pair to be accessed is specified by the register pair specification code in

an instruction code.

This addressing can be carried out for all the memory spaces.

[Operand format]

Identifier

—

Description

[DE], [HL]

[Description example]

MOV A, [DE]; When selecting register pair [DE]

Instruction code

0

1

0

1

0

1

[Illustration]

15

8

7

0

DE

D

E

Memory address

specified with

register pair DE

Addressed memory

contents are

transferred

7

0

A

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CHAPTER 3 CPU ARCHITECTURE

3.4.6 Based addressing

[Function]

8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is

used to address the memory. Addition is performed by expanding the offset data as a positive number to 16

bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces.

[Operand format]

Identifier

—

Description

[HL+byte]

[Description example]

MOV A, [HL+10H]; When setting byte to 10H

Instruction code

0

1

0

1

0

1

0

1

0

3.4.7 Stack addressing

[Function]

The stack area is indirectly addressed with the stack pointer (SP) contents.

This addressing method is automatically employed when the PUSH, POP, subroutine call, and RETURN

instructions are executed or the register is saved/reset upon generation of an interrupt request.

Stack addressing can only be used to address the internal high-speed RAM area.

[Description example]

In the case of PUSH DE

Instruction code

1

0

1

0

1

0

1

0

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CHAPTER 4 PORT FUNCTIONS

4.1 Port Functions

The µPD789800 Subseries provides the ports shown in Figure 4-1, enabling various methods of control.

Numerous other functions are provided that can be used in addition to the digital I/O port functions. For more

information on these additional functions, see CHAPTER 2 PIN FUNCTIONS.

Figure 4-1. Port Types

P20

P00

Port 2

Port 0

P26

P40

P07

P10

Port 4

Port 1

P47

P17

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CHAPTER 4 PORT FUNCTIONS

Table 4-1. Functions of Ports

Pin Name

I/O

Function

After Reset

Input

Alternate

Function

P00 to

P07

I/O

Port 0

—

8-bit I/O port

Input/output can be specified in 1-bit units.

When used as an input port, use of on-chip pull-up resistors can be

specified by pull-up resistor option register 0 (PU0).

When used as an output port, CMOS output or N-ch open-drain

output can be specified in 8-bit units by port output mode register 0

(POM0).

P10 to

P17

I/O

Port 1

Input

—

8-bit I/O port

Input/output can be specified in 1-bit units.

When used as an input port, use of on-chip pull-up resistors can be

specified by pull-up resistor option register 0 (PU0).

When used as an output port, CMOS output or N-ch open-drain

output can be specified in 8-bit units by port output mode register 0

(POM0).

SCK10

P20

P21

P22

P23

P24

P25

P26

I/O

Port 2

Input

7-bit I/O port

SO10

SI10

Input/output can be specified in 1-bit units.

When used as an input port, use of on-chip pull-up resistors can be

specified by pull-up resistor option register 0 (PU0).

—

When P25 or P26 is used as an output port, CMOS output or N-ch

open-drain output can be specified in 1-bit units by port output mode

register 1 (POM1).

INTP0/TI01/TO01

KR00 to KR07

P40 to

P47

I/O

Port 4

Input

8-bit I/O port

Input/output can be specified in 1-bit units.

When used as an input port, use of on-chip pull-up resistors can be

specified by pull-up resistor option register 0 (PU0).

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CHAPTER 4 PORT FUNCTIONS

4.2 Port Configuration

Ports consists the following hardware.

Table 4-2. Configuration of Port

Parameter

Configuration

Control registers

Port mode register (PMm: m = 0 to 2, 4)

Pull-up resistor option register (PU0)

Port output mode register (POMm: m = 0, 1)

Total: 31 (N-ch open-drain output is specifiable for 18 ports.)

Software control: 31

Ports

Pull-up resistors

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CHAPTER 4 PORT FUNCTIONS

4.2.1 Port 0

This is an 8-bit I/O port with an output latch. Port 0 can be specified in the input or output mode in 1-bit units by

using port mode register 0 (PM0). When the P00 to P07 pins are used as input port pins, on-chip pull-up resistors

can be connected in 8-bit units by using pull-up resistor option register 0 (PU0). CMOS output or N-ch open-drain

output can also be specified in 8-bit unit by using port output mode register 0 (POM0).

Port 0 is set in the input mode when the RESET signal is input.

Figure 4-2 shows a block diagram of port 0.

Figure 4-2. Block Diagram of P00 to P07

WRPOM0

POM00

PU00

V

DD0

WR^PU0

P-ch

RD

P00 to P07

VDD0

WRPORT

WRPM

P-ch

Output latch

(P00 to P07)

N-ch

PM00 to PM07

POM0:

PU0:

PM:

Port output mode register 0

Pull-up resistor option register 0

Port mode register

RD:

Port 0 read signal

WR:

Port 0 write signal

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CHAPTER 4 PORT FUNCTIONS

4.2.2 Port 1

This is an 8-bit I/O port with an output latch. Port 1 can be specified in the input or output mode in 1-bit units by

using port mode register 1 (PM1). When the P10 to P17 pins are used as input port pins, on-chip pull-up resistors

can be connected in 8-bit units by using pull-up resistor option register 0 (PU0). CMOS output or N-ch open-drain

output can also be specified in 8-bit unit by using port output mode register 0 (POM0).

Port 0 is set in the input mode when the RESET signal is input.

Figure 4-3 shows a block diagram of port 1.

Figure 4-3. Block Diagram of P10 to P17

WR^POM0

POM01

PU01

VDD0

WRPU0

P-ch

RD

P10 to P17

VDD0

WRPORT

WRPM

P-ch

Output latch

(P10 to P17)

N-ch

PM10 to PM17

POM0:

Port output mode register 0

Pull-up resistor option register 0

Port mode register

PU0:

PM:

RD:

Port 1 read signal

WR:

Port 1 write signal

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CHAPTER 4 PORT FUNCTIONS

4.2.3 Port 2

This is a 7-bit I/O port with an output latch. Port 2 can be specified in the input or output mode in 1-bit units by

using port mode register 2 (PM2). When using the P20 to P26 pins as input port pins, on-chip pull-up resistors can be

connected in 7-bit units by using pull-up resistor option register 0 (PU0).

When P25 or P26 is used, CMOS output or N-ch open-drain output can be specified in 1-bit units by using port

output mode register 1 (POM1).

The port is also used as a data I/O and clock I/O to and from the serial interface, timer I/O, and external interrupt.

This port to set to the input mode when the RESET signal is input.

Figures 4-4 through 4-9 show block diagrams of port 2.

Caution

When using the pins of port 2 as the serial interface, the I/O or output latch must be set

according to the function to be used. For how to set the latches, see Table 9-2.

Figure 4-4. Block Diagram of P20

VDD0

WR^PU0

PU02

P-ch

Alternate

function

RD

WR^PORT

Output latch

(P20)

P20/SCK10

WRPM

PM20

Alternate

function

PU0:

PM:

RD:

Pull-up resistor option register 0

Port mode register

Port 2 read signal

WR:

Port 2 write signal

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CHAPTER 4 PORT FUNCTIONS

Figure 4-5. Block Diagram of P21

VDD0

WR^PU0

PU02

P-ch

RD

WRPORT

WRPM

Output latch

(P21)

P21/SO10

PM21

Alternate

function

PU0:

PM:

RD:

Pull-up resistor option register 0

Port mode register

Port 2 read signal

WR:

Port 2 write signal

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CHAPTER 4 PORT FUNCTIONS

Figure 4-6. Block Diagram of P22

V

DD0

WR^PU0

PU02

P-ch

Alternate

function

RD

WR^PORT

Output latch

(P22)

P22/SI10

WRPM

PM22

PU0:

PM:

RD:

Pull-up resistor option register 0

Port mode register

Port 2 read signal

WR:

Port 2 write signal

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CHAPTER 4 PORT FUNCTIONS

Figure 4-7. Block Diagram of P23 and P24

V

DD0

WRPU0

PU02

P-ch

RD

WR^PORT

Output latch

(P23, P24)

P23, P24

WRPM

PM23, PM24

PU0:

PM:

RD:

Pull-up resistor option register 0

Port mode register

Port 2 read signal

WR:

Port 2 write signal

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CHAPTER 4 PORT FUNCTIONS

Figure 4-8. Block Diagram of P25

WR^POM1

POM125

PU02

V

DD0

WRPU0

P-ch

RD

V

DD0

P25

WRPORT

WRPM

P-ch

Output latch

(P25)

N-ch

PM25

POM1:

PU0:

PM:

Port output mode register 1

Pull-up resistor option register 0

Port mode register

RD:

Port 2 read signal

WR:

Port 2 write signal

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CHAPTER 4 PORT FUNCTIONS

Figure 4-9. Block Diagram of P26

WR^POM1

POM126

PU02

V

DD0

WRPU0

P-ch

RD

V

DD0

P26

WRPORT

WRPM

P-ch

Output latch

(P26)

N-ch

PM26

POM1:

PU0:

PM:

Port output mode register 1

Pull-up resistor option register 0

Port mode register

RD:

Port 2 read signal

WR:

Port 2 write signal

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CHAPTER 4 PORT FUNCTIONS

4.2.4 Port 4

This is an 8-bit I/O port with an output latch. Port 4 can be specified in the input or output mode in 1-bit units by

using port mode register 4 (PM4). When using P40 to P47 pins as input port pins, on-chip pull-up resistors can be

connected in 8-bit units by using pull-up resistor option register 0 (PU0).

The port is also used as a key return input.

This port is set in the input mode when the RESET signal is input.

Figure 4-10 shows a block diagram of port 4.

Caution

When using the pins of port 4 as the key return, key return mode register 00 (KRM00) must be

set according to the function to be used. For how to set the register, see Section 11.3 (5) Key

return mode register 00 (KRM00).

Figure 4-10. Block Diagram of P40 to P47

V

DD0

WR^PU0

PU04

P-ch

RD

WRKRM

KRM000 to

KRM007

WR^PORT

Output latch

(P40 to P47)

P40/KR00 to

P47/KR07

WRPM

PM40 to PM47

Alternate

function

KRM00: Key return mode register 00

PU0:

PM:

RD:

Pull-up resistor option register 0

Port mode register

Port 4 read signal

WR:

Port 4 write signal

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CHAPTER 4 PORT FUNCTIONS

4.3 Registers Controlling Port Function

The following three types of registers control the ports.

• Port mode registers (PM0, PM1, PM2, PM4)

• Pull-up resistor option register (PU0)

• Port output mode registers (POM0, POM1)

(1) Port mode registers (PM0, PM1, PM2, PM4)

These registers are used to set port input/output in 1-bit units.

The port mode registers are independently set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets registers to FFH.

When port pins are used as alternate-function pins, set the port mode register and output latch according to

Table 4-3.

Caution

As P26 can be used as an external interrupt input, when the port function output mode is

specified and the output level is changed, the interrupt request flag is set. When the output

mode is used, therefore, the interrupt mask flag should be set to 1 beforehand.

Figure 4-11. Format of Port Mode Register

Symbol

PM0

7

6

5

4

3

2

1

0

Address

FF20H

After reset

FFH

R/W

PM07 PM06 PM05 PM04 PM03 PM02 PM01 PM00

PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10

FF21H

FF22H

FFH

R/W

PM2

PM4

1

PM26 PM25 PM24 PM23 PM22 PM21 PM20

PM47 PM46 PM45 PM44 PM43 PM42 PM41 PM40

FF24H

FFH

R/W

Pmn pin input/output mode selection

PMmn

0

1

Output mode (output buffer on)

Input mode (output buffer off)

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CHAPTER 4 PORT FUNCTIONS

Table 4-3. Port Mode Register and Output Latch Settings When Using Alternate Functions

Secondary Function

Pin Name

PMxx

Pxx

Name

Input/Output

Output

P26

TO01

TI01

0

1

0

×

Input

INTP0

P40 to

P47^Note

KR00 to KR07

Note Set key return mode register 00 (KRM00) to 1 when using the alternate function (see Section 11.3 (5)

Key return mode register 00 (KRM00)).

Caution

When Port 2 is used as a serial interface pin, the I/O latch or output latch must be set

according to its function. For the setting method, see Table 9-2 Settings of Serial interface

10 Operating Mode.

Remark x:

Don’t care

PMxx: Port mode register

Pxx: Port output latch

(2) Pull-up resistor option register 0 (PU0)

The pull-up resistor option register (PU0) sets whether an on-chip pull-up resistor on each port is used or not.

On the port which is specified to use the on-chip pull-up resistor in the PU0, the pull-up resistor can be internally

used only for the bits set to the input mode. No on-chip pull-up resistors can be used for the bits set in the output

mode regardless of the setting PU0. This applies to the case when using the output pins for alternate functions.

PU0 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets PU0 to 00H.

Figure 4-12. Format of Pull-up Resistor Option Register 0

Symbol

PU0

7

0

6

0

5

0

<4>

3

0

<2> <1> <0>

PU02 PU01 PU00

Address

FFF7H

After reset

00H

R/W

PU04

PU0m

Pm on-chip pull-up resistor selection

(m = 0 to 2, 4)

0

1

On-chip pull-up resistor not connected

On-chip pull-up resistor connected

Caution

Bits 3 and 5 to 7 must be set to 0.

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CHAPTER 4 PORT FUNCTIONS

(3) Port output mode registers (POM0 and POM1)

The port output mode registers (POM0 and POM1) are used to switch from CMOS output to N-ch open-drain

output for port 0, port 1, pin P25, and pin P26.

Set POM0 and POM1 with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets P0M0 and POM1 to 00H.

Figure 4-13. Format of Port Output Mode Register 0

Symbol

POM0

7

0

6

0

5

0

4

0

3

0

2

0

<1> <0>

Address

FF30H

After reset

00H

R/W

POM01POM00

Pm output mode selection^Note

(m = 0, 1)

POM0m

0

1

CMOS output

N-ch open-drain output

Note POM0 selects the output mode for a port in 8-bit units.

Caution Bits 2 to 7 must be set to 0.

Figure 4-14. Format of Port Output Mode Register 1

Symbol

POM1

7

0

<6> <5>

4

0

3

0

2

0

1

0

Address

FF31H

After reset

00H

R/W

POM126 POM125

Output mode selection for bit n of port 2^Note

(n = 5, 6)

POM12n

0

1

CMOS output

N-ch open-drain output

Note POM1 selects the output mode for P25 or P26 in 1-bit units.

Caution Bits 0 to 4 and 7 must be set to 0.

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CHAPTER 4 PORT FUNCTIONS

4.4 Port Function Operation

The operation of a port differs depending on whether the port is set to the input or output mode, as described

below.

4.4.1 Writing to I/O port

(1) In output mode

A value can be written to the output latch of a port by using a transfer instruction. The contents of the output

latch can be output from the pins of the port.

The data once written to the output latch is retained until new data is written to the output latch.

(2) In input mode

A value can be written to the output latch by using a transfer instruction. However, the status of the port pin is

not changed because the output buffer is off.

The data once written to the output latch is retained until new data is written to the output latch.

Caution

A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port.

However, this instruction accesses the port in 8-bit units. When this instruction is

executed to manipulate a bit of an input/output port, therefore, the contents of the output

latch of the pin that is set to the input mode and not subject to manipulation become

undefined.

4.4.2 Reading from I/O port

(1) In output mode

The status of a pin can be read by using a transfer instruction. The contents of the output latch are not changed.

(2) In input mode

The status of a pin can be read by using a transfer instruction. The contents of the output latch are not changed.

4.4.3 Arithmetic operation of I/O port

(1) In output mode

An arithmetic operation can be performed on the contents of the output latch. The result of the operation is

written to the output latch. The contents of the output latch are output from the port pins.

The data once written to the output latch is retained until new data is written to the output latch.

(2) In input mode

The contents of the output latch become undefined. However, the status of the pin is not changed because the

output buffer is off.

Caution

A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port.

However, this instruction accesses the port in 8-bit units. When this instruction is

executed to manipulate a bit of an input/output port, therefore, the contents of the output

latch of the pin that is set to the input mode and not subject to manipulation become

undefined.

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CHAPTER 5 CLOCK GENERATOR

5.1 Clock Generator Functions

The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following type of

system clock oscillator is used.

• System clock oscillator

This circuit oscillates at 6.0 MHz. Oscillation can be stopped by executing the STOP instruction.

5.2 Clock Generator Configuration

The clock generator consists of the following hardware.

Table 5-1. Configuration of Clock Generator

Item

Control register

Oscillator

Configuration

Processor clock control register (PCC)

System clock oscillator

Figure 5-1. Block Diagram of Clock Generator

Prescaler

Clock for peripheral

hardware

X1

X2

System

clock oscillator

Prescaler

f

X

f

X

2²

Standby

controller

Wait

controller

CPU clock (fCPU

)

STOP

PCC1

Processor clock

control register (PCC)

Internal bus

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CHAPTER 5 CLOCK GENERATOR

5.3 Register Controlling Clock Generator

The clock generator is controlled by the following register.

• Processor clock control register (PCC)

(1) Processor clock control register (PCC)

PCC selects the CPU clock and sets the of division ratio.

PCC is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets the PCC to 02H.

Figure 5-2. Format of Processor Clock Control Register

Symbol

PCC

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Address

FFFBH

After reset

02H

R/W

PCC1

Minimum instruction execution time: 2/fCPU

= 6.0 MHz operation

CPU clock (fCPU) selection

f

X

0

1

f

X

0.33

1.33

µ

s

f

/2²

Caution

Bits 0 and 2 to 7 must be set to 0.

Remark f^X: system clock oscillation frequency

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CHAPTER 5 CLOCK GENERATOR

5.4 System Clock Oscillators

5.4.1 System clock oscillator

The system clock oscillator is oscillated by the crystal resonator (6.0 MHz TYP.) connected across the X1 and X2

pins.

An external clock can also be input to the circuit. In this case, input the clock signal to the X1 pin, and leave the X2

pin open.

Figure 5-3 shows the external circuit of the system clock oscillator.

Figure 5-3. External Circuit of System Clock Oscillator

(a) Crystal oscillation

(b) External clock

External

clock

V

SS0

X1

OPEN

X2

Crystal resonator

Caution

When using the system clock oscillator, wire as follows in the area enclosed by the broken

lines in Figure 5-3 to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with other signal lines. Do not route the wiring near a signal line

through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as V^SS0. Do not

ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

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CHAPTER 5 CLOCK GENERATOR

5.4.2 Examples of incorrect resonator connection

Figure 5-4 shows examples of incorrect resonator connection.

Figure 5-4. Examples of Incorrect Resonator Connection (1/2)

(a) Too long wiring

(b) Crossed signal line

PORTn

(n = 0, 1, 2, 4)

VSS0

X1

X2

VSS0

X1

X2

(c) Wiring near high fluctuating current

(d) Current flowing through ground line of oscillator

(potential at points A, B, and C fluctuates)

V

DD0

Pmn

X1

X2

VSS0

V

SS0

X1

X2

High current

A

B

C

High current

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CHAPTER 5 CLOCK GENERATOR

Figure 5-4. Examples of Incorrect Resonator Connection (2/2)

(e) Signals are fetched

X1

X2

VSS0

5.4.3 Frequency divider

The frequency divider divides the output of the system clock oscillator (f^X) to generate various clocks.

5.5 Clock Generator Operation

The clock generator generates the following clocks and controls the operation modes of the CPU, such as the

standby mode.

• System clock

• CPU clock

f^X

f^CPU

• Clock to peripheral hardware

The operation of the clock generator is determined by the processor clock control register (PCC), as follows.

(a) The slow mode (1.33 µs: at 6.0 MHz operation) of the system clock is selected when the RESET signal is

generated (PCC = 02H). While a low level is being input to the RESET pin, oscillation of the system clock is

stopped.

(b) Two types of minimum instruction execution time (0.33 µs and 1.33 µs: at 6.0 MHz operation) can be

selected by the PCC setting.

(c) Two standby modes, STOP and HALT, can be used.

(d) The clock pulse for the peripheral hardware is generated by dividing the frequency of the system clock. So,

the other hardware stops when the system clock stops (except for external clock pulses).

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CHAPTER 5 CLOCK GENERATOR

5.6 Changing Setting of CPU Clock

5.6.1 Time required for switching CPU clock

The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC).

Actually, the specified clock is not selected immediately after the setting of PCC has been changed; the old clock is

used for the duration of several instructions after that (see Table 5-2).

Table 5-2. Maximum Time Required for Switching CPU Clock

Set Value Before Switching

PCC1

Set Value After Switching

PCC1 PCC1

0

1

0

1

4 clocks

2 clocks

Remark Before switching, the minimum instruction execution time of the CPU clock is two clocks.

5.6.2 Switching CPU clock

The following figure illustrates how the CPU clock switches.

Figure 5-5. Switching of CPU Clock

VDD

RESET

CPU clock

Slow

Fastest operation

operation

Wait (5.46 ms: at 6.0 MHz operation)

Internal reset operation

<1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is released

when the RESET pin is later made high, and the system clock starts oscillating. At this time, the time during

which oscillation stabilization (2¹⁵/fX) is automatically secured.

After that, the CPU starts instruction execution at the slow speed of the system clock (1.33 µs: at 6.0 MHz

operation).

<2> After the time required for the V^DDvoltage to rise to the level at which the CPU can operate at the highest

speed has elapsed, the processor clock control register (PCC) is rewritten so that the highest speed operation

can be selected.

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01

6.1 Functions of 8-Bit Timer/Event Counters 00 and 01

The 8-bit timer/event counters (TM00 and TM01) have the following functions.

• Interval timer (TM00 and TM01)

• External event counter (TM01 only)

• Square wave output (TM01 only)

The µPD789800 Subseries is provided with a 1-channel (TM01) 8-bit timer/event counter and a 1-channel (TM00)

8-bit timer. When reading the description of TM00, “timer/event counter” should be read as “ timer”.

(1) 8-bit interval timer

When the 8-bit timer/event counter is used as an interval timer, it generates an interrupt at any preset time

interval.

Table 6-1. Interval Time of 8-Bit Timer 00

Minimum Interval Time

2⁶/fX (10.7 µs)

2⁹/fX (85.3 µs)

Maximum Interval Time

2¹⁴/fX (2.73 ms)

2¹⁷/fX (21.8 ms)

Resolution

2⁶/fX (10.7 µs)

2⁹/fX (85.3 µs)

Remarks 1. f^X: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 6.0 MHz.

Table 6-2. Interval Time of 8-Bit Timer/Event Counter 01

Minimum Interval Time

2⁴/fX (2.67 µs)

2⁸/fX (42.7 µs)

Maximum Interval Time

Resolution

2¹²/fX (682.7 µs)

2⁴/fX (2.67 µs)

2⁸/fX (42.7 µs)

2¹⁶/fX (10.9 ms)

Remarks 1. f^X: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 6.0 MHz.

(2) External event counter

The number of pulses of an externally input signal can be measured.

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01

(3) Square wave output

A square wave of arbitrary frequency can be output.

Table 6-3. Square Wave Output Range of 8-Bit Timer/Event Counter 01

Minimum Pulse Width

2⁴/fX (2.67 µs)

2⁸/fX (42.7 µs)

Maximum Pulse Width

2¹²/fX (682.7 µs)

2¹⁶/fX (10.9 ms)

Resolution

2⁴/fX (2.67 µs)

2⁸/fX (42.7 µs)

Remarks 1. fX: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 6.0 MHz

6.2 Configuration of 8-Bit Timer/Event Counters 00 and 01

8-bit timer/event counters 00 and 01 consist of the following hardware.

Table 6-4. Configuration of 8-Bit Timer/Event Counters 00 and 01

Item

Configuration

8 bits × 2 (TM00 and TM01)

Timer counter

Register

Compare register: 8 bits × 2 (CR00 and CR01)

1 (TO01)

Timer outputs

Control registers

8-bit timer mode control registers 00 and 01 (TMC00 and TMC01)

Port mode register 2 (PM2)

Figure 6-1. Block Diagram of 8-Bit Timer 00

Internal bus

8-bit compare register 00

(CR00)

Match

INTTM00

f

X

/2⁶

/2⁹

8-bit timer counter 00

(TM00)

fX

Clear

Selector

TCE00 TCL000

8-bit timer mode control register 00 (TMC00)

Internal bus

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01

Figure 6-2. Block Diagram of 8-Bit Timer/Event Counter 01

Internal bus

8-bit compare register 01

(CR01)

P26

Output latch

PM26

Match

INTTM01

f

X

/2⁴

/2⁸

8-bit timer counter 01

(TM01)

TO01/P26/

INTP0/TI01

fX

F/F

Clear

Selector

TI01/P26

/INTP0/TO01

2

TCE01 TCL011 TCL010 TOE01

8-bit timer mode control register 01 (TMC01)

Internal bus

(1) 8-bit compare register 0n (CR0n)

This is an 8-bit register used to compare the value set to CR0n with the 8-bit timer counter 0n (TM0n) count

value, and if they match, generate used an interrupt request (INTTM0n).

CR0n is set with an 8-bit memory manipulation instruction. Values from 00H to FFH can be set.

RESET input sets CR0n undefined.

Caution

Be sure to set CR0n after the timer operation is stopped.

Remark n = 0 or 1

(2) 8-bit timer counter 0n (TM0n)

This is an 8-bit register used to count pulses.

TM0n is read with an 8-bit memory manipulation instruction.

RESET input sets TMn to 00H.

Remark n = 0 or 1

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01

6.3 Registers Controlling 8-Bit Timer/Event Counters 00 and 01

The following two types of registers are used to control 8-bit timer/event counters 00 and 01.

• 8-bit timer mode control registers 00 and 01 (TMC00 and TMC01)

• Port mode register 2 (PM2)

(1) 8-bit timer mode control register 00 (TMC00)

This register enables/stops operation of 8-bit timer counter 00 (TM00) and sets the counter clock of 8-bit timer

00.

TMC00 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets TMC00 to 00H.

Figure 6-3. Format of 8-Bit Timer Mode Control Register 00

<7>

6

0

5

0

4

0

3

0

2

0

1

0

Symbol

Address

FF53H

After reset

00H

R/W

TMC00 TCE00

TCL000

TCE00

8-bit timer counter 00 operation control

0

1

Operation disabled (TM00 cleared to 0)

Operation enabled

TCL000

8-bit timer 00 count clock selection

f

X

/2⁶(93.8 kHz)

/2⁹(11.7 kHz)

0

f

X

Caution

Be sure to set the count clock after the timer operation is stopped (TCE00 = 0).

Refer to 6.4 Operation of 8-Bit Timer/Event Counters 00 and 01 for details.

Remarks 1. f^X: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 6.0 MHz.

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01

(2) 8-bit timer mode control register 01 (TMC01)

TMC01 determines whether to enable or disable 8-bit timer counter 01 (TM01), specifies the count clock for the

8-bit timer/event counter, and controls the operation of the output controller.

TMC01 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets TMC01 to 00H.

Figure 6-4. Format of 8-Bit Timer Mode Control Register 01

Symbol <7>

6

0

5

0

4

0

3

0

2

1

<0>

Address

FF57H

After reset

00H

R/W

TMC01 TCE01

TCL011TCL010TOE01

TCE01

8-bit timer counter 01 operation control

0

1

Operation disabled (TM01 is cleared to 0.)

Operation enabled

TCL011TCL010

8-bit timer/event counter 01 count clock selection

/2⁴(375 kHz)

/2⁸(23.4 kHz)

0

1

0

1

0

1

f

X

f

Rising edge of TI01^Note

Falling edge of TI01^Note

TOE01

8-bit timer/event counter 01 output control

0

1

Output disabled (port mode)

Output enabled

Note When inputting a clock signal externally, timer output cannot be used.

Caution

Be sure to set the count clock after the timer operation is stopped (TCE01 = 0).

Refer to 6.4 Operation of 8-Bit Timer/Event Counters 00 and 01 for details.

Remarks 1. f^X: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 6.0 MHz.

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01

(3) Port mode register 2 (PM2)

This register sets port 2 input/output in 1-bit units.

When using the P26/TO01/INTP0/TI01 pin for timer output, set P26 and the output latch of P26 to 0.

When P26/TO01/INTP0/TI01 pin is used as a timer input, set PM26 to 1.

PM2 is set by a 1-bit or 8-bit memory manipulation instruction.

RESET input sets PM2 to FFH.

Figure 6-5. Format of Port Mode Register 2

7

1

6

5

4

3

2

1

0

Symbol

PM2

Address

FF22H

After reset

FFH

R/W

PM26 PM25 PM24 PM23 PM22 PM21 PM20

PM26

P26 pin input/output mode selection

0

1

Output mode (output buffer on)

Input mode (output buffer off)

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01

6.4 Operation of 8-Bit Timer/Event Counters 00 and 01

6.4.1 Operation as interval timer

Interval timer repeatedly generates an interrupt at time intervals specified by the count value set to 8-bit compare

registers 00 and 01 (CR00 and CR01) in advance.

To operate the 8-bit timer/event counter as an interval timer, the following settings are required.

<1> Disable operation of the 8-bit timer counter 0n (TM0n) by setting TCE0n (bit 7 of 8-bit timer mode control

register 0n (TMC0n)) to 0.

<2> Set the count clock of the 8-bit timer/event counter (see Tables 6-5 and 6-6).

<3> Set count values to CR0n.

<4> Enable operation of TM0n by setting TCE0n to 1.

When the count value of 8-bit timer counter 0n (TM0n) matches the value set to CR0n, the value of TMn is cleared

to 0 and TM0n continues counting. At the same time, an interrupt request signal (INTTM0n) is generated.

Tables 6-5 and 6-6 show the interval time, and Figures 6-6 and 6-7 show the timing of interval timer operation.

Caution

When the TMC0n count clock is set and the operation of TM0n is enabled simultaneously by an

8-bit memory manipulation instruction, an error of more than 1 clock may occur in 1 cycle after

the timer has been started. Therefore, be sure to follow the settings above when the 8-bit

timer/event counter is operating as an interval timer.

Remark n = 0 or 1

Table 6-5. Interval Time of 8-Bit Timer 00

TCL000

Minimum Interval Time

2⁶/fX (10.7 µs)

2⁹/fX (85.3 µs)

Maximum Interval Time

2¹⁴/fX (2.73 µs)

Resolution

2⁶/fX (10.7 µs)

2⁹/fX (85.3 µs)

0

1

2¹⁷/fX (21.8 ms)

Remarks 1. f^X: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 6.0 MHz.

Table 6-6. Interval Time of 8-Bit Timer/Event Counter 01

TCL011

TCL010

Minimum Interval Time

2⁴/fX (2.67 µs)

Maximum Interval Time

2¹²/fX (682.7 µs)

Resolution

2⁴/fX (2.67 µs)

0

1

0

1

0

1

2⁸/fX (42.7 µs)

2¹⁶/fX (10.9 ms)

2⁸× TI01 input cycle

TI01 input cycle

TI01 input edge cycle

Remarks 1. f^X: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 6.0 MHz.

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01

Figure 6-6. Interval Timer Operation Timing of 8-Bit Timer 00

t

Count clock

TM00 count value

00

01

N

00

01

N

00

01

N

Clear

CR00

N

TCE00

Count starts

INTTM00

Interrupt acknowledged

Interval time

Interrupt acknowledged

Interval time

Remark Interval time = (N + 1) × t where N = 00H to FFH

Figure 6-7. Interval Timer Operation Timing of 8-Bit Timer/Event Counter 01

t

Count clock

TM01 count value

00

01

N

00

01

N

00

01

N

Clear

CR01

N

TCE01

Count start

INTTM01

Interrupt acknowledged

Interval time

Interrupt acknowledged

Interval time

TO01

Interval time

Remark Interval time = (N + 1) × t, where N = 00H to FFH

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01

6.4.2 Operation as external event counter (timer 01 only)

The external event counter counts the number of external clock pulses input to the TI01/P26/INTP0/TO01 pin by

using timer counter 01 (TM01).

To operate the 8-bit timer/event counter as an external event counter, the following settings are required.

<1> Disable operation of 8-bit timer counter 01 (TM01) by setting TCE01 (bit 7 of 8-bit timer mode control register

01 (TMC01)) to 0.

<2> Specify the rising/falling edge of TI01 (see Table 6-6), and set TO01 to output-disabled (TOE01 (bit 0 of

TMC01) = 0).

<3> Set count values to CR01.

<4> Enable operation of TM01 by setting TCE01 to 1.

Each time the valid edge specified by bit 1 or 2 (TCL011 or TCL010) of TMC01 is input, the value of 8-bit timer

counter 01 (TM01) is incremented.

When the count value of TM01 matches the value set to CR01, the value of TM01 is cleared to 0 and TM01

continues counting. At the same time, an interrupt request signal (INTTM01) is generated.

Figure 6-8 shows the timing of external event counter operation (with rising edge specified).

Caution

When the TMC01 count clock is set and the operation of TM01 is enabled simultaneously by an

8-bit memory manipulation instruction, an error of more than 1 clock may occur in 1 cycle after

the timer has been started. Therefore, be sure to follow the settings above when the 8-bit

timer/event counter is operating as an external event counter.

Figure 6-8. Timing of External Event Counter Operation (with Rising Edge Specified)

TI01 pin input

TM01 count value

CR01

00

01

02

03

04

05

N

N – 1

N

00

01

02

03

TCE01

INTTM01

Remark N = 00H to FFH

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01

6.4.3 Operation as square-wave output (timer 01 only)

The 8-bit timer/event counter can generate output square waves of arbitrary frequency at intervals specified by the

count value set to 8-bit compare register 01 (CR01) in advance.

To operate 8-bit timer/event counter 01 as square wave output, the following settings are required.

<1> Set P26 to output mode (PM26 = 0) and the output latch of P26 to 0.

<2> Disable operation of 8-bit timer counter 01 (TM01) by setting TCE01 (bit 7 of 8-bit timer mode control register

01 (TMC01)) to 0.

<3> Set the count clock of 8-bit timer/event counter 01 (see Table 6-7) and enable output of TO01 by setting

TOE01 (bit 0 of TMC01) to 1

<4> Set count values to CR01.

<5> Enable operation of TM01 by setting TCE01 to 1.

When the count value of 8-bit timer counter 01 (TM01) matches the value set to CR01, the TO01/P26/INTP0/TI01

pin output will be inverted. Through application of this mechanism, square waves of any frequency can be output. As

soon as a match occurs, the TM01 value is cleared to 0, TM01 resumes counting, and an interrupt request signal

(INTTM01 is generated).

Setting bit 7 of TMC01 (TCE01) to 0 clears the square-wave output to 0.

Table 6-7 lists the square wave output range, and Figure 6-9 shows timing of square wave output.

Caution

When the TMC01 count clock is set and the operation of TM01 is enabled simultaneously by an

8-bit memory manipulation instruction, an error of more than 1 clock may occur in 1 cycle after

the timer has been started. Therefore, be sure to follow the settings above when the 8-bit

timer/event counter is operating as square-wave output.

Table 6-7. Square-Wave Output Range of 8-Bit Timer/Event Counter 01

TCL011

TCL010

Minimum Pulse Width

2⁴/fX (2.67 µs)

2⁸/fX (42.7 µs)

Maximum Pulse Width

2¹²/fX (682.7 µs)

2¹⁶/fX (10.9 ms)

Resolution

2⁴/fX (2.67 µs)

2⁸/fX (42.7 µs)

0

1

Remarks 1. f^X: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 6.0 MHz.

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01

Figure 6-9. Timing of Square-Wave Output

Count clock

TM01 count value

00

01

N

00

01

N

00

01

N

Clear

CR01

N

TCE01

Count start

INTTM01

Interrupt acknowledged

TO01^Note

Note The initial value of TO01 when output is enabled (TOE01 = 1) becomes low level.

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01

6.5 Notes on Using 8-Bit Timer/Event Counters 00 and 01

(1) Error on starting timer

An error of up to 1 clock occurs after the timer is started until a match signal is generated. This is because 8-bit

timer counters 00 and 01 (TM00 and TM01) are started asynchronously to the count pulse.

Figure 6-10. Start Timing of 8-Bit Timer Counter

Count pulse

TM00, TM01 count value

00H

01H

02H

03H

04H

Timer starts

(2) Setting of 8-bit compare register

8-bit compare registers 00 and 01 (CR00 and CR01) can be set to 00H.

Therefore, one pulse can be counted when the 8-bit timer/event counter operates as an event counter.

Figure 6-11. Timing of External Event Counter Operation

TI00, TI01 input

CR00, CR01

TM00, TM01 count value

Interrupt request flag

00H

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CHAPTER 7 WATCHDOG TIMER

7.1 Watchdog Timer Functions

The watchdog timer has the following functions.

• Watchdog timer

• Interval timer

Caution

Select the watchdog timer mode or interval timer mode by using the watchdog timer mode

register (WDTM).

(1) Watchdog timer

The watchdog timer is used to detect inadvertent program loops. When an inadvertent loop is detected, a non-

maskable interrupt or the RESET signal can be generated.

Table 7-1. Inadvertent Loop Detection Time of Watchdog Timer

Inadvertent Loop

Detection Time

Operation at fX = 6.0 MHz

2¹¹× 1/fX

341 µs

2¹³× 1/fX

2¹⁵× 1/fX

2¹⁷× 1/fX

1.37 ms

5.46 ms

21.8 ms

fX: System clock oscillation frequency

(2) Interval timer

The interval timer generates an interrupt at arbitrary intervals set in advance.

Table 7-2. Interval Time

Interval Time

Operation at fX = 6.0 MHz

341 µs

2¹¹× 1/fX

2¹³× 1/fX

2¹⁵× 1/fX

2¹⁷× 1/fX

1.37 ms

5.46 ms

21.8 ms

fX: System clock oscillation frequency

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CHAPTER 7 WATCHDOG TIMER

7.2 Watchdog Timer Configuration

The watchdog timer consists of the following hardware.

Table 7-3. Configuration of Watchdog Timer

Item

Configuration

Control register

Timer clock select register 2 (TCL2)

Watchdog timer mode register (WDTM)

Figure 7-1. Block Diagram of Watchdog Timer

Internal bus

f

X

2⁴

TMMK4

Prescaler

f

X

2⁶

f

X

2⁸

f

X

2¹⁰

INTWDT

maskable

TMIF4

interrupt request

Controller

7-bit counter

Clear

RESET

INTWDT

non-maskable

interrupt request

3

TCL22 TCL21 TCL20

RUN WDTM4 WDTM3

Timer clock select register 2

(TCL2)

Watchdog timer mode register (WDTM)

Internal bus

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CHAPTER 7 WATCHDOG TIMER

7.3 Registers Controlling Watchdog Timer

The following two registers are used to control the watchdog timer.

• Timer clock select register 2 (TCL2)

• Watchdog timer mode register (WDTM)

(1) Timer clock select register 2 (TCL2)

This register sets the watchdog timer count clock.

TCL2 is set with an 8-bit memory manipulation instruction.

RESET input sets TCL2 to 00H.

Figure 7-2. Format of Timer Clock Select Register 2

Symbol

TCL2

7

0

6

0

5

0

4

0

3

0

2

1

0

Address

FF42H

After reset

00H

R/W

TCL22 TCL21TCL20

Watchdog timer count clock selection

Interval time

TCL22 TCL21 TCL20

2¹¹/f

X

(341 µs)

fX

/2⁴

0

1

0

1

0

1

0

(375 kHz)

/2⁶

2¹³/f

2¹⁵/f

2¹⁷/f

(1.37 ms)

(5.46 ms)

(21.8 ms)

(93.8 kHz)

/2⁸

(23.4 kHz)

/2¹⁰

(5.86 kHz)

Other than above Settings prohibited

Remarks 1. f^X: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 6.0 MHz.

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CHAPTER 7 WATCHDOG TIMER

(2) Watchdog timer mode register (WDTM)

This register sets the operation mode of the watchdog timer, and enables/disables counting of the watchdog

timer.

The WDTM is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets the WDTM to 00H.

Figure 7-3. Format of Watchdog Timer Mode Register

<7>

6

0

5

0

4

3

2

0

1

0

Address

FFF9H

After reset

00H

R/W

Symbol

WDTM RUN

WDTM4 WDTM3

Selection of operation of watchdog timer^{Note 1}

RUN

0

1

Stop counting

Clear counter and start counting

Selection of operation mode of watchdog timer^{Note 2}

WDTM4 WDTM3

0

1

0

1

0

1

Operation disabled

Interval timer mode (overflow and maskable interrupt occur)^{Note 3}

Watchdog timer mode 1 (overflow and non-maskable interrupt occur)

Watchdog timer mode 2 (overflow occurs and reset operation started)

Notes 1. Once RUN has been set (1), it cannot be cleared (0) by software. Therefore, when counting is

started, it cannot be stopped by any means other than RESET input.

2. Once WDTM3 and WDTM4 have been set (1), they cannot be cleared (0) by software.

3. The watchdog timer starts operations as an interval timer when RUN is set to 1.

Cautions 1. When the watchdog timer is cleared by setting RUN to 1, the actual overflow time is up

to 0.8% shorter than the time set by timer clock select register 2 (TCL2).

2. In watchdog timer mode 1 or 2, set WDTM4 to 1 after confirming TMIF4 (bit 0 of the

interrupt request flag register 0 (IF0)) is set to 0. While TMIF4 is 1, a non-maskable

interrupt is generated upon write completion if watchdog timer mode 1 or 2 is selected.

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CHAPTER 7 WATCHDOG TIMER

7.4 Watchdog Timer Operation

7.4.1 Operation as watchdog timer

The watchdog timer detects an inadvertent program loop when bit 4 (WDTM4) of the watchdog timer mode register

(WDTM) is set to 1.

The count clock (inadvertent loop detection time interval) of the watchdog timer can be selected by bits 0 to 2

(TCL20 to TCL22) of timer clock select register 2 (TCL2). By setting bit 7 (RUN) of WDTM to 1, the watchdog timer is

started. Set RUN to 1 within the set inadvertent loop detection time interval after the watchdog timer has been

started. By setting RUN to 1, the watchdog timer can be cleared and start counting. If RUN is not set to 1, and the

inadvertent loop detection time is exceeded, the system is reset or a non-maskable interrupt is generated by the value

of bit 3 (WDTM3) of WDTM.

The watchdog timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set RUN to 1

before entering the STOP mode to clear the watchdog timer, and then execute the STOP instruction.

Caution

The actual inadvertent loop detection time may be up to 0.8% shorter than the set time.

Table 7-4. Inadvertent Loop Detection Time of Watchdog Timer

TCL22

TCL21

TCL20

Inadvertent Loop Detection Time

Operation at fX = 6.0 MHz

341 µs

2¹¹× 1/fX

2¹³× 1/fX

2¹⁵× 1/fX

2¹⁷× 1/fX

0

1

0

1

0

1

0

1.37 ms

5.46 ms

21.8 ms

fX: System clock oscillation frequency

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7.4.2 Operation as interval timer

When bit 4 (WDTM4) and bit 3 (WDTM3) of the watchdog timer mode register (WDTM) are set to 0 and 1,

respectively, the watchdog timer also operates as an interval timer that repeatedly generates an interrupt at time

intervals specified by a count value set in advance.

Select the count clock (or interval time) by setting bits 0 to 2 (TCL20 to TCL22) of timer clock select register 2

(TCL2). The watchdog timer starts operation as an interval timer when the RUN bit (bit 7 of WDTM) is set to 1.

In the interval timer mode, the interrupt mask flag (TMMK4) is valid, and a maskable interrupt (INTWDT) can be

generated. The priority of INTWDT is set as the highest of all the maskable interrupts.

The interval timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set RUN to 1

before entering the STOP mode to clear the interval timer, and then execute the STOP instruction.

Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (when the watchdog timer mode is selected), the

interval timer mode is not set, unless the RESET signal is input.

2. The interval time immediately after the setting by WDTM may be up to 0.8% shorter than

the set time.

Table 7-5. Interval Time of Interval Timer

TCL22

TCL21

TCL20

Interval Time

Operation at fX = 6.0 MHz

341 µs

2¹¹× 1/fX

2¹³× 1/fX

2¹⁵× 1/fX

2¹⁷× 1/fX

0

1

0

1

0

1

0

1.37 ms

5.46 ms

21.8 ms

fX: System clock oscillation frequency

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CHAPTER 8 USB FUNCTION

8.1 USB Overview

The USB (Universal Serial Bus) is suitable for connecting personal computers and external devices such as audio

equipment, keyboards, pointing devices, and telephones. Two data transfer rates, 12 Mbps and 1.5 Mbps, are

provided.

Plug & Play can also be realized.

Figure 8-1 shows an example of USB connection to a desktop PC. The USB consists of the host controller

installed in the PC, hubs installed for port expansion and connection, and functions installed at bus ends. These

functions are called endpoints and are the data transfer destinations or data transfer sources in the USB.

Figure 8-1. USB Bus Topology (Desktop Type PC)

Host

Host (Root Tier)

RootHub

Tier 1

Hub

Tier 2

Function

(monitor)

Hub

Function

(modem)

Tier 3

Function

(keyboard)

Function

(mouse)

Hub

Tier 4

Function

(CD-ROM)

Function

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CHAPTER 8 USB FUNCTION

8.2 USB Function Features

The features of the on-chip USB function provided for the µPD789800 Subseries are described below.

(1) Video display devices and human interface devices are assumed to be the target applications. For this

reason, only Endpoint 0 for control transfer and Endpoint 1 for interrupt transfer are supported.

(2) 1.5 Mbps (low speed) data transfer using a 6.0 MHz system clock is supported.

(3) The following buffers are provided on-chip.

• Receive token bank: 1 bank (3 bytes)

• Receive data bank: 1 bank (9 bytes)

• Transmit data bank: 2 banks (9 bytes × 2)

(4) NRZI (Non Return to Zero Invert) decode/encode function specified by the USB communication protocol, bit

stuffing function, and on-chip CRC (Cyclic Redundancy Check) function are also provided and automatically

executed.

8.3 USB Function Configuration

The USB function consists of the following hardware.

Table 8-1. Configuration of USB Function

Item

Configuration

Buffer

Receive bank switching ID detection buffer (internal buffer)

Registers

Transmit/receive pointer (USBPOW)

Receive token PID (USBRTP)

Receive token bank

Receive data bank

Transmit data bank 0

Transmit data bank 1

Receive token address L, H (USBRAL, USBRAH)

Receive data PID (USBRD)

Receive data address (USBR0 to USBR7)

Transmit data PID bank 0 (USBTD0)

Transmit data bank 0 address (USBT00 to USBT07)

Transmit data PID bank 1 (USBTD1)

Transmit data bank 1 address (USBT10 to USBT17)

Data/handshake packet receive byte number counter (DRXCON)

Data packet transmit byte number counter 0, 1 (DTXCO0, DTXCO1)

Token PID compare register (TIDCMP)

Token address compare register (ADRCMP)

Data/handshake PID compare register (DIDCMP)

Control registers

USB receiver enable register (USBMOD)

Data/handshake packet receive mode register (URXMOD)

Packet receive status register (RXSTAT)

Data/handshake packet receive result store register (DRXRSL)

Token packet receive result store register (TRXRSL)

Data packet transmit reservation register (DTXRSV)

Handshake packet transmit reservation register (HTXRSV)

USB timer start reservation control register (USBTCL)

Remote wakeup control register (REMWUP)

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CHAPTER 8 USB FUNCTION

Figure 8-2. Block Diagram of USB Function

Internal bus

Transmit reservation

register (HTXRSV,

DTXRSV)

USB receiver

enable register

(USBMOD)

Data/handshake

packet receive mode

register (URXMOD)

Counter^{Note 1}

Transmit/receive pointer

(USBPOB, USBPOW)

Remote wakeup

control register

(REMWUP)

• Handshake packet

• SYNC packet

EOP generation/detection

Resume & reset

detection control

NRZI

encoder

Output

latch

Transmit buffer

USBDP

USBDM

Receive bank

switching ID

detection buffer

SYNC detection/

USB clock generator

Receive buffer

fX

USB clock

Bit stuff/bit strip

controller

Overflow

INTUSBTM

Compare register^{Note 2}

INTUSBRD

USB timer^{Note 4}

(7-bit counter)

Start

CRC

circuit

ENDP

detector

USB timer start

reservation control

register (USBTCL)

Packet receive status

register (RXSTAT)

Receive result

store register^{Note 3}

Internal bus

Notes 1. Data/handshake packet receive byte number counter (DRXCON), data packet transmit byte number

counter 0, 1 (DTXCO0, DTXCO1)

2. Token address compare register (ADRCMP), token PID compare register (TIDCMP), data/handshake

PID compare register (DIDCMP)

3. Token packet receive result store register (TRXRSL), data/handshake packet receive result store

register (DRXRSL)

4. See Figure 8-3 for USB timer configuration.

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CHAPTER 8 USB FUNCTION

Figure 8-3. Block Diagram of USB Timer

INTUSBTM

In high-

In low-

speed mode speed mode

Shift register

UWDERR

RESUME RX^Note

Clear circuit

fX

Clock controller

USBCLK

JUDGE TX^Note

JUDGE TOKEN^Note

TX MASTER EN^Note

SETRX^Note

OUT RX^Note

DATATX SETORX

USB timer start reservation

control register (USBTCL)

Internal bus

Note As these signals are used internally, confirmation by software is not possible.

Remark System clock oscillation frequency

fX:

UWDERR: Bit 7 of packet receive status register (RXSTAT)

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CHAPTER 8 USB FUNCTION

(1) Receive bank switching ID detection buffer (internal buffer)

This is an internal 2-bit buffer placed before a receive buffer. It detects the lower 2 bits below the packet ID

during packet reception and determines the store bank of a packet.

The following controls are performed depending on the stored 2-bit data. For details, see Section 8.5.3 Receive

bank switching ID detection buffer operation.

<1> If the first 2 bits of the stored bits (lower 2 bits in ID area) are 01B, TOSTAT (bit 0 of the packet receive

status register (RXSTAT)) indicating token packet reception is set and a signal specifying packet store at

the receive token address is output to the transmit/receive pointer.

<2> If the first 2 bits of the stored bits are 11B, DASTAT (bit 1 of RXSTAT) indicating data packet reception

is set and a signal specifying packet store at the receive data address is sent to the transmit/receive

pointer.

<3> If the first 2 bits of the stored bits are 10B, HSSTAT (bit 2 of RXSTAT) indicating handshake packet

reception is set and a signal specifying packet store at the receive data address is output to the

transmit/receive pointer.

(2) Transmit/receive pointer (USBPOB and USBPOW)

The USBPOB is a pointer on the bit side in the transmit/receive buffer and the USBPOW is a pointer on the word

side of the transmit/receive buffer. USBPOB and USBPOW output a control signal to the CRC circuit, etc.

They are reset and started by the packet ID detection signal from the receive bank switching ID detection buffer.

USBPOB is incremented by the USB clock. USBPOW is incremented by USBPOB overflow.

USBPOW is read with an 8-bit memory manipulation instruction. As USBPOB is an internal pointer, control with

software is not possible.

RESET input sets these pointers to 00H.

The value of USBPOW is changed as follows depending on the receive/transmit byte length match signal or

transmit reservation. Moreover, control signals are also output. For details, see Section 8.8.1 Operation of

transmit/receive pointer.

• If the token packet receive signal is detected by the receive bank switching ID detection buffer, the pointers

are set to 00H.

• If the data/handshake packet receive signal is detected by the receive bank switching ID detection buffer, the

pointers are set to 10H.

• If USBPOW is set to 01H, a signal specifying CRC5 (CRC5 bit mode) execution start is output.

• If USBPOW is set to 11H, 21H, or 31H, a signal specifying CRC16 (CRC16 bit mode) execution start is

output.

• If USBPOB is set to 02H after USBPOW is set to 02H, a signal specifying CRC5 comparison start is output

and USBPOW is set to 70H.

• If the value of USBPOW matches that of the data/handshake packet receive byte number counter (DRXCON),

a signal specifying CRC16 comparison start is output when USBPOB overflows, and USBPOW is set to 70H.

• If a signal specifying transmit start is received from the transmit controller, USBPOW is set to 7FH. After that,

USBPOW is set to 20H, 30H, 40H, 50H, or 60H depending on the error between the present transmit

reservation and previous receive data, when USBPOB overflows.

• If the value of USBPOW matches that of data packet transmit byte number counter 0 (DTXCO0) or data

packet transmit byte number counter 1 (DTXCO1), USBPOW is set to 70H when USBPOB overflows (CRC

redundant bits are appended).

• USBPOW is set to 71H, then a signal specifying EOP transmission is output when USBPOB overflows.

• When USBPOW is set to 40H, 50H, or 60H, a signal specifying EOP transmission is output if USBPOB

overflows.

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(3) Receive token bank

(a) Receive token PID (USBRTP)

This is the receive token packet ID area. The data input to the token PID compare register (TIDCMP) is

stored here.

USBRTP is read with an 8-bit memory manipulation instruction.

RESET input sets USBRTP to 00H.

(b) Receive token address L and H (USBRAL and USBRAH)

This stores the token packet to be transferred from the host. USBRAL and USBRAH consist of 16 bits. Bits

0 to 6 of USBRAL store the data input to the token address compare register (ADRCMP).

Both USBRAL and USBRAH are read with an 8-bit memory manipulation instruction.

RESET input sets these registers to 00H.

Figure 8-4. Configuration of Receive Token Bank

USBPOB address

Symbol

07H

06H

05H

04H

03H

02H

01H

00H

01H

02H

ID area

Address area

USBRTP

USBRAL

Endpoint

area

Fixed to 0

Endpoint area

USBRAH

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CHAPTER 8 USB FUNCTION

(4) Receive data bank

(a) Receive data PID (USBRD)

This is the receive data packet ID area. The data input to the data/handshake PID compare register

(DIDCMP) is stored here.

USBRD is read with an 8-bit memory manipulation instruction.

RESET input sets USBRD to 00H.

(b) Receive data address (USBR0 to USBR7)

This is an 8-byte register that stores the data/handshake packet transferred from the host.

USBR0 to USBR7 are read with an 8-bit memory manipulation instruction.

If the following combinations are used, they are read with a 16-bit memory manipulation instruction.

• USBR10: USBR0 and USBR1

• USBR32: USBR2 and USBR3

• USBR54: USBR4 and USBR5

• USBR76: USBR6 and USBR7

RESET input makes USBR0 to USBR7 undefined.

Figure 8-5. Configuration of Receive Data Bank

USBPOB address

Symbol

USBRD

07H

06H

05H

04H

ID area

03H

02H

01H

00H

10H

USBR0

USBR1

11H

12H

USBR2

USBR3

USBR4

USBR5

USBR6

USBR7

13H

14H

15H

16H

17H

18H

Data area (8 bytes)

The operation during reception appears as follows.

Packet from host controller

SETUP

DATA0

OUT

DATA1

Response packet

1st byte

ACK

1st byte

ACK





















USBT00

.

8th byte

USBT07

8th byte

USBT07

The data packet from the host controller is stored in the USBT00 to USBT07 registers.

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(5) Transmit data banks 0 and 1

(a) Transmit data PID banks 0 and 1 (USBTD0 and USBTD1)

USBTD0 and USBTD1 correspond to the transmit buffer 0 ID area and transmit buffer 1 ID area,

respectively. USBTD0 and USBTD1 store DATA0 (C3H) or DATA1 (4BH).

USBTD0 and USBTD1 are set with an 8-bit memory manipulation instruction.

RESET input makes both USBTD0 and USBTD1 undefined.

(b) Transmit data bank 0 address (USBT00 to USBT07) and transmit data bank 1 address (USBT10 to

USBT17)

These are 8-byte registers that store the data to be transferred to the host. USBT00 to USBT07 and

USBT10 to USBT17 correspond to transmit buffer 0 of the data area and transmit buffer 1 of the data area,

respectively. Because CRC redundant bits (16 bits) are always appended to packets sent from these

registers, these registers cannot be used for transmitting handshake packets.

USBT00 to USBT07 and USBT10 to USBT17 are set with an 8-bit memory manipulation instruction.

RESET input makes this area undefined.

Figure 8-6. Configuration of Transmit Data Bank 0 (Buffer 0)

USBPOB address

Symbol

07H

06H

05H

04H

ID area

03H

02H

01H

00H

USBTD0

20H

USBT00

USBT01

21H

22H

USBT02

USBT03

USBT04

USBT05

USBT06

USBT07

23H

24H

25H

26H

27H

28H

Data area (8 bytes)

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CHAPTER 8 USB FUNCTION

Figure 8-7. Configuration of Transmit Data Bank 1 (Buffer 1)

USBPOB address

Symbol

07H

06H

05H

04H

03H

02H

01H

00H

USBTD1

USBT10

30H

31H

ID area

USBT11

USBT12

32H

33H

USBT13

USBT14

Data area (8 bytes)

34H

35H

USBT15

USBT16

USBT17

36H

37H

38H

The operation during transmission appears as follows.

Packet from host controller

IN

ACK

IN

ACK

Response packet

1st byte

DATA0

DATA1











USBT00

.

8th byte

USBT07

USBT10

USBT07











1st byte

8th byte

USBT10

.

USBT17

Data is read according to the data sequence in the control read data stage and is transmitted to the host. In the

DATA0 sequence, the values saved in USBT00 to USBT07 are transmitted in sequence to the host. In the

DATA1 sequence, the values saved in USBT10 to USBT17 are transmitted in sequence to the host.

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CHAPTER 8 USB FUNCTION

(6) Data/handshake packet receive byte number counter (DRXCON)

This register sets the number of data of the data/handshake packet to be received. During data/handshake

packet reception, if this register value and the transmit/receive pointer (USBPOW) value match, a match signal is

output from the comparator.

During data packet reception, set the USBPOW address at which the last byte before the appended CRC

redundant bits is stored to DRXCON. When a handshake packet is received, set DRXCON to 10H.

DRXCON is set with an 8-bit memory manipulation instruction.

RESET input sets DRXCON to 18H.

SETUP reception^Notealso sets DRXCON to 18H.

Note SETUP reception implies the satisfaction of all the following three conditions.

• Matching of address

• Endpoint 0 received

• No error in reception

(7) Data packet transmit byte number counters 0 and 1 (DTXCO0 and DTXCO1)

DTXCO0 sets the data packet data number of transmit data bank 0 and DTXCO1 sets the transmit data number

of transmit data bank 1. During data packet transmission, if these register values and the transmit/receive

pointer (USBPOW) value match, a match signal is output from the comparator.

The value to be set to these registers is the USBPOW address (buffer 0: 20H to 28H, buffer 1: 30H to 38H) at

which the last byte before the appended CRC redundant bits is stored.

DTXCO0 and DTXCO1 are set with an 8-bit memory manipulation instruction.

RESET input sets DTXCO0 to 20H and DTXCO1 to 30H.

(8) Token PID compare register (TIDCMP)

This register sets the token packet ID to be received. If this register value and the value of the receive token PID

(USBRTP) match during token packet reception match, TIDRST (bit 1 of the token packet receive result store

register (TRXRSL)) is set.

TIDCMP is set with an 8-bit memory manipulation instruction.

RESET input sets TIDCMP to 00H.

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CHAPTER 8 USB FUNCTION

(9) Token address compare register (ADRCMP)

This register sets the address specified from the host during control transfer. If this register value and the

address area of the receive token bank (bits 0 to 6 of receive token address L (USBRAL)) match during token

packet reception coincide, ADRRST (bit 2 of the token packet receive result store register (TRXRSL)) is set.

00H must be set by software when an USB reset is received.

ADRCMP is set with an 8-bit memory manipulation instruction.

RESET input sets ADRCMP to 00H.

Figure 8-8. Configuration of TIDCMP and ADRCMP

USBPOB address

07H 06H 05H 04H 03H 02H 01H 00H

00H

USBRTP

USBRAL

USBRAH

Receive token bank

ENDP.0

01H

02H

ENDP.3-1

Match signal (TIDRST)

SETUP packet detection signal (SETRX)

0 0 1 0 1 1 0 1

0 1 1 0 1 0 0 1

IN packet detection signal (INRX) ^Note

ID packet set

in TIDCMP

OUT packet detection signal (OUTRX)^Note

1 1 1 0 0 0 0 1

TIDCMP

Match signal (ADRRST)

ADRCMP

Endpoint 0 detection

signal (END0RX)

Endpoint 1 detection

signal (END1RX)

Note Because these signals are used internally, confirmation by software is not possible.

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CHAPTER 8 USB FUNCTION

(10) Data/handshake PID compare register (DIDCMP)

This register sets the data/handshake packet ID to be received. If this register value and the value of the receive

data PID (USBRD) match during data/handshake packet reception coincide, the DIDRST (bit 1 of the

data/handshake packet receive result store register (DRXRSL)) is set.

DIDCMP is set with an 8-bit memory manipulation instruction.

RESET input sets DIDCMP to C3H.

SETUP reception^Notealso sets DIDCMP to C3H.

Note SETUP reception implies the satisfaction of all the following three conditions.

• Matching of address

• Endpoint 0 received

• No error in reception

Figure 8-9. Configuration of DIDCMP

USBPOB address

07H 06H 05H 04H 03H 02H 01H 00H

00H

11H

USBRD

Receive data bank

Data area (8 bytes)

18H

Match signal (DIDRST)

DIDCMP

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CHAPTER 8 USB FUNCTION

8.4 Registers Controlling USB Function

The following nine registers are used to control the USB function.

• USB receiver enable register (USBMOD)

• Data/handshake packet receive mode register (URXMOD)

• Packet receive status register (RXSTAT)

• Data/handshake packet receive result store register (DRXRSL)

• Token packet receive result store register (TRXRSL)

• Data packet transmit reservation register (DTXRSV)

• Handshake packet transmit reservation register (HTXRSV)

• USB timer start reservation control register (USBTCL)

• Remote wakeup control register (REMWUP)

(1) USB receiver enable register (USBMOD)

This register controls USB receiver operation and halt.

Because a single-ended receiver does not have an enable flag, regular operation is possible. Thus reception of

the USB reset signal, Resume signal, and EOP signal for bus idle can be performed any time.

USBMOD is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets USBMOD to 00H.

Figure 8-10. Format of USB Receiver Enable Register

Symbol

7

0

6

0

5

0

4

0

3

0

2

0

1

0

<0>

Address

FF6DH

After reset

00H

R/W

USBMOD

RXEN

USB receiver operation control

0

1

USB receiver operation is stopped.

USB receiver operation is possible.

(2) Data/handshake packet receive mode register (URXMOD)

This register sets the data/handshake packet receive mode.

Bit 0 (DWRMSK) is set while saving a data packet and prevents an address greater than 11H in the receive data

address from being overwritten when the next packet is received.

Bit 1 (DINTEN) is a flag used to set the receive status synchronous interrupt (to generate the INTUSBRD

interrupt request to perform data packet reception and data save simultaneously).

Bit 2 (RESMOD) is a flag used to switch the detection mode of the USB reset signal between bus idle mode and

bus suspend mode.

URXMOD is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets URXMOD to 00H.

SETUP reception^Notealso sets the URXMOD to 00H.

Note SETUP reception implies the satisfaction of all the following three conditions.

• Matching of address

• Endpoint 0 received

• No error in reception

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Figure 8-11. Format of Data/Handshake Packet Receive Mode Register

Symbol

7

0

6

0

5

0

4

0

3

0

<2>

<1>

<0>

Address

FF66H

After reset

00H

R/W

URXMOD

RESMOD DINTEN DWRMSK

RESMOD

USB reset signal detection mode setting^{Note 1}

0

1

Reject USB reset signal less than 3.0

µs SE0 (Single-ended 0) period.

Detect transition from J state to SE0 as USB reset signal.^{Note 2}

DINTEN

Data packet receive status synchronous interrupt enable flag

0

1

Do not generate data packet receive status synchronous interrupt.

Generate data packet receive status synchronous interrupt ^{Note 3}

.

DWRMSK

Data/handshake packet write disable setting

0

1

Enable write operation to all addresses in data/handshake packet receive buffer.

Disable write operation to addresses greater than 11H in data/handshake packet receive buffer.

Notes 1. Because this is the flag used to detect a USB reset in bus suspend mode, do not set data in bus

idle mode. And do not set data immediately before entering bus suspend mode. Clear

immediately when returning from the bus suspend mode.

2. If the bus is disturbed by noise, the noise is detected as a USB reset signal. Confirm whether the

USB reset signal has been input by checking the URESRX flag (bit 4 of the USB receive status

register (RXSTAT)) more than once by software.

3. The receive status synchronous interrupt occurs at the following timing during data/handshake

packet receive interrupt (INTUSBRD) signal input.

Sync

Data0 Data1

DataX

CRC16

EOP

EOP received

Packet ID detected

INTUSBRD

(DINTEN = 0)

INTUSBRD

(DINTEN = 1)

Data packet

receive status

synchronous interrupt

Data/handshake packet

receive interrupt

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(3) Packet receive status register (RXSTAT)

This register indicates the receive status of each packet.

Bits 0 to 2 (TOSTAT, DASTAT, and HSSTAT) are flags that indicate that a token packet, data packet, or

handshake packet is currently being received. These flags are set upon detection of a packet ID by an ID

detection buffer, and cleared upon reception of EOP.

Bits 3 to 6 (EOPRX, URESRX, SE0RX, RESMRX) are flags that detect bus status transition. These flags are set

immediately after each bus transition is detected. These flags are cleared by software but cannot be set to 1 by

software.

Bit 7 (UWDERR) is set if an inadvertent program loop is detected by the USB timer. The flags are cleared by

software. UWDERR cannot be set by software. An inadvertent program loop of the USB timer means a status in

which the USB clock does not stop when EOP cannot be detected in a packet received from the host, or when

noise on the bus was detected as a bus status transition.

RXSTAT is set with an 8-bit memory manipulation instruction.

RESET input sets RXSTAT to 00H.

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Figure 8-12. Format of Packet Receive Status Register

Symbol

7

6

5

4

3

2

1

0

Address

FF67H

After reset

00H

R/W

RXSTAT UWDERR RESMRX SE0RX URESRX EOPRX HSSTAT DASTAT TOSTAT

R/W^Note

UWDERR

0

USB timer inadvertent program loop detection

No USB timer inadvertent program loop was detected.

USB timer inadvertent program loop (USB clock operation faster than 85.3

µs (at 6.0 MHz)) was detected,

1

forcibly terminating USB clock. This flag is also set when USB reset or Resume signal was received.

RESMRX

Resume signal receive status

No Resume signal was received.

0

1

Received Resume signal (level detection)

SE0RX

Single-ended 0 signal detection status

No Single-ended 0 (SE0) signal was detected.

0

1

Detected SE0 signal one or more times

URESRX

USB reset signal detection status

No USB reset signal was detected.

0

1

Detected USB reset signal one or more times

EOPRX

EOP detection status

No EOP signal was detected.

0

1

Detected EOP one or more times

HSSTAT

Handshake packet receive status

No handshake packet was received.

0

1

Receiving handshake packet

DASTAT

Data packet receive status

No data packet was received.

0

1

Receiving data packet

TOSTAT

Token packet receive status

No token packet was received.

0

1

Receiving token packet

Note Bits 0 to 2: read only

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Table 8-2 shows the state of each flag after receiving the USB reset signal and the Resume signal during the bus

idle state and bus suspend state.

Table 8-2. Flag of RXSTAT After Reception of USB Reset Signal and Resume Signal

Bus State

Device State

Received Signal

USB reset

Resume

RESMRX

SE0RX

URESRX

Idle

Main system clock

operation mode

0

1

0

1

0

1

0

Suspend

STOP mode

USB reset

Resume

(4) Data/handshake packet receive result store register (DRXRSL)

This register stores the data/handshake packet reception result.

Register contents are updated upon reception of data/handshake EOP.

DRXRSL is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets DRXRSL to 00H.

Figure 8-13. Format of Data/Handshake Packet Receive Result Store Register

Symbol

<7>

<6>

<5>

4

0

3

0

2

0

<1>

0

Address

FF65H

After reset

00H

R/W

DRXRSL CR16ER DBITER DBYER

DIDRST

CR16ER

CRC error detection (16-bit mode)

0

1

CRC error did not occur in received data packet.

CRC error occurred in received data packet.

DBITER

Bit stuffing error detection

0

1

Bit stuffing error did not occur in received data/handshake packet.

Bit stuffing error occurred in received data/handshake packet.

DBYER

Received data/handshake packet length error detection

Packet length of received data/handshake packet is normal.

Packet length of received data/handshake packet is abnormal.

0

1

DIDRST

Data/handshake packet ID comparison result

Received data/handshake packet ID and value of data/handshake PID compare register (DIDCMP)

do not match.

0

1

Received data/handshake packet ID and value of DIDCMP match.

(5) Token packet receive result store register (TRXRSL)

This register stores the token packet reception status.

Register contents are updated upon reception of token packet EOP.

TRXRSL is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets TRXRSL to 00H.

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Figure 8-14. Format of Token Packet Receive Result Store Register

Symbol

<7>

<6>

<5>

<4>

<3>

<2>

<1>

<0>

Address

After reset

00H

R/W

TRXRSL CRC5ER TBITER TBYER END1RX END0RX ADRRST TIDRST SETRX

FF62H

CRC5ER

CRC error detection (5-bit mode)

CRC error did not occur in received token packet.

CRC error occurred in received token packet.

0

1

TBITER

Bit stuffing error detection

0

1

Bit stuffing error did not occur in received token packet.

Bit stuffing error occurred in received token packet.

TBYER

Received token packet length error detection

0

1

Packet length of received token packet is normal.

Packet length of received token packet is abnormal.

END1RX

Endpoint 1 reception detection

0

1

No token packet corresponding to Endpoint 1 is received.

Token packet corresponding to Endpoint 1 was received.

END0RX

Endpoint 0 reception detection

0

1

No token packet corresponding to Endpoint 0 is received.

Token packet corresponding to Endpoint 0 was received.

ADRRST

Token packet address compare result

0

1

Received token packet address and value of token address compare register (ADRCMP) do not match.

Received token packet address and value of ADRCMP match.

TIDRST

Token packet ID compare result detection

Received token packet ID and value of token PID compare register (TIDCMP) do not match.

Received token packet ID and value of TIDCMP match.

0

1

SETRX

Setup token packet reception detection

0

1

Received token packet ID is other than Setup packet.

Received token packet ID is Setup packet ^Note

.

Note If SETRX is set to 1, the following occurs.

• All reservations are cleared

• DNAEN (bit 1 of the handshake packet transmit reservation register (HTXRSV)) is cleared

• DWRMSK (bit 0 of the data/handshake packet receive mode register (URXMOD)) is cleared

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(6) Data packet transmit reservation register (DTXRSV)

This register sets the bank where the data packet to be transmitted is stored. By setting each flag of this

register, the stored data is transmitted following normal reception of the IN token packet.

DTXRSV is set with a 1-bit or 8-bit memory manipulation instruction. When DTXRSV is used in combination with

the handshake packet transmit reservation register (HTXRSV) as the 16-bit register USBCON, DTXRSV is set

with a 16-bit memory manipulation instruction.

RESET input sets DTXRSV to 00H.

SETUP reception^Notealso sets DTXRSV to 00H.

Note SETUP reception implies the satisfaction of all the following three conditions.

• Matching of address

• Endpoint 0 received

• No error in reception

Figure 8-15. Format of Data Packet Transmit Reservation Register

Symbol

7

0

6

0

5

0

4

0

3

2

1

0

Address

FF15H

After reset

00H

R/W

DTXRSV

DT11EN DT10EN DT01EN DT00EN

DT11EN

Transmit reservation flag for transmit bank 1 (Endpoint 1)

0

1

No data is transmitted.

Stored data is transmitted when all the following conditions are satisfied in EOP during IN packet reception.

Setting is disabled during control read transmission.

INRX (Internal signal) = 1, ADRRST = 1, END1RX = 1, TBYER = 0, TBITER = 0, CRC5ER = 0

DT10EN

Transmit reservation flag for transmit bank 1 (Endpoint 0)

No data is transmitted.

0

1

Stored data is transmitted when all the following conditions are satisfied in EOP during IN packet reception.

INRX (internal signal) = 1, TIDRST = 1, ADRRST = 1, END0RX = 1, TBYER = 0, TBITER = 0, CRC5ER = 0

DT01EN

Transmit reservation flag for transmit buffer 0 (Endpoint 1)

No data is transmitted.

0

1

Stored data is transmitted when all the following conditions are satisfied in EOP during IN packet reception.

Setting is disabled during control read transmission.

INRX (internal signal) = 1, ADRRST = 1, END1RX = 1, TBYER = 0, TBITER = 0, CRC5ER = 0

DT00EN

Transmit reservation flag for transmit buffer 0 (Endpoint 0)

No data is transmitted.

0

1

Stored data is transmitted when all the following conditions are satisfied in EOP during IN packet reception.

INRX (internal signal) = 1, TIDRST = 1, ADRRST = 1, END0RX = 1, TBYER = 0, TBITER = 0, CRC5ER = 0

Caution Setting bits 1 and 3 (DT01EN, DT11EN) is prohibited during control transfer.

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(7) Handshake packet transmit reservation register (HTXRSV)

This register sets the handshake packet to be transmitted. By setting each flag of this register, a handshake

packet is transmitted following normal reception of an IN packet, or normal or abnormal reception of a data

packet.

Bit 0 corresponds to the ACK packet transmit reservation flag, bits 1 to 3 correspond to the NAK packet transmit

reservation flag, and bits 4 to 7 correspond to the STALL packet transmit reservation flag.

HTXRSV is set with a 1-bit or 8-bit memory manipulation instruction. When HTXRSV is used in combination with

the data packet transmit reservation register (DTXRSV) as the 16-bit register USBCON, HTXRSV is set with a

16-bit memory manipulation instruction.

RESET input sets HTXRSV to 00H.

SETUP reception^Notealso sets HTXRSV to 00H.

Note SETUP reception implies the satisfaction of all the following three conditions.

• Matching of address

• Endpoint 0 received

• No error in reception

Figure 8-16. Format of Handshake Packet Transmit Reservation Register (1/2)

Symbol

7

6

5

4

3

2

1

0

Address

FF14H

After reset

00H

R/W

HTXRSV E1STEN E0STEN DSTEN STALEN E1NAEN E0NAEN DNAEN ACKEN

E1STEN

STALL packet transmit reservation flag for Endpoint 1 after IN packet

No data is transmitted.

0

1

STALL handshake is transmitted when all the following conditions are satisfied in EOP during IN packet reception.

INRX (internal signal) = 1, ADRRST = 1, END1RX = 1, TBYER = 0, TBITER = 0, CRC5ER = 0

E0STEN

STALL packet transmit reservation flag for Endpoint 0 after IN packet

No data is transmitted.

0

1

STALL handshake is transmitted when all the following conditions are satisfied in EOP during IN packet reception.

INRX (internal signal) = 1, TIDRST = 1, ADRRST = 1, END0RX = 1, TBYER = 0, TBITER = 0, CRC5ER = 0

DSTEN

STALL packet transmitted reservation flag for data packet receive byte length error

No data is transmitted.

0

1

STALL handshake is transmitted when all the following conditions are satisfied in EOP during data packet reception.

Set this flag to transmit STALL handshake when byte length error has occurred in one data packet during

control write transfer.

DIDRST = 1, DBYER = 1, DBITER = 0

STALEN

STALL packet transmit reservation flag after data packet

No data is transmitted.

0

1

STALL handshake is transmitted when all the following conditions are satisfied in EOP during data packet reception.

Set this flag when length error of transfer occurs in control write transfer.

DIDRST = 0, DBITER = 0

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Figure 8-16. Format of Handshake Packet Transmit Reservation Register (2/2)

E1NAEN

NAK packet transmit reservation flag for Endpoint 1 after IN packet

No data is transmitted.

0

1

NAK handshake is transmitted when all the following conditions are satisfied in EOP during IN packet reception.

INRX (internal signal) = 1, ADRRST = 1, END1RX = 1, TBYER = 0, TBITER = 0, CRC5ER = 0

E0NAEN

NAK packet transmit reservation flag for Endpoint 0 after IN packet

No data is transmitted.

0

1

NAK handshake is transmitted when all the following conditions are satisfied in EOP during IN packet reception.

INRX (internal signal) = 1, TIDRST = 1, ADRRST = 1, END0RX = 0, TBYER = 0, TBITER = 0, CRC5ER = 0

DNAEN

NAK packet transmit reservation flag after data packet reception

No data is transmitted.

0

1

If all the following conditions are met, NAK handshake is transmitted in EOP during data packet reception.

Set this flag when saving data from reception data addresses (USBR0 to USBR7).

OUTRX (internal signal) = 1, DIDRST = 1, DBYER = 0, DBITER = 0, CR16ER = 0, UWDERR = 0

ACKEN

ACK packet transmit reservation flag after data packet reception

No data is transmitted.

0

1

ACK handshake is transmitted when all the following conditions are satisfied in EOP during data packet reception.

DIDRST = 1, DBYER = 0, DBITER = 0, CR16ER = 0

During transmit reservation, all the conditions listed in Table 8-3 below must be satisfied.

Table 8-3. Conditions in Transmit Reservation (1/2)

(a) Transmit reservation for Endpoint 0 and IN token packet

Type of Reservation

DT00EN

DT10EN

E0STEN

E0NAEN

Transmit reservation of data in transmit buffer 0

Transmit reservation of data in transmit buffer 1

1

0

1

0

1

0

Endpoint 0 STALL transmit reservation

(occurrence of length error, or halt status)

Endpoint 0 NAK transmit reservation

(data creation incomplete)

0

1

Two or more reservations above

Setting prohibited

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Table 8-3. Conditions in Transmit Reservation (2/2)

(b) Transmit reservation for Endpoint1 and IN token packet

Type of Reservation

DT01EN

DT11EN

E1STEN

E1NAEN

Transmit reservation of data in transmit buffer 0

Transmit reservation of data in transmit buffer 1

1

0

1

0

1

0

Endpoint 1 STALL transmit reservation

(halt status)

Endpoint 1 NAK transmit reservation

(no transmit data)

0

1

Two or more reservations above

Setting prohibited

(c) Handshake transmit reservation for data packet

Type of Reservation

STALEN

1

DNAEN

STALL transmit reservation during occurrence

of length error

0

NAK transmit reservation during previous

receive data save^Note

0

1

Two or more reservations above

Setting prohibited

Type of Reservation

ACKEN

1

DNAEN

0

ACK transmit reservation during normal data

packet reception

NAK transmit reservation during previous

receive data save^Note

0

1

Two or more reservations above

Setting prohibited

Note When saving the receive data packet, set DWRMSK to 1 (bit 0 of the data/handshake packet

receive mode register (URXMOD)) at the same time.

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Figure 8-17. Configuration of Handshake Packet Transmit Reservation Register

E1STEN E0STEN DSTEN STALEN E1NAEN E0NAEN DNAEN ACKEN

END1RX

END0RX

IN RX^Note

TIDRST

ADRRST

TBYER

TBITER

CRC5ER

JUDGE

TOKEN^Note

TX

JUDGE

MASTER EN^Note

DATA^Note

DIDRST

DBYER

DBITER

CR16ER

Note Because these signals are used internally, confirmation by software is not possible.

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(8) USB timer start reservation control register (USBTCL)

This register reserves USB timer start after reception of a SETUP/OUT packet or transmission of a data packet.

USBTCL is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets USBTCL to 01H.

SETUP reception^Notealso sets USBTCL to 01H.

Note SETUP reception implies the satisfaction of all the following three conditions.

• Matching of address

• Endpoint 0 received

• No error in reception

Figure 8-18. Format of USB Timer Start Reservation Control Register

Symbol

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Address

FF6CH

After reset

01H

R/W

USBTCL

DATATX SETORX

DATATX

USB timer start reservation after data packet transmission

0

1

Do not start USB timer.

USB timer starts when all the following conditions are satisfied in EOP during data packet transmission.

DIDRST = 1, DBYER = 0, DBITER = 0, CR16ER = 0

SETORX

USB timer start reservation after SETUP/OUT token packet reception

Do not start USB timer.

0

1

USB timer starts when all the following conditions are satisfied in EOP during SETUP/OUT token packet reception.

OUTRX (internal signal) = 1 or SETRX = 1, ADRRST = 1, END0RX = 1, TBYER = 0, TBITER = 0, CRC5ER = 0

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(9) Remote wake-up control register (REMWUP)

This register transmits the Resume signal to perform remote wakeup.

Remote wakeup must be performed after confirming that bus idle has continued longer than 5 ms.

REMWUP is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets REMWUP to 08H.

Figure 8-19. Format of Remote Wakeup Control Register

Symbol

7

0

6

0

5

0

4

0

<3>

<2>

<1>

<0>

Address

FF6AH

After reset

08H

R/W

REMWUP

PULLDM PULLDP PULLEN WAKEUP

PULLDM

D- lead low/high fixed output setting

0

1

D- (TXDM) is fixed to low output.

D- (TXDM) is fixed to high output.

PULLDP

D+ lead low/high fixed output setting

0

1

D+ (TXDP) is fixed to low output.

D+ (TXDP) is fixed to high output.

PULLEN

D+/D- lead fixed output enable

0

1

Output from transmit buffer is input to USB driver.

Level set to PULLDP or PULLDM is input to USB driver.

WAKEUP

Wakeup signal output

0

1

No data is sent.

Pin status set to PULLDP or PULLDM is output.

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8.5 USB Function Operation

8.5.1 USB timer operation

The USB timer is a 7-bit counter that performs time management during packet transmission and reception and

inadvertent program loop detection of the USB clock.

The USB timer has two modes: high-speed mode (source clock = f^X) and low-speed mode (source clock = USB

clock: f^X= 1.5 MHz during 6.0 MHz operation). In the high-speed mode, the USB functions as a 6-bit counter.

High-speed mode is used for time management during packet transmission and reception. The timer starts after

EOP reception or data packet EOP transmission. The start condition is set by the USB timer start reservation control

register (USBTCL).

Low-speed mode is used for detecting inadvertent program loops of the USB clock. The timer starts upon

detection of the SYNC signal of a receive packet, or upon reception of the USB reset or Resume signals.

When the USB timer overflows, an interrupt request signal (INTUSBTM) is generated, regardless of whether the

current mode is the high-speed or low-speed mode. When overflow of the USB timer occurs in the low-speed mode,

UWDERR (bit 7 of the packet receive status register (RXSTAT)) is set, allowing detection of an inadvertent loop of the

USB timer. At this time, the USB clock is forcibly stopped.

Figure 8-20 shows the operation flowchart of the USB timer.

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Figure 8-20. Flowchart of USB Timer Operation (1/2)

1

Idle state

N

SYNC detected?

Y

2

USB timer reset

USB timer start

(low-speed mode)

N

EOP received?

Y

N

Low-speed

mode overflow?

USB timer reset

Y

INTUSBTM occurred

N

SETUP/OUT

packet?

UWDERR set

(inadvertent program

loop detection)

Y

SETORX

(internal signal)

= 1?

N

IN packet?

Y

Transmit data

transferring?

Y

N

Transmit EOP is

output?

Y

DATA TX

(internal signal)

= 1?

Y

3

UWDERR: Bit 7 of packet receive status register (RXSTAT)

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Figure 8-20. Flowchart of USB Timer Operation (2/2)

3

USB timer start

(high-speed mode)

N

Next SYNC

detected?

Y

2

N

High-speed

mode overflow?

Y

INTUSBTM occurred

1

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8.5.2 Remote wakeup control operation

Figure 8-21. Flow Chart of Remote Wakeup Control Operation

Idle state

N

Resume output

started?

Y

Is bus idle

duration longer

than 5 ms?

Did HOST

output USB reset or

Resume?

N

Y

PULLDP = 0

PULLDM = 1

PULLDP = 0

PULLDM = 1

A ← 00000111B

PULLEN = 1

Resume

Idle state

output^{Note 1}

WAKEUP = 1

REMWUP ← A

N

10 ms to 15 ms

elapsed?

Y

WAKEUP = 0

Resume output

completion^{Note 2}

PULLEN =0

PULLDP = 0

PULLDM = 1

Idle state

PULLDP: Bit 2 of remote wakeup control register (REMWUP)

PULLDM: Bit 3 of remote wakeup control register (REMWUP)

PULLEN: Bit 1 of remote wakeup control register (REMWUP)

WAKEUP: Bit 0 of remote wakeup control register (REMWUP)

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Notes 1. Be sure to follow the exact instruction sequence when the Resume signal (“K” state) is output.

SET1

CLR1

MOV

SET1

MOV

REMWUP.3

REMWUP.2

; (PULLDM ← 1)

; (PULLDP ← 0)

“J” state generation

A, #00000111B ; (A ← 00000111B)

REMWUP.1

REMWUP.0

REMWUP, A

; (PULLEN ← 1)

; (WAKEUP ← 1), “J” state output

; (REMWUP ← A), “K” state output

2. Be sure to follow the exact instruction sequence to append EOP when terminating Resume output.

CLR1

SET1

REMWUP.0

REMWUP.1

REMWUP.2

REMWUP.3

; (WAKEUP ← 0) , Resume output end

; (PULLEN ← 0)

; (PULLDP ← 0)

“J” state generation

; (PULLDM ← 1)

Figure 8-22. Configuration of Remote Wakeup Control

TXEN^Note

WAKEUP (REMWUP.0)

Transmit data (+ side)

PULLDP (REMWUP.2)

Transmit data (- side)

PULLDM (REMWUP.3)

D+ pin (USBDP)

D- pin (USBDM)

PULLEN (REMWUP.1)

SEP, SEM disable signal

TX MASTER EN^Note

Note Because this signal is used internally, confirmation by software is not possible.

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8.6 Interrupt Request from USB Function

8.6.1 Interrupt sources

Interrupt request sources generated by the USB function fall into the following five categories.

Table 8-4. List of Sources of Interrupts from USB Function

Type of Interrupt Priority^Note

Interrupt Source

Trigger

Vector Table

Address

Name

Maskable

1

2

3

4

5

INTUSBTM

INTUSBRT

INTUSBRD

INTUSBST

INTUSBRE

USB timer overflow

0006H

0008H

000AH

000CH

000EH

EOP detection when a USB token packet is received

EOP detection when a USB data/handshake packet is received

EOP detection when a USB data/handshake packet is transmitted

Detection of transition from J state to K state or SE0 on the USB bus

Note The priority is the order of priority when multiple maskable interrupts are generated simultaneously.

(1) Token packet receive interrupt (INTUSBRT)

Upon EOP detection during token packet reception, an interrupt request signal is generated and an interrupt

request flag (USBRTIF) is set. If ADRRST (bit 2 of the token packet receive result store register (TRXRSL)) is 0,

no interrupt request is generated because a token packet of another device exists on the bus.

(2) Data/handshake packet receive interrupt (INTUSBRD)

Upon EOP detection during data/handshake packet reception, an interrupt request signal is generated and an

interrupt request flag (USBRDIF) is set regardless of error at reception.

If DINTEN (bit 1 of the data/handshake packet receive mode register (URXMOD)) is set to 1, an interrupt request

(receive status synchronous interrupt) signal is generated when 11B is detected by the ID detection buffer.

Figure 8-23. Timing of Data/Handshake Packet Receive Interrupt Request Generation

Sync

Data0 Data1

DataX

CRC16

EOP

EOP received

Packet ID detected

INTUSBRD

(DINTEN = 0)

INTUSBRD

(DINTEN = 1)

Data packet

receive status

synchronous interrupt

Data/handshake packet

receive interrupt

DINTEN: Bit 1 of data/handshake packet receive mode register (URXMOD)

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(3) Data/handshake packet transmit interrupt (INTUSBST)

Upon EOP detection during data/handshake packet transmission, an interrupt request signal is generated and an

interrupt request flag (USBSTIF) is set.

(4) USB timer overflow interrupt (INTUSBTM)

If the USB timer overflows, an interrupt request signal is generated and an interrupt request flag (USBTMIF) is

set.

(5) USB reset/Resume detection interrupt (INTUSBRE)

This is an interrupt to release the STOP mode.

If transition from J state (logic 0) to K state (logic 1) is detected on the bus, or transition to SE0 is detected, an

interrupt request signal is generated and an interrupt request flag (USBREIF) is set.

Figure 8-24. Timing of INTUSBRE Generation

(a) Period of RESMOD = 0 and Single-ended 0 (SE0) is 3.0 µs or longer (microcontroller operation)

D+ (USBDP)

L

D- (USBDM)

µ

3.0 s or longer

INTUSBRE

3.0 µs

(b) Period of RESMOD = 0 and SE0 is shorter than 3.0 µs (microcontroller operation)

D+ (USBDP)

L

D- (USBDM)

Shorter than 3.0 µs

INTUSBRE

Not set

(c) RESMOD = 1^Note

D+ (USBDP)

L

D- (USBDM)

INTUSBRE

Set irrespective of SE0 period

Note Do not set RESMOD to 1 during bus idle. Set RESMOD immediately before the STOP instruction.

Remark RESMOD: Bit 2 of data/handshake packet receive mode register (URXMOD)

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8.6.2 Cautions when using interrupts

Pay attention to the following when using an interrupt request generated by the USB function.

(1) Because USBREIF is set by transition from the J state to the K state on the bus, it is also set during sync

detection or packet reception. Thus, disable the generation of interrupt requests by setting the interrupt mask

flag (USBREMK) during bus idle or control transfer.

(2) Because USBREIF is set by transition from the J state to the SE0 state, or by transition from the K state to the

SE0 state on the bus, it is also set during EOP reception or bus idle retention EOP reception. Thus, disable

the generation of interrupt requests by setting the interrupt mask flag (USBREMK) during bus idle or control

transfer.

(3) When clearing the interrupt mask flag (USBREMK), do so immediately before the transition to bus suspend

mode (immediately before the STOP instruction execution).

(4) When the USB reset signal or the Resume signal is received, the USB clock starts operating. As a

consequence, USBTMIF and UWDERR are set after the elapse of a certain period (85.3 µs: fX = 6.0 MHz

operation) of time from reception start. Therefore, when shifting to bus suspend mode (execution of stop

instruction), set the interrupt mask flag (USBTMMK) and disable the generation of interrupt requests.

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CHAPTER 8 USB FUNCTION

8.7 USB Function Control

8.7.1 Relationship between packets and operation modes

The relationship between packets and operation modes in the USB function is as follows.

(1) Control transfer (OUT) (Transfer byte count: 8 bytes or less)

Packet flow

Packet from

PD789800

Packet from

host controller

Operation of host

controller

Operation of USB

µ

function of PD789800

µ

SETUP

DATA0

Setup

stage

ACK transmission

reservation

Request

• ACK transmission

• NAK transmission

reservation

ACK

OUT

Data

stage OUT

reception

OUT packet

• NAK transmission

reservation clear

• ACK transmission

reservation

DATA1

ACK

• ACK transmission

•

DATA1 transmission

reservation

Status

stage IN

reception

IN

IN packet

DATA1

DATA1 transmission

ACK

ACK packet

NAK transmission

reservation

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CHAPTER 8 USB FUNCTION

(2) Control transfer (OUT) (Transfer byte count: 9 bytes or more)

Packet flow

Packet from

PD789800

µ

Packet from

host controller

Operation of

host controller

Operation of USB

function of PD789800

µ

SETUP

DATA0

ACK transmission

reservation

Setup

stage

Request

• ACK transmission

• NAK transmission

reservation

ACK

OUT

Data

stage OUT

reception

OUT packet

• NAK transmission

reservation clear

• ACK transmission

reservation

DATA1

• ACK transmission

• NAK transmission

reservation

ACK

OUT

OUT packet

• NAK transmission

reservation clear

• ACK transmission

reservation

DATA0

• ACK transmission

• NAK transmission

reservation

OUT

OUT packet

• NAK transmission

reservation clear

• ACK transmission

reservation

DATA1

• ACK transmission

• NAK transmission

reservation

OUT

OUT packet

• NAK transmission

reservation clear

• ACK transmission

reservation

DATA1/0

ACK

• ACK transmission

•

DATA1 transmission

reservation

Status stage

IN reception

IN

IN packet

DATA1

DATA1 transmission

ACK

ACK packet

NAK transmission

reservation

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CHAPTER 8 USB FUNCTION

(3) Control transfer (IN) (Transfer byte count: 8 bytes or less)

Packet flow

Packet from

host controller

Operation of host

controller

Operation of USB

PD789800

µ

function of PD789800

µ

SETUP

DATA0

Setup

stage

ACK transmission

reservation

Request

• ACK transmission

ACK

•

DATA1 transmission

reservation

IN

Data

stage IN

reception

IN packet

•

DATA1 transmission

DATA1

• NAK transmission

reservation

ACK

NAK transmission

reservation clear

OUT

OUT packet

ACK transmission

reservation

DATA1

Status

stage OUT

reception

• ACK transmission

ACK

•

USB communication

completion timer

start

OUT

reception

wait

USB communication

completion timer timeout^Note

NAK transmission

reservation

Note If the ACK from the device cannot be received normally, the host transmits OUT again. Therefore, set

the OUT receive wait state for a period so that the OUT can be received. Use a normal 8-bit timer for

counting during this period.

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CHAPTER 8 USB FUNCTION

(4) Control transfer (IN) (Transfer byte count: 9 bytes or more)

Packet flow

Packet from

PD789800

Packet from

host controller

Operation of host

controller

Operation of USB

µ

function of PD789800

µ

SETUP

DATA0

Setup

stage

ACK transmission

reservation

Request

• ACK transmission

ACK

•

DATA1 transmission

reservation

Data

stage IN

reception

IN

IN packet

•

DATA1 transmission

DATA1

• NAK transmission

reservation

ACK

IN

NAK transmission

reservation clear

IN packet

• NAK transmission

NAK

•

DATA0 transmission

reservation

IN

IN packet

•

DATA0 transmission

DATA0

• NAK transmission

reservation

ACK

ACK packet

NAK transmission

reservation clear

IN

IN packet

• NAK transmission

NAK

•

DATA1 transmission

reservation

IN

IN packet

ACK packet

OUT packet

•

DATA0/1 transmission

DATA0/1

• NAK transmission

reservation

ACK

NAK transmission

reservation clear

OUT

ACK transmission

reservation

Status

stage OUT

reception

DATA1

• ACK transmission

ACK

•

USB communication

completion timer start

OUT

reception

wait

USB communication

completion timer

timeout^Note

NAK transmission

reservation

Note If the ACK from the device cannot be received normally, the host transmits OUT again. Therefore, set

the OUT receive wait state for a period so that the OUT can be received. Use a normal 8-bit timer for

counting during this period.

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CHAPTER 8 USB FUNCTION

(5) No data control

Packet flow

Packet from

PD789800

Packet from

host controller

Operation of host

controller

Operation of USB

µ

function of PD789800

µ

Setup

stage

SETUP

ACK transmission

reservation

Request

DATA0

• ACK transmission

ACK

•

DATA1 transmission

reservation

Status

stage

No data

control

IN

IN packet

DATA1

DATA1 transmission

ACK

ACK packet

NAK transmission

reservation

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CHAPTER 8 USB FUNCTION

(6) Interrupt transfer

Packet flow

Packet from

host controller

Operation of host

controller

Operation of USB

PD789800

µ

function of PD789800

µ

ACK transmission

reservation

IN

• NAK transmission

NAK

•

DATA1 transmission

reservation

IN

IN packet

•

DATA1 transmission

DATA1

• NAK transmission

reservation

ACK

IN

NAK transmission

reservation clear

IN packet

•

NAK transmission

DATA0 transmission

reservation

NAK

IN

•

DATA0 transmission

DATA0

• NAK transmission

reservation

ACK

IN

IN packet

• NAK transmission

reservation

NAK

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CHAPTER 8 USB FUNCTION

8.7.2 Interrupt servicing flow

(1) USB token packet reception interrupt servicing

INTUSBRT occurrence

Yes

Receive error occurred?

No

Token mismatch

processing

Yes

Receive token is OUT?

No

Yes

Waiting for OUT token?

Yes

Receive token is

SETUP?

No

OUT token reception

processing

No

Yes

Receive token is

unplanned token?

No

Yes

OUT to ENDPOINT 1?

No

SETUP token

reception processing

OUT token reception

processing to ENDPOINT 1

Yes

IN token reception

to ENDPOINT 1?

IN token reception

processing to ENDPOINT 0

No

OUT token reception

processing when status stage

IN or data stage IN is received

IN token reception

processing to ENDPOINT 1

RETI

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CHAPTER 8 USB FUNCTION

(2) Data/handshake packet reception interrupt servicing

INTUSBRD occurrence

Yes

No

Planned packet

was received?

No

USB_MODE is

data stage OUT

reception?

Yes

Transition processing to

status stage OUT reception

Re-transmit data reception

reservation processing

USB_MODE is

waiting for communication

request?

No

Yes

No

USB_MODE is SETUP?

Yes

ACK reception processing

to ENDPOINT 1

USB request processing

DATA/ACK reception

processing to ENDPOINT 0

RETI

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CHAPTER 8 USB FUNCTION

(3) USB timer inadvertent program loop detection interrupt servicing

INTUSBTM occurrence

Processing for each

operation mode when

ACK is not received

and for when

DATA is not received

after receiving OUT

RETI

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CHAPTER 8 USB FUNCTION

(4) 1 ms timer interrupt servicing

INTTM00 occurrence

DURATION base

timer processing

10 ms timer counting

USB communication

completion timer processing

Waiting for

resume signal

completion?

Yes

No

Yes

RESET received?

No

Resume signal completion

wait processing

USB reset processing

No

Communication

operating?

Yes

No

Standby detected?

Yes

Standby processing

No

REMOTE WAKEUP?

Yes

RESUME output processing

RETI

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CHAPTER 8 USB FUNCTION

8.8 USB Function Internal Circuit Operations

8.8.1 Operation of transmit/receive pointer

Figure 8-25. Flowchart of Transmit/Receive Pointer Operation (1/7)

(1) Token packet reception (1/2)

Idle state

1

EOP

Transmit/receive

signal?

Bit normal write?

Y

Token reception

Set TBYER flag

Idle state

Set USBPOW to 00H

Y

Does bit stuffing

signal = 1?

Set USBPOB to 00H

N

USBPOB increment

EOP

Bit normal write?

Y

N

USBPOB

= 02H?

Set TBYER flag

Idle state

Y

Does bit stuffing

signal = 1?

EOP

Bit normal write?

N

USBPOB increment

Set TBYER flag

Idle state

Y

Does bit stuffing

signal = 1?

N

USBPOB

overflow?

N

Y

Set USBPOW to 70H

USBPOW increment

Set USBPOB to 00H

Y

USBPOW

= 01H?

Set CRC5 execution

start signal

2

N

USBPOW

= 02H?

Y

1

TBYER: Bit 5 of token packet receive result store register (TRXRSL)

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CHAPTER 8 USB FUNCTION

Figure 8-25. Flowchart of Transmit/Receive Pointer Operation (2/7)

(1) Token packet reception (2/2)

2

EOP

Bit normal write?

Y

Set TBYER flag

Idle state

Y

Does bit stuffing

signal = 1?

N

USBPOB increment

N

USBPOW

= 05H?

Y

EOP

normal receive?

N

Y

Set TBYER flag

Idle state

TBYER: Bit 5 of token packet receive result store register (TRXRSL)

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CHAPTER 8 USB FUNCTION

Figure 8-25. Flowchart of Transmit/Receive Pointer Operation (3/7)

(2) Data/Handshake packet reception (1/2)

Idle state

EOP

Transmit/receive

signal?

Bit normal write?

Y

Data/handshake reception

Set DBYER flag

Idle state

Set USBPOW to 10H

Y

Does bit stuffing

signal = 1?

Set USBPOB to 00H

N

USBPOB increment

Does

Y

USBPOW match

DRXCON?

N

USBPOB

overflow?

N

Y

EOP

Bit normal write?

Y

HSSTAT = 1?

1

Set DBYER flag

Idle state

N

Y

Does bit stuffing

signal = 1?

Set USBPOW to 70H

N

USBPOB increment

2

N

USBPOB

overflow?

Y

USBPOW increment

Y

USBPOW

= 11H?

Set CRC16 execution

start signal

N

DBYER:

Bit 5 of data/handshake packet receive result store register (DRXRSL)

Data/handshake packet receive byte number counter

DRXCON:

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CHAPTER 8 USB FUNCTION

Figure 8-25. Flowchart of Transmit/Receive Pointer Operation (4/7)

(2) Data/Handshake packet reception (2/2)

2

EOP

Bit normal write?

Y

Set DBYER flag

Idle state

Y

N

Y

Does bit stuffing

signal = 1?

N

USBPOB increment

USBPOB

overflow?

Y

USBPOW increment

USBPOW

= 71H?

1

N

USBPOB increment

EOP

received normally?

N

Y

Set DBYER flag

Idle state

DBYER: Bit 5 of data/handshake packet receive result store register (DRXRSL)

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CHAPTER 8 USB FUNCTION

Figure 8-25. Flowchart of Transmit/Receive Pointer Operation (5/7)

(3) Data packet transmit (1/2)

1

Idle state

m = 0: send buffer 0

m = 1: send buffer 1

Does

USBPOW match

DTXCOm?

Y

Transmit/receive

signal?

2

Y

N

Data/handshake transmission

Set USBPOW to 7FH

Set USBPOB to 00H

Bit read

Bit Read

Y

Does bit stuffing

signal = 1?

N

USBPOB increment

Y

Does bit stuffing

signal = 1?

N

USBPOB

overflow?

N

USBPOB increment

Y

USBPOW increment

N

USBPOB

overflow?

Y

USBPOW

= n1H?

Y

Set CRC16 execution

start signal

N

Handshake

Go to (4)

Transmit area?

(reservation flag

judgment)

Transmit buffer

n = 2: Transmit buffer 0

n = 3: Transmit buffer 1

Set USBPOW to n0H

1

DTXCO0, DTXCO1: Data packet transmit byte number counter

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CHAPTER 8 USB FUNCTION

Figure 8-25. Flowchart of Transmit/Receive Pointer Operation (6/7)

(3) Data packet transmit (2/2)

2

3

Set EOP

transmit signal

Bit Read

Y

Does bit stuff

signal = 1?

Idle state

N

USBPOB increment

N

USBPOB

overflow?

Y

Set USBPOW to 70H

Read CRC

redundant bit

Y

Does bit stuffing

signal = 1?

N

USBPOB increment

N

USBPOB

overflow?

Y

USBPOW increment

Y

USBPOW

= 71H?

N

3

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CHAPTER 8 USB FUNCTION

Figure 8-25. Flowchart of Transmit/Receive Pointer Operation (7/7)

(4) Handshake packet transmission

Idle state

1

Bit read

Transmit/receive

signal?

Y

Data/handshake transmission

Y

Does bit stuffing

signal = 1?

Set USBPOW to 7FH

N

Set USBPOB to 00H

USBPOB increment

Bit read

N

USBPOB

overflow?

Y

Does bit stuffing

signal = 1?

Set EOP

transmit signal

N

USBPOB increment

Idle state

N

USBPOB

overflow?

Y

Transmit buffer

Transmit area?

(reservation flag

judgment)

Go to (3)

Handshake

n = 4: ACK

n = 5: NAK

n = 6: STALL

Set USBPOW to n0H

1

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CHAPTER 8 USB FUNCTION

8.8.2 Receive bank switching ID detection buffer operation

Figure 8-26. Flowchart of Receive Bank Switching ID Detection Buffer Operation

Idle state

Sync1 detection

signal = 1?

Y

2-bit store & shift

Bit judgment enable

00B

Store bit ?

11B

10B

01B

Set DASTAT

Set HSSTAT

Set TOSTAT

Y

Bit judgment mask

1-bit store & shift

EOP received?

N

Y

Set buffer to 00H

Idle state

TOSTAT:

DASTAT:

HSSTAT:

Bit 0 of packet receive status register (RXSTAT)

Bit 1 of packet receive status register (RXSTAT)

Bit 2 of packet receive status register (RXSTAT)

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CHAPTER 8 USB FUNCTION

8.8.3 Sync detection/USBCLK detector operation

This circuit generates the USBCLK signal (1.5 MHz) upon detecting the sync part of the receive packet. In

addition, it contains an NRZI decoder that decodes receive packets and detects the last bit of the sync part.

When the last sync bit is detected, a signal that specifies start of storing in the ID detection buffer is output.

Figure 8-27. Timing of Sync Detection/USBCLK Detector Operation

Receive packet

USBCLK generation

USBCLK

NRZI decode

SYNC last bit detection

Data after decoding

SYNC pattern

After token packet

Figure 8-28. Timing of Sync Detection/USBCLK Generation Operation

f

X

TX MASTER EN^Note

USBCLK

L

0

1

0

1

0

1

0

1

0

Receive data

(RXD)

Idle

Sync

Resume RX^Note

(INTUSBRE)

Note Because these signals are used internally, confirmation by software is not possible.

Remark The USB clock starts operating at the falling edge of f^Xafter transition from the J state to the K state of

the bus. However, this control is masked if TX MASTER EN = 1.

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CHAPTER 8 USB FUNCTION

Figure 8-29. Flowchart of Sync Detection/USBCLK Detector Operation

Idle state

N

Did state change

to K state?

Y

USB clock

oscillation start

Output 0

from NRZI decoder

Receive next bit

Y

Did bus state

change?

N

Output 1

from NRZI decoder

Detect last Sync bit

Y

Was EOP receive

signal set?

N

Receive next bit

N

Did bus state

change?

USB clock stop

Idle state

Y

Output 0

from NRZI decoder

Output 1

from NRZI decoder

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CHAPTER 8 USB FUNCTION

8.8.4 NRZI encoder operation

This circuit performs NRZI encoding of data to be transmitted.

Figure 8-30. Timing of NRZI Encoder Operation

Data

before encoding

Sync pattern

NRZI encoding

Data/handshake packet

Transmit packet

USB clock generation

Figure 8-31. Flow Chart of NRZI Encoder Operation

Idle state

N

Transmit start?

Y

Sync.0 input

Reverse output level

(1 output)

Next bit input

N

Input bit = 0?

Y

Maintain

Reverse output level

previous output level

Was

N

EOP transmit signal

set?

Y

Idle state

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CHAPTER 8 USB FUNCTION

8.8.5 Bit stuffing/strip controller operation

This circuit counts the number of “logic 1” of transmit/receive packets. If six successive logic 1s are detected, it

outputs an increment disable signal to the transmit/receive pointer (USBPOB). During packet transmission, it inserts

“logic 0” simultaneously with the increment disable signal.

Moreover, during bit stripping, if the bit that should be deleted was a “logic 1,” this is detected as a bit stuffing error.

Figure 8-32. Timing of Bit Stuffing/Strip Controller Operation

(1) Bit stuffing

If “1” occurs six successive times, a “0” is inserted forcibly to shift the level.

RAW data

Idle

Sync pattern

Packet data

Stuff bit

Bit stuffing

data

Logic 1 × 6 times

NRZI

encoding data

Packet data

(2) Bit striping

If “1” occurs six successive times, the next bit is deleted as a stuffing bit.

Stuffing bit

Bit stuffing data

(NRZI decoding)

Idle

Sync pattern

Packet data

Logic 1 × 6 times

Bit strip data

Packet data

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CHAPTER 8 USB FUNCTION

Figure 8-33. Flow Chart of Bit Stuffing Control Operation

Idle state

N

Transmission start?

Y

Transmit bit input

N

Transmit bit = 1?

Y

Shift bit

Reset bit

stuffing register

N

Bit stuffing register

= 3FH?

Y

Disable

USBPOB increment

Reset bit

stuffing register

Disable save

of next transmit bit

Was

EOP receive signal

set?

N

Y

Idle state

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CHAPTER 8 USB FUNCTION

Figure 8-34. Flow Chart of Bit Strip Control Operation

Idle state

N

Reception start?

Y

Receive bit input

N

Receive bit = 1?

Y

Shift bit

Reset bit

stuffing register

N

Y

N

Bit stuffing register

= 3FH?

Y

Disable

USBPOB increment

Was

EOP receive signal

set?

1

N

Receive bit input

Receive bit = 1?

Reset bit

stuffing register

Y

Bit stuffing error output

Was

EOP receive signal

set?

N

Y

1

Idle state

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CHAPTER 9 SERIAL INTERFACE 10

9.1 Functions of Serial Interface 10

Serial interface 10 has the following two modes.

• Operation stop mode

• 3-wire serial I/O mode

(1) Operation stop mode

This mode is used when serial transfer is not carried out. It enables a reduction in power consumption.

(2) 3-wire serial I/O mode (MSB/LSB start bit switchable)

In this mode, 8-bit data transfer is carried out with three lines: one for the serial clock (SCK10) and two for serial

data (SI10 and SO10).

The 3-wire serial I/O mode supports simultaneous transmit and receive operations, reducing data transfer

processing time.

It is possible to switch the start bit of 8-bit data to be transmitted between the MSB and the LSB, thus allowing

connection to devices with either start bit.

The 3-wire serial I/O mode is effective for connecting display controllers and peripheral I/Os such as the 75XL

Series, 78K Series, and 17K Series that have an internal conventional clocked serial interface.

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CHAPTER 9 SERIAL INTERFACE 10

9.2 Configuration of Serial Interface 10

Serial interface 10 consists of the following hardware.

Table 9-1. Configuration of Serial Interface 10

Item

Configuration

Register

Control register

Transmit/receive shift register 10 (SIO10)

Serial operating mode register 10 (CSIM10)

(1) Transmit/receive shift register 10 (SIO10)

This is an 8-bit register used for parallel-to-serial conversion and to perform serial data transmission/reception in

synchronization with the serial clock.

SIO10 is set with an 8-bit memory manipulation instruction.

RESET input makes SIO10 undefined.

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CHAPTER 9 SERIAL INTERFACE 10

9.3 Register Controlling Serial Interface 10

The following register is used to control serial interface 10.

• Serial operation mode register 10 (CSIM10)

(1) Serial operation mode register 10 (CSIM10)

This register is used to control serial interface 10 and set the serial clock and start bit.

CSIM10 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets CSIM10 to 00H.

Figure 9-2. Format of Serial Operation Mode Register 10

<7>

6

0

5

0

4

3

0

2

1

0

Address

FF72H

After reset

00H

R/W

Symbol

CSIM10 CSIE10

TPS100

DIR10 CSCK10

CSIE10

Operation control in 3-wire serial I/O mode

0

1

Operation disabled

Operation enabled

TPS100

Count clock selection when operation enabled in 3-wire serial I/O mode

f

X

/2²

/2³

0

1

fX

DIR10

Start bit specification

0

1

MSB

LSB

CSCK10

Clock selection in 3-wire serial I/O mode

0

1

Clock input to SCK10 pin from external

Internal clock selected by TPS100

Caution

Bits 0, 3, 5, and 6 must be set to 0.

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CHAPTER 9 SERIAL INTERFACE 10

Table 9-2. Operating Mode Settings of Serial Interface 10

(1) Operation stop mode

CSIM10

PM22 P22 PM21 P21 PM20 P20 Start

Bit

Shift

P22/SI10

P21/SO10

P20/SCK10

Pin Function

CSIE10 DIR10 CSCK10

Clock

Pin Function

Note 1

×

Note 1

×

Note 1

×

Note 1

×

Note 1

×

Note 1

×

0

—

P22

P21

P20

Other than above

Setting prohibited

(2) 3-wired serial I/O mode

CSIM10

PM22 P22 PM21 P21 PM20 P20 Start

Shift

P22/SI10

P21/SO10

P20/SCK10

Pin Function

CSIE10 DIR10 CSCK10

Bit

Clock

Pin Function

Note 2

×

1

×

1

0

1

0

1

1^{Note 2}

0

1

0

1

0

MSB External SI10^{Note 2}

clock

SO10

SCK10 input

SCK10 output

SCK10 input

SCK10 output

(CMOS output)

Internal

clock

1

LSB External

clock

Internal

clock

Other than above

Setting prohibited

Notes 1. Can be used as port function.

2. If used only for transmission, can be used as P22 (CMOS input/output).

Remark ×: don’t care

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CHAPTER 9 SERIAL INTERFACE 10

9.4 Operation of Serial Interface 10

Serial interface 10 provides the following two modes.

• Operation stop mode

• 3-wire serial I/O mode

9.4.1 Operation stop mode

In the operation stop mode, serial transfer is not executed; therefore, the power consumption can be reduced.

The P20/SCK10, P21/SO10, and P22/SI10 pins can be used as normal I/O ports.

(1) Register setting

Operation stop mode is set by serial operation mode register 10 (CSIM10).

Serial operation mode register 10 (CSIM10)

CSIM10 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets CSIM10 to 00H.

<7>

6

0

5

0

4

3

0

2

1

0

Address

FF72H

After reset

00H

R/W

Symbol

CSIM10 CSIE10

TPS100

DIR10 CSCK10

CSIE10

Operation control in 3-wire serial I/O mode

0

1

Operation disabled

Operation enabled

Caution

Bits 0, 3, 5, and 6 must be set to 0.

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CHAPTER 9 SERIAL INTERFACE 10

9.4.2 3-wire serial I/O mode

The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which

incorporate a conventional synchronous serial interface, such as the 75XL Series, 78K Series, 17K Series, etc.

Communication is performed using three lines: the serial clock (SCK10), serial output (SO10), and serial input

(SI10).

(1) Register setting

3-wire serial I/O mode settings are performed using serial operating mode register 10 (CSIM10).

(a) Serial operation mode register 10 (CSIM10)

CSIM10 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets CSIM10 to 00H.

<7>

6

0

5

0

4

3

0

2

1

0

Address

FF72H

After reset

00H

R/W

Symbol

CSIM10 CSIE10

TPS100

DIR10 CSCK10

CSIE10

Operation control in 3-wire serial I/O mode

0

1

Operation disabled

Operation enabled

TPS100

Count clock selection when operation enabled in 3-wire serial I/O mode

f

X

/2²

/2³

0

1

X

DIR10

Start bit specification

0

1

MSB

LSB

CSCK10

Clock selection in 3-wire serial I/O mode

0

1

Clock input to SCK10 pin from external

Internal clock selected by TPS100

Caution

Bits 0, 3, 5, and 6 must be set to 0.

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CHAPTER 9 SERIAL INTERFACE 10

(2) Communication operation

In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units.

transmitted/received bit by bit in synchronization with the serial clock.

Data is

Transmit/receive shift register 10 (SIO10) shift operations are performed in synchronization with the fall of the

serial clock (SCK10). Then transmit data is held in the SO10 latch and output from the SO10 pin. Also, receive

data input to the SI10 pin is latched in the input bits of SIO10 on the rise of SCK10.

At the end of an 8-bit transfer, the operation of SIO10 stops automatically, and the interrupt request signal

(INTCSI10) is generated.

Figure 9-3. 3-Wire Serial I/O Mode Timing

SCK10

SI10

1

2

3

4

5

6

7

8

DI7

DI6

DI5

DI4

DI3

DI2

DI1

DI0

DO7

DO6

DO5

DO4

DO3

DO2

DO1

DO0

SO10

INTCSI10

End of transfer

Transfer start at the falling edge of SCK10

Cautions 1. When data is written to SIO10 in the serial operation disabled status (CSIE10 = 0), the

data cannot be transmitted or received.

2. When data is written to SIO10 in the serial operation disabled status (CSIE10 = 0) and

then serial operation is enabled (CSIE10 = 1), the data cannot be transmitted or

received.

3. Once data has been written to SIO10 with the serial clock selected (CSCK10 = 0),

overwriting the data does not update the contents of SIO10.

4. When CSIM10 is operated during data transmission/reception, data cannot be

transmitted or received normally.

5. When SIO10 is operated during data transmission/reception, the data cannot be

transmitted or received normally.

(3) Transfer start

Serial transfer is started by setting transfer data to transmit/receive shift register 10 (SIO10) when the following

two conditions are satisfied.

• Bit 7 (CSIE10) of serial operation mode register 10 (CSIM10) = 1

• Internal serial clock is stopped or SCK10 is high level after 8-bit serial transfer.

Termination of 8-bit transfer stops the serial transfer automatically and generates the interrupt request signal

(INTCSI10).

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CHAPTER 10 REGULATOR

The µPD789800 incorporates a regulator that powers the USB driver/receiver. The features are as follows.

• Generates V^REG(3.3 0.3 V) from VDD0, VDD1 (4.0 to 5.5 V) and outputs it to the REGC pin.

• Supports power-saving mode, reducing power consumption in mode.

Figure 10-1. Block Diagram of Regulator and USB Driver/Receiver

PD789800

µ

V

DD0

V

REG

Regulator

REGC

22

F

µ

V

SS

1.5 kΩ

V

SS0

V

DD0

RXD

SEP

USBDM

USBDP

SEM

USB driver/

receiver

Hub

TXDP

TXDM

TXEN

RXEN

V

SS0

Cautions 1. To stabilize the V^REGvoltage, connect the REGC pin to VSS via 22 µF capacitor.

2. Connect the pull-up resistor (1.5 kΩ) for the USBDM pin to the REGC pin.

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CHAPTER 11 INTERRUPT FUNCTIONS

11.1 Interrupt Function Types

The following two types of interrupt functions are used.

(1) Non-maskable interrupt

This interrupt is acknowledged unconditionally. It does no undergo interrupt priority control and is given top

priority over all other interrupt requests.

A standby release signal is generated.

One interrupt source from the watchdog timer is incorporated as a non-maskable interrupt.

(2) Maskable interrupt

These interrupts undergo mask control. If two or more interrupts with the same priority are simultaneously

generated, each interrupt has a predetermined priority as shown in Table 11-1.

A standby release signal is generated.

Two external and nine internal interrupt sources are incorporated as maskable interrupts.

11.2 Interrupt Sources and Configuration

A total of 12 non-maskable and maskable interrupts are incorporated as interrupt sources (see Table 11-1).

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CHAPTER 11 INTERRUPT FUNCTIONS

Table 11-1. Interrupt Source List

Type of Interrupt Priority^{Note 1}

Interrupt Source

Trigger

Vector

Table

Address

Basic

Internal/

External

Configuration

Type^{Note 2}

Name

Nonmaskable

Maskable

-

INTWDT

Watchdog timer overflow (when

Internal

0004H

(A)

(B)

watchdog timer mode 1 is selected)

0

INTWDT

Watchdog timer overflow (when

interval timer mode is selected)

1

2

INTUSBTM USB timer overflow

INTUSBRT EOP detection when a USB token

packet is received

0006H

0008H

3

4

5

INTUSBRD EOP detection when a USB

data/handshake packet is received

000AH

000CH

000EH

INTUSBST

EOP detection when a USB data/

handshake packet is transmitted

INTUSBRE

Detection of transition from J state to

K state or SE0 on the USB bus

6

7

INTP0

Detection of a pin input edge

External

Internal

0010H

0012H

(C)

(B)

INTCSI10

End of three-wire SIO bus interface

transmission and reception

8

9

INTTM00

INTTM01

INTKR00

Generation of the 8-bit timer 00

match signal

0014H

0016H

0018H

Generation of the 8-bit timer/event

counter 01 match signal

10

Detection of the key return signal

External

(C)

Notes 1. The priority is the order of priority when multiple maskable interrupts are generated simultaneously. 0

is the highest priority and 10 is the lowest.

2. Types (A) to (C) in the basic configuration correspond to (A) to (C) in Figure 11-1, respectively.

Remark Only one of the two watchdog timer interrupt (INTWDT) sources, non-maskable or maskable (internal),

can be selected.

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CHAPTER 11 INTERRUPT FUNCTIONS

Figure 11-1. Basic Configuration of Interrupt Function

(A) Internal non-maskable interrupt

Internal bus

Vector table

address generator

Interrupt request

Standby release signal

(B) Internal maskable interrupt

Internal bus

IE

MK

Vector table

address generator

Interrupt request

IF

Standby release signal

(C) External maskable interrupt

Internal bus

INTM0, KRM00

MK

IE

Vector table

address generator

Interrupt

request

Edge

detector

IF

Standby

release signal

IF:

Interrupt request flag

Interrupt enable flag

Interrupt mask flag

IE:

MK:

INTM0: External interrupt mode register 0

KRM00: Key return mode register 00

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CHAPTER 11 INTERRUPT FUNCTIONS

11.3 Registers Controlling Interrupt Function

The following five registers are used to control the interrupt functions.

• Interrupt request flag registers 0 and 1 (IF0 and IF1)

• Interrupt mask flag registers 0 and 1 (MK0 and MK1)

• External interrupt mode register 0 (INTM0)

• Program status word (PSW)

• Key return mode register 00 (KRM00)

Table 11-2 gives a listing of interrupt request flag and interrupt mask flag names corresponding to interrupt

requests.

Table 11-2. Flags Corresponding to Interrupt Request Signals

Interrupt Request Signal Name

Interrupt Request Flag

Interrupt Mask Flag

INTWDT

TMIF4

TMMK4

INTUSBTM

INTUSBRT

INTUSBRD

INTUSBST

INTUSBRE

INTP0

USBTMIF

USBRTIF

USBRDIF

USBSTIF

USBREIF

PIF0

USBTMMK

USBRTMK

USBRDMK

USBSTMK

USBREMK

PMK0

INTCSI10

INTTM00

INTTM01

INTKR00

CSIIF10

TMIF00

TMIF01

KRIF00

CSIMK10

TMMK00

TMMK01

KRMK00

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CHAPTER 11 INTERRUPT FUNCTIONS

(1) Interrupt request flag registers (IF0 and IF1)

The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is

executed. It is cleared to 0 when an instruction is executed upon acknowledgement of an interrupt request or

upon RESET input.

IF0 and IF1 are set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets IF0 and IF1 to 00H.

Figure 11-2. Format of Interrupt Request Flag Register

Address

FFE0H

After reset

00H

R/W

<7>

<6>

<5>

<4>

3

0

2

0

<1>

<0>

Symbol

IF0

TMIF01 TMIF00 CSIIF10 KRIF00

PIF0

TMIF4

7

<6>

<5>

<4>

<3>

<2>

1

0

USBTMIFUSBRTIFUSBRDIFUSBSTIF USBREIF

IF1

FFE1H

00H

R/W

Interrupt request flag

XXIFX

0

1

No interrupt request signal is generated

Interrupt request signal is generated; interrupt request state

Cautions 1. The TMIF4 flag is R/W enabled only when the watchdog timer is used as an interval

timer. If watchdog timer mode 1 or 2 is used, set the TMIF4 flag to 0.

2. Because port 2 has an alternate function as an external interrupt input, when the

output level is changed by specifying the output mode of the port function, an

interrupt request flag is set. Therefore, the interrupt mask flag should be set to 1

before using the output mode.

3. If an interrupt is acknowledged, an interrupt request flag is automatically cleared and

then the interrupt routine is entered.

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CHAPTER 11 INTERRUPT FUNCTIONS

(2) Interrupt mask flag registers (MK0 and MK1)

The interrupt mask flag is used to enable/disable the corresponding maskable interrupt servicing.

MK0 and MK1 are set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets MK0 and MK1 to FFH.

Figure 11-3. Format of Interrupt Mask Flag Register

Address

FFE4H

After reset

FFH

R/W

<7>

<6>

<5>

<4>

3

1

2

1

<1>

<0>

Symbol

MK0 TMMK01TMMK00 CSIMK10 KRMK00

PMK0 TMMK4

7

<6>

<5>

<4>

<3>

<2>

1

0

1

0

USBTMMKUSBRTMKUSBRDMKUSBSTMK USBREIF

MK1

FFE5H

FFH

R/W

XXMKX

Interrupt servicing control

0

1

Interrupt servicing enabled

Interrupt servicing disabled

Cautions 1. If the TMMK4 flag is read when the watchdog timer is used in watchdog timer mode 1

or 2, its value becomes undefined.

2. Because port 2 has an alternate function as an external interrupt input, when the

output level is changed by specifying the output mode of the port function, an

interrupt request flag is set. Therefore, the interrupt mask flag should be set to 1

before using the output mode.

(3) External interrupt mode register 0 (INTM0)

This register is used to set the valid edge of INTP0.

INTM0 is set with an 8-bit memory manipulation instruction.

RESET input sets INTM0 to 00H.

Figure 11-4. Format of External Interrupt Mode Register 0

Address

FFECH

After reset

00H

R/W

7

0

6

0

5

0

4

0

3

2

1

0

Symbol

INTM0

ES01 ES00

INTP0 valid edge selection

ES00

ES01

0

1

0

1

0

1

Falling edge

Rising edge

Setting prohibited

Both rising and falling edges

Cautions 1. Bits 0, 1 and 4 to 7 must be set to 0.

2. Before setting the INTM0 register, be sure to set xxMKx of the relevant interrupt mask

flag to 1 to disable interrupts. After that clear the interrupt mask flag (xxMKx = 0) to

enable interrupts after clearing the interrupt request flag(xxIFx = 0).

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CHAPTER 11 INTERRUPT FUNCTIONS

(4) Program status word (PSW)

The program status word is a register used to hold the instruction execution result and the current status for

interrupt requests. The IE flag to set maskable interrupt enable/disable is mapped here.

Besides 8-bit unit read/write, this register can carry out operations with bit manipulation instructions and

dedicated instructions (EI, DI). When a vectored interrupt is acknowledged, the PSW is automatically saved into

a stack, and the IE flag is reset to 0.

RESET input sets the PSW to 02H.

Figure 11-5. Configuration of Program Status Word

After reset

02H

7

6

Z

5

0

4

3

0

2

0

1

0

Symbol

PSW

IE

AC

CY

Used when normal instruction is executed

IE

0

Interrupt acknowledgment enabled/disabled

Disabled

Enabled

1

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CHAPTER 11 INTERRUPT FUNCTIONS

(5) Key return mode register 00 (KRM00)

This register sets the pin that detects a key return signal (rising edge of port 4).

KRM00 is set with a 1-bit an 8-bit memory manipulation instruction.

Bit 0 (KRM000) is set in 4-bit units for the KR00/P40 to KR03/P43 pins. Bits 4 to 7 (KRM004 to KRM007) are set

in 1-bit units for the KR04/P44 to KR07/P47 pins, respectively.

RESET input sets KRM00 to 00H.

Figures 11-6 and 11-7 show the format of key return mode register 00 and the block diagram of the falling edge

detector, respectively.

Figure 11-6. Format of Key Return Mode Register 00

Address

FFF5H

After reset

00H

R/W

7

6

5

4

3

0

2

0

1

0

Symbol

KRM00 KRM007 KRM006 KRM005 KRM004

KRM000

KRM00n

Key return signal detection selection for P4n/KR0n pin (n = 4 to 7)

0

1

No detection

Detection (detecting falling edge of P4n/KR0n)

KRM000

Key return signal detection selection for P40/KR00 to P43/KR03 pins

0

1

No detection

Detection (detecting falling edge of P40/KR00 to P43/KR03)

Cautions 1. Bits 1 to 3 must be set to 0.

2. When the KRM00 register is set to 1, a pull-up resistor is connected automatically.

However, the pull-up resistor is cut for pins in output mode.

3. Before setting KRM00, always set bit 4 of MK0 (KRMK00 = 1) to disable interrupts in

advance. After setting KRM00, clear bit 4 of MK0 (KRMK00 = 0) after clearing bit 4 of

IF0 (KRIF00 = 0) to enable interrupts.

Figure 11-7. Block Diagram of Falling Edge Detector

Key return mode register 00 (KRM00)^Note

P40/KR00

P41/KR01

P42/KR02

P43/KR03

P44/KR04

P45/KR05

KRIF00 set signal

Falling edge detector

KRMK00

Standby release

signal

P46/KR06

P47/KR07

Note Register that selects the pin used for falling edge input.

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CHAPTER 11 INTERRUPT FUNCTIONS

11.4 Interrupt Servicing Operation

11.4.1 Non-maskable interrupt acknowledgment operation

The non-maskable interrupt is unconditionally acknowledged even when interrupts are disabled. It is not subject to

interrupt priority control and takes precedence over all other interrupts.

When the non-maskable interrupt request is acknowledged, the PSW and PC are saved to the stack in that order,

the IE flag is reset to 0, the contents of the vector table are loaded to the PC, and then program execution branches.

Caution

During non-maskable interrupt service program execution, do not input another non-maskable

interrupt request; if it is input, the service program will be interrupted and the new interrupt

request will be acknowledged.

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CHAPTER 11 INTERRUPT FUNCTIONS

Figure 11-8. Flowchart of Non-Maskable Interrupt Request Acknowledgment

Start

WDTM4 = 1

No

(watchdog timer mode

is selected)

Interval timer

Yes

No

WDT

overflows

Yes

WDTM3 = 0

(non-maskable interrupt

is selected)

Reset processing

Yes

Interrupt request is generated

Interrupt servicing is started

WDTM: Watchdog timer mode register

WDT: Watchdog timer

Figure 11-9. Timing of Non-Maskable Interrupt Request Acknowledgment

Save PSW and PC, and

jump to interrupt servicing

CPU processing

TMIF4

Instruction

Interrupt servicing program

Figure 11-10. Acknowledging Non-Maskable Interrupt Request

Main routine

First interrupt servicing

NMI request

(second)

NMI request

(first)

Second interrupt servicing

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CHAPTER 11 INTERRUPT FUNCTIONS

11.4.2 Maskable interrupt acknowledgment operation

A maskable interrupt can be acknowledged when the interrupt request flag is set to 1 and the corresponding

interrupt mask flag is cleared to 0. A vectored interrupt is acknowledged in the interrupt enabled status (when the IE

flag is set to 1).

The time required to start the interrupt servicing after a maskable interrupt request has been generated is as

follows.

Table 11-3. Time from Generation of Maskable Interrupt Request to Servicing

Minimum Time

Maximum Time^Note

19 clocks

8 clocks

Note The wait time is maximum when an interrupt request is generated immediately before a BT or BF

instruction.

1

Remark 1 clock:

(f^CPU: CPU clock)

f

CPU

When two or more maskable interrupt requests are generated at the same time, they are acknowledged starting

from the one assigned the highest priority.

A pending interrupt is acknowledged when the status in which it can be acknowledged is set.

Figure 11-11 shows the algorithm of acknowledging interrupts.

When a maskable interrupt request is acknowledged, the PSW and PC are saved to the stack in that order, the IE

flag is reset to 0, the data in the vector table determined for each interrupt request is loaded to the PC, and execution

branches.

To return from interrupt servicing, use the RETI instruction.

Figure 11-11. Interrupt Acknowledgment Program Algorithm

Start

No

xxIF = 1 ?

Yes (interrupt request generated)

No

xxMK = 0 ?

Yes

Interrupt request pending

No

IE = 1 ?

Yes

Vectored interrupt

servicing

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CHAPTER 11 INTERRUPT FUNCTIONS

Figure 11-12. Timing of Interrupt Request Acknowledgment (Example of MOV A,r)

8 clocks

Clock

Saving PSW and PC,

and jump to interrupt

handling

MOV A,r

Interrupt servicing program

CPU

Interrupt

When an interrupt request flag (xxIF) is generated before clock n (n = 4 to 10) of the instruction being executed

turns to n - 1, the interrupt is acknowledged after the instruction has been executed. Figure 11-12 shows an example

for 8-bit data transfer instruction MOV A,r. It takes 4 clocks for this instruction to be executed. So, when an interrupt

occurs within 3 clocks after the instruction execution started, the interrupt is acknowledged after MOV A,r has been

executed.

Figure 11-13. Timing of Interrupt Request Acknowledgment

(When Interrupt Request Flag Is Generated at Last Clock of Instruction Execution)

8 clocks

Clock

Interrupt

servicing

program

Save PSW and PC, and

jump to interrupt servicing

NOP

MOV A,r

CPU

Interrupt

When an interrupt request flag (xxIF) is generated at the last clock for instruction execution, after the next

instruction has been executed, the interrupt acknowledgment servicing starts.

Figure 11-13 shows an example when an interrupt request flag is generated at the second clock for NOP (2-clock

instruction). In this case, the interrupt is acknowledged after MOV A,r has been executed after the NOP instruction

execution.

Caution

Interrupt requests are held pending during access to interrupt request flag registers 0, 1 (IF0,

IF1) or interrupt mask flag registers 0, 1 (MK0, MK1).

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CHAPTER 11 INTERRUPT FUNCTIONS

11.4.3 Multiplexed interrupt servicing

Servicing in which another interrupt is acknowledged while an interrupt is being processed is called multiplexed

interrupt servicing.

Multiplexed interrupt is not performed unless interrupt requests are enabled (IE = 1) (except the non-maskable

interrupt request). Other interrupt requests are disabled (IE = 0) as soon as an interrupt request is acknowledged.

Therefore, it is necessary to set (1) the IE flag to realize the interrupt enable state using the EI instruction during

interrupt request servicing in order to enable multiplexed interrupt servicing.

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CHAPTER 11 INTERRUPT FUNCTIONS

Figure 11-14. Example of Multiplexed Interrupt Servicing

Example 1. Acknowledging multiplexed interrupts

INTxx processing

INTyy processing

Main processing

IE = 0

EI

INTxx

INTyy

RETI

The interrupt request INTyy is acknowledged and multiplexed interrupt servicing is performed during the interrupt

INTxx servicing. Before each interrupt is acknowledged, the IE instruction is issued and interrupt requests are

enabled.

Example 2. Multiplexed interrupts are not performed because interrupts are disabled.

INTxx processing

INTyy processing

Main processing

EI

IE = 0

INTyy is held pending

INTyy

RETI

INTxx

IE = 0

RETI

Interrupt requests are disabled (EI instruction is not issued) in the interrupt INTxx servicing. The interrupt request

INTyy is not acknowledged and multiplexed interrupt servicing is not performed. INTyy is held pending and is

acknowledged after INTxx servicing is completed.

IE = 0: Interrupt request acknowledgment disabled.

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CHAPTER 11 INTERRUPT FUNCTIONS

11.4.4 Interrupt request hold

If an interrupt (such as a maskable, non-maskable, or external interrupt) is requested when a certain type of

instruction is being executed, the interrupt request will not be acknowledged until the instruction is completed. Such

instructions include:

• Instructions that manipulate interrupt request flag registers 0 and 1 (IF0 and IF1)

• Instructions that manipulate interrupt mask flag registers 0 and 1 (MK0 and MK1)

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CHAPTER 12 STANDBY FUNCTION

12.1 Standby Function and Configuration

12.1.1 Standby function

The standby function is used to reduce the power consumption of the system and can be effected in the following

two modes.

(1) HALT mode

This mode is set when the HALT instruction is executed. The HALT mode stops the operation clock of the CPU.

The system clock oscillator continues oscillating. This mode does not reduce the power consumption as much

as the STOP mode, but is useful for resuming processing immediately when an interrupt request is generated, or

for intermittent operations.

(2) STOP mode

This mode is set when the STOP instruction is executed. The STOP mode stops the system clock oscillator and

stops the entire system. The power consumption of the CPU can be substantially reduced in this mode.

The STOP mode can be released by an interrupt request, so that this mode can be used for intermittent

operations. However, some time is required until the system clock oscillator stabilizes after the STOP mode has

been released. If processing must be resumed immediately by using an interrupt request, therefore, use the

HALT mode.

In both modes, the previous contents of the registers, flags, and data memory before setting the standby mode are

all retained. In addition, the statuses of the output latches of the I/O ports and output buffers are also retained.

Caution

To set the STOP mode, be sure to stop the operations of the peripheral hardware, and then

execute the STOP instruction.

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CHAPTER 12 STANDBY FUNCTION

12.1.2 Register controlling standby function

The wait time after the STOP mode is released upon interrupt request until oscillation stabilizes is controlled with

the oscillation stabilization time select register (OSTS).

OSTS is set with an 8-bit memory manipulation instruction.

RESET input sets OSTS to 04H. However, it takes 2¹⁵/fX until oscillation stabilizes after RESET input.

Figure 12-1. Format of Oscillation Stabilization Time Select Register

7

0

6

0

5

0

4

0

3

0

2

1

0

Symbol

OSTS

Address

FFFAH

After reset

04H

R/W

OSTS2 OSTS1 OSTS0

Oscillation stabilization time selection

2¹²/f

2¹⁵/f

2¹⁷/f

X

µ

(683 s)

0

1

0

1

0

(5.46 ms)

(21.8 ms)

Other than above

Setting prohibited

Caution

The wait time after the STOP mode is released does not include the time from STOP mode

release to clock oscillation start (“a” in the figure below), regardless of release by RESET input

or by interrupt generation.

STOP mode release

X1 pin voltage

waveform

a

Remarks 1. f

X

: System clock oscillation frequency

2. The parenthesized values apply to operation at f

X

= 6.0 MHz.

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CHAPTER 12 STANDBY FUNCTION

12.2 Standby Function Operation

12.2.1 HALT mode

(1) HALT mode

The HALT mode is set by executing the HALT instruction.

The operation status in the HALT mode is shown in the following table.

Table 12-1. HALT Mode Operation Status

Item

HALT Mode Operation Status

Clock generator

CPU

Oscillation enabled

Operation disabled

Port (output latch)

8-bit timer 00 (TM00)

8-bit timer/event counter 01 (TM01)

Watchdog timer

Remains in the state before the selection of HALT mode.

Operation enabled

USB function

Operation enabled

Serial interface

Operation enabled

Key return

Operation enabled^{Note 1}

Operation enabled^{Note 2}

External interrupt

Notes 1. Operation is enabled only for pins set in key return mode register 00 (KRM00).

2. Maskable interrupt that is not masked

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CHAPTER 12 STANDBY FUNCTION

(2) Releasing HALT mode

The HALT mode can be released by the following three sources.

(a) Releasing by unmasked interrupt request

The HALT mode is released by an unmasked interrupt request. In this case, if interrupts are enabled to be

acknowledged, vectored interrupt servicing is performed. If interrupts are disabled, the instruction at the

next address is executed.

Figure 12-2. Releasing HALT Mode by Interrupt

HALT

instruction

Wait

Standby

release signal

Operation

mode

HALT mode

Operation mode

Oscillation

Clock

Remarks 1. The broken lines indicate the case where the interrupt request that has released the

standby mode is acknowledged.

2. The wait time is as follows.

• When vectored interrupt servicing is performed:

9 to 10 clocks

• When vectored interrupt servicing is not performed: 1 to 2 clocks

(b) Releasing by non-maskable interrupt request

The HALT mode is released regardless of whether interrupts are enabled or disabled, and vectored interrupt

servicing is performed.

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CHAPTER 12 STANDBY FUNCTION

(c) Releasing by RESET input

When the HALT mode is released by the RESET signal, execution branches to the reset vector address in

the same manner as the ordinary reset operation, and program execution is started.

Figure 12-3. Releasing HALT Mode by RESET Input

Wait

X

HALT

instruction

(2¹⁵/f

: 5.46 ms)

RESET

signal

Oscillation

stabilization

wait status

Reset

period

Operation

mode

Operation

mode

HALT mode

Oscillation

stops

Oscillation

Clock

Remarks 1. f^X: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 6.0 MHz.

Table 12-2. Operation After Release of HALT Mode

Releasing Source

MKxx

IE

Operation

Maskable interrupt request

0

1

Executes next address instruction

Executes interrupt servicing

Retains HALT mode

×

1

×

Non-maskable interrupt request

RESET input

—

Executes interrupt servicing

Reset processing

—

×: don’t care

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CHAPTER 12 STANDBY FUNCTION

12.2.2 STOP mode

(1) Setting and operation status of STOP mode

The STOP mode is set by executing the STOP instruction.

Cautions 1. When the STOP mode is set, the X2 pin is internally pulled up to V^DDto suppress the

current leakage of the crystal oscillator block. Therefore, do not use the STOP mode

in a system where an external clock is used as the system clock.

2. Because the standby mode can be released by an interrupt request signal, the standby

mode is released as soon as it is set if there is an interrupt source whose interrupt

request flag is set and interrupt mask flag is reset. When the STOP mode is set,

therefore, the HALT mode is set immediately after the STOP instruction has been

executed, the wait time set by the oscillation stabilization time select register (OSTS)

elapses, and then the operation mode is set.

The operation status in the STOP mode is shown in the following table.

Table 12-3. STOP Mode Operation Status

Item

STOP Mode Operation Status

Clock generator

CPU

Oscillation disabled

Operation disabled

Port (output latch)

8-bit timer 00 (TM00)

8-bit timer/event counter 01 (TM01)

Watchdog timer

Remains in the state before the selection of STOP mode.

Operation disabled

Operation enabled^{Note 1}

Operation disabled

USB function

Operation enabled^{Note 2}

Serial interface 10

Key return

Operation enabled^{Note 3}

Operation enabled^{Note 4}

External interrupt

Operation enabled^{Note 5}

Notes 1. Operation is enabled only when TI01 is selected as the count clock.

2. Operation is enabled only when the USB reset or Resume signal is received.

3. Operation is enabled only when an external clock is selected.

4. Operation is enabled only for pins set in key return mode register 00 (KRM00).

5. Maskable interrupt that is not masked

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CHAPTER 12 STANDBY FUNCTION

(2) Releasing STOP mode

The STOP mode can be released by the following two sources.

(a) Releasing by unmasked interrupt request

The STOP mode can be released by an unmasked interrupt request. In this case, if interrupts are enabled

to be acknowledged, vectored interrupt servicing is performed, after the oscillation stabilization time has

elapsed. If interrupt acknowledgement is disabled, the instruction at the next address is executed.

Figure 12-4. Releasing STOP Mode by Interrupt

Wait

STOP

instruction

( set time by OSTS)

Standby

release signal

Oscillation stabilization

Operation

mode

Operation

mode

wait status

STOP mode

Oscillation

stops

Oscillation

Clock

Remark The broken lines indicate the case where the interrupt request that has released the standby

mode is acknowledged.

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CHAPTER 12 STANDBY FUNCTION

(b) Releasing by RESET input

When the STOP mode is released by the RESET signal, the reset operation is performed after the

oscillation stabilization time has elapsed.

Figure 12-5. Releasing STOP Mode by RESET Input

Wait

X

STOP

instruction

(2¹⁵/f

: 5.46 ms)

RESET

signal

Oscillation

stabilization

wait status

Operation

mode

Reset

period

Operation

mode

STOP mode

Oscillation

stops

Oscillation

Clock

Remarks 1. f : System clock oscillation frequency

X

2. The parenthesized values apply to operation at 6.0 MHz.

Table 12-4. Operation After Release of STOP Mode

Releasing Source

MKxx

IE

Operation

Maskable interrupt request

0

1

Executes next address instruction

Executes interrupt servicing

Retains STOP mode

×

1

RESET input

—

Reset processing

×: don’t care

(3) Cautions an executing STOP instruction

After the STOP instruction is executed in the SE0 state (USBDM = 0, USBDP = 0), the STOP mode cannot be

released by a USB reset/Resume detection interrupt (INTUSBRE).

Therefore, the following control should be performed.

Do not execute the STOP instruction in the SE0 state.

In addition, when executing the STOP instruction in the suspend mode, execute both the following two

software countermeasures.

•

Do not clear the USB reset/Resume detection interrupt request flag (USBREIF) between when the suspend

state is detected and when the STOP instruction is executed.

•

Clear the USB reset/Resume detection interrupt request flag (USBREIF) when the 8-bit timer that is used

as the 3 ms timer for suspend state detection is reset.

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CHAPTER 13 RESET FUNCTION

The following two operations are available to generate reset signals.

(1) External reset input via RESET pin

(2) Internal reset by inadvertent program loop time detected by watchdog timer

External and internal reset have no functional differences. In both cases, program execution starts at the address

at 0000H and 0001H by RESET input.

When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and each of the

hardware is set to the status shown in Table 13-1. Each pin is high impedance during reset input or during the

oscillation stabilization time just after reset release.

When a high level is input to the RESET pin, the reset is released and program execution is started after the

oscillation stabilization time (2¹⁵/fx) has elapsed. The reset applied by watchdog timer overflow is automatically

released after reset, and program execution is started after the oscillation stabilization time (2¹⁵/fx) has elapsed (see

Figures 13-2 through 13-4.)

Cautions 1. For an external reset, input a low level for 10 µs or more to the RESET pin.

2. When the STOP mode is released by reset, the STOP mode contents are held during reset

input. However, the port pins become high impedance.

Figure 13-1. Block Diagram of Reset Function

RESET

Reset signal

Reset controller

Over-

flow

Interrupt function

Count clock

Watchdog timer

Stop

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CHAPTER 13 RESET FUNCTION

Figure 13-2. Reset Timing by RESET Input

X1

Oscillation

During normal

operation

Reset period

stabilization

Normal operation

(reset processing)

(oscillation stops)

time wait

RESET

Internal

reset signal

Delay

Hi-Z

Port pin

Figure 13-3. Reset Timing by Overflow in Watchdog Timer

X1

Oscillation

stabilization

time wait

During normal

operation

Reset period

(oscillation stops)

Normal operation

(reset processing)

Overflow in

watchdog timer

Internal

reset signal

Hi-Z

Port pin

Figure 13-4. Reset Timing by RESET Input in STOP Mode

X1

STOP instruction execution

Oscillation

During normal

operation

Stop status

Reset period

Normal operation

(reset processing)

stabilization

time wait

(oscillation stops)

RESET

Internal

reset signal

Delay

Hi-Z

Port pin

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CHAPTER 13 RESET FUNCTION

Table 13-1. Hardware Status After Reset (1/2)

Hardware

Status After Reset

Program counter (PC)^{Note 1}

The contents of reset

vector tables (0000H

and 0001H) are set.

Stack pointer (SP)

Program status word (PSW)

RAM

Undefined

02H

Data memory

Undefined^{Note 2}

00H

General-purpose register

Port (P0 to P2, P4) output latch

Port mode register (PM0 to PM2, PM4)

Pull-up resistor option register (PU0)

FFH

00H

Port output mode register (POM0, POM1)

Processor clock control register (PCC)

Oscillation stabilization time select register (OSTS)

8-bit timer/event counter

00H

02H

04H

Timer counter (TM00, TM01)

00H

Compare register (CR00, CR01)

Mode control register (TMC00, TMC01)

Timer clock select register (TCL2)

Mode register (WDTM)

Undefined

00H

Watchdog timer

USB function

00H

Transmit receive pointer (USBPOW)

Receive token PID (USBRTP)

00H

Receive token address (USBRAL, USBRAH)

Receive data PID (USBRD)

00H

Receive data address (USBR0 to USBR7)

Transmit data PID bank (USBTD0, USBTD1)

Undefined

Transmit data bank address (USBT00 to USBT07,

USBT10 to USBT17)

Data/handshake packet receive byte number counter

(DRXCON)

18H

Notes 1. During reset input and oscillation stabilization time wait, only the PC contents among the hardware

statuses become undefined.

All other hardware remains unchanged after reset.

2. The post-reset values are retained in the standby mode.

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CHAPTER 13 RESET FUNCTION

Table 13-1. Hardware Status After Reset (2/2)

Hardware

Status After Reset

20H

USB function

Data packet transmit byte number counter 0 (DTXCO0)

Data packet transmit byte number counter 1 (DTXCO1)

Token PID compare register (TIDCMP)

Token address compare register (ADRCMP)

USB receiver enable register (USBMOD)

Packet receive status register (RXSTAT)

30H

00H

Data/handshake packet receive result store register

(DRXRSL)

Token packet receive result store register (TRXRSL)

Data/handshake PID compare register (DIDCMP)

Data packet transmit reservation register (DTXRSV)

00H

C3H

00H

Handshake packet transmit reservation register

(HTXRSV)

USB timer start reservation control register (USBTCL)

Remote wakeup control register (REMWUP)

Mode register (CSIM10)

01H

08H

Serial interface

Interrupt

00H

Transmit/receive shift register (SIO10)

Request flag register (IF0, IF1)

Undefined

00H

Mask flag register (MK0, MK1)

FFH

External interrupt mode register (INTM0)

Key return mode register (KRM00)

00H

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CHAPTER 14 µPD78F9801

The µPD78F9801 is a product that substitutes flash memory for the internal ROM of the mask ROM version. The

differences between the µPD78F9801 and the mask ROM versions are shown in Table 14-1.

Table 14-1. Differences Between µPD78F9801 and Mask ROM Versions

Item

Flash Memory Version

Mask ROM Version

µPD78F9801

µPD789800

Internal memory

ROM

16 KB (Flash memory)

8 KB

High-speed RAM

256 bytes

Not provided

Provided

IC pin

Provided

VPP pin

Not provided

Electrical specifications

Refer to CHAPTER 16 ELECTRICAL SPECIFICATIONS.

Caution

There are differences in noise immunity and noise radiation between the flash memory and

mask ROM versions. When pre-producing an application set with the flash memory version

and then mass-producing it with the mask ROM version, be sure to conduct sufficient

evaluations for the commercial samples (not engineering samples) of the mask ROM version.

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CHAPTER 14 µPD78F9801

14.1 Flash Memory Characteristics

Flash memory programming is performed by connecting a dedicated flash programmer (Flashpro III (part no. FL-

PR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4)) to the target system with the µPD78F9801 mounted on the

target system (on-board). A flash memory program adapter (FA adapter), which is a target board used exclusively for

programming, is also provided.

Remark FL-PR3, FL-PR4, and the program adapter are products made by Naito Densei Machida Mfg. Co., Ltd.

(TEL +81-45-475-4191).

Programming using flash memory has the following advantages.

• Software can be modified after the microcontroller is solder-mounted on the target system.

• Distinguishing software facilities small-quantity, varied model production

• Easy data adjustment when starting mass production

14.1.1 Programming environment

The following shows the environment required for µPD78F9801 flash memory programming.

When Flashpro III (part no. FL-PR3, PG-FP3) or Flashpro IV (part no. FL-PR4, PG-FP4) is used as a dedicated

flash programmer, a host machine is required to control the dedicated flash programmer. Communication between

the host machine and flash programmer is performed via RS-232C/USB (Rev. 1.1).

For details, refer the manuals for Flashpro III/Flashpro IV.

Remark USB is supported by Flashpro IV only.

Figure 14-1. Environment for Writing Program to Flash Memory

V

PP

V

DD

SS

RS-232C

USB

V

RESET

3-wire serial I/O

or pseudo-3-wire

µ

Dedicated flash

programmer

PD78F9801

Host machine

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CHAPTER 14 µPD78F9801

14.1.2 Communication mode

Use the communication mode shown in Table 14-2 to perform communication between the dedicated flash

programmer and µPD78F9801.

Table 14-2. Communication Mode List

Communication

Mode

TYPE Setting^{Note 1}

CPU Clock

Pins Used

Number of

V^PPPulses

COMM PORT

SIO ch-0

SIO Clock

100 Hz to

Flash Clock

Multiple Rate

3-wire serial

I/O

Optional

1 to 5 MHz^{Note 2}1.0

SI10/P22

0

(3-wire, sync.) 1.25 MHz^{Note 2}

SO10/P21

SCK10/P20

Pseudo-3-wire Port A

(pseudo-

3-wire)

100 Hz to

1 kHz

Optional

1 to 5 MHz^{Note 2}1.0

P10 (serial clock input) 12

P11 (serial data output)

P12 (serial data input)

Notes 1. Selection items for TYPE settings on the dedicated flash programmer (Flashpro III (part no. FL-PR3,

PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4)).

2. The possible setting range differs depending on the voltage. For details, refer to CHAPTER 16

ELECTRICAL SPECIFICATIONS.

Figure 14-2. Communication Mode Selection Format

10 V

VPP

VDD

1

2

n

V^SS

V^PPpulses

VDD

VSS

RESET

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CHAPTER 14 µPD78F9801

Figure 14-3. Example of Connection with Dedicated Flash Programmer

(a) 3-wire serial I/O

Dedicated flash programmer

PD78F9801

µ

VPP1

VDD

V

PP

V

DD0, VDD1

RESET

SCK

RESET

SCK10

SI10

SO

SI

CLK^Note

SO10

X1

GND

V

SS0, VSS1

(b) Pseudo-3-wire

µ

Dedicated flash programmer

PD78F9801

VPP1

VDD

V

PP

V

DD0, VDD1

RESET

SCK

RESET

P10

SO

P12

SI

P11

CLK^Note

X1

GND

V

SS0, VSS1

Note Connect this pin when the system clock is supplied from the dedicated flash programmer. If a resonator is

already connected to the X1 pin, the CLK pin does not need to be connected.

Caution The V^DDpin, if already connected to the power supply, must be connected to the VDD pin of the

dedicated flash programmer. When using the power supply connected to the V^DDpin, supply

voltage before starting programming.

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CHAPTER 14 µPD78F9801

If Flashpro III (part no. FL-PR3, PG-FP3)/Flashpro IV is used as a dedicated flash programmer, the following

signals are generated for the µPD78F9801. For details, refer to the manual of Flashpro III/Flashpro IV.

Table 14-3. Pin Connection List

Signal Name

VPP1

VPP2

VDD

I/O

Output

−

Pin Function

Pin Name

3-Wire Serial I/O Pseudo-3-Wire

Write voltage

VPP

×

−

Note

I/O

VDD voltage generation/voltage monitoring

Ground

VDD0, VDD1

VSS0, VSS1

X1

−

GND

CLK

Output

Input

Output

Input

Clock output

RESET

SI

Reset signal

RESET

SO10/P11

SI10/P12

SCK10/P10

−

Receive signal

SO

Transmit signal

SCK

Transfer clock

×

HS

Handshake signal

Note V^DDvoltage must be supplied before programming is started.

Remark : Pin must be connected.

: If the signal is supplied on the target board, pin does not need to be connected.

×: Pin does not need to be connected.

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CHAPTER 14 µPD78F9801

14.1.3 On-board pin processing

When performing programming on the target system, provide a connector on the target system to connect the

dedicated flash programmer.

An on-board function that allows switching between normal operation mode and flash memory programming mode

may be required in some cases.

<V^PPpin>

In normal operation mode, input 0 V to the V^PPpin. In flash memory programming mode, a write voltage of 10.0 V

(TYP.) is supplied to the V^PPpin, so perform either of the following.

(1) Connect a pull-down resistor (RVPP = 10 kΩ) to the VPP pin.

(2) Use the jumper on the board to switch the V^PPpin input to either the writer or directly to GND.

A V^PPpin connection example is shown below.

Figure 14-4. V^PPPin Connection Example

PD78F9801

µ

Connection pin of dedicated flash programmer

VPP

Pull-down resistor (RV^PP

)

The following shows the pins used by the serial interface.

Serial Interface

3-wire serial I/O

Pins Used

SI10, SO10, SCK10

P12, P11, P10

Pseudo-3-wire

When connecting the dedicated flash programmer to a serial interface pin that is connected to another device on-

board, signal conflict or abnormal operation of the other device may occur. Care must therefore be taken with

such connections.

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CHAPTER 14 µPD78F9801

(1) Signal conflict

If the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to

another device (output), a signal conflict occurs. To prevent this, isolate the connection with the other device

or set the other device to the output high impedance status.

Figure 14-5. Signal Conflict (Input Pin of Serial Interface)

µ

PD78F9801

Connection pin of

dedicated flash

programmer

Signal conflict

Input pin

Other device

Output pin

In the flash memory programming mode, the signal output by another

device and the signal sent by the dedicated flash programmer conflict;

therefore, isolate the signal of the other device.

(2) Abnormal operation of other device

If the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that

is connected to another device (input), a signal is output to the device, and this may cause an abnormal

operation. To prevent this abnormal operation, isolate the connection with the other device or set so that the

input signals to the other device are ignored.

Figure 14-6. Abnormal Operation of Other Device

PD78F9801

µ

Connection pin of

dedicated flash

programmer

Other device

Input pin

If the signal output by the

memory programming mode, isolate the signals of the other device.

µ

PD78F9801 affects another device in the flash

µ

PD78F9801

Connection pin of

dedicated flash

programmer

Other device

Input pin

If the signal output by the dedicated flash programmer affects another

device in the flash memory programming mode, isolate the signals of the

other device.

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CHAPTER 14 µPD78F9801

If the reset signal of the dedicated flash programmer is connected to the RESET pin connected to the reset signal

generator on-board, a signal conflict occurs. To prevent this, isolate the connection with the reset signal generator.

If the reset signal is input from the user system in the flash memory programming mode, a normal programming

operation cannot be performed. Therefore, do not input reset signals from other than the dedicated flash

programmer.

Figure 14-7. Signal Conflict (RESET Pin)

µ

PD78F9801

Connection pin of

dedicated flash

programmer

Signal conflict

RESET

Reset signal generator

Output pin

The signal output by the reset signal generator and the signal output from

the dedicated flash programmer conflict in the flash memory programming

mode, so isolate the signal of the reset signal generator.

When the µPD78F9801 enters the flash memory programming mode, all the pins other than those that

communicate with flash programmer are in the same status as immediately after reset.

If the external device does not recognize initial statuses such as the output high impedance status, therefore,

connect the external device to V^DD0, VDD1, VSS0, or VSS1 via a resistor.

When using the on-board clock, connect X1 and X2 as required in the normal operation mode.

When using the clock output of the flash programmer, connect it directly to X1, disconnecting the main resonator

on-board, and leave the X2 pin open.

To use the power output from the flash programmer, connect the V^DD0and VDD1 pins to VDD of the flash

programmer, and the V^SS0and VSS1 pins to GND of the flash programmer.

To use the on-board power supply, make connections in accordance with the normal operation mode. However,

because the voltage is monitored by the flash programmer, be sure to connect VDD of the flash programmer.

Process the other pins (USBDP, USBDM, REGC) in the same manner as in the normal operation mode.

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CHAPTER 14 µPD78F9801

14.1.4 Connection of adapter for flash writing

The following figure shows an example of recommended connection when the adapter for flash writing is used.

Figure 14-8. Wiring Example for Flash Writing Adapter with 3-Wire Serial I/O

VDD (4.0 to 5.5 V)

GND

VDD2(LVDD)

VDD

GND

44 43 42 41 40 39 38 37 36 35 34

1

2

3

4

5

6

7

8

33

32

31

30

29

28

27

PD78F9801

µ

26

25

24

23

9

10

11

12 13 14 15 16 17 18 19 20 21 22

SI

SO SCK CLKOUT RESET VPP RESERVE/HS

FRASHWRITER

INTERFACE

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CHAPTER 14 µPD78F9801

Figure 14-9. Wiring Example for Flash Writing Adapter with Pseudo-3-Wire Method

VDD (4.0 to 5.5 V)

GND

VDD2(LVDD)

VDD

GND

44 43 42 41 40 39 38 37 36 35 34

1

2

3

4

5

6

7

8

33

32

31

30

29

28

27

PD78F9801

µ

26

25

24

23

9

10

11

12 13 14 15 16 17 18 19 20 21 22

SI

SO SCK CLKOUT RESET VPP RESERVE/HS

FRASHWRITER

INTERFACE

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CHAPTER 15 INSTRUCTION SET

This chapter lists the instruction set of the µPD789800 Subseries. For details of the operation and machine

language (instruction code) of each instruction, refer to 78K/0S Series Instruction User’s Manual (U11047E).

15.1 Operation

15.1.1 Operand identifiers and description methods

Operands are described in the “Operands” column of each instruction in accordance with the description method of

the instruction operand identifier (see the assembler specifications for details). When there are two or more

description methods, select one of them. Uppercase letters and the symbols #, !, $, and [ ] are keywords and are

described as they are. Each symbol has the following meaning.

• #: Immediate data specification

• !: Absolute address specification

• $: Relative address specification

• [ ]: Indirect address specification

In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to

describe the #, !, $ and [ ] symbols.

For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in

parentheses in the table below: R0, R1, R2, etc.) can be used for description.

Table 15-1. Operand Identifiers and Description Methods

Identifier

Description Method

r

X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)

AX (RP0), BC (RP1), DE (RP2), HL (RP3)

Special-function register symbol

rp

sfr

saddr

FE20H to FF1FH Immediate data or label

saddrp

FE20H to FF1FH Immediate data or label (even addresses only)

addr16

addr5

0000H to FFFFH Immediate data or label (only even addresses for 16-bit data transfer instructions)

0040H to 007FH Immediate data or label (even addresses only)

word

byte

bit

16-bit immediate data or label

8-bit immediate data or label

3-bit immediate data or label

Remark See Table 3-2 Special Function Register List for symbols of special function registers.

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CHAPTER 15 INSTRUCTION SET

15.1.2 Description of “operation” column

A:

A register; 8-bit accumulator

X register

X:

B:

B register

C:

C register

D:

D register

E:

E register

H:

H register

L:

L register

AX:

BC:

DE:

HL:

PC:

SP:

PSW:

CY:

AC:

Z:

AX register pair; 16-bit accumulator

BC register pair

DE register pair

HL register pair

Program counter

Stack pointer

Program status word

Carry flag

Auxiliary carry flag

Zero flag

IE:

Interrupt request enable flag

NMIS: Flag indicating non-maskable interrupt servicing in progress

( ):

x^H, xL:

∧:

Memory contents indicated by address or register contents in parenthesis

Higher 8 bits and lower 8 bits of 16-bit register

Logical product (AND)

∨:

Logical sum (OR)

V:

Exclusive logical sum (exclusive OR)

Inverted data



:

addr16: 16-bit immediate data or label

jdisp8: Signed 8-bit data (displacement value)

15.1.3 Description of “flag operation” column

(Blank): Unchanged

0:

1:

x:

Cleared to 0

Set to 1

Set/cleared according to the result

Previously saved value is restored

R:

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CHAPTER 15 INSTRUCTION SET

15.2 Operation List

Mnemonic

Operands

Bytes Clocks

Operation

Flag

Z

AC CY

r ← byte

MOV

r,#byte

3

2

3

2

1

2

1

2

1

2

6

4

8

6

4

6

4

6

8

(saddr) ← byte

sfr ← byte

A ← r

saddr,#byte

sfr,#byte

A,r^{Note 1}

r,A^{Note 1}

r ← A

A ← (saddr)

(saddr) ← A

A ← sfr

A,saddr

saddr,A

A,sfr

sfr ← A

sfr,A

A ← (addr16)

(addr16) ← A

PSW ← byte

A ← PSW

PSW ← A

A ← (DE)

(DE) ← A

A ← (HL)

A,!addr16

!addr16,A

PSW,#byte

A,PSW

PSW,A

A,[DE]

×

[DE],A

A,[HL]

(HL) ← A

[HL],A

A ← (HL+byte)

(HL+byte) ← A

A ↔ X

A,[HL+byte]

[HL+byte],A

A,X

XCH

A,r^{Note 2}

A ↔ r

A ↔ (saddr)

A ↔ sfr

A,saddr

A,sfr

A ↔ (DE)

A ↔ (HL)

A ↔ (HL+byte)

A,[DE]

A,[HL]

A,[HL+byte]

Notes 1. Except r = A.

2. Except r = A, X.

Remark One instruction clock cycle is one CPU clock cycle (f^CPU) selected by the processor clock control register

(PCC).

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CHAPTER 15 INSTRUCTION SET

Mnemonic

Operands

Bytes Clocks

Operation

Flag

Z

AC CY

rp ← word

MOVW

rp,#word

3

2

1

2

3

2

3

1

2

3

2

3

1

2

3

2

3

1

2

6

8

4

8

4

6

4

8

6

4

6

4

8

6

4

6

4

8

6

AX ← (saddrp)

(saddrp) ← AX

AX ← rp

AX,saddrp

saddrp,AX

AX,rp^Note

rp,AX^Note

AX,rp^Note

A,#byte

rp ← AX

AX ↔ rp

XCHW

ADD

A,CY ← A+byte

×

(saddr),CY ← (saddr) + byte

A,CY ← A+r

saddr,#byte

A,r

A,CY ← A+(saddr)

A,saddr

A,!addr16

A,[HL]

A,CY ← A+(addr16)

A,CY ← A+(HL)

A,CY ← A+(HL+byte)

A,CY ← A+byte+CY

(saddr),CY ← (saddr)+byte+CY

A,CY ← A+r+CY

A,[HL+byte]

A,#byte

ADDC

saddr,#byte

A,r

A,CY ← A+(saddr)+CY

A,CY ← A+(addr16)+CY

A,CY ← A+(HL)+CY

A,CY ← A+(HL+byte)+CY

A,CY ← A−byte

A,saddr

A,!addr16

A,[HL]

A,[HL+byte]

A,#byte

SUB

(saddr), CY ← (saddr)− byte

A,CY ← A−r

saddr,#byte

A,r

A,CY ← A−(saddr)

A,saddr

A,!addr16

A,[HL]

A,CY ← A−(addr16)

A,CY ← A−(HL)

A,CY ← A−(HL+byte)

A,[HL+byte]

Note Only when rp = BC, DE, or HL.

Remark One instruction clock cycle is one CPU clock cycle (f^CPU) selected by the processor clock control register

(PCC).

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CHAPTER 15 INSTRUCTION SET

Mnemonic

Operands

Bytes Clocks

Operation

Flag

Z

×

AC CY

A,CY ← A−byte−CY

×

SUBC

A,#byte

2

3

2

3

1

2

3

2

3

1

2

3

2

3

1

2

3

2

3

1

2

4

6

4

8

6

4

6

4

8

6

4

6

4

8

6

4

6

4

8

6

(saddr),CY ← (saddr)−byte−CY

A,CY ← A−r−CY

A,CY ← A−(saddr)−CY

A,CY ← A−(addr16)−CY

A,CY ← A−(HL)−CY

A,CY ← A−(HL+byte)−CY

A ← A∧byte

saddr,#byte

A,r

A,saddr

A,!addr16

A,[HL]

A,[HL+byte]

A,#byte

saddr,#byte

A,r

AND

(saddr) ← (saddr)∧byte

A ← A∧r

A ← A∧(saddr)

A,saddr

A,!addr16

A,[HL]

A ← A∧(addr16)

A ← A∧(HL)

A ← A∧(HL+byte)

A ← A∨byte

A,[HL+byte]

A,#byte

saddr,#byte

A,r

OR

(saddr) ← (saddr)∨byte

A ← A∨r

A ← A∨(saddr)

A,saddr

A,!addr16

A,[HL]

A ← A∨(addr16)

A ← A∨(HL)

A ← A∨(HL+byte)

A ← AVbyte

A,[HL+byte]

A,#byte

saddr,#byte

A,r

XOR

(saddr) ← (saddr)Vbyte

A ← AVr

A ← AV(saddr)

A,saddr

A,!addr16

A,[HL]

A ← AV(addr16)

A ← AV(HL)

A ← AV(HL+byte)

A,[HL+byte]

Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register

(PCC).

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CHAPTER 15 INSTRUCTION SET

Mnemonic

Operands

Bytes Clocks

Operation

Flag

Z

×

AC CY

A−byte

×

CMP

A,#byte

2

3

2

3

1

2

3

2

1

3

2

3

2

3

2

3

2

1

4

6

4

8

6

4

2

6

4

6

10

6

4

6

10

2

(saddr)−byte

A−r

saddr,#byte

A,r

A−(saddr)

A,saddr

A,!addr16

A,[HL]

A,[HL+byte]

AX,#word

r

A−(addr16)

A−(HL)

A−(HL+byte)

AX,CY ← AX+word

AX,CY ← AX−word

AX−word

ADDW

SUBW

CMPW

INC

r ← r+1

(saddr) ← (saddr)+1

r ← r−1

saddr

r

DEC

(saddr) ← (saddr)−1

rp ← rp+1

saddr

rp

INCW

DECW

ROR

rp ← rp−1

rp

(CY,A⁷← A0, Am−1 ← Am)×1

(CY,A⁰← A7, Am+1 ← Am)×1

(CY ← A⁰, A7 ← CY, Am−1 ← Am)×1

(CY ← A⁷, A0 ← CY, Am+1 ← Am)×1

(saddr.bit) ← 1

sfr.bit ← 1

×

A,1

ROL

A,1

RORC

ROLC

SET1

A,1

saddr.bit

sfr.bit

A.bit

A.bit ← 1

PSW.bit ← 1

×

PSW.bit

[HL].bit

saddr.bit

sfr.bit

A.bit

(HL).bit ← 1

(saddr.bit) ← 0

sfr.bit ← 0

CLR1

A.bit ← 0

PSW.bit ← 0

PSW.bit

[HL].bit

CY

(HL).bit ← 0

CY ← 1

SET1

CLR1

NOT1

1

0

×

CY ← 0

CY

CY ← CY

CY

Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register

(PCC).

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CHAPTER 15 INSTRUCTION SET

Mnemonic

Operands

Bytes Clocks

Operation

Flag

Z

AC CY

(SP−1) ← (PC+3)^H, (SP−2) ← (PC+3)L,

PC ← addr16, SP ← SP−2

CALL

!addr16

[addr5]

3

1

6

8

(SP−1) ← (PC+1)^H, (SP−2) ← (PC+1)L,

PC^H← (00000000, addr5+1),

CALLT

PC^L← (00000000, addr5), SP ← SP−2

PC^H← (SP+1), PCL ← (SP), SP ← SP+2

RET

1

6

8

PC^H← (SP+1), PCL ← (SP),

RETI

R

PSW ← (SP+2), SP ← SP+3, NMIS ← 0

(SP−1) ← PSW, SP ← SP−1

(SP−1) ← rp^H, (SP−2) ← rpL, SP ← SP−2

PSW ← (SP), SP ← SP+1

rp^H← (SP+1), rpL ← (SP), SP ← SP+2

SP ← AX

PUSH

POP

PSW

1

2

3

2

1

2

4

3

4

3

4

2

3

2

4

rp

PSW

4

rp

6

MOVW

BR

SP, AX

AX, SP

!addr16

$addr16

AX

8

AX ← SP

6

PC ← addr16

6

PC ← PC+2+jdisp8

6

PC^H← A, PCL ← X

6

PC ← PC+2+jdisp8 if CY=1

PC ← PC+2+jdisp8 if CY=0

PC ← PC+2+jdisp8 if Z=1

PC ← PC+2+jdisp8 if Z=0

PC ← PC+4+jdisp8 if (saddr.bit)=1

PC ← PC+4+jdisp8 if sfr.bit=1

PC ← PC+3+jdisp8 if A.bit=1

PC ← PC+4+jdisp8 if PSW.bit=1

PC ← PC+4+jdisp8 if (saddr.bit)=0

PC ← PC+4+jdisp8 if sfr.bit=0

PC ← PC+3+jdisp8 if A.bit=0

PC ← PC+4+jdisp8 if PSW.bit=0

B ← B−1, then PC ← PC+2+jdisp8 if B≠0

C ← C−1, then PC ← PC+2+jdisp8 if C≠0

BC

$saddr16

6

BNC

BZ

6

BNZ

BT

6

saddr.bit,$addr16

sfr.bit,$addr16

A.bit,$addr16

PSW.bit,$addr16

saddr.bit,$addr16

sfr.bit,$addr16

A.bit,$addr16

PSW.bit,$addr16

B,$addr16

10

8

10

8

BF

10

6

DBNZ

C,$addr16

6

(saddr) ← (saddr)−1, then

saddr,$addr16

8

PC ← PC+3+jdisp8 if (saddr)≠0

NOP

EI

1

3

1

2

6

2

No Operation

IE ← 1 (Enable interrupt)

IE ← 0 (Disable interrupt)

Set HALT mode

DI

HALT

STOP

Set STOP mode

Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register

(PCC).

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CHAPTER 15 INSTRUCTION SET

15.3 Instructions Listed by Addressing Type

(1) 8-bit instructions

MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH,

POP, DBNZ

2nd Operand

1st Operand

#byte

A

r

sfr

saddr !addr16 PSW

[DE]

[HL]

[HL+byte] $addr16

1

None

ADD

ADDC

SUB

SUBC

AND

OR

MOV^NoteMOV

XCH^NoteXCH

ADD

MOV

XCH

ADD

MOV

ADD

MOV

XCH

MOV

XCH

ADD

MOV

XCH

ADD

ROR

A

ROL

RORC

ROLC

ADDC

SUB

ADDC ADDC

SUB SUB

SUBC SUBC

ADDC ADDC

SUB SUB

SUBC SUBC

SUBC

XOR

CMP

AND

OR

AND

OR

AND

OR

AND

OR

XOR

CMP

XOR

CMP

XOR

CMP

XOR

CMP

r

MOV

INC

DEC

B, C

sfr

DBNZ

MOV

saddr

MOV

ADD

ADDC

SUB

SUBC

AND

OR

INC

DEC

XOR

CMP

!addr16

PSW

MOV

PUSH

POP

[DE]

MOV

[HL]

[HL+byte]

Note Except r = A.

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CHAPTER 15 INSTRUCTION SET

(2) 16-bit instructions

MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW

2nd Operand

1st Operand

#word

AX

rp^Note

saddrp

SP

None

AX

ADDW

MOVW

XCHW

MOVW

SUBW

CMPW

rp

MOVW

MOVW^Note

INCW

DECW

PUSH

POP

saddrp

SP

MOVW

Note Only when rp = BC, DE, or HL .

(3) Bit manipulation instructions

SET1, CLR1, NOT1, BT, BF

2nd Operand

$addr16

None

1st Operand

A.bit

BT

BF

SET1

CLR1

sfr.bit

BT

BF

SET1

CLR1

saddr.bit

PSW.bit

[HL].bit

CY

BT

BF

SET1

CLR1

BT

BF

SET1

CLR1

SET1

CLR1

SET1

CLR1

NOT1

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CHAPTER 15 INSTRUCTION SET

(4) Call instructions/branch instructions

CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ

2nd Operand

1st Operand

AX

!addr16

[addr5]

$addr16

Basic Instructions

BR

CALL

BR

CALLT

BR

BC

BNC

BZ

BNZ

Compound Instructions

DBNZ

(5) Other instructions

RET, RETI, NOP, EI, DI, HALT, STOP

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CHAPTER 16 ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (TA = 25°C)

Parameter

Supply voltage

Symbol

VDD

V^PP

VI

Conditions

Rating

−0.3 to +6.5

−0.3 to +10.5

−0.3 to V^DD+ 0.3^{Note 2}

−10

Unit

V

µPD78F9801 only^{Note 1}

V

Input voltage

V

Output voltage

Output current, high

VO

V

IOH

Per pin

mA

°C

−30

Total for all pins

Per pin

Output current, low

IOL

TA

30

Total for all pins

In normal operation mode

During flash memory programming

Mask ROM version

µPD78F9801

160

−40 to +85

10 to 40

Operating ambient temperature

Storage temperature

−65 to +150

−40 to +125

Tstg

Notes 1. Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash

memory is written.

• When supply voltage rises

V^PPmust exceed VDD 10 µs or more after VDD has reached the lower-limit value (4.0 V) of the

operating voltage range (see a in the figure below).

• When supply voltage drops

VDD must be lowered 10 µs or more after VPP falls below the lower-limit value (4.0 V) of the operating

voltage range of VDD (see b in the figure below).

4.0 V

V

DD

0 V

a

b

V

PP

4.0 V

0 V

2. Must be 6.5 V or lower

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for

any parameter. That is, the absolute maximum ratings are rated values at which the product is

on the verge of suffering physical damage, and therefore the product must be used under

conditions that ensure that the absolute maximum ratings are not exceeded.

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port

pins.

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CHAPTER 16 ELECTRICAL SPECIFICATIONS

System Clock Oscillation Circuit Characteristics (TA = −40 to +85°C, VDD = 4.0 to 5.5 V)

Resonator Recommended Circuit

Crystal

Parameter

Conditions

MIN. TYP. MAX. Unit

Oscillator frequency (fX)^{Note 1}

6.0

MHz

V

PP X1

X2

C1

C2

Oscillation stabilization

time^{Note 2}

10

ms

External

clock

X1 input frequency (fX)^{Note 1}

6.0

71

6.0

83

MHz

ns

X1

X2

X1 input high-low-level

OPEN

width (t^XH, tXL

)

Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for the instruction execution time.

2. Time required to oscillation after reset or STOP mode release. Use a resonator that can stabilize

oscillation before the oscillation stabilization time elapses.

Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines

in the above figure to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with other signal lines.

• Do not route the wiring near a signal line through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as V^SS0

.

• Do not ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

Remark For the resonator selection and oscillator constant, customers are required to either evaluate the

oscillation themselves or apply to the resonator manufacturer for evaluation.

Flash Memory Write/Erase Characteristics (T = 10 to 40°C, VDD = 4.0 to 5.5 V) (µPD78F9801 only)

A

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

18^Note

Unit

mA

Write current (VDD pin)

I

DDW

When VPP supply voltage = VPP1

(in 6.0 MHz operation mode)

Write current (VPP pin)

Erase current (VDD pin)

I

PPW

DDE

When VPP supply voltage = VPP1

7.5

mA

When VPP supply voltage = VPP1

(in 6.0 MHz operation mode)

18^Note

Erase current (VPP pin)

Unit erase time

Total erase time

Write count

I

t

PPE

When VPP supply voltage = VPP1

100

1

mA

er

1

s

era

20

s

Times

V

Erase/write are regarded as 1 cycle.

In normal operation

1

V

PP supply voltage

V

PP0

PP1

0

0.2VDD

10.3

During flash memory programming

9.7

10.0

V

Note The current flowing to the ports (including the current flowing through the on-chip pull-up resistors) is not

included.

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CHAPTER 16 ELECTRICAL SPECIFICATIONS

DC Characteristics (TA = −40 to +85°C, VDD = 4.0 to 5.5 V) (1/2)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

−1

Unit

mA

V

Output current, high

IOH

Per pin

−15

10

Total for all pins

Output current, low

Input voltage, high

IOL

Per pin

Total for all pins

80

VIH1

VIH2

VIH3

V^IH4

VIL1

VIL2

VIL3

V^IL4

VOH1

P00 to P07, P10 to P17

RESET, P20 to P26, P40 to P47

X1

0.7VDD

VDD

0.8VDD

VDD

V

V^DD− 0.1

V^DD

V

USBDM, USBDP T^A= 0 to +70°C

P00 to P07, P10 to P17

RESET, P20 to P26, P40 to P47

X1

2.0

3.6

V

Input voltage, low

0

0.3VDD

0.2VDD

0.1

V

0

V

0

V

USBDM, USBDP T^A= 0 to +70°C

0.8

V

I^O= −1 mA

VDD − 1.0

Output voltage, high

Output voltage, low

Pins other than USBDM

and USBDP

V

USBDM, USBDP T^A= 0 to +70°C,

RL = 15 kΩ (connected to V^SS)^Note

V^OH2

VOL1

V^OL2

ILIH1

2.8

V

Pins other than USBDM IO = 10 mA

and USBDP

1.0

0.3

3

USBDM, USBDP T^A= 0 to +70°C,

RL = 1.5 kΩ (connected to V^DD)^Note

V

µA

Input leakage current, high

Pins other than X1, X2, VI = VDD

USBDM, and USBDP

µA

ILIH2

X1, X2

VI = VDD

20

10

0 V ≤ V^I≤ VREG

I^LIH3

USBDM, USBDP

T^A= 0 to +70°C

−3

µA

Input leakage current, low

ILIL1

Pins other than X1, X2, VI = 0 V

USBDM, and USBDP

−20

−10

µA

ILIL2

X1, X2

VI = 0 V

0 V ≤ V^I≤ VREG

I^LIL3

USBDM, USBDP

TA = 0 to +70°C

µA

kΩ

V

Output leakage current, high ILOH

VO = 0 V

3

−3

Output leakage current, low

Software pull-up resistance

Regulator output voltage

ILOL

R

VO = 0 V

VI = 0 V

50

100

3.3

200

3.6

I^O= 0 to −3 mA

VREG

3.0

Note RL is the resistance connected to the bus line.

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port

pins.

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CHAPTER 16 ELECTRICAL SPECIFICATIONS

DC Characteristics (TA = −40 to +85°C, VDD = 4.0 to 5.5 V) (2/2)

Parameter

Symbol

Conditions

MIN.

TYP.

1.5

MAX.

3.0

Unit

mA

Supply current^{Note 1}

IDD1

6.0 MHz crystal oscillation (operating

mode)^{Note 2}

(Mask ROM Version)

IDD2

6.0 MHz crystal oscillation (HALT

mode)^{Note 2}

0.5

10

50

1.1

30

mA

µA

I^DD3

STOP

mode

When the USB function

is disabled

When the USB function

is enabled

100

(T^A= 0 to +70°C)

Supply current^{Note 1}

IDD1

IDD2

I^DD3

6.0 MHz crystal oscillation (operating

mode)^{Note 2}

5.0

1.5

10

10.0

3.5

30

mA

µA

(µPD78F9801)

6.0 MHz crystal oscillation (HALT

mode)^{Note 2}

STOP

mode

When the USB function is

disabled

µA

When the USB function is

enabled

50

100

(T^A= 0 to +70°C)

Notes 1. The power supply current does not include the current flowing through the on-chip pull-up resistors.

2. During high-speed mode operation (when the processor clock control register (PCC) is cleared to 00H)

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CHAPTER 16 ELECTRICAL SPECIFICATIONS

AC Characteristics

(1) Basic operations (T^A= −40 to +85°C, VDD = 4.0 to 5.5 V)

Parameter

Symbol

Conditions

MIN.

0.333

1.333

0

TYP.

0.333

1.333

MAX.

0.333

1.333

4.0

Unit

µs

Cycle time (minimum

TCY

When PCC = 00H (fX = 6.0 MHz)

When PCC = 02H (f^X= 6.0 MHz)

instruction execution time)

µs

TI01 input frequency

fTI

MHz

µs

TI01 input high-/low-level

width

tTIH, tTIL

0.1

µs

Interrupt input high-/low-level

width

tINTH, tINTL

INTP0

10

RESET input low-level width

t^RSL

(2) Serial interface

(a) USB function (T^A= 0 to +70°C, VDD = 4.0 to 5.5 V)

Parameter

Symbol

Conditions

MIN.

75

TYP.

MAX.

300

Unit

ns

%

USBDM and USBDP rise time tR

CL = 50 pF^Note

CL = 350 pF^Note

CL = 50 pF^Note

CL = 350 pF^Note

tR/tF

USBDM and USBDP fall time tF

75

300

120

2.0

tR and tF matching

tRFM

VCRS

80

Differential output signal

cross-over point

1.3

V

Data transfer rate

tDRATE

When the microcontroller operates at the

system clock (f^X) of 6.0 MHz

1.5

Mbps

−95

−150

1.25

Transmission differential

signal jitter

tUDJ1

Upon transferring the next bit

0

95

ns

µs

t^UDJ2

Upon transferring the bit following the next bit

150

1.50

300

Transmission EOP width

Reception EOP width

tEOPT1

tEOPR1

t^EOPR2

tURES1

t^URES2

1.33

EOP width to be eliminated

EOP width to be detected

675

5.5

Reception USB reset width

USB reset width to be eliminated

USB reset width to be detected

2.5

Note CL is the capacitance of the USBDM and USBDP output lines.

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215

CHAPTER 16 ELECTRICAL SPECIFICATIONS

(b) 3-wire serial I/O mode (TA = −40 to +85°C, VDD = 4.0 to 5.5 V)

(i) SCK10 ...Internal clock output (when fX = 6.0 MHz)

Parameter

Symbol

t^KCY1

Conditions

When TPS100^{Note 1}= 0

MIN.

667

1,333

283

617

150

333

667

0

TYP.

667

MAX.

667

Unit

ns

SCK10 cycle time

When TPS100^{Note 1}= 1

When TPS100^{Note 1}= 0

When TPS100^{Note 1}= 1

To SCK10 ↑

1,333

333

1,333

SCK10 high-/low-level width

t^KH1,

t^KL1

667

SI10 setup time

SI10 hold time

tSIK1

tKSI1

When TPS100^{Note 1}= 0

When TPS100^{Note 1}= 1

From SCK10 ↑

From SCK10 ↓, CL = 100 pF^{Note 2}

SO10 output delay

tKSO1

200

Notes 1. Bit 4 of serial operation mode register 10 (CSIM10)

2. CL is the capacitance of the SO output line.

(ii) SCK10 ...External clock output

Parameter

Symbol

t^KCY2

Conditions

MIN.

667

283

TYP.

MAX.

Unit

ns

SCK10 cycle time

SCK10 high-/low-level width

t^KH2,

t^KL2

ns

SI10 setup time

SI10 hold time

tSIK2

tKSI2

tKSO2

100

333

0

ns

From SCK10 ↓, CL = 100 pF^Note

SO10 output delay

250

Note CL is the capacitance of the SO output line.

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CHAPTER 16 ELECTRICAL SPECIFICATIONS

AC Timing Measurement Points (Except X1 Input and USB Function)

0.8VDD

0.2VDD

0.8VDD

0.2VDD

Measurement

points

Clock timing

1/f

X

t

XH

t

XL

V

IH3 (MIN.)

X1 input

V

IL3 (MAX.)

TI Timing

1/fTI

t

TIH

t

TIL

TI01

Interrupt Input Timing

t

INTL

t

INTH

INTP0

RESET Input Timing

tRSL

RESET

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CHAPTER 16 ELECTRICAL SPECIFICATIONS

Serial Transfer Timing

USB function:

USBDM and USBDP rise/fall time

0.9VDD

USBDM, USBDP

0.1VDD

t

R

t

F

Transmission differential signal jitter

1,333 ns

667 ns

Bit following

the next bit

Next bit

USBDM, USBDP

t

UDJ2

tUDJ1

Differential output signal cross-over point, transmission EOP width, reception EOP width, and reception

USB reset width

V

CRS

USBDM, USBDP

t

EOPT1, tEOPRm

URESm

,

m = 1, 2

3-wire serial I/O mode:

tKCYm

t

KLm

tKHm

0.8VDD

SCK10

0.2VDD

tSIKm

t

KSIm

SI10

Input data

tKSOm

Output data

SO10

m = 1, 2

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CHAPTER 16 ELECTRICAL SPECIFICATIONS

Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = −40 to +85°C)

Item

Symbol

VDDDR

tSREL

Conditions

MIN.

4.0

0

TYP.

MAX.

5.5

Unit

V

Data hold supply voltage

Release signal set time

µs

Oscillation stabilization time^Notet^WAIT

2¹⁵/fX

ms

Release by RESET

Release by interrupt request

1

Note 2

ms

Notes 1. During the oscillation stabilization time, CPU operations are disabled to prevent them from becoming

unstable upon the start of oscillation.

2. 2¹²/fX, 2¹⁵/fX, or 2¹⁷/fX can be selected according to the setting of bits 0 to 2 (OSTS0 to OSTS2) of the

oscillation stabilization time selection register.

Remark f^X: System clock oscillation frequency

Data Hold timing (STOP Mode Release by RESET )

Internal reset operation

HALT mode

STOP mode

Operating mode

Data hold mode

VDD

tSREL

V

DDDR

STOP instruction execution

RESET

tWAIT

Data Hold Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)

HALT mode

STOP mode

Operating mode

Data hold mode

V

DD

VDDDR

t

SREL

STOP instruction execution

Standby release signal

(interrupt request)

tWAIT

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CHAPTER 17 PACKAGE DRAWINGS

44 PIN PLASTIC LQFP (10x10)

A

B

detail of lead end

23

22

33

34

S

P

T

C

D

R

L

12

11

44

U

1

Q

F

J

M

G

H

I

K

M

N

S

ITEM MILLIMETERS

NOTE

Each lead centerline is located within 0.20 mm of

its true position (T.P.) at maximum material condition.

A

B

C

D

F

12.0 0.2

10.0 0.2

12.0 0.2

1.0

G

1.0

+0.08

H

0.37

−0.07

I

0.20

J

K

L

0.8 (T.P.)

1.0 0.2

0.5

+0.03

0.17

M

−0.06

N

P

Q

0.10

1.4 0.05

0.1 0.05

+4°

3°

R

−3°

S

T

1.6 MAX.

0.25 (T.P.)

0.6 0.15

U

S44GB-80-8ES-2

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CHAPTER 18 RECOMMENDED SOLDERING CONDITIONS

The µPD789800 Subseries should be soldered and mounted under the following recommended conditions.

For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting

Technology Manual (C10535E).

For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales

representative.

Table 18-1. Surface Mounting Type Soldering Conditions

(1) µ PD789800GB-×××-8ES:

µ PD78F9801GB-8ES:

44-pin plastic LQFP (10x10)

Soldering Method

Soldering Conditions

Symbol

Infrared reflow

Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),

Count: Twice or less

IR35-00-2

VPS

Package peak temperature: 215°C, Time: 40 seconds max. (at 200 °C or higher),

Count: Twice or less

VP15-00-2

WS60-00-1

−

Wave soldering

Partial heating method

Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once,

Preheating temperature: 120°C max. (package surface temperature)

Pin temperature: 350°C max. Time: 3 seconds max. (per pin row)

Caution Do not use different soldering methods together (except for partial heating).

(2) µ PD789800GB-×××-8ES-A: 44-pin plastic LQFP (10x10)

µ PD78F9801GB-8ES-A:

44-pin plastic LQFP (10x10)

Soldering Method

Soldering Conditions

Symbol

Package peak temperature: 260°C, Time: 60 seconds max. (at 220°C or higher),

Count: Three times or less, Exposure limit: 7 days^Note(after that, prebake at 125°C for

20 to 72 hours)

Infrared reflow

IR60-207-3

−

Wave soldering

When the pin pitch of the package is 0.65 mm or more, wave soldering can also be

performed.

For details, contact an NEC Electronics sales representative.

Partial heating method

Pin temperature: 350°C max. Time: 3 seconds max. (per pin row)

Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.

Caution Do not use different soldering methods together (except for partial heating).

Remark Products that have the part numbers suffixed by "-A" are lead-free products.

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APPENDIX A DEVELOPMENT TOOLS

The following development tools are available for development of systems using the µPD789800 Subseries.

Figure A-1 shows the development tools.

• Support of the PC98-NX series

Unless otherwise stated, the µPD789800 Subseries, which is supported by IBM PC/AT™ and compatibles, can

be used for the PC98-NX series. When using the PC98-NX series, refer to the descriptions of IBM PC/AT and

compatibles.

• Windows

Unless otherwise stated, “Windows” indicates the following OSs.

•

Windows 3.1

Windows 95, 98, 2000

Windows NT^TMVer.4.0

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APPENDIX A DEVELOPMENT TOOLS

Figure A-1. Development Tools

Software package

·

Software package

Language processing software

Debugging software

·

Assembler package

C compiler package

Device file

·

Integrated debugger

System simulator

·

C library source file^{Note 1}

Control software

Project Manager

(Windows version only)^{Note 2}

·

Host machine

(PC or EWS)

Interface adapter

Power supply unit

Flash memory writing environment

Flash programmer

In-circuit emulator

Emulation board

Flash memory

writing adapter

Flash memory

Emulation probe

Conversion socket or

conversion adapter

Target system

Notes 1. C library source file is not included in the software package.

2. Project Manager is included in the assembler package.

Project Manager is used only in the Windows environment.

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APPENDIX A DEVELOPMENT TOOLS

A.1 Software Package

SP78K0S

Software tools for development of the 78K/0S Series are combined in this package.

The following tools are included.

Software package

RA78K0S, CC78K0S, ID78K0S-NS, SM78K0S, and device files

Part number: µS××××SP78K0S

Remark ×××× in the part number differs depending on the OS used.

µS××××SP78K0S

××××

AB17

BB17

Host Machine

OS

Supply Medium

CD-ROM

PC-9800 series, IBM PC/AT

compatibles

Japanese Windows

English Windows

A.2 Language Processing Software

RA78K0S

Program that converts a program written in mnemonic into object codes that can be

executed by a microcontroller.

Assembler package

In addition, automatic functions to generate a symbol table and optimize branch instructions

are also provided.

Used in combination with a device file (DF789801) (sold separately).

The assembler package is a DOS-based application but may be used in the Windows

environment by using the Project Manager of Windows (included in the assembler package).

Part number: µS××××RA78K0S

CC78K0S

Program that converts a program written in C language into object codes that can be

executed by a microcontroller.

C compiler package

Used in combination with an assembler package (RA78K0S) and device file (DF789801)

(both sold separately).

The C compiler package is a DOS-based application but may be used in the Windows

environment by using the Project Manager of Windows (included in the assembler package).

Part number: µS××××CC78K0S

DF789801^{Note 1}

Device file

File containing information inherent to the device.

Used in combination with the RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S (all sold

separately).

Part number: µS××××DF789801

CC78K0S-L^{Note 2}

Source file of functions for generating the object library included in the C compiler package.

Necessary for changing the object library included in the C compiler package according to

the customer’s specifications. Since this is a source file, its working environment does not

depend on any particular operating system.

C library source file

Part number: µS××××CC78K0S-L

Notes 1. DF789801 is a common file that can be used with RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S.

2. CC78K0S-L is not included in the software package (SP78K0S).

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APPENDIX A DEVELOPMENT TOOLS

Remark ×××× in the part number differs depending on the host machine and operating system to be used.

µS××××RA78K0S

µS××××CC78K0S

××××

AB13

BB13

AB17

BB17

3P17

3K17

Host Machine

PC-9800 series,

OS

Supply Medium

3.5" 2HD FD

Japanese Windows

English Windows

IBM PC/AT compatibles

Japanese Windows

CD-ROM

English Windows

HP9000 series 700^TM

SPARCstation^TM

HP-UX^TM(Rel. 10.10)

SunOS^TM(Rel. 4.1.4),

Solaris^TM(Rel. 2.5.1)

µS××××DF789801

µS××××CC78K0S-L

××××

Host Machine

OS

Supply Medium

AB13

BB13

3P16

3K13

3K15

PC-9800 series,

Japanese Windows

English Windows

HP-UX (Rel. 10.10)

SunOS (Rel. 4.1.4),

Solaris (Rel. 2.5.1)

3.5" 2HD FD

IBM PC/AT compatibles

HP9000 series 700

SPARCstation

DAT

3.5" 2HD FD

1/4-inch CGMT

A.3 Control Software

Project Manager

Control software created for efficient development of the user program in the Windows

environment. User program development operations such as editor startup, build, and

debugger startup can be performed from the Project Manager.

The Project Manager is included in the assembler package (RA78K0S).

The Project Manager is used only in the Windows environment.

A.4 Flash Memory Writing Tools

Flashpro III (FL-PR3, PG-FP3)

Flashpro IV (FL-PR4, PG-FP4)

Flash programmer

Dedicated flash programmer for microcontrollers incorporating flash memory

FA-44GB-8ES

Adapter for writing to flash memory and connected to Flashpro III or Flashpro IV.

FA-44GB-8ES: For 44-pin plastic LQFP (GB-8ES type)

Flash memory writing adapter

Remark The FL-PR3, FL-PR4 and FA-44GB-8ES are products made by Naito Densei Machida Mfg. Co., Ltd.

(TEL +81-45-475-4191).

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APPENDIX A DEVELOPMENT TOOLS

A.5 Debugging Tools (Hardware)

IE-78K0S-NS

In-circuit emulator for debugging hardware and software of an application system using the

78K/0S Series. Supports a integrated debugger (ID78K0S-NS). Used in combination with an AC

adapter, emulation probe, and interface adapter for connecting the host machine.

In-circuit emulator

IE-78K0S-NS-A

The IE-78K0S-NS-A provides a coverage function in addition to the IE-78K0S-NS functions, thus

enhancing the debug functions, including the tracer and timer functions.

In-circuit emulator

IE-70000-MC-PS-B

AC adapter

Adapter for supplying power from an AC 100 to 240 V outlet.

IE-70000-98-IF-C

Interface adapter

Adapter necessary when using PC-9800 series PC (except notebook type) as host machine (C

bus supported)

IE-70000-CD-IF-A

PC card interface

PC card and interface cable necessary when using notebook PC as host machine (PCMCIA

socket supported)

IE-70000-PC-IF-C

Interface adapter

Interface adapter necessary when using IBM PC/AT compatible as host machine (ISA bus

supported)

IE-70000-PCI-IF-A

Interface adapter

Adapter necessary when using personal computer incorporating PCI bus as host machine

IE-789801-NS-EM1

Emulation board

Board for emulating the peripheral hardware inherent to the device. Used in combination with an

in-circuit emulator.

NP-44GB-TQ

Cable to connect the in-circuit emulator and target system.

Used in combination with the TGB-044SAP.

NP-H44GB-TQ

Emulation probe

TGB-044SAP

Conversion adapter to connect the NP-44GB-TQ or NP-H44GB-TQ and a target system board on

which a 44-pin plastic LQFP (GB-8ES type) can be mounted

Conversion

adapter

Remarks 1. The NP-44GB-TQ and NP-H44GB-TQ are products made by Naito Densei Machida Mfg. Co., Ltd.

(TEL +81-45-475-4191).

2. The TGB-044SAP is a product made by TOKYO ELETECH CORPORATION.

For further information, contact: Daimaru Kogyo, Ltd.

Tokyo Electronics Department (TEL +81-3-3820-7112)

Osaka Electronics Department (TEL +81-6-6244-6672)

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APPENDIX A DEVELOPMENT TOOLS

A.6 Debugging Tools (Software)

ID78K0S-NS

Integrated debugger

This debugger supports the in-circuit emulators IE-78K0S-NS and IE-78K0S-NS-A for the

78K/0S Series. The ID78K0S-NS is Windows-based software.

It has improved C-compatible debugging functions and can display the results of tracing with

the source program using an integrating window function that associates the source

program, disassemble display, and memory display with the trace result.

Used in combination with a device file (DF789801) (sold separately).

Part number: µS××××ID78K0S-NS

SM78K0S

System simulator

This is a system simulator for the 78K/0S Series. The SM78K0S is Windows-based software.

It can be used to debug the target system at C source level or assembler level while

simulating the operation of the target system on the host machine.

Using SM78K0S, the logic and performance of the application can be verified independently

of hardware development. Therefore, the development efficiency can be enhanced and the

software quality can be improved.

Used

in combination with a device file (DF789801) (sold separately).

Part number: µS××××SM78K0S

DF789801^Note

Device file

File containing information inherent to the device.

Used in combination with the RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S (sold

separately).

Part number: µS××××DF789801

Note DF789801 is a common file that can be used with the RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S.

Remark ×××× in the part number differs depending on the operating system and supply medium to be used.

µS××××ID78K0S-NS

µS××××SM78K0S

××××

AB13

BB13

AB17

BB17

Host Machine

PC-9800 series

IBM PC/AT compatibles

OS

Japanese Windows

English Windows

Japanese Windows

English Windows

Supply Medium

3.5" 2HD FD

CD-ROM

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APPENDIX A DEVELOPMENT TOOLS

A.7 Notes on Target System Design

Figures A-2 and A-3 show the conditions when connecting the emulation probe to the conversion adapter. Follow

the configuration below and consider the shape of parts to be mounted on the target system when designing a

system.

Figure A-2. Distance Between In-Circuit Emulator and Conversion Adapter

In-circuit emulator

IE-78K0S-NS or IE-78K0S-NS-A

Target system

Emulation board

IE-789801-NS-EM1

170 mm^Note

CN1

Emulation probe

NP-44GB-TQ, NP-H44GB-TQ

Conversion adapter:

TGB-044SAP

Note Distance when NP-44GB-TQ is used. When NP-H44GB-TQ is used, the distance is 370 mm.

Remarks 1. NP-44GB-TQ and NP-H44GB-TQ are products of Naito Densei Machida Mfg. Co., Ltd.

2. TGB-044SAP is a product of TOKYO ELETECH CORPORATION.

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APPENDIX A DEVELOPMENT TOOLS

Figure A-3. Connection Condition of Target System (NP-H44GB-TQ)

Emulation board

IE-789801-NS-EM1

Emulation probe

NP-H44GB-TQ

23 mm

11 mm

Conversion adapter

TGB-044SAP

10 mm

40 mm

34 mm

Target system

Remarks 1. NP-H44GB-TQ is a product of Naito Densei Machida Mfg. Co., Ltd.

2. TGB-044SAP is a product of TOKYO ELETECH CORPORATION.

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229

APPENDIX B REGISTER INDEX

B.1 Register Index (Alphabetic Order of Register Name)

8-bit compare register 00 (CR00)........................................................................................................................... 82

8-bit compare register 01 (CR01)........................................................................................................................... 82

8-bit timer mode control register 00 (TMC00)......................................................................................................... 83

8-bit timer mode control register 01 (TMC01)......................................................................................................... 84

8-bit timer counter 00 (TM00)................................................................................................................................. 82

8-bit timer counter 01 (TM01)................................................................................................................................. 82

[D]

Data/handshake packet receive result store register (DRXRSL).......................................................................... 114

Data packet transmit reservation register (DTXRSV)........................................................................................... 116

Data/handshake packet receive byte number counter (DRXCON)....................................................................... 107

Data/handshake packet receive mode register (URXMOD) ................................................................................. 110

Data packet transmit byte number counter (DTXCO0, DTXCO1) ........................................................................ 107

Data/handshake PID compare register (DIDCMP)............................................................................................... 109

[E]

External interrupt mode register 0 (INTM0) .......................................................................................................... 169

[H]

Handshake packet transmit reservation register (HTXRSV)................................................................................. 117

[I]

Interrupt mask flag register 0 (MK0)..................................................................................................................... 169

Interrupt mask flag register 1 (MK1)..................................................................................................................... 169

Interrupt request flag register 0 (IF0).................................................................................................................... 168

Interrupt request flag register 1 (IF1).................................................................................................................... 168

[K]

Key return mode register 00 (KRM00).................................................................................................................. 171

[O]

Oscillation stabilization time select register (OSTS)............................................................................................. 180

[P]

Packet receive status register (RXSTAT)............................................................................................................. 112

Port 0 (P0).............................................................................................................................................................. 61

Port 1 (P1) ............................................................................................................................................................. 62

Port 2 (P2).............................................................................................................................................................. 63

Port 4 (P4).............................................................................................................................................................. 69

Port mode register 0 (PM0) .................................................................................................................................... 70

Port mode register 1 (PM1) .................................................................................................................................... 70

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APPENDIX B REGISTER INDEX

Port mode register 2 (PM2).................................................................................................................................... 70

Port mode register 4 (PM4).................................................................................................................................... 70

Port output mode register 0 (POM0)...................................................................................................................... 72

Port output mode register 1 (POM1)...................................................................................................................... 72

Processor clock control register (PCC).................................................................................................................. 75

Pull-up resistor option register 0 (PU0).................................................................................................................. 71

[R]

Receive data address (USBR0 to USBR7) ........................................................................................................... 104

Receive data PID (USBRD) .................................................................................................................................. 104

Receive token address (USBRAL, USBRAH)....................................................................................................... 103

Receive token PID (USBRTP) .............................................................................................................................. 103

Remote wake-up control register (REMWUP)....................................................................................................... 122

[S]

Serial operation mode register 10 (CSIM10)......................................................................................................... 158

[T]

Timer clock select register 2 (TCL2) ...................................................................................................................... 94

Token address compare register (ADRCMP)........................................................................................................ 108

Token packet receive result store register (TRXRSL)........................................................................................... 114

Token PID compare register (TIDCMP)................................................................................................................ 107

Transmit/receive shift register 10 (SIO10) ............................................................................................................ 156

Transmit data bank 0 address (USBT00 to USBT07) ........................................................................................... 105

Transmit data bank 1 address (USBT10 to USBT17) ........................................................................................... 105

Transmit data PID bank 0 (USBTD0).................................................................................................................... 105

Transmit data PID bank 1 (USBTD1).................................................................................................................... 105

Transmit/receive pointer (USBPOB, USBPOW) ................................................................................................... 102

[U]

USB receiver enable register (USBMOD) ............................................................................................................. 110

USB timer start reservation control register (USBTCL)......................................................................................... 121

[W]

Watchdog timer mode register (WDTM) ................................................................................................................ 95

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APPENDIX B REGISTER INDEX

B.2 Register Index (Alphabetic Order of Register Symbol)

[A]

ADRCMP:

Token address compare register....................................................................................... 108

[C]

CR00:

CR01:

CSIM10:

8-bit compare register 00.................................................................................................... 82

8-bit compare register 01.................................................................................................... 82

Serial operation mode register 10..................................................................................... 158

[D]

DIDCMP:

DRXCON:

DRXRSL:

Data/handshake PID compare register............................................................................. 109

Data/handshake packet receive byte number counter...................................................... 107

Data/handshake packet receive result store register........................................................ 114

DTXCO0, DTXCO1: Data packet transmit byte number counter....................................................................... 107

DTXRSV:

Data packet transmit reservation register......................................................................... 116

[H]

HTXRSV:

Handshake packet transmit reservation register .............................................................. 117

[I]

IF0:

Interrupt request flag register 0 ........................................................................................ 168

Interrupt request flag register 1 ........................................................................................ 168

External interrupt mode register 0 .................................................................................... 169

IF1:

INTM0:

[K]

KRM00:

Key return mode register 00............................................................................................. 171

[M]

MK0:

MK1:

Interrupt mask flag register 0............................................................................................ 169

Interrupt mask flag register 1............................................................................................ 169

[O]

OSTS:

Oscillation settling time select register.............................................................................. 180

[P]

P0:

Port 0.................................................................................................................................. 61

Port 1.................................................................................................................................. 62

Port 2.................................................................................................................................. 63

Port 4.................................................................................................................................. 69

Processor clock control register ......................................................................................... 75

Port mode register 0........................................................................................................... 70

Port mode register 1........................................................................................................... 70

Port mode register 2........................................................................................................... 70

Port mode register 4........................................................................................................... 70

Port output mode register 0................................................................................................ 72

Port output mode register 1................................................................................................ 72

P1:

P2:

P4:

PCC:

PM0:

PM1:

PM2:

PM4:

POM0:

POM1:

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232

APPENDIX B REGISTER INDEX

PU0:

Pull-up resistor option register 0 ........................................................................................ 71

[R]

REMWUP:

RXSTAT:

Remote wake-up control register ...................................................................................... 122

Packet receive status register........................................................................................... 112

[S]

SIO10:

Transmit/receive shift register 10...................................................................................... 156

[T]

TCL2:

Timer clock select register 2 .............................................................................................. 94

Token PID compare register ............................................................................................. 107

8-bit timer counter 00......................................................................................................... 82

8-bit timer counter 01......................................................................................................... 82

8-bit timer mode control register 00 ................................................................................... 83

8-bit timer mode control register 01 ................................................................................... 84

Token packet receive result store register ........................................................................ 114

TIDCMP:

TM00:

TM01:

TMC00:

TMC01:

TRXRSL:

[U]

URXMOD:

USBMOD:

Data/handshake packet receive mode register................................................................. 110

USB receiver enable register ............................................................................................ 110

USBPOB, USBPOW: Transmit/receive pointer.................................................................................................... 102

USBR0 to USBR7: Receive data address ....................................................................................................... 104

USBRAL, USBRAH: Receive token address...................................................................................................... 103

USBRD:

USBRTP:

USBTCL:

Receive data PID.............................................................................................................. 104

Receive token PID ............................................................................................................ 103

USB timer start reservation control register ...................................................................... 121

USBT00 to USBT07: Transmit data bank 0 address........................................................................................... 105

USBT10 to USBT17: Transmit data bank 1 address........................................................................................... 105

USBTD0:

USBTD1:

Transmit data PID bank 0 ................................................................................................. 105

Transmit data PID bank 1 ................................................................................................. 105

[W]

WDTM:

Watchdog timer mode register........................................................................................... 95

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APPENDIX C REVISION HISTORY

The revision history is described below. The “Applied to” column indicates the chapters in each edition.

(1/3)

Edition

Major Revisions from Previous Edition

Applied to:

Throughout

Deletion of description “under development” for µPD789800, since it has been

2nd edition

developed

Addition of GB-8ES type package

Modification of recommended connection of unused pins in type of

input/output circuit for each pin

CHAPTER 2 PIN

FUNCTIONS

Addition of illustration in direct addressing

CHAPTER 3 CPU

ARCHITECTURE

Addition of caution regarding operation of 8-bit compare register n (CR0n)

Addition to setting method in description of operation as interval timer

CHAPTER 6 8-BIT

TIMER/EVENT COUNTER

Addition to setting method in description of operation as external event

counter

Addition to setting method in description of operation as square wave output

Addition of the value of each register when SETUP received

CHAPTER 8 USB FUNCTION

Deletion of setting RXSTAT with a 1-bit memory manipulation instruction in

description of packet receive status register (RXSTAT)

Modification of each bit of RXSTAT from reserved words to non-reserved

words in packet receive status register format

Modification of note in Format of Packet Receive Status Register

Modification of flag names in Conditions in Transmit Reservation

Modification of contents in block diagram of regulator and USB driver/receiver

CHAPTER 10 REGULATOR

CHAPTER 14 µPD78F9801

Addition of caution regarding replacement of flash memory version with mask

ROM version

Modification of description from Flashpro II to Flashpro III in µPD78F9801

Addition of restrictions to pins used when pseudo 3-wire mode is selected as

communication mode

Addition of setting example when Flashpro III (PG-FP3) is used

Whole appendix revised for supporting IE-78K0S-NS

APPENDIX A

DEVELOPMENT TOOLS

Addition of ordering information of MX78K0S in embedded software

APPENDIX B EMBEDDED

SOFTWARE

3rd

Deletion of CU-type and GB-3BS type packages

Throughout

Deletion of indication “under development” for µPD78F9801

Modification of operating ambient temperature when flash memory is written

CHAPTER 1 GENERAL

in 1.1 Features

Addition of outline of timer in 1.7 Functions

Modification of handling of REGC and V^PPpins

CHAPTER 2 PIN

FUNCTIONS

User’s Manual U12978EJ3V3UD

234

APPENDIX C REVISION HISTORY

(2/3)

Edition

Major Revisions from Previous Edition

Applied to:

Correction of address values in Figure 3-1 Memory Map (µPD789800) and

Figure 3-2 Memory Map (µPD78F9801)

3rd

CHAPTER 3 CPU

ARCHITECTURE

Modification of Figure 5-3 External Circuit of System Clock Oscillator (b)

CHAPTER 5 CLOCK

GENERATOR

External clock

CHAPTER 8 USB

FUNCTION

• Modification of chapter composition

• Standardization of buffer name indications as receive token bank, receive

data bank, and transmit data banks 0 and 1

• Addition of image diagrams for reception and transmission

• Addition of register value for SETUP reception

• Modification of description on data handshake packet receive mode register

(URXMOD)

• Addition of description on packet receive status register (RXSTAT) and

modification of read-only bit

• Addition of Note for token packet receive result store register (TRXRSL)

• Addition of Caution for data packet transmit reservation register (DTXRSV)

• Modification of description of bit 1 (DNAEN) of handshake packet transmit

reservation register (HTXRSV)

• Change of contents of 8.5.2 Remote wakeup control operation

• Addition of Table 8-4 List of Sources of Interrupts from USB Function

• Correction of incorrect flag name in 8.6 Interrupt Request from USB

Function

•

Addition of description on USB reset/Resume detection interrupt (INTUSBRE)

• Addition of 8.7 USB Function Control

Modification of Figure 10-1 Block Diagram of Regulator and USB

Driver/Receiver and Cautions

CHAPTER 10 REGULATOR

Addition of Remark in Table 11-1 Interrupt Source List

CHAPTER 11 INTERRUPT

FUNCTIONS

Addition of Caution 3 on watchdog timer interrupt to Figure 11-2 Format of

Interrupt Request Flag Register

Addition of 12.2.2 STOP mode (3) Cautions on STOP instruction

CHAPTER 12 STANDBY

FUNCTION

execution

CHAPTER 14 µPD78F9801

Revision of contents of flash memory programming as 14.1 Flash Memory

Characteristics

Addition of CHAPTER 16 ELECTRICAL SPECIFICATIONS

Addition of CHAPTER 17 PACKAGE DRAWING

CHAPTER 16 ELECTRICAL

SPECIFICATIONS

CHAPTER 17 PACKAGE

DRAWING

Addition of CHAPTER 18 RECOMMENDED SOLDERING CONDITIONS

CHAPTER 18 ECOMMENDED

SOLDERING CONDITIONS

Revision of APPENDIX A DEVELOPMENT TOOLS

APPENDIX A

Deletion of embedded software and addition of notes on target system design

DEVELOPMENT TOOLS

Addition of the revision contents in 3rd edition in APPENDIX C REVISION

APPENDIX C REVISION

HISTORY

3rd

Modification of Figure 6-8. Timing of External Event Counter Operation

CHAPTER 6 8-BIT

(modification

ver.2)

(with Rising Edge Specified)

TIMER/EVENT COUNTER

Modification of conditions of VIL2 and VOL2

CHAPTER 16 ELECTRICAL

SPECIFICATIONS

User’s Manual U12978EJ3V3UD

235

APPENDIX C REVISION HISTORY

(3/3)

Edition

Major Revisions from Previous Edition

Applied to:

3rd

Addition of lead-free products

CHAPTER 1 GENERAL

(modification

ver.3)

Addition of soldering conditions of lead-free products in Table 18-1 Surface

CHAPTER 18 ECOMMENDED

SOLDERING CONDITIONS

Mounting Type Soldering Conditions

236

User’s Manual U12978EJ3V3UD


型号：	UPD78F9801GB-8ES-A
厂家：	NEC
描述：	Microcontroller, 8-Bit, FLASH, 6MHz, CMOS, PQFP44, 10 X 10 MM, LEAD FREE, PLASTIC, LQFP-44 微控制器
文件：	总236页 (文件大小：1552K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UPD78F9801GB-8ES-A [NEC]

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