UPD8880 [NEC]
(10680 ®10680) PIXELS x 3 COLOR CCD LINEAR IMAGE SENSOR; （ 10680 ®10680 ）像素× 3彩色CCD线性图像传感器
| 型号： | UPD8880 |
| 厂家： | 
NEC |
| 描述： | (10680 ®10680) PIXELS x 3 COLOR CCD LINEAR IMAGE SENSOR |
| 文件： | 总24页 (文件大小：194K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD8880
(10680 × 10680) PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR
DESCRIPTION
The µPD8880 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to
electrical signal and has the function of color separation.
The µPD8880 has 3 rows of (10680+10680) staggered pixels, and each row has a dual-sided readout type of
charge transfer register. And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is
suitable for 2400 dpi/A4 color image scanners, color facsimiles and so on.
FEATURES
• Valid photocell
: (10680+10680) pixels × 3
• Photocell pitch : 4 µm
• Line spacing
: 64 µm (16 lines) Red line - Green line, Green line - Blue line
8 µm (2 lines) Odd line – Even line (for each color)
• Color filter
: Primary colors (red, green and blue), pigment filter (with light resistance 107 lx•hour)
: 96 dot/mm A4 (210 × 297 mm) size (shorter side)
• Resolution
:
2400 dpi US letter (8.5” × 11”) size (shorter side)
• Drive clock level : CMOS output under 5 V operation
• Data rate
: 8 MHz Max.
: +12 V
• Power supply
• On-chip circuits : Reset feed-through level clamp circuits
:: Voltage amplifiers
ORDERING INFORMATION
Part Number
Package
CCD linear image sensor 32-pin plastic DIP (10.16 mm (400))
µPD8880CY
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
The mark
shows major revised points.
Document No. S16032EJ3V0DS00 (3rd edition)
Date Published July 2003 NS CP (K)
Printed in Japan
2002
µPD8880
BLOCK DIAGRAM
φ
φ
φ
1
GND
1
2L
2
V
OD
GND
16
29
20
13
19
CCD analog shift register
Transfer gate
φ
TG1
(Blue)
18
17
15
V
(Blue)
OUT
1
30
31
32
Photocell
(Blue)
····
····
····
Transfer gate
CCD analog shift register
CCD analog shift register
Transfer gate
φ
TG2
(Green)
VOUT
2
Photocell
(Green)
(Green)
Transfer gate
CCD analog shift register
CCD analog shift register
Transfer gate
φ
TG3
(Red)
VOUT
3
Photocell
(Red)
(Red)
Transfer gate
CCD analog shift register
3
2
14
5
4
φ
φ
1
φ
φ
1L
2
φ
RB
CLB
2
Data Sheet S16032EJ3V0DS
µPD8880
PIN CONFIGURATION (Top View)
CCD linear image sensor 32-pin plastic DIP (10.16 mm (400))
• µPD8880CY
Ground
GND
RB
1
2
3
4
5
6
7
8
9
32
31
30
29
V
V
V
V
OUT
OUT
OUT
OD
3
2
1
Output signal 3 (Red)
Reset gate clock
φ
Output signal 2 (Green)
Output signal 1 (Blue)
Output drain voltage
No connection
Reset feed-through level
clamp clock
φ
CLB
Shift register clock 1
Shift register clock 2
Internal connection
Internal connection
No connection
φ
φ
1
2
28 NC
27 IC
26 IC
25 NC
24 NC
23 NC
22 IC
21 IC
IC
IC
Internal connection
Internal connection
No connection
NC
NC
No connection
No connection
No connection
NC 10
IC 11
IC 12
No connection
Internal connection
Internal connection
Shift register clock 1
Last stage shift register clock 1
Internal connection
Internal connection
Shift register clock 2
Last stage shift register clock 2
φ
1
13
14
15
20
19
18
17
φ
φ
φ
φ
2
φ
2L
1L
TG3
Transfer gate clock 3
(for Red)
Transfer gate clock 1
(for Blue)
φ
TG1
TG2
Transfer gate clock 2
(for Green)
GND 16
Ground
Cautions 1. Leave pins 6 , 7, 11, 12, 21, 22, 26, 27 (IC) unconnected.
2. Connect the No connection pins (NC) to GND.
3
Data Sheet S16032EJ3V0DS
µPD8880
PHOTOCELL STRUCTURE DIAGRAM
2
µ
m
2 µm
µ
Channel stopper
Aluminum
shield
PHOTOCELL ARRAY STRUCTURE DIAGRAM (Line spacing)
4 µm
4 µm
4 µm
Blue photocell array
Blue photocell array
2 lines
(8 m)
µ
16 lines
(64 m)
µ
14 lines
(56 m)
µ
4 µm
4 µm
4 µm
Green photocell array
Green photocell array
2 lines
(8 m)
µ
16 lines
(64 m)
µ
14 lines
(56 m)
µ
4
4
4
µ
µ
µ
m
m
m
Red photocell array
Red photocell array
2 lines
(8 m)
µ
4
Data Sheet S16032EJ3V0DS
µPD8880
ABSOLUTE MAXIMUM RATINGS (TA = +25°C)
Parameter
Output drain voltage
Symbol
Ratings
−0.3 to +15
−0.3 to +8
−0.3 to +8
−0.3 to +8
Unit
V
VOD
Shift register clock voltage
Reset gate clock voltage
Vφ 1, Vφ 2, Vφ 1L, Vφ 2L
V
Vφ RB
V
Reset feed-through level clamp
clock voltage
Vφ CLB
V
Transfer gate clock voltage
Operating ambient temperature Note
Storage temperature
Vφ TG1 to Vφ TG3
−0.3 to +8
0 to +60
V
TA
°C
°C
Tstg
−40 to +70
Note Use at the condition without dew condensation.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
RECOMMENDED OPERATING CONDITIONS (TA = +25°C)
Parameter
Output drain voltage
Symbol
Min.
11.4
4.8
Typ.
12.0
5.0
0
Max.
12.6
5.5
Unit
V
VOD
Shift register clock high level
Shift register clock low level
Reset gate clock high level
Reset gate clock low level
Vφ 1_H, Vφ 2_H, Vφ 1LH, Vφ 2LH
V
Vφ 1_L, Vφ 2_L, Vφ 1LL, Vφ 2LL
−0.3
4.5
+0.2
5.5
V
Vφ RBH
Vφ RBL
Vφ CLBH
5.0
0
V
−0.3
4.5
+0.5
5.5
V
Reset feed-through level clamp clock
high level
5.0
V
Reset feed-through level clamp clock
low level
Vφ CLBL
−0.3
0
+0.5
V
Note
Note
Transfer gate clock high level
Transfer gate clock low level
CCD Transfer speed
Data rate
Vφ TG1H to Vφ TG3H
Vφ TG1L to Vφ TG3L
fφ 1, fφ 2
4.8
−0.3
−
Vφ 1_H
Vφ 1_H
V
0
1
2
+0.15
V
6
8
MHz
MHz
fφ RB
−
Note When Transfer gate clock high level (Vφ TG1H to Vφ TG3H) is higher than Shift register clock high level (Vφ 1_H),
Image lag can increase.
5
Data Sheet S16032EJ3V0DS
µPD8880
ELECTRICAL CHARACTERISTICS
TA = +25°C, VOD = 12 V, data rate (fφ RB) = 2 MHz, storage time = 11.0 ms, input signal clock = 5 Vp-p,
light source : 3200 K halogen lamp + C-500S (infrared cut filter, t = 1 mm) + HA-50 (heat absorbing filter, t = 3 mm)
Parameter
Saturation voltage 1
Symbol
Vsat1
Vsat2
PRNU
ADS
DSNU
PW
Test Conditions
Min.
Typ.
3.5
Max.
−
Unit
V
Note 1
Note 2
2.5
Saturation voltage 2
1.5
2.5
−
V
Photo response non-uniformity
Average dark signal
VOUT = 1.0 V
−
6
20
4.0
8.0
450
1
%
Light shielding
Light shielding
−
0.4
mV
mV
mW
kΩ
Dark signal non-uniformity
Power consumption
−
2.0
−
290
0.3
Output impedance
ZO
−
2.52
2.31
1.26
−
Response
Red
RR
3.60
3.30
1.80
1.0
4.68
4.29
2.34
7.0
7.5
−
V/lx•s
V/lx•s
V/lx•s
%
Green
Blue
RG
RB
Image lag
Offset level Note 3
Output fall delay time Note 4
Total transfer efficiency
Register imbalance
Response peak
IL
VOUT = 1.0 V
VOS
td
4.5
−
6.0
V
VOUT = 1.0 V
25
ns
TTE
RI
VOUT = 1.0 V, fφ 1, fφ 2 = 6 MHz
VOUT = 1.0 V
92
−
98
−
%
1.0
4.0
−
%
Red
−
630
540
460
1750
3500
−500
1.0
nm
nm
nm
times
times
mV
mV
Green
Blue
−
−
−
−
Dynamic range
DR1
Vsat1/DSNU, Note 1
Vsat1/σ CDS, Note 1
Light shielding
−
−
DR2
−
−
Reset feed-through noise Note 3
Random noise (CDS)
RFTN
σ CDS
−2000
−
+500
−
Light shielding
Notes 1. Vsat1: fφ 1, fφ 2 ≤ 4 MHz, fφ RB ≤ 8 MHz
2. Vsat2: 4 MHz < (fφ 1, fφ 2) < 6 MHz, fφ RB ≤ 8 MHz (refer to TIMING CHART 3)
3. Refer to TIMING CHART 2.
4. When the fall time of φ 1L (t1’) is the Typ. value (refer to TIMING CHART 2).
6
Data Sheet S16032EJ3V0DS
µPD8880
INPUT PIN CAPACITANCE (TA = +25°C, VOD = 12 V)
Parameter
Symbol Pin name Pin No.
Min.
−
Typ.
1100
1100
2200
1100
1100
2200
70
Max.
−
Unit
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
Shift register clock pin capacitance 1
Cφ 1
φ 1
4
13
−
−
φ 1 total capacitance
φ 2
−
−
Shift register clock pin capacitance 2
Cφ 2
5
−
−
20
−
−
φ 2 total capacitance
−
−
Last stage shift register clock pin capacitance 1
Last stage shift register clock pin capacitance 2
Reset gate clock pin capacitance
Cφ 1L
Cφ 2L
Cφ RB
Cφ CLB
Cφ TG
φ 1L
14
19
2
−
−
φ 2L
−
70
−
φ RB
−
20
−
Reset feed-through level clamp clock pin capacitance
Transfer gate clock pin capacitance
φ CLB
φ TG1
φ TG2
φ TG3
3
−
20
−
18
17
15
−
200
200
200
−
−
−
−
−
Remarks 1. Pins 4 and 13 (φ 1), 5 and 20 (φ 2) are each connected inside of the device.
2. Cφ 1 and Cφ 2 show the equivalent capacity of the real drive including the capacity of between φ 1 and
φ 2.
7
Data Sheet S16032EJ3V0DS
TIMING CHART 1-1 (Bit clamp mode, for each color)
φ
TG1 to
φ
1,
2,
TG3
φ
φ
φ
φ
1L
2L
φ
RB
Note
Note
φ
CLB
VOUT1 to VOUT3
Optical black
(48 pixels)
Valid photocell
(21360 pixels)
Invalid photocell
(4 pixels)
Invalid photocell
(4 pixels)
µ
Note Set the φ RB and φ CLB to high level during this period.
TIMING CHART 1-2 (Line clamp mode, for each color)
φ
TG1 to
φ
1,
2,
TG3
φ
φ
φ
φ
1L
2L
φ
RB
Note
Note
φ
CLB
(φTG1 toφ TG3)
VOUT1 to VOUT3
Optical black
(48 pixels)
Valid photocell
(21360 pixels)
Invalid photocell
(4 pixels)
Invalid photocell
(4 pixels)
µ
Note Set the φ RB to high level during this period.
Remark Inverse pulse of the φ TG1 to φ TG3 can be used as φ CLB.
µPD8880
TIMING CHART 2-1 (Bit clamp mode, for each color)
t1
t2
90%
φ
φ
1
2
10%
90%
10%
t1’
t2’
90%
10%
φ
φ
1L
2L
90%
10%
t5
t6
t5
t6
t3
t4
t3
t4
90%
10%
φ
RB
t9
t10
t9
t10
t7
t8
t11
t7
t8
t11
90%
10%
φ
CLB
t
d
t
d
RFTN
VOUT
VOS
10%
Symbol
t1, t2
Min.
Typ.
30
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
0
−
−
−
−
−
−
−
−
−
t1’, t2’
t3
5
20
75
0
100
200
10
t4
t5, t6
t7
30
20
0
100
100
10
t8
t9, t10
t11
5
25
10
Data Sheet S16032EJ3V0DS
µPD8880
TIMING CHART 2-2 (Line clamp mode, for each color)
t2
t1
90%
φ
φ
1
2
10%
90%
10%
t2’
t1’
90%
10%
φ
1L
90%
10%
φ
2L
t5
t6
t5
t6
t3
t4
t3
t4
90%
10%
φ
RB
“H”
φ
CLB
t
d
t
d
RFTN
VOUT
VOS
10%
Symbol
t1, t2
Min.
0
Typ.
30
Max.
Unit
ns
−
−
−
−
−
t1’, t2’
t3
0
5
ns
20
75
0
100
200
10
ns
t4
ns
t5, t6
ns
TIMING CHART 3 (Sift Register Pulse φ 1, φ 2 = 6 MHz (Max.))
φ
1
2
4.8 V or more
30 ns or more
0.2 V or less
φ
30 ns or more
11
Data Sheet S16032EJ3V0DS
µPD8880
φ TG1 to φ TG3, φ 1, φ 2 TIMING CHART
t13
90%
10%
t15
t14
t12
φ
TG1 to φ TG3
t16
90%
φ
φ
1
2
t17
90%
t7
Note 1
t18
φ
RB
90%
φ
CLB
(Bit clamp mode)
t20
t21
t22
Note 2
t23
90%
10%
φ
CLB
(Line clamp mode)
t9
t19
t10
Symbol
Min.
Typ.
100
10
Max.
Unit
t7
30
0
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
t9, t10
t12
−
5000
0
10000
50
50000
t13, t14
t15, t16
t17, t18
t19
−
900
200
t12
0
1000
400
t12
−
−
50000
t20, t21
t22, t23
50
−
−
30
350
Notes 1. Set the φ RB and φ CLB to high level during this period.
2. Set the φ RB to high level during this period.
Remark Inverse pulse of the φ TG1 to φ TG3 can be used as φ CLB.
12
Data Sheet S16032EJ3V0DS
µPD8880
φ 1, φ 2 cross points
φ 1, φ 2L cross points
φ
φ
2
1
1.5 V to 3.5 V
1.5 V to 3.5 V
φ
1
2 V or more
0.5 V or more
φ
2L
φ 2, φ 1L cross points
φ
2
2 V or more
0.5 V or more
φ
1L
Remark Adjust cross points (φ 1, φ 2), (φ 1, φ 2L) and (φ 2, φ 1L) with input resistance of each pin.
13
Data Sheet S16032EJ3V0DS
µPD8880
DEFINITIONS OF CHARACTERISTIC ITEMS
1. Saturation voltage : Vsat
Output signal voltage at which the response linearity is lost.
2. Saturation exposure : SE
Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs.
3. Photo response non-uniformity : PRNU
The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light
of uniform illumination. This is calculated by the following formula.
x
∆
PRNU (%) =
× 100
x
∆
x : maximum of x
j
− x
21360
x
j
Σ
j = 1
21360
: Output voltage of valid pixel number j
x =
xj
VOUT
x
Register Dark
DC level
∆
x
4. Average dark signal : ADS
Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following
formula.
21360
d
j
Σ
j = 1
21360
ADS (mV) =
d
j
: Dark signal of valid pixel number j
14
Data Sheet S16032EJ3V0DS
µPD8880
5. Dark signal non-uniformity : DSNU
Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the
valid pixels at light shielding. This is calculated by the following formula.
DSNU (mV) : maximum of d
j
− ADS j = 1 to 21360
d
j
: Dark signal of valid pixel number j
VOUT
ADS
Register Dark
DC level
DSNU
6. Output impedance : ZO
Impedance of the output pins viewed from outside.
7. Response : R
Output voltage divided by exposure (lx•s).
Note that the response varies with a light source (spectral characteristic).
8. Image lag : IL
The rate between the last output voltage and the next one after read out the data of a line.
φ
TG
Light
ON
OFF
V
OUT
V1
VOUT
V
1
IL (%) =
× 100
OUT
V
15
Data Sheet S16032EJ3V0DS
µPD8880
9. Register Imbalance : RI
The rate of the difference between the averages of the output voltage of Odd and Even bits, against the
average output voltage of all the valid pixels.
n
2
2
n
∑
(V2j –1 – V2j
n
)
j = 1
RI (%) =
× 100
1
n
∑
V
j
j = 1
n
V
: Number of valid pixels
: Output voltage of each pixel
j
10. Random noise (CDS) : σ CDS
Random noise σ CDS is defined as the standard deviation of a valid pixel output signal with 100 times (=100
lines) data sampling at dark (light shielding). σ CDS is calculated by the following procedure.
1. One valid photocell in one reading is fixed as measurement point.
2. The output level is measured during the reset feed-through period which is averaged over 100 ns to get
“VDi”.
3. The output level is measured during the Video Output time averaged over 100 ns to get “VOi”.
4. The correlated double sampling output is defined by VCDSi = VDi – VOi
5. Repeat the above procedure (1 to 4) for 100 times (= 100 lines).
6. Calculate the standard deviation σ CDS using the following formula equation.
100
100
(VCDS
100
i
– V)2
1
Σ
σ
CDS (mV) =
, V =
VCDS
i
100 Σ
i = 1
i = 1
Video Output
Reset feed-through
16
Data Sheet S16032EJ3V0DS
µPD8880
STANDARD CHARACTERISTIC CURVES (Reference Value)
DARK OUTPUT TEMPERATURE
CHARACTERISTIC
STORAGE TIME OUTPUT VOLTAGE
CHARACTERISTIC (T = +25°C)
A
8
2
1
4
2
1
0.5
0.2
0.1
0.25
0.1
0
10
20
30
40
50
1
5
10
Operating Ambient Temperature TA (°C)
Storage Time (ms)
TOTAL SPECTRAL RESPONSE CHARACTERISTICS
(without infrared cut filter and heat absorbing filter ) (T = +25°C)
A
100
80
R
B
G
60
40
20
G
B
0
400
500
600
700
800
Wavelength (nm)
17
Data Sheet S16032EJ3V0DS
µPD8880
APPLICATION CIRCUIT EXAMPLE
+5 V
+
µ
PD8880
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
10
µ
F/16 V
0.1 µF
GND
V
OUT
OUT
OUT
3
2
1
B3
B2
B1
200
47
Ω
+12 V
φ
φ
φ
φ
V
V
RB
RB
CLB
1
Ω
3
φ
CLB
+
1
1
Ω
4
φ
φ
VOD
1
2
Ω
5
0.1
µ
µ
F
47
µ
F/25 V
φ
NC
IC
2
+5 V
6
IC
7
+
IC
IC
8
NC
NC
NC
IC
NC
NC
NC
IC
10 µF/16 V
0.1
F
9
10
11
12
13
14
15
16
φ
TG
IC
IC
1
Ω
1
Ω
φ
φ
φ
φ
φ
2
φ
2
1
1
100
4.7
Ω
Ω
100 Ω
4.7 Ω
4.7 Ω
φ
1L
TG3
φ
2L
φ
2L
1L
φ
φ
TG1
TG2
GND
Cautions 1. Leave pins 6, 7, 11, 12, 21, 22, 26, 27 (IC) unconnected.
2. Connect the No connection pins (NC) to GND.
Remarks 1. The inverters shown in the above application circuit example are the 74HC04 (fφ RB < 2 MHz, (fφ 1, fφ 2)
< 1 MHz) or 74AC04 (2 MHz ≤ fφ RB ≤ 8 MHz, 1 MHz ≤ (fφ 1, fφ 2) ≤ 6 MHz).
2. The input clock register of φ RB (2 pin) shown in the above application circuit example are the 200 Ω
(74HC04) or 300 Ω (74AC04).
3. Inverters B1 to B3 in the above application circuit example are shown in the figure blow.
B1 to B3 EQUIVALENT CIRCUIT
+12 V
+
µ
47 F/25 V
100 Ω
2SC945
2 kΩ
100 Ω
CCD
VOUT
18
Data Sheet S16032EJ3V0DS
µPD8880
PACKAGE DRAWING
µ
PD8880CY
CCD LINEAR IMAGE SENSOR 32-PIN PLASTIC DIP (10.16 mm (400) )
(Unit : mm)
55.2 0.5
54.8 0.5
1st valid pixel
1
5.9 0.3
32
17
1
16
46.7
2.0
12.6 0.5
4.1 0.5
10.16 0.20
4.55 0.5
1.02 0.15
2
(1.80)
3
2.58 0.3
0.46 0.1
2.54 0.25
0.25 0.05
(5.42)
+0.7
10.16
−0.2
4.21 0.5
Name
Dimensions
Refractive index
Plastic cap
52.2×6.4×0.7
1.5
1 1st valid pixel
The center of the pin1
2 The surface of the CCD chip
3 The bottom of the package
The top of the cap
The surface of the CCD chip
32C-1CCD-PKG4-2
19
Data Sheet S16032EJ3V0DS
µPD8880
RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below.
If other soldering processes are used, or if the soldering is performed under different conditions, please make sure
to consult with our sales offices.
Type of Through-hole Device
µPD8880CY : CCD linear image sensor 32-pin plastic DIP (10.16 mm (400))
Process
Conditions
Partial heating method
Pin temperature : 300°C or below, Heat time : 3 seconds or less (per pin)
Cautions1. During assembly care should be taken to prevent solder or flux from contacting the plastic
cap. The optical characteristics could be degraded by such contact.
2. Soldering by the solder flow method may have deleterious effects on prevention of plastic cap
soiling and heat resistance. So the method cannot be guaranteed.
20
Data Sheet S16032EJ3V0DS
µPD8880
NOTES ON HANDLING THE PACKAGES
1
DUST AND DIRT PROTECTING
The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning. Don’t either
touch plastic cap surface by hand or have any object come in contact with plastic cap surface. Should dirt
stick to a plastic cap surface, blow it off with an air blower. For dirt stuck through electricity ionized air is
recommended. And if the plastic cap surface is grease stained, clean with our recommended solvents.
CLEANING THE PLASTIC CAP
Care should be taken when cleaning the surface to prevent scratches.
We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below.
Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is
recommended that a clean surface or cloth be used.
RECOMMENDED SOLVENTS
The following are the recommended solvents for cleaning the CCD plastic cap.
Use of solvents other than these could result in optical or physical degradation in the plastic cap.
Please consult your sales office when considering an alternative solvent.
Solvents
Ethyl Alcohol
Symbol
EtOH
MeOH
IPA
Methyl Alcohol
Isopropyl Alcohol
N-methyl Pyrrolidone
NMP
2
MOUNTING OF THE PACKAGE
The application of an excessive load to the package may cause the package to warp or break, or cause chips
to come off internally. Particular care should be taken when mounting the package on the circuit board. Don't
have any object come in contact with plastic cap. You should not reform the lead frame. We recommended to
use a IC-inserter when you assemble to PCB.
Also, be care that the any of the following can cause the package to crack or dust to be generated.
1. Applying heat to the external leads for an extended period of time with soldering iron.
2. Applying repetitive bending stress to the external leads.
3. Rapid cooling or heating
3
4
OPERATE AND STORAGE ENVIRONMENTS
Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject
to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So avoid
storage or usage in such conditions.
Keep in a case to protect from dust and dirt. Dew condensation may occur on CCD image sensors when the
devices are transported from a low-temperature environment to a high-temperature environment. Avoid such
rapid temperature changes.
For more details, refer to our document "Review of Quality and Reliability Handbook" (C12769E)
ELECTROSTATIC BREAKDOWN
CCD image sensor is protected against static electricity, but destruction due to static electricity is sometimes
detected. Before handling be sure to take the following protective measures.
1. Ground the tools such as soldering iron, radio cutting pliers of or pincer.
2. Install a conductive mat or on the floor or working table to prevent the generation of static electricity.
3. Either handle bare handed or use non-chargeable gloves, clothes or material.
4. Ionized air is recommended for discharge when handling CCD image sensor.
5. For the shipment of mounted substrates, use box treated for prevention of static charges.
6. Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on
which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle
straps which are grounded via a series resistance connection of about 1 MΩ.
21
Data Sheet S16032EJ3V0DS
µPD8880
[MEMO]
22
Data Sheet S16032EJ3V0DS
µPD8880
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
23
Data Sheet S16032EJ3V0DS
µPD8880
•
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•
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M8E 02. 11-1
相关型号：
UPD8894CY-A
CCD Sensor, 5340 Horiz pixels, 5340 Vert pixels, 2.50-2.80V, Rectangular, Through Hole Mount, PLASTIC, DIP-32
NEC
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