UPD98433S9-K6 [NEC]
LAN Controller, 8 Channel(s), 125MBps, CMOS, PBGA756, 45 X 45 MM, PLASTIC, BGA-756;
| 型号： | UPD98433S9-K6 |
| 厂家： | 
NEC |
| 描述： | LAN Controller, 8 Channel(s), 125MBps, CMOS, PBGA756, 45 X 45 MM, PLASTIC, BGA-756 时钟 局域网 数据传输 外围集成电路 |
| 文件： | 总142页 (文件大小：1360K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary User’s Manual
µPD98433
10/100/1000 Mbps EthernetTM Controller
Document No. S15212EJ3V0UM00 (3rd edition)
Date Published September 2003 NS CP(K)
2001
Printed in Japan
[MEMO]
Preliminary User’s Manual S15212EJ3V0UM
2
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Ethernet is a trademark of XEROX Corporation.
3
Preliminary User’s Manual S15212EJ3V0UM
•
The information contained in this document is being issued in advance of the production cycle for the
product. The parameters for the product may change before final production or NEC Electronics
Corporation, at its own discretion, may withdraw the product prior to its production.
• Not all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent
of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC Electronics or others.
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative purposes
in semiconductor product operation and application examples. The incorporation of these circuits, software and
information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC
Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of
these circuits, software and information.
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products,
customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and
anti-failure features.
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-designated
"quality assurance program" for a specific application. The recommended applications of an NEC Electronics
products depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC
Electronics product before using it in a particular application.
•
•
•
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and
visual equipment, home electronic appliances, machine tools, personal electronic equipment and
industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life
support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support
systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M5D 02. 11-1
Preliminary User’s Manual S15212EJ3V0UM
4
Major Revisions in This Edition
Page
Description
pp. 13 to 15
1.3 Pin Configuration
Modified the names of pins No. 64 (AP31), 359 (C17), and 428 (AK31).
p. 17
Changed the figure of 1.5 Sample System Configuration
pp. 18, 22, 24, 27 CHAPTER 2 PIN FUNCTIONS
Modified the description of the pins; TX_CLK[7:0], GTX_CLK[7:0], RX_CLK[7:0]0.
Modified the numbers of the pins; INT#, TEST[3, 1, 0] and TEST[5, 4, 2].
p. 31
p. 33
p. 34
p. 36
Modified the description in 3.2.9 Operation clocks.
Modified the description in 3.4.1 (2) Addition of CRC and (3) Addition of PAD.
Modified the description in 3.4.2 Start of packet transmission.
Modified the description in 3.4.5 (6) Occurrence of transmit FIFO underrun and (7)
Occurrence of parity errors.
p. 36
Added 3.4.5 (8) Transmit FIFO overrun.
p. 37
Modified the SFD-bit pattern in 3.5.1 Preamble and SFD detection.
Added the conditions of receive packet filtering in 3.5.4 Packet filtering.
Modified the description of the RPPD bit in Table 3-1. Receive Status Information.
Added description in 3.6 Full-Duplex Operation.
p. 37
p. 40
p. 41
p. 54
Modified the description in 3.8.4 (1) MDC clock.
p. 61
Modified the description in 3.10 Back Pressure.
p. 61
Modified the bit width of the counters in 3.12 Statistics Counters.
Modified the description in 3.13 Loopback.
p. 62
p. 62
Modified the description in 3.14 Low Power Mode.
Added 3.16 Turning Power ON.
p. 64
pp. 65 to 113
CHAPTER 4 REGISTER DESCRIPTION
Added CLKCHK register to global registers.
Modified register address name of PCS configuration registers.
Modified the description of registers; MACC1, MACC2, IPGIFG, HDREG, LMAX, MCMD, CAR1,
CAR2, CAM1, CAM2, AFR, ICFPT, TSVREG, RSVREG, FSVREG, RFIC3, TFIC1, MISCR,
PYSTS, PYTBIC.
Modified default value of VERID register.
pp.114 to 128
CHAPTER 5 STATISTICS COUNTERS
Modified bit map of all counters to 32 bits.
Modified register names and functions in register address 86H and A6H.
Modified the descriptions of counters; RXPF, ROVR, RJBR, TOVR, RDRP, TFPE.
p. 133
Modified the description in 6.4.2 (1) Test-Logic-Reset.
The mark shows major revised points.
5
Preliminary User’s Manual S15212EJ3V0UM
PREFACE
Target Readers
Purpose
This manual is intended for users who wish to understand the functions of the µPD98433
and to design and develop systems using it.
This manual is intended to give users an understanding of the hardware functions of the
µPD98433 described in the Organization below.
Organization
The contents of this manual are structured as follows.
• Overview
• Pin functions
• Function description
• Register description
• Statistics counters
• JTAG boundary scan
How to Read This Manual It is assumed that the reader of this manual has general knowledge in the fields of
electrical engineering, logic circuits, and microcontrollers.
To understand the overall functions of the µPD98433:
→ Read this manual in the order of the Contents.
Conventions
Data significance:
Higher digits on the left and lower digits on the right
Active low representation: XXX# (# after pin or signal name)
Memory map address:
Higher addresses on the top and lower addresses on the
bottom
Note:
Footnote for item marked with Note in the text
Information requiring particular attention
Supplementary information
Caution:
Remark:
Numerical representation: Binary ... ×××× or ××××B
Decimal ... ××××
Hexadecimal ... ××××H
Prefix indicating the power of 2 (address space, memory capacity):
K (kilo):
210 = 1024
M (mega): 220 = 10242
G (giga): 230 = 10243
Related Documents
The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
• Data sheet: S15238E
6
Preliminary User’s Manual S15212EJ3V0UM
CONTENTS
CHAPTER 1 OVERVIEW..........................................................................................................................11
1.1 Features .......................................................................................................................................11
1.2 Ordering Information..................................................................................................................11
1.3 Pin Configuration........................................................................................................................12
1.4 Internal Block Diagram...............................................................................................................17
1.5 Sample System Configuration...................................................................................................17
CHAPTER 2 PIN FUNCTIONS................................................................................................................18
CHAPTER 3 FUNCTION DESCRIPTION................................................................................................28
3.1 System Configuration.................................................................................................................28
3.2 Function Blocks..........................................................................................................................29
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.2.8
3.2.9
MAC module .................................................................................................................................. 29
PCS module................................................................................................................................... 30
Station Address Logic (SAL) module ............................................................................................. 30
Statistics counter (STAT) module .................................................................................................. 30
On-chip FIFO ................................................................................................................................. 30
FIFO bus module ........................................................................................................................... 30
MII management module ............................................................................................................... 30
Register bus module ...................................................................................................................... 31
Operation clocks ............................................................................................................................ 31
3.3 Frame Formats............................................................................................................................32
3.4 Transmit Operation.....................................................................................................................33
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
Generation of transmit packets ...................................................................................................... 33
Start of packet transmission........................................................................................................... 34
Setting interpacket gaps................................................................................................................. 34
Collisions and retransmission ........................................................................................................ 35
End of transmission and abort ....................................................................................................... 35
3.5 Receive Operations ....................................................................................................................37
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.5.6
3.5.7
3.5.8
Preamble and SFD detection......................................................................................................... 37
Length field check.......................................................................................................................... 37
CRC check..................................................................................................................................... 37
Packet filtering ............................................................................................................................... 37
Address filtering ............................................................................................................................. 38
Receive FIFO overflow................................................................................................................... 38
Clearing receive FIFO.................................................................................................................... 39
Adding status information............................................................................................................... 39
3.6 Full-Duplex Operation ................................................................................................................41
3.7 System Bus Interface .................................................................................................................42
3.7.1
3.7.2
FIFO bus interface ......................................................................................................................... 42
Register bus interface .................................................................................................................... 51
3.8 Network Interface........................................................................................................................53
3.8.1
3.8.2
3.8.3
GMII (Gigabit Media Independent Interface).................................................................................. 53
TBI (Ten Bit Interface).................................................................................................................... 53
MII (Media Independent Interface)................................................................................................. 53
7
Preliminary User’s Manual S15212EJ3V0UM
3.8.4
3.8.5
3.8.6
MII management interface..............................................................................................................54
µPD98433 connection of MII output signal pins .............................................................................56
Auto-negotiation .............................................................................................................................56
3.9 Flow Control ................................................................................................................................57
3.9.1
3.9.2
3.9.3
Control frame reception..................................................................................................................57
Flow control pause timer ................................................................................................................57
Pause control frame transmission ..................................................................................................58
3.10 Back Pressure .............................................................................................................................61
3.11 Operations on VLAN Frames .....................................................................................................61
3.11.1 VLAN frame detection ....................................................................................................................61
3.11.2 VLAN frame reception....................................................................................................................61
3.11.3 VLAN frame transmission...............................................................................................................61
3.12 Statistics Counters .....................................................................................................................61
3.13 Loopback .....................................................................................................................................62
3.14 Low Power Mode.........................................................................................................................62
3.15 Software Reset ............................................................................................................................63
3.16 Turning Power ON.......................................................................................................................64
CHAPTER 4 REGISTER DESCRIPTION................................................................................................65
4.1 Control Register Map..................................................................................................................65
4.2 Port Configuration Registers.....................................................................................................67
4.3 Global Registers..........................................................................................................................99
4.4 PCS Configuration Registers.................................................................................................. 104
CHAPTER 5 STATISTICS COUNTERS............................................................................................... 114
CHAPTER 6 JTAG BOUNDARY SCAN ............................................................................................. 129
6.1 Features .................................................................................................................................... 129
6.2 Internal Configuration of Boundary Scan Circuit................................................................. 130
6.2.1
6.2.2
6.2.3
6.2.4
Instruction register........................................................................................................................130
TAP (Test Access Port) controller................................................................................................130
Bypass register ............................................................................................................................130
Boundary scan register ................................................................................................................130
6.3 Pin Function.............................................................................................................................. 131
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
TCK (JTAG Test Clock) pin..........................................................................................................131
TMS (JTAG Test Mode Select) pin ..............................................................................................131
TDI (JTAG Test Data Input) pin....................................................................................................131
TDO (JTAG Test Data Output) pin...............................................................................................131
TRST# (JTAG Reset) pin .............................................................................................................131
6.4 Operation Description ............................................................................................................. 132
6.4.1
6.4.2
TAP controller ..............................................................................................................................132
TAP controller state......................................................................................................................132
6.5 TAP Controller Operation........................................................................................................ 137
6.6 Initializing TAP Controller ....................................................................................................... 140
6.7 Instruction Register ................................................................................................................. 140
6.7.1
6.7.2
6.7.3
BYPASS instruction......................................................................................................................141
EXTEST instruction......................................................................................................................141
SAMPLE/PRELOAD instruction ...................................................................................................141
8
Preliminary User’s Manual S15212EJ3V0UM
LIST OF FIGURES
Figure No.
Title
Page
3-1
Sample System Configuration Using µPD98433 ............................................................................................28
µPD98433 Function Block Diagram................................................................................................................29
Ethernet/IEEE802.3 Frame Structure.............................................................................................................32
VLAN Frame Structure ...................................................................................................................................32
Configuration of Status and RBYT Fields.......................................................................................................39
FIFO Interface Write Timing ...........................................................................................................................42
Timing of Switching Transmit Data Write Port Using TXFPT[2:0]...................................................................44
FIFO Interface Read Timing...........................................................................................................................45
Timing of Switching Ports After Receive Data Is Read...................................................................................47
Timing of Switching Read Port Due to SKIP Signal (Before Start of Read)....................................................48
Timing of Read Port Switch Due to SKIP Signal (During Read) .....................................................................49
Register Address Bus.....................................................................................................................................51
MII Management Frame Structure..................................................................................................................55
Connection of MII Output Signal Pin...............................................................................................................56
Pause Control Frame Transmission ...............................................................................................................58
Reissuance of Pause Control Frame by Pause Retransmission Interval Timer..............................................59
Recommended Timing of Turning Power ON.................................................................................................64
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
6-1
6-2
6-3
6-4
6-5
Block Diagram of Boundary Scan Circuit......................................................................................................130
State Transition of TAP Controller................................................................................................................132
Operation Timing in Controller State ............................................................................................................133
Operation of Test Logic (Instruction Scan) ...................................................................................................138
Operation of Test Logic (Data Scan) ............................................................................................................139
9
Preliminary User’s Manual S15212EJ3V0UM
LIST OF TABLES
No.
Title
Page
3-1
3-2
3-3
3-4
3-5
Receive Status Information.............................................................................................................................40
RBYT Field .....................................................................................................................................................41
TXFDQ Pins and Transmit Data Attributes.....................................................................................................43
RXFDQ Pins and Receive Data Attributes......................................................................................................46
CLKS Field of MIIC Register and Frequency of MDC.....................................................................................54
4-1
6-1
Pause Order of Precedence Resolution Table..............................................................................................107
Operation in Each Controller State ...............................................................................................................137
10
Preliminary User’s Manual S15212EJ3V0UM
CHAPTER 1 OVERVIEW
The µPD98433 is a 10/100/1000 Mbps Ethernet controller with an eight-port on-chip Media Access Control (MAC)
function compliant with IEEE Standard 802.3 1998 Edition. Its main features are as follows.
1.1 Features
• 8-port 10/100/1000 Mbps on-chip MAC compliant with IEEE Standard 802.3 1998 Edition
• Interface with physical layer device can be selected from TBI, GMII, and MII
• On-chip 6 KB receive FIFO and 6 KB transmit FIFO for each port
• On-chip high-speed FIFO data bus of 128 bits × 125 MHz per transmit or receive
• On-chip data bus of 32 bits × 62.5 MHz as a CPU bus
• Full-duplex operation (for 10/100/1000 Mbps operation) or half-duplex operation (for 10/100 Mbps operation) is
possible
• Compatible with IEEE Standard 802.3 1998 Edition flow control
• Compatible with IEEE Standard 802.3 1998 Edition 8B10B PCS Encoder/Decoder
• Compatible with IEEE Standard 802.3 1998 Edition Chapter 37 Auto-Negotiation
• Filtering that responds to address types can be established
• Provides statistical information for supporting RMON/SNMP
• On-chip functions including VLAN frame detection function, low power function, and others
• JTAG support
• 0.25 µm CMOS process 2.5 V, 3.3 V dual system power supply
• Package: 756-pin plastic BGA
1.2 Ordering Information
Part No.
Package
µPD98433S9-K6
756-pin plastic BGA (C/D advanced type) (45 × 45)
11
Preliminary User’s Manual S15212EJ3V0UM
CHAPTER 1 OVERVIEW
1.3 Pin Configuration
µPD98433
756-pin plastic BGA
Top view
Index mark
067
195
100
34
32
226
33
31
315
344
427
454
531
556
30
28
627
650
29
27
715
736
26
24
25
23
22
20
21
19
µPD98433
756-pin plastic BGA
Bottom view
18
16
17
15
14
12
13
11
10
8
9
7
756
673
694
581
604
6
4
481
506
5
3
373
400
257
286
133
164
2
034
001
1
AN
AL
AJ
AG
AE
AC
AA
W
U
R
N
L
J
G
E
C
A
Index mark
AP
AM
AK
AH
AF
AD
AB
Y
V
T
P
M
K
H
F
D
B
12
Preliminary User’s Manual S15212EJ3V0UM
CHAPTER 1 OVERVIEW
(1/4)
Pin No.
1 (A1)
2 (B1)
3 (C1)
4 (D1)
5 (E1)
6 (F1)
7 (G1)
8 (H1)
Pin Name
GND
GND
GND
FC7
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
TXD24
51 (AP18) RXFDQ0
52 (AP19) RXFCK
53 (AP20) VDD
101 (A33) GND
102 (A32) GND
103 (A31) TXFBA3
104 (A30) TXFBA0
105 (A29) VDD
151 (Y2)
152 (AA2) TX_ER2
153 (AB2) COL2
54 (AP21) RXFD74
55 (AP22) RXFD80
56 (AP23) RXFD86
57 (AP24) RXFD92
58 (AP25) RXFD97
59 (AP26) VDDQ
60 (AP27) RXFD108
61 (AP28) RXFD114
62 (AP29) VDD
63 (AP30) TMS
64 (AP31) TEST4
65 (AP32) GND
66 (AP33) GND
67 (AP34) GND
154 (AC2) RXD26
155 (AD2) RXD23
156 (AE2) RXD20
157 (AF2) TX_ER3
158 (AG2) LINK3#
159 (AH2) RX_DV3
160 (AJ2) RXD34
161 (AK2) RXD32
162 (AL2) RXFD3
163 (AM2) GND
TXFD4
VDD
106 (A28) TXFD114
107 (A27) TXFD108
108 (A26) VDDQ
109 (A25) TXFD97
110 (A24) TXFD92
111 (A23) TXFD86
112 (A22) TXFD80
113 (A21) TXFD74
114 (A20) VDD
115 (A19) TXFCK
116 (A18) TXFDQ0
117 (A17) TXFD62
118 (A16) TXFD56
119 (A15) VDD
TXD06
EWRAP0
VDDQ
TXD10
TXD12
TXD15
EWRAP1
RX_CLK11
VDD
CRS1
HD4
HA2
HA8
9 (J1)
10 (K1)
11 (L1)
12 (M1)
13 (N1)
14 (P1)
15 (R1)
16 (T1)
17 (U1)
18 (V1)
19 (W1)
20 (Y1)
21 (AA1)
22 (AB1)
23 (AC1)
24 (AD1)
25 (AE1)
26 (AF1)
27 (AG1)
28 (AH1)
29 (AJ1)
30 (AK1)
31 (AL1)
32 (AM1)
33 (AN1)
34 (AP1)
35 (AP2)
36 (AP3)
37 (AP4)
38 (AP5)
39 (AP6)
40 (AP7)
41 (AP8)
42 (AP9)
164 (AN2) GND
165 (AN3) GND
166 (AN4) RXETH2
167 (AN5) RXFPT0
168 (AN6) RXFPT2
169 (AN7) RXFD6
170 (AN8) RXFD12
171 (AN9) RXFD17
172 (AN10) RXFD23
173 (AN11) RXFD29
174 (AN12) RXFD34
175 (AN13) RXFD40
176 (AN14) RXFD46
177 (AN15) RXFD51
178 (AN16) RXFD57
179 (AN17) RXFD63
180 (AN18) RXFDQ1
181 (AN19) RXFD64
182 (AN20) RXFD69
183 (AN21) RXFD75
184 (AN22) RXFD81
185 (AN23) RXFD87
186 (AN24) RXFD93
187 (AN25) RXFD98
188 (AN26) RXFD103
189 (AN27) RXFD109
190 (AN28) RXFD115
191 (AN29) RXFD120
192 (AN30) TCK
68 (AN34) GND
69 (AM34) GND
70 (AL34) RXD40
71 (AK34) RXD43
72 (AJ34) VDD
VDD
120 (A14) TXFD45
121 (A13) TXFD39
122 (A12) TXFD33
123 (A11) TXFD28
124 (A10) TXFD22
GTX_CLK2
RX_CLK20
RXD25
RXD22
CRS2
VDDQ
COL3
RXD37
VDD
RXFD4
RXETH7
GND
GND
GND
73 (AH34) COL4
74 (AG34) TX_ER4
75 (AF34) VDDQ
76 (AE34) CRS5
77 (AD34) RXD55
78 (AC34) RX_CLK50
79 (AB34) GTX_CLK5
80 (AA34) TXD54
81 (Y34)
82 (W34)
83 (V34)
84 (U34)
85 (T34)
86 (R34)
87 (P34)
88 (N34)
89 (M34)
90 (L34)
91 (K34)
92 (J34)
93 (H34)
94 (G34)
95 (F34)
96 (E34)
97 (D34)
98 (C34)
99 (B34)
125 (A9)
126 (A8)
127 (A7)
128 (A6)
129 (A5)
130 (A4)
131 (A3)
132 (A2)
133 (B2)
134 (C2)
135 (D2)
136 (E2)
137 (F2)
138 (G2)
139 (H2)
140 (J2)
141 (K2)
142 (L2)
143 (M2)
144 (N2)
145 (P2)
146 (R2)
147 (T2)
148 (U2)
149 (V2)
150 (W2)
VDDQ
TXFD11
TXFD5
VDD
TXFEN#
FC1
GND
GND
GND
GND
TXFD3
TXD01
TXD03
TXD07
TX_CLK0
RX_ER0
TXD11
TXD13
TXD16
TX_CLK1
RX_ER1
RXD14
HRW
VDD
HD12
HD18
HD24
HD30
VDD
RX_DV6
LINK6#
TXD67
TXD63
TXD60
VDDQ
LINK7#
TX_EN7
VDD
GND
GND
RXETH1
RXFEN#
VDD
RXFD5
RXFD11
VDDQ
43 (AP10) RXFD22
44 (AP11) RXFD28
45 (AP12) RXFD33
46 (AP13) RXFD39
47 (AP14) RXFD45
48 (AP15) VDD
193 (AN31) TDO
194 (AN32) GND
195 (AN33) GND
196 (AM33) GND
197 (AL33) CRS4
198 (AK33) RXD42
199 (AJ33) RXD46
200 (AH33) RX_CLK40
TXD72
TXD70
GND
HD5
HA3
HA9
49 (AP16) RXFD56
50 (AP17) RXFD62
GND
100 (A34) GND
13
Preliminary User’s Manual S15212EJ3V0UM
CHAPTER 1 OVERVIEW
(2/4)
Pin Name
Pin No.
Pin Name
Pin No.
251 (B8)
252 (B7)
253 (B6)
254 (B5)
255 (B4)
256 (B3)
257 (C3)
258 (D3)
259 (E3)
260 (F3)
261 (G3)
262 (H3)
263 (J3)
264 (K3)
265 (L3)
266 (M3)
267 (N3)
268 (P3)
269 (R3)
270 (T3)
271 (U3)
272 (V3)
273 (W3)
274 (Y3)
275 (AA3) TX_EN2
276 (AB3) LINK2#
277 (AC3) RXD27
278 (AD3) RXD24
279 (AE3) RXD21
280 (AF3) TX_EN3
281 (AG3) TX_CLK3
282 (AH3) RX_ER3
283 (AJ3) RXD35
284 (AK3) RXD33
285 (AL3) RXETH0
286 (AM3) GND
Pin Name
TXFD12
TXFD6
TXFPT2
TXFPT0
FC2
GND
GND
FC0
TXD02
TXD04
TX_EN0
LINK0#
RX_DV0
RXD04
TXD14
TXD17
LINK1#
RX_DV1
RXD13
HD0
Pin No.
Pin Name
Pin No.
201 (AG33) GTX_CLK4
202 (AF33) TXD44
203 (AE33) RXD50
204 (AD33) RXD54
205 (AC33) RX_CLK51
206 (AB33) EWRAP5
207 (AA33) TXD55
208 (Y33) HD6
209 (W33) HD11
210 (V33) HD17
211 (U33) HD23
212 (T33) HD29
213 (R33) RXD62
214 (P33) RXD67
215 (N33) COL6
216 (M33) TX_EN6
217 (L33) TXD64
218 (K33) TXD61
219 (J33) RXD77
220 (H33) COL7
221 (G33) TX_ER7
222 (F33) TXD75
223 (E33) TXD73
224 (D33) TXD71
225 (C33) GND
301 (AM18) RXFDQ2
302 (AM19) RXFD65
303 (AM20) RXFD70
304 (AM21) RXFD76
305 (AM22) RXFD82
306 (AM23) RXFD88
307 (AM24) RXFD94
308 (AM25) RXFD99
309 (AM26) RXFD104
310 (AM27) RXFD110
311 (AM28) RXFD116
312 (AM29) RXFD121
313 (AM30) TDI
351 (C25) TXFD99
352 (C24) TXFD94
353 (C23) TXFD88
354 (C22) TXFD82
355 (C21) TXFD76
356 (C20) TXFD70
357 (C19) TXFD65
358 (C18) TXFDQ2
359 (C17) TEST3
360 (C16) TXFD58
361 (C15) TXFD52
362 (C14) TXFD47
363 (C13) TXFD41
364 (C12) TXFD35
365 (C11) TXFD30
366 (C10) TXFD24
314 (AM31) TRST#
315 (AM32) GND
316 (AL32) RXFCKOUT
317 (AK32) RXD41
318 (AJ32) RXD45
319 (AH32) RX_CLK41
320 (AG32) EWRAP4
321 (AF32) TXD45
322 (AE32) RXD51
323 (AD32) RXD53
324 (AC32) RX_ER5
325 (AB32) TX_CLK5
326 (AA32) TXD56
327 (Y32) TXD53
328 (W32) HD10
367 (C9)
368 (C8)
369 (C7)
370 (C6)
371 (C5)
372 (C4)
373 (D4)
374 (E4)
375 (F4)
376 (G4)
377 (H4)
378 (J4)
379 (K4)
380 (L4)
381 (M4)
382 (N4)
383 (P4)
384 (R4)
385 (T4)
386 (U4)
387 (V4)
388 (W4)
389 (Y4)
TXFD18
TXFD13
TXFD7
TXFD0
TXFPT1
FC3
HACK#
HA4
HA10
VDD
FC4
TXD23
TXD05
TX_ER0
COL0
RXD07
RXD03
VDD
TX_EN1
GND
RXD17
RXD12
HD1
226 (B33) GND
227 (B32) GND
228 (B31) TXFBA4
229 (B30) TXFBA1
230 (B29) TXFD120
231 (B28) TXFD115
232 (B27) TXFD109
233 (B26) TXFD103
234 (B25) TXFD98
235 (B24) TXFD93
236 (B23) TXFD87
237 (B22) TXFD81
238 (B21) TXFD75
239 (B20) TXFD69
240 (B19) TXFD64
241 (B18) TXFDQ1
242 (B17) TXFD63
243 (B16) TXFD57
244 (B15) TXFD51
245 (B14) TXFD46
246 (B13) TXFD40
247 (B12) TXFD34
248 (B11) TXFD29
249 (B10) TXFD23
329 (V32) HD16
330 (U32) HD22
331 (T32) HD28
332 (R32) RXD61
333 (P32) RXD66
334 (N32) RX_CLK60
335 (M32) TX_ER6
336 (L32) TXD65
337 (K32) CRS7
338 (J32) RXD76
339 (H32) RX_CLK70
340 (G32) GTX_CLK7
341 (F32) TXD76
342 (E32) TXD74
343 (D32) TXFBA7
344 (C32) GND
345 (C31) TXFBA6
346 (C30) TXFBA2
347 (C29) TXFD121
348 (C28) TXFD116
349 (C27) TXFD110
350 (C26) TXFD104
HCLK
HA5
HCS#
TXD22
287 (AM4) RXETH3
288 (AM5) RXFPT1
289 (AM6) RXFD0
290 (AM7) RXFD7
291 (AM8) RXFD13
292 (AM9) RXFD18
293 (AM10) RXFD24
294 (AM11) RXFD30
295 (AM12) RXFD35
296 (AM13) RXFD41
297 (AM14) RXFD47
298 (AM15) RXFD52
299 (AM16) RXFD58
300 (AM17) RXABT
390 (AA4) TXD27
391 (AB4) GND
392 (AC4) RX_DV2
393 (AD4) VDD
394 (AE4) TXD34
395 (AF4) TXD37
396 (AG4) VDD
397 (AH4) RX_CLK31
398 (AJ4) RXD36
399 (AK4) RXETH4
400 (AL4) VDD
250 (B9)
TXFD17
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Preliminary User’s Manual S15212EJ3V0UM
CHAPTER 1 OVERVIEW
(3/4)
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
401 (AL5) RXETH5
402 (AL6) RXFD1
403 (AL7) RXFD8
404 (AL8) RXFD14
405 (AL9) RXFD19
406 (AL10) RXFD25
407 (AL11) VDD
408 (AL12) RXFD36
409 (AL13) RXFD42
410 (AL14) RXFD48
411 (AL15) RXFD53
412 (AL16) RXFD59
413 (AL17) SKIP
414 (AL18) RXFDQ3
415 (AL19) RXFD66
416 (AL20) RXFD71
417 (AL21) RXFD77
418 (AL22) RXFD83
419 (AL23) RXFD89
420 (AL24) VDD
421 (AL25) RXFD100
422 (AL26) RXFD105
423 (AL27) RXFD111
424 (AL28) RXFD117
425 (AL29) RXFD122
426 (AL30) RXFD125
427 (AL31) VDD
428 (AK31) TEST5
429 (AJ31) RXD44
430 (AH31) RX_ER4
431 (AG31) VDD
432 (AF31) TXD46
433 (AE31) RXD52
434 (AD31) VDD
435 (AC31) RX_DV5
436 (AB31) GND
437 (AA31) TXD57
438 (Y31) TXD52
439 (W31) HD9
451 (G31) VDD
501 (AE5) TXD33
502 (AF5) TXD36
503 (AG5) EWRAP3
504 (AH5) RX_CLK30
505 (AJ5) CRS3
551 (K30) RXD71
552 (J30) RXD74
553 (H30) RX_ER7
554 (G30) EWRAP7
555 (F30) TXFD127
556 (E30) TXFD126
557 (E29) TXFD123
558 (E28) TXFD118
559 (E27) TXFD112
560 (E26) TXFD106
561 (E25) TXFD101
562 (E24) TXFD95
563 (E23) TXFD90
564 (E22) TXFD84
565 (E21) TXFD78
566 (E20) TXFD72
567 (E19) TXFD67
568 (E18) TXFDQ4
569 (E17) TEST0
570 (E16) TXFD60
571 (E15) TXFD54
572 (E14) TXFD49
573 (E13) TXFD43
574 (E12) TXFD37
575 (E11) TXFD31
576 (E10) TXFD26
452 (F31) TXD77
453 (E31) TXFBA5
454 (D31) VDD
455 (D30) TXFD125
456 (D29) TXFD122
457 (D28) TXFD117
458 (D27) TXFD111
459 (D26) TXFD105
460 (D25) TXFD100
461 (D24) VDD
462 (D23) TXFD89
463 (D22) TXFD83
464 (D21) TXFD77
465 (D20) TXFD71
466 (D19) TXFD66
467 (D18) TXFDQ3
468 (D17) TEST1
469 (D16) TXFD59
470 (D15) TXFD53
471 (D14) TXFD48
472 (D13) TXFD42
473 (D12) TXFD36
474 (D11) VDD
506 (AK5) RXETH6
507 (AK6) RXFD2
508 (AK7) RXFD9
509 (AK8) RXFD15
510 (AK9) RXFD20
511 (AK10) RXFD26
512 (AK11) RXFD31
513 (AK12) RXFD37
514 (AK13) RXFD43
515 (AK14) RXFD49
516 (AK15) RXFD54
517 (AK16) RXFD60
518 (AK17) PASS
519 (AK18) RXFDQ4
520 (AK19) RXFD67
521 (AK20) RXFD72
522 (AK21) RXFD78
523 (AK22) RXFD84
524 (AK23) RXFD90
525 (AK24) RXFD95
526 (AK25) RXFD101
527 (AK26) RXFD106
528 (AK27) RXFD112
529 (AK28) RXFD118
530 (AK29) RXFD123
531 (AK30) RXFD126
532 (AJ30) RXFD127
533 (AH30) RX_DV4
534 (AG30) TX_CLK4
535 (AF30) TXD47
536 (AE30) TXD42
537 (AD30) TXD41
538 (AC30) RXD57
539 (AB30) LINK5#
540 (AA30) TX_EN5
541 (Y30) TXD51
542 (W30) HD8
475 (D10) TXFD25
476 (D9)
477 (D8)
478 (D7)
479 (D6)
480 (D5)
481 (E5)
482 (F5)
483 (G5)
484 (H5)
485 (J5)
486 (K5)
487 (L5)
488 (M5)
489 (N5)
490 (P5)
491 (R5)
492 (T5)
493 (U5)
494 (V5)
495 (W5)
496 (Y5)
TXFD19
TXFD14
TXFD8
TXFD1
FC5
577 (E9)
578 (E8)
579 (E7)
580 (E6)
581 (F6)
582 (G6)
583 (H6)
584 (J6)
585 (K6)
586 (L6)
587 (M6)
588 (N6)
589 (P6)
590 (R6)
591 (T6)
592 (U6)
593 (V6)
594 (W6)
595 (Y6)
TXFD20
TXFD15
TXFD9
TXFD2
MDC
TXD00
RX_CLK01
RXD05
RXD01
CRS0
GTX_CLK1
RX_CLK10
RXD15
RXD10
HD3
FC6
MDIO
GTX_CLK0
RX_CLK00
RXD06
RXD02
RXD00
TX_ER1
COL1
RXD16
RXD11
HD2
440 (V31) HD15
441 (U31) HD21
442 (T31) HD27
443 (R31) RXD60
444 (P31) RXD65
445 (N31) GND
446 (M31) GTX_CLK6
447 (L31) GTX_REF_CLK 497 (AA5) TXD26
HA1
HA7
RESET#
TXD20
HA0
HA6
INT#
TXD21
543 (V30) HD14
544 (U30) HD20
545 (T30) HD26
546 (R30) CRS6
547 (P30) RXD64
548 (N30) RX_CLK61
549 (M30) EWRAP6
550 (L30) TXD66
596 (AA6) TXD25
597 (AB6) EWRAP2
598 (AC6) RX_CLK21
599 (AD6) TXD30
600 (AE6) TXD32
448 (K31) RXD72
449 (J31) RXD75
450 (H31) RX_CLK71
498 (AB5) TX_CLK2
499 (AC5) RX_ER2
500 (AD5) TXD31
15
Preliminary User’s Manual S15212EJ3V0UM
CHAPTER 1 OVERVIEW
(4/4)
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
601 (AF6) TXD35
602 (AG6) GTX_CLK3
603 (AH6) RXD31
604 (AJ6) RXD30
605 (AJ7) RXFD10
606 (AJ8) RXFD16
607 (AJ9) RXFD21
608 (AJ10) RXFD27
609 (AJ11) RXFD32
610 (AJ12) RXFD38
611 (AJ13) RXFD44
612 (AJ14) RXFD50
613 (AJ15) RXFD55
614 (AJ16) RXFD61
615 (AJ17) RXFA
616 (AJ18) RXPAR
617 (AJ19) RXFD68
618 (AJ20) RXFD73
619 (AJ21) RXFD79
620 (AJ22) RXFD85
621 (AJ23) RXFD91
622 (AJ24) RXFD96
623 (AJ25) RXFD102
624 (AJ26) RXFD107
625 (AJ27) RXFD113
626 (AJ28) RXFD119
627 (AJ29) RXFD124
628 (AH29) RXD47
629 (AG29) LINK4#
630 (AF29) TX_EN4
631 (AE29) TXD43
632 (AD29) TXD40
633 (AC29) RXD56
634 (AB29) COL5
651 (F28) TXFD119
652 (F27) TXFD113
653 (F26) TXFD107
654 (F25) TXFD102
655 (F24) TXFD96
656 (F23) TXFD91
657 (F22) TXFD85
658 (F21) TXFD79
659 (F20) TXFD73
660 (F19) TXFD68
661 (F18) TXPAR
662 (F17) TEST2
663 (F16) TXFD61
664 (F15) TXFD55
665 (F14) TXFD50
666 (F13) TXFD44
667 (F12) TXFD38
668 (F11) TXFD32
669 (F10) TXFD27
701 (AH14) VDDQ
702 (AH15) GND
703 (AH16) VDD
704 (AH17) GND
705 (AH18) GND
706 (AH19) VDD
707 (AH20) GND
708 (AH21) VDDQ
709 (AH22) GND
710 (AH23) VDD
711 (AH24) GND
712 (AH25) VDDQ
713 (AH26) GND
714 (AH27) VDD
715 (AH28) GND
716 (AG28) VDD
717 (AF28) GND
718 (AE28) VDDQ
719 (AD28) GND
720 (AC28) VDD
721 (AB28) GND
722 (AA28) VDDQ
723 (Y28) GND
724 (W28) VDD
725 (V28) VDDQ
726 (U28) GND
727 (T28) VDD
728 (R28) GND
729 (P28) VDDQ
730 (N28) GND
731 (M28) VDD
732 (L28) GND
733 (K28) VDDQ
734 (J28) GND
735 (H28) VDD
736 (G28) GND
737 (G27) VDD
738 (G26) GND
739 (G25) VDDQ
740 (G24) GND
741 (G23) VDD
742 (G22) GND
743 (G21) VDDQ
744 (G20) GND
745 (G19) VDD
746 (G18) GND
747 (G17) GND
748 (G16) VDD
749 (G15) GND
750 (G14) VDDQ
751 (G13) GND
752 (G12) VDD
753 (G11) GND
754 (G10) VDDQ
755 (G9)
756 (G8)
GND
VDD
670 (F9)
671 (F8)
672 (F7)
673 (G7)
674 (H7)
675 (J7)
676 (K7)
677 (L7)
678 (M7)
679 (N7)
680 (P7)
681 (R7)
682 (T7)
683 (U7)
684 (V7)
685 (W7)
686 (Y7)
TXFD21
TXFD16
TXFD10
GND
VDD
GND
VDDQ
GND
VDD
GND
VDDQ
GND
VDD
GND
VDDQ
VDD
GND
635 (AA29) TX_ER5
636 (Y29) TXD50
637 (W29) HD7
638 (V29) HD13
639 (U29) HD19
687 (AA7) VDDQ
688 (AB7) GND
689 (AC7) VDD
690 (AD7) GND
691 (AE7) VDDQ
692 (AF7) GND
693 (AG7) VDD
694 (AH7) GND
695 (AH8) VDD
696 (AH9) GND
697 (AH10) VDDQ
698 (AH11) GND
699 (AH12) VDD
700 (AH13) GND
640 (T29) HD25
641 (R29) HD31
642 (P29) RXD63
643 (N29) RX_ER6
644 (M29) TX_CLK6
645 (L29) TXD62
646 (K29) RXD70
647 (J29) RXD73
648 (H29) RX_DV7
649 (G29) TX_CLK7
650 (F29) TXFD124
16
Preliminary User’s Manual S15212EJ3V0UM
CHAPTER 1 OVERVIEW
1.4 Internal Block Diagram
TBI
GMII
MII
PORT #7
PORT #6
×8
PORT #5
PORT #4
PORT #3
PORT #2
PORT #1
PORT #0
FIFO data
Tx FIFO
Rx FIFO
FIFO
common
10M/100M/1G
MAC
data
bus
interface
bus
Register set/statistics counter
MII
serial
CPU bus
interface
CPU
bus
management
MII management interface
TEST
port
JTAG
1.5 Sample System Configuration
Control Module
CPU
Memory
Line Interface Module
(LIM)
Address Search
10/100/1000M
Multi-MAC
µ
PD98421
Optical
Module
Switch
Chip
10/100/1000M
Multi-PHY
Forwarding
Engine
µ
PD98433
Line Interface Module
(LIM)
Address Search
10/100M
Multi-MAC
µ
PD98421
10/100M
Multi-PHY
Switch
Chip
Optical
Module
Forwarding
Engine
LIM
PD98431
µ
Switching
Module
17
Preliminary User’s Manual S15212EJ3V0UM
CHAPTER 2 PIN FUNCTIONS
(1) Register interface
Pin Name
HCS#
Pin No.
I/O
Function
388
147
Input
Chip select
When this signal is low level, registers within the chip can be accessed.
HRW
Input
Host read/write
This is used when the host system accesses the register bus. A read access
is executed when high level is input to this pin; a write access is executed
when a low level is input.
HA[10:0]
273, 150, 19,
593, 494, 387,
272, 149, 18,
592, 493
Input
Register address
When accessing a register within the µPD984330, addresses needed to
select the port and register for access are given to HA[10:0]. The µPD98433
has a 32-bit wide register for each port. HA[10:8] specifies the port and
HA[7:0] specifies the register address.
The relationship between HA[10:8] and port numbers is as follows.
Port 0 → HA[10:8] = 000B
Port 1 → HA[10:8] = 001B
Port 2 → HA[10:8] = 010B
Port 3 → HA[10:8] = 011B
Port 4 → HA[10:8] = 100B
Port 5 → HA[10:8] = 101B
Port 6 → HA[10:8] = 110B
Port 7 → HA[10:8] = 111B
HD[31:0]
641, 85, 212, 331,
442, 545, 640, 84,
211, 330, 441, 544,
639, 83, 210, 329,
440, 543, 638, 82,
209, 328, 439, 542,
637, 208, 148, 17,
591, 492, 385, 270
I/O
Register data
3 states
This is a bidirectional data bus for accessing on-chip registers of the
µPD98433.
INT#
495
594
271
386
Output
Open-
drain
Interrupt signal
This is an interrupt request signal. It becomes low level when an interrupt
occurs. When an interrupt has occurred, this maintains low level until every
interrupt status is cleared.
RESET#
HACK#
HCLK
Input
Hardware reset
This is an asynchronous reset signal. Immediately after a hardware reset, all
registers are set to default values and every FIFO and every counter is
cleared.
Output
Register data acknowledge
3 states
On a register read operation, this shows that data at HD[31:0] is valid. When
this signal is low level, data that was read exists at HD[31:0].
On a register write operation, this shows that the write operation completed.
Input
Register interface clock
This is synchronization clock input for register access. Its maximum
frequency is 62.5 MHz.
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Preliminary User’s Manual S15212EJ3V0UM
CHAPTER 2 PIN FUNCTIONS
(2) FIFO interface
(1/3)
Pin Name
Pin No.
I/O
Function
RXFCK
52
Input
Receive FIFO bus clock
This is the reference clock for RXFCKOUT output. Its maximum frequency is
125 MHz. Give it the same frequency as TXFCK.
RXFCKOUT
TXFCK
316
115
Output
Input
Receive FIFO bus clock output
A copy of RXFCK is output. The receive FIFO bus performs receive
operations in synchronization with RXFCKOUT.
Transmit FIFO bus clock
The FIFO bus performs transmit operations in synchronization with TXFCK.
The maximum frequency is 125 MHz. Give this the same frequency as
RXFCK.
RXFEN#
TXFEN#
38
Input
Input
FIFO bus receive enable
When this signal becomes low level, the receive FIFO bus interface is
enabled and it becomes possible to read from the receive FIFO.
129
FIFO bus transmit enable
When this signal becomes low level, the transmit FIFO bus interface is
enabled and it becomes possible to write to the transmit FIFO.
RXFPT[2:0]
168, 288, 167
Output
Receive port number
3 states
On a receive FIFO read access, this shows the port number where receive
data is output.
The relationship between RXFPT[2:0] and port numbers is shown below.
Port 0 → RXFPT[2:0] = 000B
Port 1 → RXFPT[2:0] = 001B
Port 2 → RXFPT[2:0] = 010B
Port 3 → RXFPT[2:0] = 011B
Port 4 → RXFPT[2:0] = 100B
Port 5 → RXFPT[2:0] = 101B
Port 6 → RXFPT[2:0] = 110B
Port 7 → RXFPT[2:0] = 111B
TXFPT[2:0]
253, 371, 254
Input
Transmit port number
On a transmit FIFO write access, this shows the port number of the transmit
FIFO to which to write transmit data.
The relationship between TXFPT[2:0] and port numbers is shown below.
Port 0 → TXFPT[2:0] = 000B
Port 1 → TXFPT[2:0] = 001B
Port 2 → TXFPT[2:0] = 010B
Port 3 → TXFPT[2:0] = 011B
Port 4 → TXFPT[2:0] = 100B
Port 5 → TXFPT[2:0] = 101B
Port 6 → TXFPT[2:0] = 110B
Port 7 → TXFPT[2:0] = 111B
19
Preliminary User’s Manual S15212EJ3V0UM
CHAPTER 2 PIN FUNCTIONS
(2/3)
Pin Name
Pin No.
I/O
Function
TXFD[127:0]
555, 556, 455, 650, 557, 456, 347,
230, 651, 558, 457, 348, 231, 106,
652, 559, 458, 349, 232, 107, 653,
560, 459, 350, 233, 654, 561, 460,
351, 234, 109, 655, 562, 352, 235,
110, 656, 563, 462, 353, 236, 111,
657, 564, 463, 354, 237, 112, 658,
565, 464, 355, 238, 113, 659, 566,
465, 356, 239, 660, 567, 466, 357,
240, 242, 117, 663, 570, 469, 360,
243, 118, 664, 571, 470, 361, 244,
665, 572, 471, 362, 245, 120, 666,
573, 472, 363, 246, 121, 667, 574,
473, 364, 247, 122, 668, 575, 365,
248, 123, 669, 576, 475, 366, 249,
124, 670, 577, 476, 367, 250, 671,
578, 477, 368, 251, 126, 672, 579,
478, 369, 252, 127, 5, 135, 580,
479, 370
Input
Transmit FIFO data bus
This provides the 128-bit wide data bus of the transmit FIFO
bus interface.
RXFD[127:0]
532, 531, 426 ,627, 530, 425, 312,
191, 626, 529, 424, 311, 190, 61,
625, 528, 423, 310, 189, 60, 624,
527, 422, 309, 188, 623, 526, 421,
308, 187, 58, 622, 525, 307, 186,
57, 621, 524, 419, 306, 185, 56,
620, 523, 418, 305, 184, 55, 619,
522, 417, 304, 183, 54, 618, 521,
416, 303, 182, 617, 520, 415, 302,
181, 179, 50, 614, 517, 412, 299,
178, 49, 613, 516, 411, 298, 177,
612, 515, 410, 297, 176, 47, 611,
514, 409, 296, 175, 46, 610, 513,
408, 295, 174, 45, 609, 512, 294,
173, 44, 608, 511, 406, 293, 172,
43, 607, 510, 405, 292, 171, 606,
509, 404, 291, 170, 41, 605, 508,
403, 290, 169, 40, 30, 162, 507,
402, 289
Output
Receive FIFO data bus
3 states
This provides the 128-bit wide data bus of the receive FIFO
bus interface.
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CHAPTER 2 PIN FUNCTIONS
(3/3)
Pin Name
Pin No.
I/O
Function
RXFDQ[4:0]
519, 414, 301,
180, 51
Output
Receive data attributes
3 states
This shows the attributes of receive data that is on the FIFO bus. On a read
access of the receive FIFO, it outputs the attributes of receive data that was
output at RXFD[127:0]. See Table 3-4 for the output patterns of RXFDQ[4:0]
TXFDQ[4:0]
TXFBA[7:0]
568, 467, 358,
241, 116
Input
Transmit data attributes
This shows the attributes of transmit data that is on the FIFO bus. On a write
access to the transmit FIFO, it inputs the attributes of transmit data that was
placed at TXFD[127:0]. See Table 3-3 for the input patterns of TXFDQ[4:0].
343, 345, 453,
228, 103, 346,
229, 104
Output
Transmit FIFO buffer available
3 states
When this signal is high level, it shows that the space within the transmit
FIFO for writing transmit data is empty. This signal becomes a low level if the
amount of data in the transmit FIFO exceeds the value set in the TFWMH
field of the TFIC1 register.
A TXFBA signal is established for each port and TXFBA[n] indicates the
TXFBA signal of port n.
Output is asynchronous.
RXFA
615
Output
Receive frame available
3 states
When this signal is high level, it shows that at least 1 packet of a receive data
stream that can be transferred to the host system has been prepared and
placed in the port shown by RXFPT or that data stored in the receive FIFO
exceeds the threshold value set in the THRX field of the RFIC3 register.
PASS
SKIP
518
413
Input
Input
Input
Receive frame pass
On a read access from the receive FIFO, this is the signal that is input to
begin the transfer of receive data of the port that currently is on the FIFO bus.
Receive frame skip
On a read access from the receive FIFO, this signal is input to skip the port
that currently is on the FIFO bus and read from the next port.
FC[7:0]
4, 481, 480, 374,
Flow control frame generation
372, 255, 130, 258
This signal designates the transmission of flow control packets by port.
Besides using register settings for automatically generating them, flow control
packet transmission can be designated directly using this pin.
RXPAR
616
661
300
Output
Receive parity bit
3 states
This shows the parity of 128-bit receive data. Even or odd parity can be
selected according to the register setting.
TXPAR
Input
Input
Transmit parity bit
This shows the parity of 128-bit transmit data. Even or odd parity can be
selected according to the register setting.
RXABT
Receive abort
This signal designates removing receive FIFO data from within the receive
FIFO before reading from the receive FIFO interface.
RXETH[7:0]
31, 506, 401, 399,
287, 166, 37, 285
Output
Receive FIFO status display
For each port, this signal is asserted when receive FIFO data exceeds a
threshold (RXETH field of RFIC3 register).
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CHAPTER 2 PIN FUNCTIONS
(3) Physical layer interface
(1/5)
Pin Name
Pin No.
I/O
Function
TX_CLK[7:0]
649, 644, 325,
534, 281, 498,
144, 139
Input
MII transmit clock
This transmit clock input is needed in order to output transmit data to the
PHY device connected to each port. Each of TXD7[3:0] to TXD0[3:0], which
is the transmit data from each port, and TX_EN[7:0], which shows that
transmit data at TXD is valid, and TX_ER[7:0], which shows that an error
occurred in transmit data at TXD, are output by port in synchronization with
this clock.
In MII mode, input a 2.5 MHz clock on 10 Mbps operation and a 25 MHz
clock on 100 Mbps operation. In this mode, TXD, TX_EN, and TX_ER are
output in synchronization with the rise of TX_CLK.
In GMII or TBI mode, fix TX_CLK to high level or low level.
For unused ports, fix TX_CLK to high level or low level.
GTX_CLK[7:0]
340, 446, 79, 201,
602, 21, 587, 483
Output
Transmit clock for 1000M
This transmit clock is output with the transmit data to the PHY device
connected to each port. Each of TXD7[3:0] to TXD0[3:0], which is the
transmit data from each port, and TX_EN[7:0], which shows that transmit
data at TXD is valid, and TX_ER[7:0], which shows that an error occurred in
transmit data at TXD, are output by port in synchronization with this clock.
In GMII mode, this functions as GTX_CLK. In TBI mode, it functions as
PMA_TX_CLK.
In MII mode, a clock signal output from this pin.
In Low Power mode, no clock signal is output from this pin.
GTX_REF_CLK 447
Input
Transmit reference clock
This reference clock is used for the internal operation and GTX_CLK[7:0]
production. Always give the clock that the frequency is 125 MHz.
TXD0[7:0]
TXD1[7:0]
TXD2[7:0]
138, 7, 375, 260,
Output
Transmit data (Port 0)
137, 259, 136, 582
This is transmit data output for the PHY device of port 0.
In MII mode, the lower 4 bits are used to output a nibble (4 bits) of transmit
data in synchronization with the rising edge of TX_CLK0.
In GMII or TBI mode, this outputs 8-bit wide transmit data in synchronization
with the rising edge of GTX_CLK0.
266, 143, 12, 265,
142, 11, 141, 10
Output
Output
Transmit data (Port 1)
This is transmit data output for the PHY device of port 1.
In MII mode, the lower 4 bits are used to output a nibble (4 bits) of transmit
data in synchronization with the rising edge of TX_CLK1.
In GMII or TBI mode, this outputs 8-bit wide transmit data in synchronization
with the rising edge of GTX_CLK1.
390, 497, 596,
151, 274, 389,
496, 595
Transmit data (Port 2)
This is transmit data output for the PHY device of port 2.
In MII mode, the lower 4 bits are used to output a nibble (4 bits) of transmit
data in synchronization with the rising edge of TX_CLK2.
In GMII or TBI mode, this outputs 8-bit wide transmit data in synchronization
with the rising edge of GTX_CLK2.
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Pin Name
TXD3[7:0]
Pin No.
I/O
Function
395, 502, 601,
394, 501, 600,
500, 599
Output
Output
Output
Output
Output
Output
Transmit data (Port 3)
This is transmit data output for the PHY device of port 3.
In MII mode, the lower 4 bits are used to output a nibble (4 bits) of transmit
data in synchronization with the rising edge of TX_CLK3.
In GMII or TBI mode, this outputs 8-bit wide transmit data in synchronization
with the rising edge of GTX_CLK3.
TXD4[7:0]
TXD5[7:0]
TXD6[7:0]
TXD7[7:0]
TX_EN[7:0]
535, 432, 321,
202, 631, 536,
537, 632
Transmit data (Port 4)
This is transmit data output for the PHY device of port 4.
In MII mode, the lower 4 bits are used to output a nibble (4 bits) of transmit
data in synchronization with the rising edge of TX_CLK4.
In GMII or TBI mode, this outputs 8-bit wide transmit data in synchronization
with the rising edge of GTX_CLK4.
437, 326, 207, 80,
327, 438, 541, 636
Transmit data (Port 5)
This is transmit data output for the PHY device of port 5.
In MII mode, the lower 4 bits are used to output a nibble (4 bits) of transmit
data in synchronization with the rising edge of TX_CLK5.
In GMII or TBI mode, this outputs 8-bit wide transmit data in synchronization
with the rising edge of GTX_CLK5.
89, 550, 336, 217,
90, 645, 218, 91
Transmit data (Port 6)
This is transmit data output for the PHY device of port 6.
In MII mode, the lower 4 bits are used to output a nibble (4 bits) of transmit
data in synchronization with the rising edge of TX_CLK6.
In GMII or TBI mode, this outputs 8-bit wide transmit data in synchronization
with the rising edge of GTX_CLK6.
452, 341, 222,
342, 223, 96,
224, 97
Transmit data (Port 7)
This is transmit data output for the PHY device of port 7.
In MII mode, the lower 4 bits are used to output a nibble (4 bits) of transmit
data in synchronization with the rising edge of TX_CLK7.
In GMII or TBI mode, this outputs 8-bit wide transmit data in synchronization
with the rising edge of GTX_CLK7.
94, 216, 540, 630,
280, 275, 381, 261
Transmit enable/transmit data bit 8
The function of this signal differs depending on the operation mode.
(1) In GMII or MII mode
This signal shows whether or not transmit data (TXD) is valid for each
port. It is high level from the first data showing the preamble until the last
data of a transmit frame is output.
(2) In TBI mode
This functions as bit 8 of the transmit data of each port (TXD[8]).
TX_ER[7:0]
221, 335, 635, 74,
157, 152, 488, 376
Output
MII transmit error/transmit data bit 9
The function of this signal differs depending on the operation mode.
(1) In GMII or MII mode
This signal shows that an error occurred in transmit data at TXD.
(2) In TBI mode
This functions as bit 9 of the transmit data of each port (TXD[9]).
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Pin Name
Pin No.
I/O
Function
RX_CLK[7:0]0
339, 334, 78, 200,
504, 22, 588, 484
Input
Receive clock
This is receive clock input given by a PHY device. Each of RXD7[7:0] to
RXD0[7:0], which is the receive data from each port, and RX_DV[7:0], which
shows that receive data at RXD is valid, and RX_ER[7:0], which shows that
an error occurred in receive data at RXD, are input by port in synchronization
with this clock.
In TBI mode, this is a 62.5 MHz clock input pin. In this case, input
RX_CLKn0 and RX_CLKn1 in an inverse phase relation.
In GMII or MII mode, input a 125 MHz clock on 1000 Mbps operation, a 25
MHz clock on 100 Mbps operation, and a 2.5 MHz clock on 10 Mbps
operation.
For unused ports, fix RX_CLKn0 to high level or low level.
RX_CLK[7:0]1
RXD0[7:0]
450, 548, 205,
319, 397, 598,
14, 583
Input
Input
Receive clock
To input a 62.5 MHz clock in TBI mode, input the clock in inverse phase to
RX_CLK[7:0]0.
378, 485, 584,
264, 379, 486,
585, 487
Receive data (Port 0)
This is receive data input from the PHY device of port 0.
In MII mode, the lower 4 bits are used to input a nibble (4 bits) of receive data
on the rising edge of RX_CLK00.
In GMII mode, this inputs 8-bit wide receive data on the rising edge of
RX_CLK00.
In TBI mode, it inputs 8-bit wide receive data on the rising edges of RXCLK00
and RX_CLK01.
RXD1[7:0]
RXD2[7:0]
RXD3[7:0]
383, 490, 589,
146, 269, 384,
491, 590
Input
Input
Input
Receive data (Port 1)
This is receive data input from the PHY device of port 1.
In MII mode, the lower 4 bits are used to input a nibble (4 bits) of receive data
on the rising edge of RX_CLK10.
In GMII mode, this inputs 8-bit wide receive data on the rising edge of
RX_CLK10.
In TBI mode, it inputs 8-bit wide receive data on the rising edges of
RX_CLK10 and RX_CLK11.
277, 154, 23, 278,
155, 24, 279, 156
Receive data (Port 2)
This is receive data input from the PHY device of port 2.
In MII mode, the lower 4 bits are used to input a nibble (4 bits) of receive data
on the rising edge of RX_CLK20.
In GMII mode, this inputs 8-bit wide receive data on the rising edge of
RX_CLK20.
In TBI mode, it inputs 8-bit wide receive data on the rising edges of
RX_CLK20 and RX_CLK21.
28, 398, 283, 160,
284, 161, 603, 604
Receive data (Port 3)
This is receive data input from the PHY device of port 3.
In MII mode, the lower 4 bits are used to input a nibble (4 bits) of receive data
on the rising edge of RX_CLK30.
In GMII mode, this inputs 8-bit wide receive data on the rising edge of
RX_CLK30.
In TBI mode, it inputs 8-bit wide receive data on the rising edges of
RX_CLK30 and RX_CLK31.
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CHAPTER 2 PIN FUNCTIONS
(4/5)
Pin Name
RXD4[7:0]
Pin No.
I/O
Function
628, 199, 318,
429, 71, 198,
317, 70
Input
Receive data (Port 4)
This is receive data input from the PHY device of port 4.
In MII mode, the lower 4 bits are used to input a nibble (4 bits) of receive data
on the rising edge of RX_CLK40.
In GMII mode, this inputs 8-bit wide receive data on the rising edge of
RX_CLK40.
In TBI mode, it inputs 8-bit wide receive data on the rising edges of
RX_CLK40 and RX_CLK41.
RXD5[7:0]
RXD6[7:0]
RXD7[7:0]
RX_DV[7:0]
538, 633, 77, 204,
323, 433, 322, 203
Input
Input
Input
Input
Receive data (Port 5)
This is receive data input from the PHY device of port 5.
In MII mode, the lower 4 bits are used to input a nibble (4 bits) of receive data
on the rising edge of RX_CLK50.
In GMII mode, this inputs 8-bit wide receive data on the rising edge of
RX_CLK50.
In TBI mode, it inputs 8-bit wide receive data on the rising edges of
RX_CLK50 and RX_CLK51.
214, 333, 444,
547, 642, 213,
332, 443
Receive data (Port 6)
This is receive data input from the PHY device of port 6.
In MII mode, the lower 4 bits are used to input a nibble (4 bits) of receive data
on the rising edge of RX_CLK60.
In GMII mode, this inputs 8-bit wide receive data on the rising edge of
RX_CLK60.
In TBI mode, it inputs 8-bit wide receive data on the rising edges of
RX_CLK60 and RX_CLK61.
219, 338, 449,
552, 647, 448,
551, 646
Receive data (Port 7)
This is receive data input from the PHY device of port 7.
In MII mode, the lower 4 bits are used to input a nibble (4 bits) of receive data
on the rising edge of RX_CLK70.
In GMII mode, this inputs 8-bit wide receive data on the rising edge of
RX_CLK70.
In TBI mode, it inputs 8-bit wide receive data on the rising edges of
RX_CLK70 and RX_CLK71.
648, 87, 435, 533,
159, 392, 268, 263
Receive data valid/receive data bit 8
The function of this signal differs depending on the operation mode.
(1) In GMII or MII mode
When this signal is high level, it shows that data at RXD is valid for each
port.
(2) In TBI mode
This functions as bit 8 of the receive data of each port (RXD[8]).
For unused ports, fix RX_DV to low level.
RX_ER[7:0]
553, 643, 324,
430, 282, 499,
145, 140
Input
Receive error/receive data bit 9
The function of this signal differs depending on the operation mode.
(1) In GMII or MII mode
This is an input signal for detecting errors that occurred on a PHY device
while receiving at each port.
(2) In TBI mode
This functions as bit 9 of the receive data of each port (RXD[9]).
For unused ports, fix RX_ER to low level.
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Pin Name
CRS[7:0]
Pin No.
I/O
Function
337, 546, 76, 197,
505, 25, 16, 586
Input
Carrier sense/SIGDET
The function of this signal differs depending on the operation mode.
(1) In GMII or MII mode
This is the carrier sense signal input from the PHY device connected to
each port.
(2) In TBI mode
This functions as SIGDET of each port.
For unused ports, fix CRS to low level.
COL[7:0]
220, 215, 634, 73,
27, 153, 489, 377
Input
Collision
This is collision signal input detected by the PHY device connected to each
port.
For unused ports, fix COL to low level.
This is not used in TBI mode.
MDC
581
482
Output
MII management clock
This is the MII serial management data transfer clock.
MDIO
I/O
MII management data
3 states
This is a bi-directional MII serial management data signal.
EWRAP[7:0]
554, 549, 206,
320, 503, 597,
13, 8
Output
Loopback designation
This signal designates realization of a loopback configuration for the physical
layer device on which an externally connected TBI is implemented for each
port. It is the signal for designating switching the data flow within a physical
layer device to a loop configuration.
LINK[7:0]#
93, 88, 539, 629,
Output
Open-
drain
LED pins
158, 276, 267, 262
These are pins for LEDs that show that a link has been established in TBI
mode for each port. Output is asynchronous.
(4) JTAG pins (This function can be supported upon customer request)
Pin Name
TMS
Pin No.
I/O
Function
63
Input
JTAG test mode select
This signal controls a boundary scan state machine.
The pin is not pulled up internally.
TDI
313
Input
JTAG test data input
This signal is the serial data input for a boundary scan.
The pin is not pulled up internally.
TDO
TCK
193
192
Output
JTAG test data output
3 states
This signal is the serial data output for a boundary scan.
Input
JTAG test clock
This is clock input that is used to synchronize test data I/O.
The pin is not pulled up internally.
TRST#
314
Input
JTAG reset
When this signal is made low level, a boundary scan operation is reset.
This must be high level during a boundary scan operation. It is low level on a
normal operation.
The pin is not pulled up internally.
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Preliminary User’s Manual S15212EJ3V0UM
CHAPTER 2 PIN FUNCTIONS
(5) Test pins and power supply pins
Pin Name
VDD
Pin No.
I/O
Function
756, 752, 748, 745, 741, 737, 735,
731, 727, 724, 720, 716, 714, 710,
706, 703, 699, 695, 693, 689, 685,
682, 678, 674, 474, 461, 454, 451,
434, 431, 427, 420, 407, 400, 396,
393, 380, 373, 128, 119, 114, 105,
95, 86, 81, 72, 62, 53, 48, 39, 29,
20, 15, 6
−
Power supply (+2.5 V)
GND
755, 753, 751, 749, 747, 746, 744,
742, 740, 738, 736, 734, 732, 730,
728, 726, 723, 721, 719, 717, 715,
713, 711, 709, 707, 705, 704, 702,
700, 698, 696, 694, 692, 690, 688,
686, 683, 681, 679, 677, 675, 673,
445, 436, 391, 382, 344, 315, 286,
257, 256, 227 to 225, 196 to 194,
165 to 163, 134 to 131, 102 to 98,
69 to 65, 36 to 32, 3 to 1
−
Ground (0 V)
VDDQ
754, 750, 743, 739, 733, 729, 725,
722, 718, 712, 708, 701, 697, 691,
687, 684, 680, 676, 125, 108, 92,
75, 59 ,42, 26, 9
−
Power supply for I/O buffer for physical layer interface
This is the power supply for the I/O buffer used for the
physical layer interface. Supply 3.3 V.
TEST[3, 1, 0]
TEST[5, 4, 2]
359, 468, 569
Output
Input
Test pins
These are pins for device test. They are not used in normal
operation.
428, 64, 662
Test pins
These are pins for device test. Always fix these pins to low
level.
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Preliminary User’s Manual S15212EJ3V0UM
CHAPTER 3 FUNCTION DESCRIPTION
3.1 System Configuration
The µPD98433 is an 8-port 10/100/1000 Mbps Ethernet Media Access Controller (MAC) that has a wide range of
operation modes and features. The µPD98433 is a device that was developed for network equipment that requires
multiple ports, namely LAN switches and routers.
The µPD98433 supports three interfaces that are compliant with IEEE802.3 as network side interfaces. In GMII
mode, it provides an interface compatible with a Gigabit Media Independent Interface (GMII). In MII mode, it provides
an interface compatible with a Media Independent Interface (MII). By connecting PHY devices that are compatible
with each of GMII and MII, it is possible to realize 10 Mbps, 100 Mbps, and 1000 Mbps Ethernets. TBI mode provides
an interface compatible with the Ten Bit Interface (TBI) that is used in 1000BASE-X.
The two system side interfaces are a FIFO bus interface and a register bus interface. The FIFO bus interface,
which is the interface for connecting FIFO within the µPD98433 to the host system, provides a high-speed interface
that is up to 125 MHz × 128 bits wide on each transmit or receive. There are 6 KB of on-chip FIFO per transmit or
receive for each port.
The register bus interface, which is a bus that is used for accessing control registers and statistics counters, is a
general-purpose bus that does not depend on a specific CPU.
Figure 3-1. Sample System Configuration Using µPD98433
ASIC
Switch
device
Quad
SERDES
µPD98433
Quad
10M/100M/
1000M
PHY
CPU
8-port switch application
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CHAPTER 3 FUNCTION DESCRIPTION
3.2 Function Blocks
As function blocks, the µPD98433 has an on-chip MAC module, PCS module, SAL module, STAT module, and
FIFO for each port. It also includes a FIFO bus module, MII management module, and register bus module as
common modules (see Figure 3-2).
Figure 3-2. µPD98433 Function Block Diagram
TXFIFO
10/100/1000M
TBI/GMII/MII
TBI/GMII/MII
PCS
MAC
RXFIFO
SAL
STAT
Port 7
128-bit bus
TXFIFO
RXFIFO
10/100/1000M
MAC
PCS
FIFO
bus
SAL
STAT
Port 6
128-bit bus
TXFIFO
RXFIFO
10/100/1000M
MAC
TBI/GMII/MII
PCS
SAL
STAT
Port 0
CPU bus
Test port
Register bus module
Management
interface
JTAG
MII management
3.2.1 MAC module
A MAC module, which is a block that realizes the 10/100/1000M Ethernet MAC function, is designed so that a PHY
device that supports GMII or MII can be connected. Connecting a PCS module to a MAC module makes it possible to
connect to a 1000BASE-X transceiver or receiver that has a TBI interface.
Within a MAC module, there is an on-chip transmit block, receive block, and MAC control block. The transmit block
and receive block realize Ethernet transmit and receive operations that conform to IEEE802.3. The MAC control block,
which is the block that executes flow control, performs the flow control frame receive processing and transmit
processing defined by IEEE802.3.
Besides processing data, the MAC module assists later data processing by sending receive operation and transmit
operation status information to later blocks.
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CHAPTER 3 FUNCTION DESCRIPTION
3.2.2 PCS module
A PCS module, which is a module for realizing a Physical Coding Sublayer function for connecting to a TBI
interface, is connected to a MAC module on the system side. On the network side of a PCS module, a GMII or MII
compatible PHY device or a 1000Base-X transceiver can be connected as an external device.
If a PCS module is set up to connect a GMII/MII compatible PHY device as an external device on the network side,
the PCS module connects a GMII/MII signal from the MAC module to the external device unchanged. Moreover, if a
PCS module is set up to connect to an external device using a TBI interface, processing that converts GMII data to
TBI data is performed in the PCS module. Thus, the PCS modules in the µPD98433 make it possible to configure
10/100/1000BASE-TX systems through GMII/MII and 1000BASE-X systems using a TBI interface.
3.2.3 Station Address Logic (SAL) module
A SAL module detects the value of the destination address field of a receive packet, performs address comparison
according to preset conditions, and reports the results to a later receive FIFO. The receive FIFO performs receive
packet selection using address conditions based on the notice from the SAL module.
Address conditions can be set by address type for each port.
For a unicast address, the SAL module performs a comparison with the value of the station address register that is
set in the control register of each port. For a multicast address, it is possible to select between receiving all multicast
packets and receiving only multicast packets selected using a hash table. For a broadcast address, it is possible to
set whether or not to receive broadcast packets.
The µPD98433 also provides settings that make it possible to accept all packets for all address types. See 3.5.5
Address filtering regarding address filtering conditions.
3.2.4 Statistics counter (STAT) module
The µPD98433 provides an effective set of statistics counters for realizing RMON/SNMP for each port. The STAT
module is the module that realizes this statistics counter set. See 3.12 Statistics Counters regarding statistics
counters.
3.2.5 On-chip FIFO
FIFO, which has on-chip high-speed dual port SRAM, has a capacity of 6 KB per port for transmission and
reception. FIFO also is responsible for mediation between the send and receive clock from the network side and the
FIFO bus clock from the host system side.
3.2.6 FIFO bus module
The FIFO bus module is a module for the interface between on-chip FIFO and the host system side. A high-speed
interface of up to 125 MHz × 128 bits per transmit or receive is possible as the bus band.
3.2.7 MII management module
The MII management module realizes the MII serial management function specified by IEEE802.3. By using this
module, the µPD98433 provides a single serial interface for accessing PHY registers using MII management frames
between external PHY devices. This also is used to access PCS registers using MII management frames to the
internal PCS module.
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3.2.8 Register bus module
The register bus module provides control registers for performing setup by port or for the entire chip and a register
bus for accessing statistics counters for each port. The separate 11-bit wide address bus and bidirectional 32-bit wide
data bus are general-purpose buses not dependent on a specific CPU.
3.2.9 Operation clocks
The µPD98433 requires four clocks as operation clocks. These four clocks are a transmit clock and receive clock
given by a PHY device, a clock for register access, and a clock for performing data transfer from the FIFO bus.
The transmit block of the MAC module reads transmit data from the transmit FIFO in synchronization with the
transmit clock input from a PHY device and generates a transmit frame that it outputs to the PHY device. The receive
block of the MAC module receives a receive frame in synchronization with the receive clock input from a PHY device
and writes data to the host system in the receive FIFO. A transmit clock and a receive clock of 125 MHz are input for
1000 Mbps operation, of 25 MHz for 100 Mbps operation, and of 2.5 MHz for 10 Mbps operation. Moreover, the
receive clock in TBI mode uses dual 62.5 MHz positive and negative clocks.
The clock for register access is given as a HCLK signal. It can be set in the range from 62.5 MHz to 25 MHz. The
MDC signal used in the MII management interface is generated by dividing this HCLK.
The clock for performing FIFO bus data transfer is a TXFCK signal and RXFCKOUT signal. The RXFCK input
signal is a reference clock for generating the RXFCKOUT signal. In the µPD98433, write operations from the host
system to on-chip FIFO and read operations from on-chip FIFO to the host system are performed in synchronization
with the TXFCK input signal and RXFCKOUT output signal, respectively. The TXFCK signal and RXFCK signal both
can be given in the range from 125 MHz to 50 MHz.
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3.3 Frame Formats
In an Ethernet network, information is transmitted and received in formats known as packets or frames. A frame or
packet used by Ethernet consist of a preamble (PA), start frame delimiter (SFD), destination address (DA), source
address (SA), type/length field (TYPE/LEN), data field (DATA), and frame check sequence (FCS) (see Figure 3-3).
The frame length, which excludes the preamble and SFD, is defined as at least 64 bytes and no more than 1518
bytes.
Figure 3-3. Ethernet/IEEE802.3 Frame Structure
TYPE/
PA
7B
SFD
1B
DA
6B
SA
6B
LEN
DATA
FCS
4B
2B
46B to 1500B
B = bytes
(1) Preamble and SFD
The preamble and SFD, which consist of 62 bits of “10” consecutively repeated and “11”, show the head of the
frame.
(2) Destination address
The destination address field, which shows the MAC address of the destination, is a field in which a unicast
address, multicast address, or broadcast address is written.
(3) Source address
The MAC address of the source is written in the source address field.
(4) Type/length field
This is used in an Ethernet frame as a field that shows the protocol type. In an IEEE802.3 frame, it is used as
a length field that shows the length of the data field.
(5) Data field
The data field has between 46 bytes and 1500 bytes set.
(6) Frame check sequence
The frame check sequence field is used as a 32-bit cyclic redundancy check (CRC) write field for checking
transfer data.
In the case of a VLAN frame, the structure differs somewhat from the normal frame structure. A 4-byte VLAN
header is inserted immediately after the source address field. The µPD98433 has a VLAN frame detection
function that performs packet processing based on this frame length if a transmit packet or a receive packet is
detected as a VLAN frame. For details, see 3.11 Operations on VLAN Frames.
Figure 3-4. VLAN Frame Structure
PA
7B
SFD
1B
DA
6B
SA
6B
TPID
2B
TCI
2B
LEN
2B
DATA
FCS
4B
42B to 1500B
VLAN header
B = bytes
TPID = Tag Protocol ID, TCI = Tag Control Information
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3.4 Transmit Operation
The µPD98433 generates transmit data frames based on data given in the transmit FIFO from a host system. If a
collision occurs, it executes a backoff algorithm and retransmits the data in the transmit FIFO. Packet status
information such as the number of transmit bytes and the occurrence of errors is set in the TSVREG register after the
end of transmission.
3.4.1 Generation of transmit packets
The data that a host system writes in the transmit FIFO normally is from the destination address to the last valid
data in the data field. The preamble, SFD, and FCS that are required as a transmit packet frame can be added
automatically by the µPD98433.
(1) Addition of preamble and SFD
The µPD98433 always outputs transmit data loaded in the transmit FIFO to the network side with a preamble
and SFD added.
(2) Addition of CRC
The µPD98433 automatically calculates the value of CRC and can add it automatically to the FCS field at the
end of the packet. Whether or not to add this automatically is determined according to specification by the
TXFDQ signal and the setting of the CRCEN bit of the MACC2 register.
If CRC addition is specified by the TXFDQ signal, CRC always is added automatically at the end of a transmit
packet. If CRC addition is not specified by the TXFDQ signal, this depends on the setting of the CRCEN bit of
the MACC2 register. In this case, CRC is not added automatically if the CRCEN bit is 0 and CRC is added
automatically if this bit is 1.
When set so that CRC is not added automatically, the value of the FCS field must be added at the end of the
transmit data stream written in the transmit FIFO on the host system side.
CRC added by the higher system is checked by the MAC module, and the result is reflected to the transmit
status register.
(3) Addition of PAD
If the data length of a packet written in the transmit FIFO is not at least the minimum frame length of 64 bytes
(also 64 bytes for a VLAN frame), the µPD98433 can add PAD automatically to ensure the minimum frame
length. If the PADEN bit of the MACC2 register was set to 1 or CRC addition was designated by a TXFDQ
signal, the PAD addition function is enabled. If the PADEN bit of the MACC2 register was set to 1, the correct
CRC is added automatically by the µPD98433 regardless of specification by the TXFDQ signal or the setting of
the CRCEN bit.
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3.4.2 Start of packet transmission
A packet transmit operation to the network side is started by either of the following conditions.
• If the amount of data in the transmit FIFO is greater than or equal to a threshold value set in advance
• If an attribute indicating the end of data is given by TXFDQ at the same time as transmit data written in the
transmit FIFO
The threshold level for start of transmission is set in the TFDWL field of the TFIC1 register.
For half-duplex operation, when a transmit operation is started, carrier sense is performed first to check whether or
not a remote station is transmitting on the network. If no remote station is transferring data and the preset interpacket
gap expired since the end of the previous data transfer, output of the transmit data stream to the PHY device is begun
immediately. If a remote station is transferring data, processing waits for the end of its communication and further
delays the start of transmission until the interpacket gap expires.
For full-duplex operation, since carrier sense is ignored, transmit data output to the PHY device begins at the time
that conditions for the start of transmission are satisfied and the interpacket gap expired.
3.4.3 Setting interpacket gaps
The µPD98433 requires that an interpacket gap (IPG) be set using a register. There is a Back to Back IPG, which
is used when transmitting sequentially using a minimum gap width, and a NON Back to Back IPG, which is used
otherwise.
(1) Back to Back IPG
The IPG for back to back transmission is set in the IPGT field of the IPGIFG register. The Back to Back IPG is
used to transmit sequentially using a minimum gap width after a local transmission. The minimum gap width in
this case is set in the IPGT field. After the local transmission ends, if the conditions for the start of the next
transmission are satisfied during this minimum gap time, the µPD98433 regards this as a Back to Back
transmission. It outputs the next transmit data stream to the PHY device immediately after the IPG time set in
the IPGT field elapses.
(2) NON Back to Back IPG
The NON Back to Back IPG set in the IPGIFG register is used to start transmit data stream output to a PHY
device after waiting for the IPG time to expire after a remote transmission ends. The NON Back to Back IPG
consists of two parts. Carrier sense is performed in the first half of the NON Back to Back IPG. If carrier is
detected during this period, the IPG count is cleared and is started again after waiting for carrier not to be
detected. If carrier is not detected in the period in which carrier sense is performed, transmit data stream
output is begun immediately after the IPG period expires.
In the IPGIFG register, the entire NON Back to Back IPG time is set in the IPGR2 field and the first half carrier
sense period is set in the IPGR1 field.
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3.4.4 Collisions and retransmission
Except in cases in which there are more collisions than the maximum number of collisions set in the RTMAX field
of the HDREG register or there are too many collisions in the collision window period set in the COLW field of the
HDREG register, the µPD98433 retransmits packets automatically when collisions occur. When a collision occurs, it
suspends transmission of data from the transmit FIFO and begins a jam transmission. The read pointer in the transmit
FIFO is returned to the head of the transmit data. When jam pattern transmission ends, the µPD98433 waits for
transmission according to a backoff algorithm. It begins retransmission automatically when the backoff period ends.
It is a network error if there are more collisions than the maximum number of collisions set in the RTMAX field of
the HDREG register or there are too many collisions in the collision window period set in the COLW field of the
HDREG register. If either condition occurs, data remaining in the transmit FIFO of the packet on which the condition
occurred is cleared and does not affect other transmit packet data that already has been stored. If there were more
collisions than the maximum number of collisions, the TMXCO bit of the TSVREG register is set to 1. If there were too
many collisions in the collision window period, the TLCOL bit of the TSVREG register is set to 1.
The retransmission time interval is determined by the backoff algorithm and the µPD98433 waits for retransmission
during a random slot time (512-bit time). In this algorithm, the coefficient r of the slot time for which the µPD98433 is
in a wait state before it retransmits for the nth time is determined by the following expression.
0 ≤ r < 2n If n > 10, let n = 10.
The constant 10 in the above inequality can be set to equal to or less than 10 arbitrary values by setting the ABEXT
field of the HDREG register. In this case, set the ABEXE bit of the HDREG register to 1.
3.4.5 End of transmission and abort
The µPD98433 ends a transmission or aborts a transmission under the conditions that follow. When a transmission
abort occurs, data of the aborted packet that remains in the transmit FIFO is cleared. Moreover, if a transmission
abort occurs on a packet that is being written to the transmit FIFO, all data written to the transmit FIFO after the abort
occurred is ignored until an end of data is specified by TXFDQ signal input. (See 3.7.1 FIFO bus interface.)
Whenever a transmission ends or is aborted, status information about the transmit operation that ended is reported
in the TSVREG register. This status information may also be an interrupt by the INT# signal due to canceling interrupt
masking by setting the TIMR register.
(1) Normal termination
If data transmission completes without any problems, the TDONE bit of the TSVREG register is set to 1 as a
normal termination.
(2) More collisions than maximum number of collisions
If there are more collisions than the maximum number of collisions set in the RTMAX field of the HDREG
register, the transmit operation is aborted and the TMXCO bit of the TSVREG register is set to 1.
(3) Occurrence of late collision
If a collision occurs outside the collision window that is set in the COLW field of the HDREG register, it is
considered a late collision and the transmit operation is aborted. When a late collision occurs, the TLCOL bit of
the TSVREG register is set to 1.
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(4) Excessive transmission delay
If a transmission cannot be started even after 24288-bit time has elapsed since the µPD98433 tried to start the
transmission, it is considered excessive delay and the transmission is aborted. When excessive delay occurs,
the TEDFR bit of the TSVREG register is set to 1.
(5) Attempt to transmit packet larger than maximum frame length
If an attempt is made to transmit a packet that has a length exceeding the maximum frame length set in the
LMAX register, the µPD98433 proceeds with transmission until the packet length reaches the value of the
LMAX register. If the HUGEN bit of the MACC2 register is set to 1, the limitation of transmit packet length by
the LMAX register is canceled. If a transmission abort occurs due to this condition, the TGNT bit of the
TSVREG register is set to 1.
(6) Occurrence of transmit FIFO underrun
If all data in the transmit FIFO is transmitted, but does not have time to write that transmit data, the system
side, the transmit FIFO generates an underrun and aborts the transmit operation. When a transmission is
aborted due to a transmit FIFO underrun, the TFUN bit of the FSVREG register and the TURUN bit of the
TSVREG register are immediately set to 1.
(7) Occurrence of parity errors
Parity errors are checked between the transmit FIFO and the MAC block. Therefore, even if a parity error
occurs in the transmit FIFO bus interface, a transmit operation is performed by writing data in the transmit FIFO
and sending transmit data from the transmit FIFO to the MAC block after the start of transmission. By default,
transmission is not suspended even if an error occurs in the data transmitted from the transmit FIFO, however
by setting the DPAR bit of the TFIC2 register to 1, transmission can be suspended at the point at which an
error occurs. CRC is not added to the suspended transmit packet. In this case, the TPER bit of the FSVREG
register is set to 1. Also, the TURUN bit of the TSVREG register is set to 1.
Moreover, by setting the DPAR bit of the TFIC2 register to 0, the µPD98433 also can terminate transmission
after transmitting data in which a parity error occurs without change as a transmit frame. If automatically
adding CRC, CRC calculation is performed ignoring parity errors. In that case, the TPER bit of the FSVREG is
set to 1. The TURUN bit of the TSVREG register does not change.
(8) Transmit FIFO overrun
If transmit FIFO overrun occurs, the packet in which the overrun occurred is transmitted up to the word
preceding the one at which the overrun has occurred, and transmission is aborted. At this time, a transmit
parity error occurs.
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3.5 Receive Operations
The µPD98433 provides receive data from a receive data stream sent by a PHY device to a host system. The
µPD98433 performs preamble and SFD detection, length field checking, and CRC checking. By setting the MACC3
register, status information can be added to the data stream that is output to the host system from the receive FIFO at
the same time that the number of receive bytes, occurrence of errors, and other status information for each receive
packet is set in the RSVREG register after an end of receive. It also is possible to set up packet filtering by address or
other conditions.
3.5.1 Preamble and SFD detection
In GMII or MII mode, each port recognizes data on a RXDn signal as receive data when the RX_DVn signal is high
level. In TBI mode, it recognizes receive data when a valid code appears on 10-bit receive data. When each port has
detected the preamble pattern (1,0,1,0,...) from the data that was received, it waits until SFD (1,0,1,0,1,0,1,1) is
detected at its end. When SFD is detected, it recognizes the beginning of a receive packet and starts storing data in
the receive FIFO. The preamble and SFD are removed from the receive packet and are not stored in the receive
FIFO.
3.5.2 Length field check
Each port of the µPD98433 counts the length of a receive packet and checks the data field length by considering
the two bytes following the source address field the length field. For a packet considered a VLAN frame, the two bytes
following the VLAN header are considered the length field. See 3.11.1 VLAN frame detection regarding VLAN frame
detection. The results of checking are reported to the host system as status information.
3.5.3 CRC check
Each port of the µPD98433 automatically calculates a 4-byte frame check sequence (FCS) from receive packet
data and compares it to the CRC data added to the end of the receive packet. The comparison result is reported to
the host system as status information.
3.5.4 Packet filtering
The µPD98433 can perform receive packet filtering using the following conditions. Filtering can be set for each
port. Filtering conditions also can be used in combination.
• Destination address
• Short packets: Packets whose packet length is less than 64 bytes
• CRC error packets
• Control frames
• Packet containing dribble nibble
The µPD98433 rejects the receive packets with following conditions compulsorily.
• Packets whose packet length is equal to or less than 16 bytes
• Packets whose inter-frame gap is shorter than MINIFG
See 3.5.5 Address filtering for a procedure that performs packet filtering using destination address conditions.
Filtering against CRC error packets, control frames, short packets, and dribble nibbles can be set using the RFIC2
register. By setting this register, packets on which CRC errors occurred, control frames, short packets, and dribble
nibbles can be removed from the receive FIFO. All filtering conditions can be canceled, and canceling all of them
transfers all received packets to the host system.
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3.5.5 Address filtering
The µPD98433 can execute filtering by receive packet destination address and remove receive packets that do not
meet conditions. Address filtering conditions are set using the AFR, HT1, HT2, LSA1, and LSA2 registers. Filtering
conditions can be set by the address types unicast address, multicast address, and broadcast address. These filtering
conditions can also be combined.
(1) Unicast address filtering
Setting the AUC bit of the AFR register to 0 makes the station address that is set in the LSA1 register and
LSA2 register a unicast address and compares it to the destination address of a receive packet. If the
compared addresses match, the receive packet is stored in the receive FIFO. Setting the AUC bit of the AFR
register to 1 stores all unicast packets in the receive FIFO.
(2) Multicast address filtering
There are two ways of filtering multicast addresses. Setting the PRM bit of the AFR register to 1 stores all
multicast packets in the receive FIFO.
Setting the AMC bit of the AFR register to 1 uses the hash table provided by the HT1 register and HT2 register
and stores only multicast packets that match the table in the receive FIFO. The method of detecting matches
using the hash table is as follows.
The hash table is referenced by calculating the CRC of a received multicast address and using bits 28 to 23 of
the resulting 32-bit CRC. The following expression is used as a polynomial in CRC calculation.
X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1
If bit positions in the six bits above are set to 1 in the HT1 register and HT2 register, the multicast packet is
stored in the receive FIFO. In order to set a hash table, multicast address CRC calculations must be
performed and the corresponding bits must be set to 1.
(3) Broadcast address filtering
Setting the ABC bit of the AFR register to 1 stores broadcast packets in the receive FIFO.
(4) Promiscuous mode
Setting the PRO bit of the AFR register to 1 makes the mode promiscuous and stores packets of all address
types in the receive FIFO.
3.5.6 Receive FIFO overflow
If an overflow occurs in the receive FIFO while storing receive packets, data storage stops immediately.
The packet that causes receive FIFO overflow is treated according to the following conditions:
(a) If RXFA threshold value control by the THRX field of the RFIC3 register is not used, the packet is rejected.
(b) If RXFA threshold value control is used, and fewer than 48 bytes of the packet were written in the receive FIFO
when the receive FIFO overflowed, the packet is rejected.
(c) If RXFA threshold value control is used, and at least 48 bytes of the packet were written in the receive FIFO
when the receive FIFO overflowed, the packet reception is suspended. The part of the packet already received
is output with RXFDQ. RXFDQ which indicates EOF and failure is added to the last received word.
It is possible for a host system to detect overflow using the FSVREG register.
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3.5.7 Clearing receive FIFO
A host system can clear the contents of receive FIFO by setting the RXFFLH bit of the MACC3 register to 1. If this
bit is set in the middle of storing a receive packet in receive FIFO, the packet being received is discarded. If a
previous receive packet already is stored in the receive FIFO at that time, that packet also is cleared.
3.5.8 Adding status information
The µPD98433 can add status information to the beginning or end of receive packet data via the receive FIFO
interface. Setting the APSS bit of the MACC3 register or the APSE bit of the MACC3 register to 1 adds status and
RBYT fields to the beginning or the end of the receive data, respectively. Figure 3-5 shows the configuration of the
status and RBYT fields that is displayed when read.
Receive status information outputs the contents of Table 3-1 and the RBYT field outputs the contents of Table 3-2.
The UFCR field displays the contents of the UFCR register.
APSE and APSS cannot be set to 1 simultaneously. Set either one to 1 or set both of them to 0. The APSS setting
cannot be used when receiving a Jumbo frame or reading receive data when one packet of data had not been
completely received according to the setting of the THRX threshold value in the RFIC3 register, since status
information cannot be requested.
Figure 3-5. Configuration of Status and RBYT Fields
127
111
95
126
110
94
125
109
93
124
108
92
123
107
91
122
106
90
121
105
89
73
57
41
25
9
120
119
103
118
102
86
70
54
38
22
6
117
101
85
69
53
37
21
5
116
100
84
68
52
36
20
4
115
99
83
67
51
35
19
3
114
98
82
66
50
34
18
2
113
97
81
65
49
33
17
1
112
96
80
64
48
32
16
0
Reserved
104
Reserved
88
87
UFCR[31:16]
79
78
77
76
75
74
72
71
UFCR[15:0]
63
62
61
60
59
58
56
55
RBYT [31:16]
47
46
45
44
43
42
40
39
RBYT [15:0]
31
30
29
28
27
26
24
23
RSV[31:16]
15
14
13
12
11
10
8
7
RSV[15:0]
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Table 3-1. Receive Status Information
Bit
Field
RFOV
Function Description
31
Receive FIFO overflow
Indicates that this is a packet for which reception was suspended because it made the receive FIFO
overflow.
14
13
VLAN
USOP
VLAN frame
Indicates that the length/type field of the frame contains the VLAN protocol identifier 8100H.
Control frame containing undefined opcode received
Indicates that the current frame was recognized as a control frame by the MAC module but that it
contains an unknown opcode.
12
11
10
RPCF
RCFR
DBNB
Pause control frame received
Indicates that the current frame was recognized as a control frame that contains a valid pause
frame opcode and a valid destination address according to the MAC module.
Control frame received
Indicates that the current frame was recognized as having a valid type field as a control frame
according to the MAC module.
Packet containing dribble nibble received
Indicates that a fractional 4 bits was received after the end of a packet.
A single nibble (called a dribble nibble) occurred, but was not transmitted to the system (10/100
Mbps only).
9
8
7
6
5
RBRO
RMUL
ROK
Broadcast packet received
Indicates that the destination address of the packet contained a broadcast address.
Multicast packet received
Indicates that the destination address of the packet contained a multicast address.
Receive OK
Indicates that the frame contains a valid CRC and had no code errors.
RLOR
RLER
Length field check
Indicates that the length/frame type field is greater than 1500.
Data length mismatch
Indicates that the length/type field value in the packet does not match the actual byte length of the
data. If the length/type field value is greater than 1500, less than 46 (not VLAN), or less than 42
(VLAN), this status is invalid.
4
3
2
RCRCE
RCV
CRC error
Indicates that the CRC of the packet did not match the internally generated CRC.
Receive code error
Indicates that at least 1 nibble was detected as a code error while receiving the packet.
RFCANote
Illegal carrier detected
Indicates that the following was input and a valid packet could not be recognized.
In MII mode, RX_ER = 1, RX_DV = 0, RXD[3:0] = EH
In GMII mode, RX_ER = 1, RX_DV = 0, RXD[7:0] = 0EH
In TBI mode, the next code after an IDLE code was not an IDLE or SPD.
REPSNote
1
0
Invalid packet received
Indicates that the received packet ended at the SFD field and a valid packet could not be
recognized.
RPPDNote
Receive packet ignored
Indicates that IFG during reception is shorter than the value set to the MINIFG field of the IPGIFG
register and the packet received is not recognized as a valid packet. The IFG is counted from the
end of the frame until the beginning of the next frame.
Note The status in RSV[2:0] is reported when the next valid packet is received.
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Table 3-2. RBYT Field
Bit
31:0
Field
RBYT
Function Description
Receive byte count
This shows the total number of bytes in a frame.
3.6 Full-Duplex Operation
Each port of the µPD98433 is capable of full-duplex operation that transmits and receives packets simultaneously.
Setting the FULLD bit of the MACC2 register to 1 enables full-duplex operation. When full-duplex operation is
enabled, the COLn signal and CRSn signal are ignored. In TBI mode, the CRSn signal functions as SIGDET.
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3.7 System Bus Interface
The µPD98433 has an on-chip FIFO bus interface and register bus interface for interfacing with a host system. The
FIFO bus interface is used to transfer transmit and receive data between on-chip FIFO and a host system. The
register bus interface is used to access the internal registers and statistics counters of the µPD98433.
3.7.1 FIFO bus interface
The µPD98433 has a 128-bit wide transmit FIFO bus for giving transmit data to transmit FIFO and a 128-bit wide
receive FIFO bus that reads receive data from receive FIFO.
A bus cycle of up to 125 MHz can be used to transfer data in the FIFO bus interface.
(1) Transmit FIFO bus interface operations
Figure 3-6. FIFO Interface Write Timing
TXFCK
TXFEN#
TXFBA[N]
TXFDQ[4]
TXFDQ[3]
TXFDQ[2]
TXFDQ[1]
TXFDQ[0]
TXFPT[2:0]
TXFD[127:0]
TXPAR
Port enable
1st word
128 bits
2nd word
3rd word
128 bits
4th word
128 bits
n
th word
24 bits
n
−
2
th word
n
−
1
th word
128 bits
128 bits
128 bits
3 byte
ending
Idle
Start
Middle
Idle
A data write to transmit FIFO is enabled by making the TXFEN# signal low level. When this signal is asserted,
the TXFBAn signal functions of all ports are enabled. Each port makes the TXFBAn signal high level if the data
stored in transmit FIFO does not exceed the value set in the TFWMH field of the TFIC1 register. This makes it
possible for the host system to recognize that at least the preset amount of free space was reserved in the
transmit FIFO for each port.
When it is confirmed that the TXFBAn signal is high level, the host system begins writing transmit data. The
host system provides the necessary data in TXFPT[2:0], TXFD[127:0], and TXFDQ[4:0].
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TXFPT[2:0] is a signal for specifying the port number of the port that performs a packet transmission. The host
system uses this pin to give the port number of the transmit FIFO to be written. TXFD[127:0] is the data bus for
writing to transmit FIFO. TXFDQ[4:0] is a signal for showing attributes of the data on the FIFO data bus. The
host uses this to input attributes of the data at TXFD[127:0] that correspond to each bus mode.
Data attributes are idle, start of data, middle of data, and end of data. If a fraction appears at the end of data,
the µPD98433 is notified that fraction processing according to the data attribute is needed. It also is possible
to designate the automatic addition of CRC codes by setting these attributes. Table 3-3 shows the relationship
between TXFDQ[4:0] input and data attributes.
Table 3-3. TXFDQ Pins and Transmit Data Attributes
TXFDQ
Meaning
Valid Data
4
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
0
0
0
0
1
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
X
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Big Endian
Little Endian
Idle
None
None
Start of data
FEDCBA9876543210
FEDCBA9876543210
FEDCBA9876543210
None
FEDCBA9876543210
FEDCBA9876543210
FEDCBA9876543210
None
Middle of data
Start of data (CRC addition)
Reserved
Reserved
None
None
End of data (EOF) 16B
End of data (EOF) 1B
End of data (EOF) 2B
End of data (EOF) 3B
End of data (EOF) 4B
End of data (EOF) 5B
End of data (EOF) 6B
End of data (EOF) 7B
End of data (EOF) 8B
End of data (EOF) 9B
End of data (EOF) 10B
End of data (EOF) 11B
End of data (EOF) 12B
End of data (EOF) 13B
End of data (EOF) 14B
End of data (EOF) 15B
FEDCBA9876543210
F
FEDCBA9876543210
0
FE
10
FED
210
FEDC
3210
FEDCB
43210
FEDCBA
543210
FEDCBA9
6543210
FEDCBA98
FEDCBA987
FEDCBA9876
FEDCBA98765
FEDCBA987654
FEDCBA9876543
FEDCBA98765432
FEDCBA987654321
76543210
876543210
9876543210
A9876543210
BA9876543210
CBA9876543210
DCBA9876543210
EDCBA9876543210
See 3.7.1 (3) Little endian/Big endian regarding little endian and big endian.
Once the start of data is written, the remaining data is written to the transmit FIFO using burst transfer.
When the amount of data in transmit FIFO exceeds the value set in the TFDWL field of the TFIC1 register, the
transfer of transmit data to the MAC module begins. Moreover, if the amount of data in transmit FIFO exceeds
the value set in the TFWMH field of the TFIC1 register, the TXFBAn signal is made low level. By designating
an idle during burst transfer, it is possible to delay writing to transmit FIFO.
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By switching TXFPT[2:0] while writing to transmit FIFO, it is possible to continue writing transmit data to the
transmit FIFO of another port. In this case, it is possible to write to another port after a rise of TXFCK
immediately after switching, but it must be confirmed that the TXFBA signal corresponding to the other port is
at high level. Moreover, a data stream that is newly written to another port can begin at data having any of the
attributes start of data, middle of data, or end of data and transmit packets can be written continuously to each
port divided into blocks. However, whenever the port is switched, the attribute of the write data must be given
correctly. Figure 3-7 shows an example of the timing of switching the port for writing transmit data using
TXFPT[2:0].
Figure 3-7. Timing of Switching Transmit Data Write Port Using TXFPT[2:0]
TXFCK
TXFEN#
TXFBA[N]
TXFBA[M]
TXFDQ[4]
TXFDQ[3]
TXFDQ[2]
TXFDQ[1]
TXFDQ[0]
TXFPT[2:0]
TXFD[127:0]
TXPAR
Port enable M
Port enable N
1st word
128 bits
2nd word
128 bits
3rd word
128 bits
4th word
128 bits
1st word
128 bits
2nd word
128 bits
3rd word
128 bits
4th word
128 bits
5th word
128 bits
Port N
Middle
Port M
Start
Start
Middle
Idle
While writing data to transmit FIFO, if something that causes transmission to abort (such as excessive
collisions or delay) occurs in the transmit packet that is being written, the portion of the data of the transmit
packet currently being written that already has been stored in transmit FIFO is cleared. Furthermore, data
written after the abort occurs is ignored until data that has an attribute indicating the end of data (EOF) is given
in the TXFDQ pin. The next packet can be written after the host system inputs an EOF.
Moreover, while writing data to transmit FIFO, if something that causes transmission to abort occurs in a
transmit packet that is waiting for a transmission that already was being stored in transmit FIFO, the
transmission is cut off and the rest of the relevant packets in the transmit FIFO are cleared. This has no affect
on other packet data stored in the transmit FIFO or packet data currently being written.
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(2) Receive FIFO bus interface operations
Figure 3-8. FIFO Interface Read Timing
RXFCKOUT
RXFEN#
RXFA
RXFDQ[4]
RXFDQ[3]
RXFDQ[2]
RXFDQ[1]
RXFDQ[0]
RXFPT[2:0]
RXFD[127:0]
RXPAR
Port number
2nd word
3rd word
n
−
1
th word
n
th word
1st word 128 bits
PASS
SKIP
3 byte
ending
Idle
Start
Middle
Idle
In the µPD98433, either a complete packet is stored in receive FIFO on a receive from the network side or the
data stored in receive FIFO can be transferred to the host system when that data exceeds the threshold value
set in the THRX field of the RFIC3 register. The following procedure reads from receive FIFO.
(a) Reading from receive FIFO
Reading data from receive FIFO is enabled by making the RXFEN# signal low level. In the µPD98433, the
port number of the receive FIFO that is read via the FIFO bus interface is designated from the µPD98433
side. When reading from receive FIFO is enabled, the µPD98433 first scans the receive FIFO of each port
and checks whether or not a complete packet of receive data is stored in the receive FIFO of any port or
checks whether or not the threshold value set in the THRX field of the RFIC3 register has been exceeded.
As a result, if at least one complete packet is stored in any receive FIFO or the threshold value set in the
THRX field of the RFIC3 register is exceeded, it makes the RXFA signal high level to notify the host system
that receive data is prepared for transfer. At the same time, it outputs the port number of the receive FIFO
in which data is prepared for transfer at RXFPT[2:0]. After the host system recognizes RXFPT[2:0], it must
input a PASS signal in order to read data from the receive FIFO of the port. When the PASS signal is
input, receive data is read from RXFD[128:0] in burst form as a receive data stream synchronized with
RXFCKOUT.
At the same time that receive data is read, the µPD98433 outputs data attributes on the FIFO data bus
corresponding to each bus mode in the RXFDQ signal. If there are fractional bytes at the end of receive
data, the valid byte positions can be known from the data attribute. Table 3-4 shows the relationship
between RXFDQ[4:0] output and data attributes.
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Table 3-4. RXFDQ Pins and Receive Data Attributes
RXFDQ
Meaning
Valid Data
4
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
0
0
0
0
1
1
1
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
0
0
1
1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
X
0
1
0
1
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Big Endian
Little Endian
Idle
None
None
Start of data
Middle of data
Reserved
FEDCBA9876543210
FEDCBA9876543210
None
FEDCBA9876543210
FEDCBA9876543210
None
Status information (Beginning) FEDCBA9876543210
FEDCBA9876543210
FEDCBA9876543210
None
Status information (End)
Reserved
FEDCBA9876543210
None
Fail (EOF)
Error
Error
Fail (SFD)
Error
Error
Fail (Middle of frame)
Reserved
Error
Error
None
None
Reserved
None
None
End of data (EOF) 16B
End of data (EOF) 1B
End of data (EOF) 2B
End of data (EOF) 3B
End of data (EOF) 4B
End of data (EOF) 5B
End of data (EOF) 6B
End of data (EOF) 7B
End of data (EOF) 8B
End of data (EOF) 9B
End of data (EOF) 10B
End of data (EOF) 11B
End of data (EOF) 12B
End of data (EOF) 13B
End of data (EOF) 14B
End of data (EOF) 15B
FEDCBA9876543210
F
FEDCBA9876543210
0
FE
10
FED
210
FEDC
3210
FEDCB
43210
FEDCBA
543210
FEDCBA9
FEDCBA98
FEDCBA987
FEDCBA9876
FEDCBA98765
FEDCBA987654
FEDCBA9876543
FEDCBA98765432
FEDCBA987654321
6543210
76543210
876543210
9876543210
A9876543210
BA9876543210
CBA9876543210
DCBA9876543210
EDCBA9876543210
See 3.5.8 Adding status information regarding the addition of status information. See 3.7.1 (3) Little
endian/Big endian regarding little endian and big endian.
If a read of one packet from the port specified in RXFPT ends and there is a port in which the next receive
data is prepared for reading, the µPD98433 makes the RXFA signal high level, outputs the port number in
RXFPT, and waits for the next receive data read.
The RXFA signal maintains high level if there is receive data that has been prepared for reading in the port
shown in RXFPT. As an exception, the RXFA signal always becomes low level once there is a shift to
another port due to skip signal input while reading.
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The order of ports when performing receive data transfer is determined in advance in the µPD98433. The
sequence Port 0 → Port 1 → Port 2 → ... Port 7 → Port 0 →... is repeated. However, on a shift to the next
port, if a complete packet of receive data has not been stored in that port and the threshold value set in the
THRX field of the RFIC3 register is not exceeded, the port is skipped and its turn goes to the next port.
Figure 3-9 shows the timing after a read of receive data from a given port is completed until a read of the
next port is started.
Figure 3-9. Timing of Switching Ports After Receive Data Is Read
RXFCKOUT
RXFEN#
RXFA
RXFDQ[4]
RXFDQ[3]
RXFDQ[2]
RXFDQ[1]
RXFDQ[0]
RXFPT[2:0]
Port number
Port number
n
−
3
th word
n
−
2
th word
2nd word
3rd word
n
−
1
th word
n
th 24 bits
RXFD[127:0]
1st word
RXPAR
PASS
SKIP
3 byte
ending
Middle
Idle
Start
Middle
Filtering conditions can be set for receive data written in receive FIFO from the network side by using
register settings. If registers are set so that packets containing CRC errors, control frames, short packets,
or dribble nibbles are not received, those packets are at first stored in receive FIFO. However, when CRC
errors and the like are confirmed, those stored in receive FIFO are cleared and the host system is not
notified that the packets were stored. Similarly, in the case of address filtering, packets that do not satisfy
filtering conditions are removed from receive FIFO and are not transferred to the host system.
If receive FIFO overflows, the packet being received is at first written to receive FIFO. However, after
overflow is detected, data of the packet being received that already was stored in receive FIFO is cleared
and data similarly is not transferred to the host system.
If data whose data length is less than 16 bytes is stored in receive FIFO from the network side, the receive
FIFO unconditionally deletes the data.
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(b) SKIP signal
The port number of the receive FIFO whose data is read via the FIFO bus is designated by the µPD98433.
However, if a SKIP signal is input when the reading of receive FIFO is enabled and the RXFA signal is high
level or in the middle of reading receive data using burst transfer, the host system can read a port other
than the one the µPD98433 specifies.
As previously stated, the order in which receive data is transferred for each port is determined in advance
by the µPD98433 and the SKIP signal is used to forcibly shift to reading receive data from the next port in
the sequence by host system designation.
When a SKIP signal is input, the µPD98433 suspends reading receive data of the current port, outputs
00000B to the RXFDQ pin, and becomes idle. The RXFA signal at first becomes low level. Next, the
µPD98433 outputs the number of the next port that is prepared to transfer receive data to the host system
in RXFPT and makes the RXFA signal high level again. After that, input of a PASS signal by the host
system starts a data read from the new port.
The data of a port skipped due to a SKIP signal is maintained. When its own turn recurs due to receive
data of other ports having been read or the input of a new SKIP signal, the skipped port waits for the input
of a new PASS signal and begins transferring the remaining receive data.
Figure 3-10 shows an example of the timing when switching ports due to a SKIP signal before read begins.
In this case, the port is switched two clocks of RXFCKOUT after detecting the SKIP signal.
Do not give a SKIP signal the width of multiple clocks. To input a SKIP signal multiple times and skip ports
consecutively, do it so that the next SKIP signal is input after confirming a port switch after input of a 1-
clock SKIP signal.
Figure 3-10. Timing of Switching Read Port Due to SKIP Signal (Before Start of Read)
RXFCKOUT
RXFEN#
RXFA
RXFDQ[4]
RXFDQ[3]
RXFDQ[2]
RXFDQ[1]
RXFDQ[0]
RXFPT[2:0]
RXFD[127:0]
RXPAR
Port number N
Port number N+1
XX
XX
2nd word
1st word
1st word
PASS
SKIP
Skip frame
Start
Middle
Idle
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Next, Figure 3-11 shows an example of the timing when switching ports due to a SKIP signal while reading.
In this case, the port switches two clocks of RXFCKOUT after the SKIP signal is detected. The µPD98433
outputs valid receive data for two clocks until the port switches. If the same port as the port skipped due to
the SKIP signal continues to be read (if there is no receive data that can be read in other ports), the
original port is shown in RXFPT[2:0] a further two clocks after the two clocks of valid data (see Figure 3-11
(b)). Since the µPD98433 is in IDLE state at the time that the next port is shown after SKIP signal input, a
PASS signal must be input in order to start reading.
When it is again the turn of a port that was skipped due to a SKIP signal, data output starts from the next
data after the receive data that was output last when it was last skipped. These operations make it
possible to use the SKIP signal to read data received by each port divided into blocks. The read unit is
determined in advance and a SKIP signal is input for each read unit until an end of data appears in the
RXFDQ signal. Thus it is possible to continuously read sequentially from each port by read unit. However,
unlike writing to transmit FIFO, the µPD98433 side specifies the port that is read.
Do not give a SKIP signal the width of multiple clocks. To input a SKIP signal multiple times to
consecutively skip ports, do it so that the next SKIP signal is input after confirming that a port was skipped
after input of a 1-clock SKIP signal.
Figure 3-11. Timing of Read Port Switch Due to SKIP Signal (During Read) (1/2)
(a) Skipped port and next port are different
RXFCKOUT
RXFEN#
RXFA
RXFDQ[4]
RXFDQ[3]
RXFDQ[2]
RXFDQ[1]
RXFDQ[0]
RXFPT[2:0]
RXFD[127:0]
RXPAR
Port number M
Port number N
n
−
3
th word
n
−
2
th word
n
−
1
th word
n th word
2nd word
1st word 128 bits
1st word 128 bits
PASS
SKIP
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Figure 3-11. Timing of Read Port Switch Due to SKIP Signal (During Read) (2/2)
(b) Skipped port and next port are the same
RXFCKOUT
RXFEN#
RXFA
RXFDQ[4]
RXFDQ[3]
RXFDQ[2]
RXFDQ[1]
RXFDQ[0]
Port number M
XX
Port number M
RXFPT[2:0]
RXFD[127:0]
2nd word
n
3
th w ord
n
2
th w ord
n
1
th w ord
n th word
−
−
−
1st word 128 bits
n+1 th word
XX
RXPAR
PASS
SKIP
(3) Little endian/Big endian
The µPD98433 has a function that sets the byte order of transmit and receive data in the FIFO bus interface to
little endian or big endian. Little endian or big endian is selected by setting the BUSMODE bit of the MISCR
register.
In little endian mode, data is transferred leading with the LSB of the data bus. In big endian mode, data is
transferred leading with the MSB. Setting the BUSMODE bit of the MISCR register has no affect on the byte
order of the register bus interface.
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3.7.2 Register bus interface
The µPD98433 provides a register bus interface for accessing control registers, statistics counters, and other on-
chip registers of the µPD98433. The register bus interface consists of a 32-bit wide bidirectional data bus, 11-bit width
address bus, and control signals (HCS# signal, HRW signal, and HACK# signal).
(1) Register read/write control
On a read access of an internal register, the host system sets the address of the register to be read in
HA[10:0] and makes the HRW signal high level and the HCS# signal low level. When the µPD98433
recognizes a read access from the states of the HRW signal and HCS# signal, it sets the HACK# signal to low
level first, and reads the necessary data. When the data that was read is set at HD[31:0], the µPD98433 sets
the HACK# signal to low level. The host system, which fetch the data at HD[31:0] after the HACK# signal
becomes low level, subsequently returns the HCS# signal to high level. The host system must maintain the
states of HA[10:0], the HRW signal, and the HCS# signal until the HACK# signal is low level and it fetches the
data. When the host system fetches the data and sets the HCS# signal high level, the µPD98433 terminates
the read cycle. The HACK# signal is low level for one cycle of HCLK.
On a write access of an internal register, the host system sets the address of the register to be written in
HA[10:0] and the write data in HD[31:0] and sets the HRW signal to low level and the HCS# signal to low level.
When the µPD98433 recognizes a write access from the states of the HRW signal and HCS# signal, it sets the
HACK# signal to high level first, and starts writing the data at HD[31:0]. When it finishes writing, the µPD98433
sets the HACK# signal to low level and notifies the host system. The host system must maintain the states of
HA[10:0], HD[31:0], the HRW signal, and the HCS# signal until the HACK# signal becomes low level and the
writing of data ends. When writing ends and the host system sets the HCS# signal to high level, the µPD98433
ends the write cycle. The HACK# signal is low level for one cycle of HCLK.
(2) Register address mapping
The registers that a host CPU accesses are classified as port control registers, statistics counters, and global
registers. Port control registers and statistics counters, which are established for each port, are used for
setting the operation and reading the status information for each port, as well as for reading statistical
information. Global registers, which are registers for making settings for all ports, are used in common when
using each port.
These registers are specified by address data at HA[10:0]. HA[10:0] is divided into two parts. Its higher bits
[10:8] input the port number of the port for which register access is desired and its lower bits HA[7:0] input the
address of the register to be accessed. Figure 3-12 shows the relationship between HA[10:0] and port
numbers and register addresses, as well as providing an example.
Figure 3-12. Register Address Bus
HA10
HA9
HA8
HA7
HA6
HA5
HA4
HA3
HA2
HA1
HA0
Port number
Register address
Example Accessing MACC3 register of port 3 (Register address: 26H)
HA10
0
HA9
1
HA8
1
HA7
0
HA6
0
HA5
1
HA4
0
HA3
0
HA2
1
HA1
1
HA0
0
The value of HA[10:8] is ignored when accessing a global register.
Moreover, registers related to the MII management interface (MIIC, MCMD, MADR, MWTD, MSTA, and MIND
registers) are valid only when the port number is set to 0.
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(3) Interrupt servicing
If an interrupt source generates, the µPD98433 makes the INT# signal low level and notifies the host system.
The following are sources of interrupts.
• Transmit packet status information shown in the TSVREG register
• Receive packet status information shown in the RSVREG register
• FIFO status information shown in the FSVREG register
• Statistics counter overflow shown in the CAR1 and CAR2 registers
When an INT# signal is asserted, the host system can find out the port at which it occurred and what status
caused the INT# signal to be asserted by reading the STIR register. It also can identify the detailed interrupt
source by reading the status register of the corresponding port. Moreover, status information is accumulated
for each packet.
When an interrupt source that asserts an INT# signal occurs in the status register established for each port,
the corresponding bit of the STIR register is set to 1. Reading the STIR register does not clear the status
register or the INT# signal.
For each interrupt source, it is possible to mask interrupts individually by their source. When an interrupt
occurs for a masked source, the corresponding bit of each status register is set to 1, but will not be the source
for asserting INT# signal, thus the corresponding bit of the STIR register is not set to 1.
Each status register is cleared automatically when it is read if the SRRC bit of the MISCR register is set to 1.
The INT# signal is deasserted when the status registers of all ports are cleared (excluding masked bits).
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3.8 Network Interface
The µPD98433 has an on-chip GMII (Gigabit Media Independent Interface), MII (Media Independent Interface) and
TBI (Ten Bit Interface) compliant with IEEE802.3 as network side interfaces. By setting the GMII/MII bit of the PYTBIC
register and the IFMOD field of the MACC2 register, it is possible to select the interface to use in each port. Each
interface is selected by the user setting registers. Moreover, the TBI is selected in initial setup of the µPD98433 and a
TBI IDLE (/I/) code is output by TXD on startup.
These three kinds of interface are implemented by port through the alternate functions of pins. Therefore, one
interface is used for one port. A pair of MII management interfaces is also implemented. These can be used in PHY
device setting, when reading status, or in negotiation with a link partner when using auto-negotiation.
Before using a line interface, set the PHY address in the PHYC register.
3.8.1 GMII (Gigabit Media Independent Interface)
GMII, which is an interface defined by IEEE802.3, realizes a transmit and receive data interface that is independent
of media type at the transfer speed of 1000 Mbps. This interface has an 8-bit wide (octet) data bus and control signals
for transmit and receive data.
The µPD98433 supports an octet data bus and control signals for transmission/reception for each port.
In order to use the GMII interface, set the GMII/MII field of the PYTBIC register of the TBI to 1 and set the IFMOD
field of the MACC2 register to ‘10’.
3.8.2 TBI (Ten Bit Interface)
TBI, which is an interface defined by IEEE802.3, is an interface for connecting to a physical layer device (mainly
SERDES) at the transfer speed of 1000 Mbps. This interface has a 10-bit wide (octet) data bus and control signals for
transmit and receive data.
The µPD98433 supports a 10-bit data bus and control signals for transmission/reception for each port.
In order to use the TBI interface, set the GMII/MII field of the PYTBIC register of the TBI to 0 and set the IFMOD
field of the MACC2 register to ‘10’.
3.8.3 MII (Media Independent Interface)
MII, which is an interface defined by IEEE802.3, realizes a transmit and receive data interface that is independent
of media type (such as STP, UTP, optical fiber) at the transfer speed of 10 Mbps or 100 Mbps. This interface has a 4-
bit wide (nibble) data bus and control signals for transmit and receive data.
The µPD98433 supports a nibble data bus and control signals for transmission/reception for each port.
In order to use the MII interface, set the GMII/MII field of the PYTBIC register of the TBI to 1 and set the IFMOD
field of the MACC2 register to ‘01’.
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3.8.4 MII management interface
The µPD98433 provides an MII management interface, which is a 2-wire serial interface for access between PHY
devices using MII management interface frames. This interface is used to access registers of an external PHY device
or internal PCS (TBI) module.
(1) MDC clock
The µPD98433 generates the MDC clock that is used by the MII management interface by dividing the clock
that is input to the HCLK pin. To satisfy IEEE standards, it is necessary to set a division ratio suited to HCLK
input. The division ratio is set according to the CLKS field of the MIIC register. Table 3-5 shows the
relationship between HCLK input and CLKS field settings.
The MDC clock is stopped when the µPD98433 is started, when software reset that is effected by the SRST bit
of the MACC1 register is executed, or when the MII management module is reset by the SRST bit of the MIIC
register. Its operation is started and the clock is output when software reset by the SRST bit of the MACC1
register and MII management module reset by the SRST bit of the MIIC register are released.
Table 3-5. CLKS Field of MIIC Register and Frequency of MDC
MIIC:CLKS
Frequency of MDC
Bit 2
0
Bit 1
0
Bit 0
0
HCLK divided by 4
0
0
1
HCLK divided by 4
HCLK divided by 6
HCLK divided by 8
HCLK divided by 10
HCLK divided by 14
HCLK divided by 20
HCLK divided by 28
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
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(2) MII management frame data
Figure 3-13 shows the MII management frame structure.
Figure 3-13. MII Management Frame Structure
(a) Write
MDC
MDIO
(Output)
(Data)
(Preamble) = all 1
(Start bit) = 01
(Operation) = 01
(Turnaround) = 10
PHYAD REGAD
(b) Read or scan
MDC
MDIO
(Output)
(Preamble) = all 1
(Start bit) = 01
(Operation) = 10
PHYAD
REGAD
MDIO
(Input)
MDI
(Input data)
(Turnaround)
The µPD98433 automatically generates the preamble and start bits in an MII management frame. The opcode
is added automatically in response to reading from or writing to an external PHY device register. PHYAD and
REGAD, which show the device address of a PHY device and the address of a register within that PHY device,
have the values set in the PYAD and RGAD fields of the MADR register, respectively, added.
An operation to read from a PHY device is executed by making the RSTAT bit of the MCMD register 1. An
operation to write to a PHY device is executed by writing data in the MCTL field of the MWTD register.
The µPD98433 first serially outputs data from the preamble through REGAD as an MDIO signal and outputs
the data set in the MCTL field of the MWTD register after turnaround if it is a write access. For a read access,
serial data is input using an MDIO signal and is written in the MSTA field of the MSTA register.
Preamble generation can be suppressed by setting the PRESUP bit of the MIIC register.
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(3) Access procedures
MII management frames are transmitted and received as follows.
First, check the BUSY bit of the MIND register to check whether or not there is a current MII management
access. If the BUSY bit is on, wait until it is turned off. Next, set the target external PHY device address and
the address of the register in the PHY in the PYAD field and RGAD field of the MADR register, respectively.
For a write access, access is started by writing write data in the MCTL field of the MWTD register. The BUSY
bit is turned on when writing to the MWTD register and turned off when write access ends.
For a read access, access is started by setting the RSTAT bit of the MCMD register from 0 to 1. When the
RSTAT bit is set to 1, the BUSY bit is on; the BUSY bit is off after read access ends. The host system can
obtain the read data by reading the MSTA field of the MSTA register after confirming that the BUSY bit is off.
The MII management interface block provides a SCAN command for continuously reading a specific PHY
register. By setting the SCAN bit of the MCMD register to 1, read accesses occur continuously and a specific
PHY register can be polled by reading the MSTA field of the MSTA register.
3.8.5 µPD98433 connection of MII output signal pins
When connecting an MII output signal (TXD, TX_EN, TX_ER, MDC, or MDIO) to a PHY device, connect a 26 Ω to
48 Ω series resistor to each MII output signal as shown in Figure 3-14 in order to make the drive capacity of the MII
output buffer match the IEEE802.3 standard.
Figure 3-14. Connection of MII Output Signal Pin
µPD98433
26 Ω to 48 Ω
External PHY device
TXD/TX_EN/TX_ER/MDC/MDIO
TXD/TXEN/TXER/MDC/MDIO
3.8.6 Auto-negotiation
The µPD98433 has an auto-negotiation function that is compliant with IEEE 802.3 Chapter 37. This function is
valid only when operating in TBI mode.
In order to access the PHY register or status that controls auto-negotiation, access it using the MII management
interface. Auto-negotiation is performed as follows.
First, write base page data in the PYANA register. Next, write 1 in the RAN bit of the PYCNT register to restart
auto-negotiation. Wait for the PRX bit of the PYANEX register to become 1 and for page swapping to end. After the
PRX bit of the PYANEX register becomes 1, read the PYANBP register. At this time, if the NEXT PAGE function is
supported both locally and by the link partner, write next page data in the PYANNP register. Then wait for the PRX bit
of the PYANEX register to become 1 and for page swapping to end. After the PRX bit of the PYANEX register
becomes 1, read the PYANLPN register. If there is further NEXT PAGE data to transmit either locally or on the link
partner, write the next page data in the PYANNP register and perform a NEXT PAGE swap.
If the NEXT PAGE function is not supported either locally or by the link partner, when NEXT PAGE swapping ends,
wait for the AND bit of the PYSTS register to become 1 and for auto-negotiation to complete. If the AND bit of the
PYSTS register becomes 1, a link is established and normal transmission/reception is possible.
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3.9 Flow Control
The µPD98433 realizes flow control by performing the pause control frame processing in IEEE 802.3 Chapter 31.
The purpose of flow control is to reduce the frequency of transmitting packets that were transmitted from another
terminal that is connected point-to-point in full-duplex operation. In a system, there are limits on the capacity of on-
chip receive FIFO. If frames are received with a certain frequency and the higher layer cannot cope with them
continuously, a receive FIFO overflow may occur. Flow control is used to prevent such a receive FIFO overflow.
When a pause control frame is received, the value of the pause timer field of the control frame is loaded in the
pause timer in the MAC. If the pause timer is not 0, the next transmit is started after the time specified in the pause
timer elapses.
On the other hand, to suppress data transmission from another terminal on the network, generate the reserved
multicast address (01-80-C2-00-00-01), pause opcode, and 16-bit pause timer value and transmit them as a pause
control frame.
3.9.1 Control frame reception
The µPD98433 enables control frame receive detection when the RFCEN bit of the MACC1 register is 1. Detection
of a pause control frame is performed by checking the destination address and the opcode of the type field. In order
for a receive data stream to be detected as a pause control frame, it must have either the reserved multicast address
(01-80-C2-00-00-01) or a unicast address given by the MAC in the destination address. In addition, it must have
8808H in the length/type field and the correct pause opcode 0001H in the control opcode field.
When the µPD98433 receives a valid pause control frame, it suppresses transmission for the period of the pause
timer value that the received pause control packet contains.
3.9.2 Flow control pause timer
The flow control pause timer, which is used as a 16-bit wide timer, stores the pause timer value of a received pause
control frame. If the pause timer value of the pause control frame is not 0, it shows that a new frame should not be
transmitted. If the pause timer value of the received control frame is 0, normal transmission is resumed.
If the RFCEN bit of the MACC1 register is 0, the value loaded in the pause timer is ignored. Regardless of the
setting of the RFCEN bit, the pause timer always is updated when a valid control frame is received. When the setting
of the RFCEN bit is changed, a software reset must be performed using the RMCRST bit of the MACC1 register.
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3.9.3 Pause control frame transmission
The µPD98433 generates and transmits pause control frames according to the status of receive FIFO use and
designation by an external pin.
(1) Pause control frame issuance by FIFO threshold value specification
When the FLWCNT bit of the MACC3 register is 1, the µPD98433 automatically generates and transmits pause
control frames according to the relationship between the amount of data in receive FIFO and the threshold
values set in the RFWMH field and RFWML field of the RFIC1 register.
When the FLWCNT bit is 1, if the amount of data in receive FIFO exceeds the threshold level set in the
RFWMH field of the RFIC1 register, a pause control frame is transmitted automatically. (Figure 3-15) If there
is a data frame already being transmitted when an attempt is made to transmit a pause control frame, the
pause control frame is transmitted after waiting for transmission of that frame to end.
The pause control frame transmitted at this time is generated as follows. The reserved multicast address (01-
80-C2-00-00-01) is given as the destination address and the station address set in the LSA1 register and LSA2
register is added as the source address.
8808H and the pause opcode 0001H are added in the length/type field and control opcode field, respectively,
and the value set in the PTIME field of the CFPT register is added as the value of the pause timer.
Once the amount of data in receive FIFO exceeds the value of the RFWMH field and the pause control frame
has been automatically transmitted, the data stored in receive FIFO is transferred to the host system. When
the amount of data in receive FIFO falls below the threshold level set in the RFWML field, the µPD98433
generates a pause control frame in which the pause timer value is 0 and automatically transmits it to prompt a
transmit resume from the destination.
Figure 3-15. Pause Control Frame Transmission
RFWMH
RFWML
Time
: Pause frame transmitted
: 0 pause frame transmitted
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(2) Pause retransmission interval timer
The µPD98433 sets the initial value of the pause retransmission interval counter according to the setting of the
IPTIME field of the ICFPT register. The pause retransmission interval timer starts a countdown when a pause
control frame is sent, and if the amount of data stored in receive FIFO when it reaches 0 exceeds the threshold
value set in the RFWMH field of the RFIC1 register, it automatically transmits a pause control frame again,
prompting an extension of the pause period.
When the amount of data in receive FIFO exceeds the value of the RFWMH field of the RFIC1 register and a
pause control frame is transmitted, the next pause control frame is not transmitted until the IPTIME period
ends, even if the value of the RFWMH field is exceeded. If the value of the RFWMH field is exceeded after the
IPTIME period ends, a pause control frame is transmitted. (Figure 3-16 (a))
When the amount of data in receive FIFO exceeds the value of the RFWMH field of the RFIC1 register and a
pause control frame is transmitted, a pause control frame is transmitted again if the RFWMH field is exceeded
when the IPTIME period ends. (Figure 3-16 (b))
When the amount of data in receive FIFO exceeds the value of the RFWMH field of the RFIC1 register and a
pause control frame is transmitted, if the value of the RFWMH field of the RFIC1 register is exceeded again
during the IPTIME period after the amount of data in receive FIFO falls below the value of the RFWML field of
the RFIC1 register and a 0 pause control frame is transmitted, a pause frame is transmitted regardless of the
IPTIME period. (Figure 3-16 (c))
If 0 is written in the IPTIME field of the ICFPT register by the µPD98433, the pause retransmission interval
timer function is disabled.
Figure 3-16. Reissuance of Pause Control Frame by Pause Retransmission Interval Timer (1/2)
(a) Issuance of pause control frame after pause period elapses
RFWMH
RFWML
IPTIME
Time
: Pause frame transmitted
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Figure 3-16. Reissuance of Pause Control Frame by Pause Retransmission Interval Timer (2/2)
(b) Reissuance of pause control frame when pause period elapses
RFWMH
RFWML
IPTIME
: Pause frame transmitted
Time
(c) Issuance of zero pause control frame during pause period
RFWMH
RFWML
IPTIME
: Pause frame transmitted
: 0 pause frame transmitted
Time
(3) Designation of pause control frame issuance by external pin
The µPD98433 can designate issuance of a pause control frame using the external pins FCn (n = 0 to 7).
These eight signal pins correspond to port numbers n (n = 0 to 7).
When the memory or FIFO of a higher layer device is about to overflow, the higher layer device can assert an
FC pin to designate transmission of a pause control frame.
The pause value of the pause control frame that is issued uses the value set in the PTIME field of the CFPT
register.
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3.10 Back Pressure
The µPD98433 has an on-chip back pressure function. This function, which is valid only for half-duplex operation,
is enabled if the amount of data in receive FIFO exceeds the threshold level set in the RFWMH field of the RFIC1
register when the BACKPE bit of the MACC3 register is 1. A dummy packet is transmitted when this function is
enabled. During a back-off period that is generated by collision of transmission of a normal packet, a dummy packet is
transmitted after completion of the back-off period. Data in receive FIFO is transferred to the host system and this
function is disabled when the amount of data in receive FIFO falls below the value of the RFWMH field of the RFIC1
register. A collision that occurs at the time of backpressure is not counted as a collision.
3.11 Operations on VLAN Frames
If the TPID field of a receive or transmit packet contains the VLAN protocol identifier 8100H, the µPD98433
recognizes it as a VLAN frame. Operations on VLAN frames are shown in the paragraphs below. Since each
configuration sets registers by port, operations can be configured for each port.
3.11.1 VLAN frame detection
The µPD98433 always compares the value of the 2-octet TPID field that follows the source address in a receive
packet or transmit packet to the value of the VLAN protocol identifier (8100H). A packet for which the two values
match is considered a VLAN frame by the µPD98433.
3.11.2 VLAN frame reception
When the value of the TPID field in a receive packet matches the value of the VLAN protocol identifier (8100H), the
VLAN bit of the RSVREG register is set to 1. In this case, decisions about the receive frame size are made based on
a maximum of 1522 bytes and a minimum of 64 bytes. When filtering using the SIFT bit of the RFIC2 register (short
packet discard), packet discard is performed using falling short of 64 bytes as the criterion even if a receive packet is
recognized as a VLAN frame.
3.11.3 VLAN frame transmission
When transmitting a frame given as a transmit frame from a higher layer in which the value of the TPID field
matches the VLAN type (8100H), it is recognized as a VLAN frame and the TVLTF bit of the TSVREG register is set to
1.
3.12 Statistics Counters
The µPD98433 has an effective statistics counter set incorporated for each port in order to realize RMON and
SNMP. Statistics counters, which are configured as 32-bit counters, provide the host system with 51 kinds of
information about transmission and reception.
Statistics counters count and save items of statistical information related to packet transmission/reception. (See
CHAPTER 5 STATISTICS COUNTERS for the items counted.) Statistics counters are updated whenever a packet
transmit or a packet receive terminates. Status information is stored in the status FIFO in the µPD98433 after an
operation terminates, and statistics counters are updated in turn based on that information.
Each counter is cleared to 0 if an overflow occurs and counting continues. Moreover, if an overflow occurs in a
counter or an overflow occurs in the status FIFO, the corresponding bits of the CAR1 register and CAR2 register are
set to 1, which causes an interrupt to occur. This interrupt can be masked by counter using the CAM1 register and
CAM2 register.
Statistics counters are cleared by a hardware reset. They also are cleared by a counter read when the ATZ bit if
the STLC register is set to 1.
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3.13 Loopback
Setting the LPBK bit of the MACC1 register to 1 loops back a GMII/MII transmit data stream internally as a
GMII/MII receive data stream. TXCLKn is connected to RXCLKn internally. COLn and CRSn are ignored. When used
in loopback, the FULLD bit of the MACC2 register must be set to 1 to set full-duplex operation mode. These settings
can be made independently for each port. In the loopback, the transmission output (TXD, TX_EN, TX_ER) stops.
3.14 Low Power Mode
The µPD98433 has an on-chip configuration register for decreasing power consumption when there are unused
ports. By setting a bit of the POWD register to 1, it is possible to cut clock supply to the corresponding port block to
lower power consumption.
Set the low power mode after transmission/reception is stopped, by clearing the TEN and REN bit of the MACC1
register to 0. Ports for which 1 is set in the POWD register enter sleep mode and are eliminated by round-robin from
the sequence in a receive operation.
Since HCLK is not supplied to a port in sleep mode, it is not possible to access port configuration registers during
sleep. Moreover, since the previous settings of a register that has entered sleep mode are not retained, they must be
reset after sleep is canceled.
If sleep mode is entered without clearing an interrupt source, an INT# signal may be asserted. Since port
configuration registers cannot be accessed and cleared in sleep mode, set ports to sleep mode by setting the POWD
register after setting the TEN and REN bits of the MACC1 register to 0, and clearing interrupt sources of the ports in
question.
To set a port to sleep mode during a read operation from receive FIFO or a write operation to transmit FIFO, do so
after the FIFO bus operation for the relevant port becomes IDLE.
If sleep is set while receiving from a network or while transmitting to a network, the packet being received or
transmitted is ended. Data already stored in FIFO also is not saved. When canceling sleep, initialize FIFO using the
TXFFLH bit of the MACC3 register and RXFFLH bit of the MACC3 register after sleep mode cancellation and execute
a software reset. (See 3.15 regarding the software reset procedure.)
Moreover, the MII serial management interface cannot be used if port 0 is set to sleep mode.
The procedure for setting sleep mode is as follows. First, perform a software reset of ports to be set to sleep mode.
Next, set ports to be set to sleep mode using the bits of the relevant ports in the POWD (FFH) register.
The procedure for canceling sleep mode is as follows. First, reset the bits of the relevant ports in sleep mode in the
POWD (FFH) register. Next, perform a software reset of ports for which sleep mode was canceled.
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3.15 Software Reset
The µPD98433 requires software resets at the following times.
• After switching TBI, GMII, and MII modes
• After manually changing full-duplex and half-duplex operation
• After switching normal operation and loopback mode
Follow the procedure below for setting or canceling a software reset of the µPD98433.
Reset setup procedure
(1) Set the TEN and REN bits of the MACC1 register to 0.
(2) Set the RST bit of the PYCNT register to 1.
(3) Set the SRT bit of the PYTBIC register to 1.
(4) Set the SRST bit of the MIIC register to 1 (port 0 only).
(5) Set the TFRST, RFRST, TMCRST, RMCRST, and SRST bits of the MACC1 register to 1.
(6) Set the TXFFLH and RXFFLH bits of the MACC3 register to 1.
(7) Set the RST bit of the STLC register to 1.
Reset cancellation procedure
(1) Set the RST bit of the STLC register to 0.
(2) Set the RXFFLH bit of the MACC3 register to 0.
(3) Set the RFRST, RMCRST, and SRST bits of the MACC1 register to 0.
(4) Set the SRST bit of the MIIC register to 0.
(5) Set the SRT bit of the PYTBIC register to 0.
(6) Set the TFRST and TMCRST bits of the MACC1 register to 0.
(7) Set the TXFFLH bit of the MACC3 register to 0.
(8) Set the TEN and REN bits of the MACC1 register to 1.
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3.16 Turning Power ON
The µPD98433 has two types of power supply pins: 2.5 V power supply pins for internal units (VDD), 3.3 V power
supply pins for physical layer interface I/O buffers (VDDQ).
This section explains the sequence when power is turned ON.
Figure 3-17. Recommended Timing of Turning Power ON
3.3 V
2.5 V
0 V
10 ms
Keep the time difference from when the 2.5-V or 3.3-V power supply rises first to when both the power supplies are
stabilized to within 10 ms.
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4.1 Control Register Map
(1) Port control register map
(1/2)
Register Address
HA[7:0]
Name
Function
R/W
Default
00H
MACC1
MACC2
IPGIFG
HDREG
LMAX
−
MAC configuration register 1
MAC configuration register 2
IPG/IFG register
R/W
8000 0000H
0000 7201H
4060 5060H
00A0 F037H
0000 0600H
−
01H
R/W
R/W
R/W
R/W
02H
03H
Half-duplex configuration register
Maximum frame length configuration register
Reserved
04H
05H to 07H
08H
−
MIIC
MII serial management configuration register
MII serial management command register
MII serial management address register
MII serial management write data register
MII serial management read data register
MII serial management indicator
PHY configuration register
Reserved
R/W
R/W
R/W
R/W
RO
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
−
09H
MCMD
MADR
MWTD
MSTA
MIND
PHYC
−
0AH
0BH
0CH
0DH
0EH
0FH
RO
R/W
−
−
10H
LSA1
LSA2
−
Station address register 1
Station address register 2
Reserved
R/W
R/W
0000 0000H
0000 0000H
−
11H
12H to 1BH
1CH
1DH
1EH
1FH
CAR1
CAR2
CAM1
CAM2
STLC
AFR
Carry register 1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 FFFFH
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
Carry register 2
Carry mask register 1
Carry mask register 2
20H
Statistics counter configuration register
Address filter configuration register
HASH table 1
21H
22H
HT1
23H
HT2
HASH table 2
24H
CFPT
ICFPT
MACC3
TIMR
RIMR
TSVREG
RSVREG
MACC pause value configuration register
Internal pause timer register
MAC configuration register 3
Transmit interrupt mask timer
Receive interrupt mask timer
Transmit status register
25H
26H
27H
28H
29H
2AH
Receive status register
Caution Do not access addresses that are “Reserved”.
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(2/2)
Register Address
HA[7:0]
Name
Function
R/W
Default
2BH
FSVREG
−
FIFO status register
R/W
0000 0000H
−
2C to 2FH
30H
Reserved
−
RFIC1
RFIC2
RFIC3
TFIC1
TFIC2
UFCR
−
Receive FIFO configuration register 1
Receive FIFO configuration register 2
Receive FIFO configuration register 3
Transmit FIFO configuration register 1
Transmit FIFO configuration register 2
User field configuration register
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
17FF 0000H
0000 000FH
1FFF 1FFFH
1200 0600H
0000 0000H
0000 0000H
−
31H
32H
33H
34H
35H
36H to 44H
−
Caution Do not access addresses that are “Reserved”.
(2) Global register map
Register Address
HA[7:0]
Name
Function
R/W
Default
FAH
−
Reserved
−
−
FBH
FCH
FDH
FEH
FFH
STIR
Status information register
FIFO configuration register
Clock check register
RO
0000 0000H
0000 0000H
07FF FFFFH
0000 0001H
0000 0000H
MISCR
CLKCHK
VERID
POWD
R/W
R/W
RO
Version register
Power down control register
R/W
Caution Do not access addresses that are “Reserved”.
(3) PCS configuration register map
Register Address
RGAD[4:0]
Name
Function
R/W
Default
00H
PYCNT
PYSTS
−
Control register
Status register
Reserved
R/W
RO
0000H
0149H
−
01H
02H and 03H
04H
−
PYANA
PYANBP
PYANEX
PYANNP
PYANLPN
PYEX
Auto-Negotiation Advertisement register
Auto-Negotiation Link Partner Base Page Ability register
Auto-Negotiation extension register
Auto-Negotiation Next Page Transmit register
Auto-Negotiation Link Partner Ability Next Page register
Extension status register
R/W
RO
0010H
0000H
0004H
0000H
0000H
A000H
0000H
0004H
05H
06H
RO
07H
R/W
RO
08H
0FH
RO
10H
PYJTR
PYTBIC
Jitter diagnosis register
R/W
R/W
11H
TBI control register
Caution Do not access addresses that are “Reserved”.
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4.2 Port Configuration Registers
Port configuration registers are registers for defining the operation of each port or for checking the status of each
port. In order to access the registers of each port, the port number is input in HA[10:8] of the address bus HA[10:0]
and the address of the register is input in HA[7:0].
MACC1 - MAC configuration register 1 (Register address HA[7:0] = 00H) R/W
31
30
29
28
27
26
25
24
23
22
21
20
4
19
18
17
16
SRST
Reserved
RMCRST TMCRST RFRST TFRST
15
14
13
12
11
10
9
8
7
6
5
3
2
1
0
Reserved
LPBK
Reserved
RFCEN
Reserved
REN Reserved TEN
(1/2)
Bit
Name
SRST
Function
Default
31
Software reset
1
Setting this bit resets MAC module. It does not reset the register setting.
30:20
19
−
Reserved
Write 0.
−
RMCRST
TMCRST
RFRST
MAC receive control block software reset
0
0
0
0
Setting this to 1 enables software reset. To cancel software reset, 0 must be
written.
18
17
16
MAC transmit control block software reset
Setting this to 1 enables software reset. To cancel software reset, 0 must be
written.
MAC receive block software reset
Setting this to 1 enables software reset. To cancel software reset, 0 must be
written.
TFRST
MAC transmit block software reset
Setting this to 1 enables software reset. To cancel software reset, 0 must be
written.
15:9
8
−
Reserved
Write 0.
−
−
LPBK
Loopback
0
0
Setting this bit loops back MAC transmit output to MAC receive input within
the MAC module. Clearing this bit makes operation normal.
7:6
5
−
Reserved
Write 0.
RFCEN
Receive flow control enable
Setting this bit detects pause flow control frames and starts the MAC control
receive block. Clearing this bit makes the MAC control receive block ignore
pause flow control frames.
4
−
Reserved
Write 1.
Note
Note After a reset, this bit is set to 0. Set this bit to 1 in register settings.
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CHAPTER 4 REGISTER DESCRIPTION
(2/2)
Bit
Name
Function
Default
3
2
−
Reserved
−
Write 0.
REN
Receive enable
0
0
Setting this bit enables frame reception from PHY. Setting it to 0 stops frame
reception.
1
0
−
Reserved
Write 0.
−
TEN
Transmit enable
Setting this bit enables the MAC to transmit frames from a system. Setting it
to 0 stops frame transmission.
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CHAPTER 4 REGISTER DESCRIPTION
MACC2 - MAC configuration register 2 (Register address HA[7:0] = 01H) R/W
31
30
29
28
27
26
25
24
23
22
21
20
4
19
3
18
2
17
1
16
0
Reserved
15
14
13
12
11
10
9
8
7
6
5
PRELN
Reserved
IFMOD
Reserved
HUGEN LENCK Reserved PADEN CRCEN FULLD
Bit
Name
Function
Default
31:16
−
Reserved
Write 0.
−
15:12
PRELN
Preamble length
7H
Specifies the length of the preamble of a packet in bytes. The range of
settings is as follows.
5H ≤ PRELN ≤ FH
The default value is 7H.
11:10
−
Reserved
Write 0.
−
9:8
IFMOD
Interface mode
2H
This field determines the type of interface the MAC is connecting.
00 = Reserved
01 = Nibble mode (10/100 Mbps MII)
10 = Byte mode (1000 Mbps GMII/TBI)
11 = Reserved
7:6
−
Reserved
Write 0.
−
5
HUGEN
Huge frame enable
0
0
This bit is set to enable the transmission/reception of frames that are longer
than LMAX. Clear this bit for the MAC to limit the length of a transmit or
receive frame to LMAX. When frame length is limited, be careful of
occurrence conditions of transmit and receive status and count conditions of
statistics counters.
4
LENCK
Length field check
Setting this bit confirms that the value of the frame length field matches the
actual data field length and outputs to transmit and receive status. Clear this
bit if length field checking is not needed.
3
2
−
Reserved
Write 0.
−
PADEN
PAD/CRC enable
0
Setting this bit performs the following operations.
(1) Perform CRC addition.
(2) For a packet whose packet length is less than 64 bytes, perform
padding and then add CRC.
1
0
CRCEN
FULLD
CRC enable
0
1
Setting this bit performs CRC addition. If the configuration bit PADEN or
PAD/CRC enable of TXFDQ is specified, the setting of the CRCEN bit is
ignored. The default value is 0.
Full-duplex
Setting this bit operates in full-duplex mode. Clearing this bit operates in half-
duplex mode.
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CHAPTER 4 REGISTER DESCRIPTION
IPGIFG - IFG/IPG register (Register address HA[7:0] = 02H) R/W
31
30
29
28
27
26
25
24
23
22
6
21
5
20
4
19
18
2
17
1
16
0
Reserved
IPGR1
Reserved
IPGR2
15
14
13
12
11
10
9
8
7
3
MINIFG
Reserved
IPGT
Bit
Name
Function
Default
−
31
−
Reserved
Write 0.
30:24
IPGR1
NON-BACK-TO-BACK INTER-PACKET-GAP PART 1
40H
This field shows the carrierSense period within the inter-packet gap when
transmitting. (The carrierSense period within the IPG is defined by IEEE
802.3/4.2.3.2.1 ‘Carrier Deference’.) The range and condition of settings are
as follows.
8H(8) ≤ IPGR1 ≤ 60H(96)
(IPGR2-38H) ≤ IPGR1 ≤ (IPGR2-1CH)
23
−
Reserved
Write 0.
−
22:16
IPGR2
NON-BACK-TO-BACK INTER-PACKET-GAP PART 2
This field shows the minimum period between packets when transmitting. It is
set in BitTime units. The range of settings is as follows.
40H(64) ≤ IPGR2 ≤ 7FH(127)
60H
50H
15:8
MINIFG
Minimum IFG
This field sets the minimum period between frames when receiving. A frame
for which the inter-frame gap is shorter than this value is not received. This is
set in BitTime units. The range of settings is as follows.
For 10/100 Mbps: 14H(20) ≤ MINIFG ≤ FFH(255)
For 1000 Mbps:
When status information addition is set Note 1
60H(96) ≤ MINIFG ≤ FFH(255)
When status information addition is not set Note 1
28H(40) ≤ MINIFG ≤ FFH(255)
7
−
Reserved
Write 0.
−
6:0
IPGT
BACK-TO-BACK INTER-PACKET-GAP
60H
This field shows the minimum period between packets when transmitting. This
value is used when in full-duplex mode or when transmitting continuously. It is
set in BitTime units. The range of settings is as follows.
For 10/100 Mbps: 40H(64) ≤ IPGT ≤ 7FH(127)
For 1000 Mbps:
When CRC automatic addition is set Note 2
48H(72) ≤ IPGT ≤ 7FH(127)
When CRC automatic addition is not set Note 2
68H(104) ≤ IPGT ≤ 7FH(127)
Notes 1. The status information is appended when the APSS or APSE bit of the MACC3 register is set to 1.
2. CRC automatic appending means specification by the TXFDQ signal or setting of the CRCE or PADEN bits
of the MACC2 register to 1.
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CHAPTER 4 REGISTER DESCRIPTION
HDREG - Half-duplex configuration register (Register address HA[7:0] = 03H) R/W
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
ABEXT
ABEXE BKPNB NBOF Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RTMAX
Reserved
COLW
Bit
Name
Function
Default
31:24
−
Reserved
Write 0.
−
23:20
ABEXT
ALTERNATE BINARY EXPONENTIAL BACKOFF TRUNCATION
0AH
When the ALTERNATE BINARY EXPONENTIAL BACKOFF ENABLE bit is
set, backoff time is calculated using this field. The backoff time r (slotTime)
calculated using this value is as follows.
0 ≤ r < 2n
n = ABEXT if n exceeds ABEXT when set value is less than 0AH.
n = 0AH if n exceeds ABEXT when set value is 0AH or greater.
19
ABEXE
BKPNB
ALTERNATE BINARY EXPONENTIAL BACKOFF ENABLE
Setting this bit makes settings that use the above ALTERNATE BINARY
EXPONENTIAL BACKOFF TRUNCATION instead of the value that is the
criterion in IEEE802.3.
0
0
18
Back pressure no backoff
Setting this bit sets the MAC so that retransmission is possible immediately
after a collision without taking a backoff period in the case of a back pressure
operation. Clearing this bit makes this follow the binary exponential backoff
rule.
17
NBOF
No backoff
0
Setting this bit sets the MAC so that retransmission is possible immediately
after a collision without taking a backoff period. Clearing this bit makes this
follow the binary exponential backoff rule.
16
−
Reserved
Write 0.
−
−
15:12
RTMAX
Maximum retransmissions
0FH
37H
This sets the maximum number of retransmissions due to collisions. Specify
0FH (15d) to conform with the IEEE802.3 standard.
11:10
9:0
−
Reserved
Write 0.
COLW
Collision window
This configuration field corresponds to the slot time in which collisions occur
(collision window) in an appropriately configured network. Since the collision
window starts from the beginning of a transmit, the preamble and SFD are
included. The relationship between the setting and the actual collision window
is collision window = HDREG:COLW + 9.
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CHAPTER 4 REGISTER DESCRIPTION
LMAX - Maximum frame length configuration register (Register address HA[7:0] = 04H) R/W
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
16
0
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
LMAX
Bit
Name
Function
Default
31:16
−
Reserved
Write 0.
−
15:0
LMAX
Maximum frame length
0600H
This field sets a limit on the maximum frame length in both the transmit and
receive directions. On a transmit, if the transmit packet length exceeds the
value set in LMAX, the transmit aborts. On a receive, the operation differs
according to the setting of the THRX field of the RFIC3 register. If THRX =
1FFFH, a packet that exceeds LMAX is rejected in receive FIFO. If another
value is set in THRX, the value of LMAX is invalid. Set a value of 40H (64) or
more to LMAX.
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CHAPTER 4 REGISTER DESCRIPTION
MIIC - MII serial management configuration register (Register address HA[7:0] = 08H) R/W
31
30
29
28
27
26
25
24
23
22
21
20
19
18
2
17
16
0
SRST
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
1
Reserved
PRESUP Reserved
CLKS
Bit
Name
SRST
Function
Default
31
MII management module reset
0
Setting this bit resets the MII management module. Clearing this bit makes it
possible to use MII management module in order to execute a serial
management read/write cycle.
30:5
−
Reserved
Write 0.
−
4
PRESUP
Preamble suppression
0
Setting this bit reduces a management cycle to 32 clocks to omit preamble
generation. This is an optional function described in IEEE 802.3/22.2.4.4.2.
When this bit is cleared, a management cycle requires 64 clocks in order to
execute a management read/write cycle after 32-clock generation of the
preamble.
3
−
Reserved
Write 0.
−
2:0
CLKS
MII management clock select
000
This field determines the clock frequency of the serial management clock
(MDC). The settings of this field are as follows.
000 = HCLK divided by 4
001 = HCLK divided by 4
010 = HCLK divided by 6
011 = HCLK divided by 8
100 = HCLK divided by 10
101 = HCLK divided by 14
110 = HCLK divided by 20
111 = HCLK divided by 28
Caution When accessing this register, input 000B in HA[10:8].
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CHAPTER 4 REGISTER DESCRIPTION
MCMD - MII serial management command register (Register address HA[7:0] = 09H) R/W
31
30
29
28
27
26
25
24
23
22
21
20
19
18
2
17
1
16
0
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
Reserved
SCAN RSTAT
Bit
Name
Function
Default
31:2
1
−
Reserved
Write 0.
−
SCAN
RSTAT
Scan cycle
0
0
Setting this bit executes a read cycle continuously. This can be used, for
example, to monitor link failure.
0
Read cycle
Setting this bit executes a read cycle one time. The read data is returned in
MSTA register.
This bit is a write only.
Caution When accessing this register, input 000B in HA[10:8].
MADR - MII serial management address register (Register address HA[7:0] = 0AH) R/W
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
16
0
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Reserved
PYAD
Reserved
RGAD
Bit
Name
Function
Default
31:13
−
Reserved
Write 0.
−
12:8
PYAD
PHY address
00H
00H
This field corresponds to the 5-bit PHY address field of a management cycle.
A maximum of 32 PHY address specifications can be made.
7:5
−
Reserved
Write 0.
−
4:0
RGAD
Register address
This field corresponds to the 5-bit register address field of a management
cycle. A maximum of 32 registers can be accessed.
Caution When accessing this register, input 000B in HA[10:8].
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CHAPTER 4 REGISTER DESCRIPTION
MWTD - MII serial management write data register (Register address HA[7:0] = 0BH) R/W
31
30
29
28
27
26
25
24
23
22
21
20
19
18
2
17
1
16
0
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
MCTL
Bit
Name
Function
Default
31:16
−
Reserved
−
15:0
MCTL
MII write data
0000H
Performing a write to this register executes an MII management write cycle.
The PHY address and register address of the MII management frame are set
using the value set in the MADR register (0AH) and write data is set using the
value set in MWTD (08H).
Caution When accessing this register, input 000B in HA[10:8].
MSTA - MII serial management read data register (Register address HA[7:0] = 0CH) Read only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
16
0
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
MSTA
Bit
Name
Function
Default
31:16
−
Reserved
Write 0.
−
15:0
MSTA
MII read data
0000H
The 16-bit data read by an MII management read cycle can be read from this
register.
Caution When accessing this register, input 000B in HA[10:8].
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CHAPTER 4 REGISTER DESCRIPTION
MIND - MII serial management indicator (Register address HA[7:0] = 0DH) Read only
31
30
29
28
27
26
25
24
23
22
21
20
19
3
18
17
1
16
0
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
2
Reserved
NVAL
SCAN BUSY
Bit
Name
Function
Default
31:3
2
−
Reserved
Write 0.
−
NVAL
MSTA register invalid
0
0
0
If 1 is returned in this bit, it shows that the MII management read cycle did not
complete or the read data is not yet valid.
1
0
SCAN
BUSY
Scan
If 1 is returned in this bit, it shows that a scan operation (continuous MII
management read cycles) is in progress.
Busy
If 1 is returned in this bit, it shows that the MII management block currently is
executing an MII management read or write cycle.
Caution When accessing this register, input 000B in HA[10:8].
PHYC - PHY configuration register (Register address HA[7:0] = 0EH) R/W
31
30
29
28
27
26
25
24
23
22
21
20
4
19
3
18
17
1
16
0
Reserved
15
14
13
12
11
10
9
8
7
6
5
2
Reserved
TBIAD
Bit
Name
Function
Default
31:5
4:0
−
Reserved
Write 0.
−
TBIAD
TBI module address
This sets the address value by which the TBI module of each port is
00000
referenced in MII serial management. Set values so they do not overlap with
another physical layer.
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CHAPTER 4 REGISTER DESCRIPTION
LSA1 - Station address register 1 (Register address HA[7:0] = 10H) R/W
31
30
29
28
27
26
25
24
23
22
21
20
4
19
3
18
2
17
1
16
0
STA1
STA3
STA2
STA4
15
14
13
12
11
10
9
8
7
6
5
Bit
Name
Function
Default
31:24
23:16
15:8
7:0
STA1
STA2
STA3
STA4
Station address, 1st octet
00H
00H
00H
00H
This field contains a station address SA[7:0]. SA[7:0] is written in 31:24.
Station address, 2nd octet
This field contains a station address SA[15:8]. SA[15:8] is written in 23:16.
Station address, 3rd octet
This field contains a station address SA[23:16]. SA[23:16] is written in 15:8.
Station address, 4th octet
This field contains a station address SA[31:24]. SA[31:24] is written in 7:0.
In MII/GMII/TBI, station addresses are transmitted and received in the order 6th → 5th → 4th → 3rd → 2nd → 1st
octet.
LSA2 - Station address register 2 (Register address HA[7:0] = 11H) R/W
31
30
29
28
27
26
25
24
23
22
21
20
4
19
3
18
2
17
1
16
0
STA5
STA6
15
14
13
12
11
10
9
8
7
6
5
Reserved
Bit
Name
Function
Default
31:24
23:16
15:0
STA5
Station address, 5th octet
00H
This field contains a station address SA[39:32]. SA[39:32] is written in 31:24.
STA6
Station address, 6th octet
00H
This field contains a station address SA[47:40]. SA[47:40] is written in 23:16.
−
Reserved
Write 0.
−
In MII/GMII/TBI, station addresses are transmitted and received in the order 6th → 5th → 4th → 3rd → 2nd → 1st
octet.
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CHAPTER 4 REGISTER DESCRIPTION
CAR1 - CARRY register 1 (Register address HA[7:0] = 1CH) R/W
31
30
29
28
27
26
25
24
23
22
6
21
20
4
19
3
18
2
17
1
16
C1R64 C1R127 C1R255 C1R511 C1R1K C1RMAX C1REXD
Reserved
C1RBY
15
14
13
12
11
10
9
8
7
5
0
C1RPK C1RFC C1RMC C1RBC C1RXC C1RXP C1RXU C1RAL C1RFL C1RCD C1RCS C1RUN C1ROV C1RFR C1RJB C1RDR
CAR1 shows that statistics counters overflowed. Each bit corresponds to a statistics counter and 1 is written in the
corresponding bit when an overflow occurs in a statistics counter. See CHAPTER 5 STATISTICS COUNTERS
regarding the statistics counters.
Bit
Name
C1R64
Function
Default
31
30
29
28
27
26
25
R64 counter carry bit
R127 counter carry bit
R255 counter carry bit
R511 counter carry bit
R1K counter carry bit
RMAX counter carry bit
REXD counter carry bit
0
0
0
0
0
0
0
C1R127
C1R255
C1R511
C1R1K
C1RMAX
C1REXD
−
24:17
Reserved
Write 0.
−
16
15
14
13
12
11
10
9
C1RBY
C1RPK
C1RFC
C1RMC
C1RBC
C1RXC
C1RXP
C1RXU
C1RAL
C1RFL
C1RCD
C1RCS
C1RUN
C1ROV
C1RFR
C1RJB
C1RDR
RBYT counter carry bit
RPKT counter carry bit
RFCS counter carry bit
RMCA counter carry bit
RBCA counter carry bit
RXCF counter carry bit
RXPF counter carry bit
RXUO counter carry bit
RALN counter carry bit
RFLR counter carry bit
RCDE counter carry bit
RCSE counter carry bit
RUND counter carry bit
ROVR counter carry bit
RFRG counter carry bit
RJBR counter carry bit
RDRP counter carry bit
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
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CHAPTER 4 REGISTER DESCRIPTION
CAR2 - Carry register 2 (Register address HA[7:0] = 1DH) R/W
31
30
29
28
27
26
25
24
23
22
6
21
5
20
19
18
17
16
C2T64 C2T127 C2T255 C2T511 C2T1K C2TMAX C2TEXD
Reserved
C2TPAR C2TJB C2TFC C2TCF C2TOV
15
14
13
12
11
10
9
8
7
4
3
2
1
0
C2TUN C2TFG C2TBY C2TPK C2TMC C2TBC C2TPF C2TDF C2TED C2TSC C2TMA C2TLC C2TXC C2TNC Reserved C2TDP
Bit
Name
C2T64
Function
Default
31
30
29
28
27
26
25
T64 counter carry bit
T127 counter carry bit
T255 counter carry bit
T511 counter carry bit
T1K counter carry bit
TMAX counter carry bit
TEXD counter carry bit
0
0
0
0
0
0
0
C2T127
C2T255
C2T511
C2T1K
C2TMAX
C2TEXD
−
24:21
Reserved
Write 0.
−
20
19
18
17
16
15
14
13
12
11
10
9
C2TPAR
C2TJB
C2TFC
C2TCF
C2TOV
C2TUN
C2TFG
C2TBY
C2TPK
C2TMC
C2TBC
C2TPF
C2TDF
C2TED
C2TSC
C2TMA
C2TLC
C2TXC
C2TNC
−
TFPE counter carry bit
TJBR counter carry bit
TFCS counter carry bit
TXCF counter carry bit
TOVR counter carry bit
TUND counter carry bit
TFRG counter carry bit
TBYT counter carry bit
TPKT counter carry bit
TMCA counter carry bit
TBCA counter carry bit
TXPF counter carry bit
TDFR counter carry bit
TEDF counter carry bit
TSCL counter carry bit
TMCL counter carry bit
TLCL counter carry bit
TXCL counter carry bit
TNCL counter carry bit
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
Reserved
Write 0.
−
0
C2TDP
TDRP counter carry bit
0
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CHAPTER 4 REGISTER DESCRIPTION
CAM1 - Carry mask register (Register address HA[7:0] = 1EH) R/W
31
30
29
28
27
26
25
24
23
22
21
20
4
19
3
18
2
17
1
16
M1R64 M1R127 M1R255 M1R511 M1R1K M1RMAX M1REXD
Reserved
M1RBY
15
14
13
12
11
10
9
8
7
6
5
0
M1RPK M1RFC M1RMC MC1RBC M1RXC M1RXP M1RXU M1RAL M1RFL M1RCD M1RCS M1RUN M1ROV M1RFR MC1RJB M1RDR
CAM1 masks INT# signals that occur when bits within the CAR1 register are set to 1. Setting a bit to 1 cancels the
masking. Masking can be done by bit.
Bit
Name
M1R64
Function
Default
31
30
29
28
27
26
25
R64 counter carry mask bit
R127 counter carry mask bit
R255 counter carry mask bit
R511 counter carry mask bit
R1K counter carry mask bit
RMAX counter carry mask bit
REXD counter carry mask bit
0
0
0
0
0
0
0
M1R127
M1R255
M1R511
M1R1K
M1RMAX
M1REXD
−
24:17
Reserved
Write 0.
−
16
15
14
13
12
11
10
9
M1RBY
M1RPK
M1RFC
M1RMC
M1RBC
M1RXC
M1RXP
M1RXU
M1RAL
M1RFL
M1RCD
M1RCS
M1RUN
M1ROV
M1RFR
M1RJB
M1RDR
RBYT counter carry mask bit
RPKT counter carry mask bit
RFCS counter carry mask bit
RMCA counter carry mask bit
RBCA counter carry mask bit
RXCF counter carry mask bit
RXPF counter carry mask bit
RXUO counter carry mask bit
RALN counter carry mask bit
RFLR counter carry mask bit
RCDE counter carry mask bit
RCSE counter carry mask bit
RUND counter carry mask bit
ROVR counter carry mask bit
RFRG counter carry mask bit
RJBR counter carry mask bit
RDRP counter carry mask bit
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
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CHAPTER 4 REGISTER DESCRIPTION
CAM2 - Carry mask register 2 (Register address HA[7:0] = 1FH) R/W
31
30
29
28
27
26
25
24
23
22
21
5
20
19
18
17
16
M2T64 M2T127 M2T255 M2T511 M2T1K M2TMAX M2TEXD
Reserved
M2TPAR M2TJB M2TFC M2TCF M2TOV
15
14
13
12
11
10
9
8
7
6
4
3
2
1
0
M2TUN M2TFG M2TBY M2TPK M2TMC M2TBC M2TPF M2TDF M2TED M2TSC M2TMA M2TLC M2TXC M2TNC Reserved M2TDP
Bit
Name
M2T64
Function
Default
31
30
29
28
27
26
25
T64 counter carry mask bit
T127 counter carry mask bit
T255 counter carry mask bit
T511 counter carry mask bit
T1K counter carry mask bit
TMAX counter carry mask bit
TEXD counter carry mask bit
0
0
0
0
0
0
0
M2T127
M2T255
M2T511
M2T1K
M2TMAX
M2TEXD
−
24:21
Reserved
Write 0.
−
20
19
18
17
16
15
14
13
12
11
10
9
M2TPAR
M2TJB
M2TFC
M2TCF
M2TOV
M2TUN
M2TFG
M2TBY
M2TPK
M2TMC
M2TBC
M2TPF
M2TDF
M2TED
M2TSC
M2TMA
M2TLC
M2TXC
M2TNC
−
TFPE counter carry mask bit
TJBR counter carry mask bit
TFCS counter carry mask bit
TXCF counter carry mask bit
TOVR counter carry mask bit
TUND counter carry mask bit
TFRG counter carry mask bit
TBYT counter carry mask bit
TPKT counter carry mask bit
TMCA counter carry mask bit
TBCA counter carry mask bit
TXPF counter carry mask bit
TDFR counter carry mask bit
TEDF counter carry mask bit
TSCL counter carry mask bit
TMCL counter carry mask bit
TLCL counter carry mask bit
TXCL counter carry mask bit
TNCL counter carry mask bit
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
Reserved
Write 0.
−
0
M2TDP
TDRP counter carry mask bit
0
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CHAPTER 4 REGISTER DESCRIPTION
STLC - Statistics counter configuration register (Register address HA[7:0] = 20H) R/W
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
16
0
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Reserved
ATZ
Reserved RST
Bit
Name
Function
Default
31:3
−
Reserved
Write 0.
−
2
1
0
ATZ
Statistics counter read reset
0
−
0
If set to 1, statistics counters are reset on a read.
−
Reserved
Write 0.
RST
Statistics counter software reset
If set to 1, software reset is set.
AFR - Address filter configuration register (Register address HA[7:0] = 21H) R/W
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
PRO
AUC
PRM
AMC
ABC
Bit
Name
Function
Default
31:5
4
−
Reserved
Write 0.
−
PRO
AUC
Promiscuous mode
0
0
When this bit is 1, packets of all destination addresses are received.
3
Unicast receive
When this bit is 1, all unicast packets are received.
When this bit is 0, unicast packets set in LSA1 and LSA2 are received.
2
PRM
Multicast receive
0
When this bit is 1, all multicast packets are received.
When receiving a broadcast packet at this time, it receives as a kind of the
multicast packet.
When this bit is 0, multicast packets set in AMC are received.
1
0
AMC
ABC
Conditional multicast receive
0
0
When this bit is 1, multicast packets selected using hash tables are received.
When this bit is 0, multicast packets are not received.
Broadcast receive
When this bit is 1, broadcast packets are received.
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CHAPTER 4 REGISTER DESCRIPTION
HT1 - HASH table 1 (Register address HA[7:0] = 22H) R/W
31
30
29
28
27
26
25
24
23
22
6
21
5
20
4
19
3
18
2
17
1
16
0
HT1[31:16]
15
14
13
12
11
10
9
8
7
HT1[15:0]
Bit
Name
HT1
Function
Default
0000 0000H
31:0
HASH table 1
This is the higher table of the hash tables used in address filtering of multicast
packets.
HT2 - HASH table 2 (Register address HA[7:0] = 23H) R/W
31
30
29
28
27
26
25
24
23
22
6
21
5
20
4
19
3
18
2
17
1
16
0
HT2[31:16]
15
14
13
12
11
10
9
8
7
HT2[15:0]
Bit
Name
HT2
Function
Default
0000 0000H
31:0
HASH table 2
This is the lower table of the hash tables used in address filtering of multicast
packets.
CFPT - MACC pause value configuration register (Register address HA[7:0] = 24H) R/W
31
30
29
28
27
26
25
24
23
22
21
20
19
18
2
17
1
16
0
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
PTIME[15:0]
Bit
Name
Function
Default
31:16
−
Reserved
Write 0.
−
15:0
PTIME
Pause parameter
FFFFH
This specifies the pause period of an opposing device that is given in a pause
control frame in pause_quanta units (512 bit time).
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CHAPTER 4 REGISTER DESCRIPTION
ICFPT - Internal pause timer register (Register address HA[7:0] = 25H) R/W
31
30
29
28
27
26
25
24
23
22
21
20
4
19
3
18
2
17
1
16
0
Reserved
15
14
13
12
11
10
9
8
7
6
5
IPTIME[15:0]
Bit
Name
Function
Default
31:16
−
Reserved
Write 0.
−
15:0
IPTIME
Pause retransmission interval timer
0000H
This register sets the initial value of the pause retransmission interval timer in
pause_quanta units (512-bit time). The pause retransmission interval timer
begins a countdown when a pause control frame is sent and if the amount of
data stored in receive FIFO exceeds a threshold value (RFWMH field of the
RFIC1 register) when it reaches 0, it automatically sends a pause frame again
to extend the pause period.
Writing 0 in this field disables the pause retransmission interval timer function.
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CHAPTER 4 REGISTER DESCRIPTION
MACC3 - MAC configuration register 3 (Register address HA[7:0] = 26H) R/W
31
30
29
28
27
26
25
24
23
22
21
20
4
19
3
18
2
17
1
16
0
Reserved
15
14
13
12
11
10
9
8
7
6
5
Reserved
APSE
APSS Reserved BACKPE FLWCNT TXFFLH RXFFLH
Bit
Name
−
Function
Default
31:7
6
Reserved
Write 0.
−
APSE
APSS
Status information addition (end of packet data)
0
When this bit is 1, status information is added at the end of a packet. Do not
set APSE and APSS to 1 simultaneously.
5
Status information addition (start of packet data)
0
When this bit is 1, status information is added at the start of a packet. Do not
set APSE and APSS to 1 simultaneously.
4
3
2
1
−
Reserved
Write 0.
−
BACKPE
FLWCNT
TXFFLH
Back pressure enable
0
0
0
When this bit is 1, the back pressure function is enabled.
Transmit flow control enable
When this bit is 1, automatic transmission of pause control frames is enabled.
Transmit FIFO flash
When this bit is 1, all contents of a transmit FIFO are cleared. To cancel this
function, 0 must be written.
Use the function of this bit only within the flow of software reset, and do not
use FIFO flash independently.
0
RXFFLH
Receive FIFO flash
0
When this bit is 1, all contents of a receive FIFO are cleared. To cancel this
function, 0 must be written.
Use the function of this bit only within the flow of software reset, and do not
use FIFO flash independently.
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CHAPTER 4 REGISTER DESCRIPTION
TIMR - Transmit interrupt mask register (Register address HA[7:0] = 27H) R/W
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
ITPER ITFOV ITFUN ITWMH
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ITVLTF IBPA
ITPCF
ITCF ITURUN ITGNT ITLCOL ITMXCO ITEDFR ITDFR ITBRO ITMUL ITDONE ITFLOR ITFLER ITCRCE
TIMR masks the occurrence of INT# signals by cause. Setting each bit to 1 cancels masking.
(1/2)
Bit
31:20
Name
Function
Default
−
Reserved
Write 0.
−
19
18
17
16
15
14
13
12
11
10
9
ITPER
Transmit FIFO parity error
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
If 0, the interrupt of the corresponding bit of the FSVREG register is masked.
ITFOV
ITFUN
ITWMH
ITVLTF
IBPA
Transmit FIFO overrun
If 0, the interrupt of the corresponding bit of the FSVREG register is masked.
Transmit FIFO underrun
If 0, the interrupt of the corresponding bit of the FSVREG register is masked.
Transmit full level exceeded
If 0, the interrupt of the corresponding bit of the FSVREG register is masked.
VLAN frame transmit
If 0, the interrupt of the corresponding bit of the TSVREG register is masked.
Back pressure
If 0, the interrupt of the corresponding bit of the TSVREG register is masked.
ITPCF
ITCF
Pause control frame transmit
If 0, the interrupt of the corresponding bit of the TSVREG register is masked.
Control frame transmit
If 0, the interrupt of the corresponding bit of the TSVREG register is masked.
ITURUN
ITGNT
ITLCOL
ITMXCO
ITEDFR
ITDFR
ITBRO
ITMUL
ITDONE
Transmit underrun occurrence
If 0, the interrupt of the corresponding bit of the TSVREG register is masked.
Transmission of packet longer than LMAX
If 0, the interrupt of the corresponding bit of the TSVREG register is masked.
Late collision
If 0, the interrupt of the corresponding bit of the TSVREG register is masked.
8
Excessive collisions
If 0, the interrupt of the corresponding bit of the TSVREG register is masked.
7
Excessive delay
If 0, the interrupt of the corresponding bit of the TSVREG register is masked.
6
Transmission delay
If 0, the interrupt of the corresponding bit of the TSVREG register is masked.
5
Broadcast packet transmit
If 0, the interrupt of the corresponding bit of the TSVREG register is masked.
4
Multicast packet transmit
If 0, the interrupt of the corresponding bit of the TSVREG register is masked.
3
Transmission termination
If 0, the interrupt of the corresponding bit of the TSVREG register is masked.
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CHAPTER 4 REGISTER DESCRIPTION
(2/2)
Bit
Name
ITFLOR
Function
Default
2
1
0
Length field check
0
0
0
If 0, the interrupt of the corresponding bit of the TSVREG register is masked.
ITFLER
ITCRCE
Data length mismatch
If 0, the interrupt of the corresponding bit of the TSVREG register is masked.
Transmit CRC error
If 0, the interrupt of the corresponding bit of the TSVREG register is masked.
RIMR - Receive interrupt mask register (Register address HA[7:0] = 28H) R/W
31
30
29
28
27
26
25
24
23
22
21
20
4
19
18
17
16
Reserved
IRFOV IRWMH IRWML Reserved
15
14
13
12
11
10
9
8
7
6
5
3
2
1
0
Reserved VLAN USOP RPCF RCFR DBNB RBRO RMUL
ROK
RLOR RLER RCRCE RCV
RFCA REPS RPPD
RIMR masks the occurrence of INT# signals by cause. Setting each bit to 1 cancels masking.
(1/2)
Bit
31:20
Name
Function
Default
−
Reserved
Write 0.
−
19
18
17
16:15
14
13
12
11
10
9
IRFOV
Receive FIFO overflow
0
0
0
If 0, the interrupt of the corresponding bit of the FSVREG register is masked.
IRWMH
IRWML
−
Pause frame transmission level
If 0, the interrupt of the corresponding bit of the FSVREG register is masked.
Zero frame transmission level
If 0, the interrupt of the corresponding bit of the FSVREG register is masked.
Reserved
Write 0.
−
VLAN
USOP
RPCF
RCFR
DBNB
RBRO
RMUL
ROK
VLAN frame
0
0
0
0
0
0
0
0
If 0, the interrupt of the corresponding bit of the RSVREG register is masked.
Undefined opcode control frame receive
If 0, the interrupt of the corresponding bit of the RSVREG register is masked.
Pause control frame receive
If 0, the interrupt of the corresponding bit of the RSVREG register is masked.
Control frame receive
If 0, the interrupt of the corresponding bit of the RSVREG register is masked.
Dribble nibble error
If 0, the interrupt of the corresponding bit of the RSVREG register is masked.
Broadcast packet receive
If 0, the interrupt of the corresponding bit of the RSVREG register is masked.
8
Multicast packet receive
If 0, the interrupt of the corresponding bit of the RSVREG register is masked.
7
Receive termination
If 0, the interrupt of the corresponding bit of the RSVREG register is masked.
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CHAPTER 4 REGISTER DESCRIPTION
(2/2)
Bit
Name
RLOR
Function
Default
6
5
4
3
2
1
0
Length field check
0
0
0
0
0
0
0
If 0, the interrupt of the corresponding bit of the RSVREG register is masked.
RLER
RCRCE
RCV
Data length mismatch
If 0, the interrupt of the corresponding bit of the RSVREG register is masked.
CRC error
If 0, the interrupt of the corresponding bit of the RSVREG register is masked.
RXER detection
If 0, the interrupt of the corresponding bit of the RSVREG register is masked.
RFCA
REPS
RPPD
False Carrier detection
If 0, the interrupt of the corresponding bit of the RSVREG register is masked.
Invalid packet receive
If 0, the interrupt of the corresponding bit of the RSVREG register is masked.
Receive packet ignored
If 0, the interrupt of the corresponding bit of the RSVREG register is masked.
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CHAPTER 4 REGISTER DESCRIPTION
TSVREG - Transmit status register (Register address HA[7:0] = 29H) R/W
31
30
29
28
27
26
25
24
23
22
21
20
4
19
3
18
2
17
1
16
0
Reserved
15
14
13
12
11
10
9
8
7
6
5
TVLTF
BPA
TPCF
TCF TURUN TGNT TLCOL TMXCO TEDFR TDFR TBRO TMUL TDONE TFLOR TFLER TCRCE
This register shows the interrupt source when the INT# signal is low level due to the status of a transmit packet
(except Reserved). When the interrupt source of each bit occurs, the corresponding bit is set to 1 and the INT# signal
is made low level. When an interrupt occurs due to a source that is masked by the TIMR register, it sets the
corresponding bit to 1 but does not cause the INT# signal to be made low level.
This register is updated whenever a transmit terminates or a transmit abort occurs.
If the SRRC bit of the MISCR register is set to 1, reading this register automatically clears all of its bits.
(1/2)
Bit
31:16
Name
Function
Default
−
Reserved
Write 0.
−
15
14
TVLTF
VLAN frame transmitted
0
0
If 1, this shows that the length/type field of the transmit frame contained the
VLAN protocol identifier 8100H.
BPA
Back pressure
If 1, this shows that a dummy packet was transmitted due to back pressure
after the previous transmit.
13
12
11
TPCF
TCF
Pause control frame transmitted
0
0
0
If 1, this shows that a pause control frame was transmitted.
Control frame transmitted
If 1, this shows that a control frame was transmitted.
TURUN
Transmit abort occurred
This shows that a transmit was aborted due to a transmit underrun or a parity
error.
10
TGNT
Packet longer than LMAX transmitted
0
If 1, this shows that a packet longer than the packet length set in the LMAX
register was transmitted. This bit is 1 only when the HUGEN bit of the MACC2
register is 0.
9
8
7
6
TLCOL
TMXCO
TEDFR
TDFR
Late collision
0
0
0
0
If 1, this shows that a collision occurred outside the collision window set in the
HDREG register.
Excessive collisions
If 1, this shows that more collisions occurred than the maximum number of
retransmissions set in the HDREG register.
Excessive delay
If 1, this shows that excessive delay (transmit could not start after 24288 bit
time elapsed) occurred.
Transmit delay
If 1, this shows that a transmit delay occurred. If the transmit is aborted, it
does not become 1 (this occurs if a transmit succeeds).
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CHAPTER 4 REGISTER DESCRIPTION
(2/2)
Bit
Name
TBRO
Function
Default
5
4
3
2
Broadcast packet transmitted
0
0
0
0
If 1, this shows that a broadcast packet was transmitted. If the transmit is
aborted, it does not become 1 (this occurs if a transmit succeeds).
TMUL
Multicast packet transmitted
If 1, this shows that a multicast packet was transmitted. If the transmit is
aborted, it does not become 1 (this occurs if a transmit succeeds).
TDONE
TFLOR
Transmit termination
If 1, this shows that a transmit terminated normally. If the transmit is aborted,
it does not become 1 (this occurs if a transmit succeeds).
Length field check
If 1, this shows that the value of the length field in a transmit packet exceeds
1500. If the LENCK bit of the MACC2 register is 0, this bit does not become 1
(this occurs if a transmit succeeds).
1
TFLER
Data length mismatch
0
If 1, this shows that the value of the length field does not match the length of
the data field in a transmit packet. If the LENCK bit of the MACC2 register is
0, this bit does not become 1. Moreover, if the value of the length field
exceeds 1500, TFLOR becomes 1 but TFLER becomes 0. In cases in which
the length field value is less than 46, this status is invalid (this occurs if a
transmit succeeds).
Transmit CRC error
0
TCRCE
0
If 1, this shows that the CRC code the host added to a transmit packet is
incorrect. The case of CRC error is as follows.
• When the resending after the collisions, a transmit was aborted due to a
transmit underrun.
• When aborted by a transmit underrun.
• When aborted by a Excessive collisions.
• When aborted by a Late collision.
• When truncated by LMAX.
Caution This bit does not become 1 when the transmit is aborted by
transmit delay or when the CRCEN bit of the MACC2 register is 1.
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CHAPTER 4 REGISTER DESCRIPTION
RSVREG - Receive status register (Register address HA[7:0] - 2AH) R/W
31
30
29
28
27
26
25
24
23
22
21
20
4
19
3
18
2
17
1
16
0
Reserved
15
14
13
12
11
10
9
8
7
6
5
Reserved VLAN USOP RPCF RCFR DBNB RBRO RMUL
ROK
RLOR RLER RCRCE RCV
RFCA REPS RPPD
This register shows the interrupt source when the INT# signal is low level due to the status of a receive packet
(except Reserved). When the interrupt source of each bit occurs, the corresponding bit is set to 1 and the INT# signal
is made low level. When an interrupt occurs due to a source that is masked by the RIMR register, it sets the
corresponding bit to 1 but does not cause the INT# signal to be made low level.
This register is updated whenever a packet is received by the MAC module.
If the SRRC bit of the MISCR register is set to 1, reading this register automatically clears all of its bits.
(1/2)
Bit
31:15
Name
Function
Default
−
Reserved
Write 0.
−
14
13
12
11
VLAN
VLAN frame
0
0
0
0
If 1, this shows that the TPID field of the received packet matched the VLAN
type (8100H).
USOP
RPCF
RCFR
Control frame containing undefined opcode received
If 1, this shows that a control frame containing an undefined opcode was
received.
Pause control frame received
If 1, this shows that a pause control frame was received, If a CRC error
occurs, this bit does not become 1.
Control frame received
If 1, this shows that a control frame was received. If a CRC error occurs, this
bit does not become 1.
10
9
DBNB
RBRO
RMUL
ROK
Packet containing dribble nibble received
0
0
0
0
If 1, this shows that a dribble nibble occurred in the received packet.
Broadcast packet received
If 1, this shows that a broadcast packet was received.
8
Multicast packet received
If 1, this shows that a multicast packet was received.
7
Receive termination
If 1, this shows that a receive terminated. If a CRC error or RX_ER occurs
while receiving, this bit does not become 1.
6
RLOR
Length field check
0
If 1, this shows that the value of the length field of the received packet was a
value exceeding 1500.
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CHAPTER 4 REGISTER DESCRIPTION
(2/2)
Bit
Name
RLER
Function
Default
5
Data length mismatch
0
If 1, this shows that the value of the length field does not match the length of
the data field in a received packet. If the LENCK bit of the MACC2 register is
0, this bit does not become 1. Moreover, if the value of the length field
exceeds 1500, RLOR becomes 1 but RLER becomes 0. In cases in which the
length field value is less than 46, this status becomes 0.
4
3
2
RCRCE
RCV
CRC error
0
0
0
If 1, this shows that a CRC error occurred in the received packet.
Receive code error
While receiving a packet, 1 or more nibbles was detected as a code error.
RFCANote
Invalid carrier detection
If 1, this shows that a False Carrier was detected after the previous receive.
In MII mode, RX_ER = 1, RX_DV = 0, RXD[3:0] = EH
In GMII mode, RX_ER = 1, RX_DV = 0, RXD[7:0] = 0EH
In TBI mode, this shows that there was input such that “when a code other
than IDLE was received, that code line began with a code other than SPD”.
REPSNote
1
0
Invalid packet receive
0
0
If 1, this shows that there was an invalid packet receive after the last receive
(packet that has only preamble + SFD or 1 nibble of data). The invalid packet
that is the reason this bit is 1 is discarded internally by the MAC.
RPPDNote
Receive packet ignored
When this bit is 1, it indicates that IFG during reception is shorter than the
value set to the MINIFG field of the IPGIFG register and is not recognized as a
valid packet. The invalid packet that is the reason this bit is 1 is discarded
internally by the MAC.
Note The status of RSVREG[2:0] is reported when the next valid packet is received.
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FSVREG - FIFO status register (Register address HA[7:0] = 2BH) R/W
31
30
29
28
27
26
25
24
23
22
21
20
4
19
3
18
2
17
1
16
Reserved
TPER
15
14
13
12
11
10
9
8
7
6
5
0
Reserved
TFOV
TFUN TWMH
Reserved
RFOV RWMH RWML
This register shows the interrupt source when the INT# signal is low level due to each status (except Reserved).
When the interrupt source of each bit occurs, the corresponding bit is set to 1 and the INT# signal is made low level.
When an interrupt occurs due to a source that is masked by the TIMR register or RIMR register, it sets the
corresponding bit to 1 but does not cause the INT# signal to be made low level.
If the SRRC bit of the MISCR register is set to 1, reading this register automatically clears all of its bits.
Bit
31:17
Name
Function
Default
−
Reserved
−
16
TPER
Transmit FIFO parity error
0
This is set to 1 if a parity error was detected in FIFO data for a transmit.
15:11
10
−
Reserved
−
TFOV
TFUN
Transmit FIFO overrun
0
0
0
This is set to 1 if an overrun occurred in transmit FIFO.
9
8
Transmit FIFO underrun
This is set to 1 if an underrun occurred in transmit FIFO.
TWMH
Transmit full level exceeded
This is set to 1 when the amount of data in transmit FIFO exceeds the value
set in the TFWMH field of the TFIC1 register.
7:3
2
−
Reserved
−
RFOV
RWMH
RWML
Receive FIFO overflow
0
0
0
If the amount of data in receive FIFO exceeds the receive FIFO capacity, it is
considered an overflow and this bit is set to 1.
1
0
Pause frame transmission level exceeded
This bit is set to 1 if the amount of data in receive FIFO exceeds the value set
in the RFWMH field of the RFIC1 register.
Zero frame transmission level exceeded
This bit is set to 1 if the amount of data in receive FIFO exceeds the value set
in the RFWML field of the RFIC1 register.
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RFIC1 - Receive FIFO configuration register 1 (Register address HA[7:0] = 30H) R/W
31
30
29
28
27
26
25
24
23
22
21
20
19
3
18
2
17
1
16
0
Reserved
RFWMH
15
14
13
12
11
10
9
8
7
6
5
4
Reserved
RFWML
Bit
Name
Function
Default
31:29
−
Reserved
Write 0.
−
28:16
RFWMH
Pause frame transmission level
17FFH
When the transmit flow control function is enabled, a pause frame that has the
pause timer value that is set in the CFPT register is transmitted automatically
if the amount of data in receive FIFO exceeds this value.
15:13
12:0
−
Reserved
Write 0.
−
RFWML
Zero frame transmission level
0000H
Once the transmit flow control function is enabled and the amount of data in
receive FIFO exceeds the value set in the RFWMH field, a control frame in
which the pause timer value is 0 is transmitted automatically if the amount of
data becomes less than this value.
Caution Observe the following expression when setting RFWML and
RFWMH.
0 ≤ RFWML < RFWMH ≤ 17FFH
Caution Since RFWMH and RFWML are handled in word units, the lower 4 bits are ignored.
Consequently, the setting values must be the values after the lower 4 bits are ignored and in the
above range of settings.
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RFIC2 - Receive FIFO configuration register 2 (Register address HA[7:0] = 31H) R/W
31
30
29
28
27
26
25
24
23
22
21
20
19
18
2
17
1
16
0
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
Reserved
DDNB
SIFT DCRCE FCRX
Bit
Name
Function
Default
31:4
3
−
Reserved
Write 0.
−
DDNB
SIFT
Dribble nibble discard
1
1
If this bit is 1, dribble nibble packets are discarded.
2
Short packet discard
If this bit is 1, packets that are less than 64 bytes are discarded. Similarly, in
the case of VLAN packets, packets that are less than 64 bytes are discarded.
However, receive packets that are less than 16 bytes always are rejected.
1
0
DCRCE
FCRX
CRC error packet discard
1
1
If this bit is 1, packets that a CRC error or RX_ER occurred while receiving are
discarded.
Control packet discard
If this bit is 1, pause control frames are discarded. Undefined control frames
other than pause frames are not discarded.
Caution If the RXFA signal is asserted using a threshold value (THRX field of the RFIC3 register), the
above discard conditions cannot be used. Write 0 in all of them.
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RFIC3 - Receive FIFO configuration register 3 (Register address HA[7:0] = 32H) R/W
31
30
29
28
27
26
25
24
23
22
21
20
19
3
18
2
17
1
16
0
Reserved
THRX
15
14
13
12
11
10
9
8
7
6
5
4
Reserved
RXETH
Bit
Name
−
Function
Default
31:29
Reserved
Write 0.
−
28:16
THRX
Receive completed threshold value
1FFFH
If receive data in receive FIFO exceeds this THRX threshold value, the RXFA
signal is asserted. Use this threshold value when packet data that was
received before a packet receive finishes completely needs to be read. When
handling a Jumbo frame that exceeds 6 Kbytes, for example, one frame
cannot be stored in the receive FIFO. Therefore, the RXFA signal is asserted
by setting this threshold value. If EOF exists in the receive FIFO, the RXFA
signal is asserted even if the receive data does not exceed this threshold
value.
Set this threshold value in a range of 0020H ≤ THRX ≤ 17FFH. If THRX =
1FFFH, the RXFA signal is asserted when reception of one packet is
completed.
15:13
12:0
−
Reserved
Write 0.
−
RXETH
Receive FIFO status display configuration
1FFFH
When receive data increases and the pointer of the receive FIFO exceeds this
RXTH threshold value, the RXETH[7:0] signals are asserted. This is used to
monitor the quantity of data in the receive FIFO at the higher side. The eight
RXETH pins correspond to the corresponding port numbers.
Set this threshold value in a range of 0020H ≤ THRX ≤ 17FFH. If RXETH =
1FFFH, the RXETH[7:0] signals are not asserted.
Caution Since the lower 4 bits of each field are ignored, the above setting ranges are established using
values after the lower 4 bits are ignored.
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TFIC1 - Transmit FIFO configuration register 1 (Register address HA[7:0] = 33H) R/W
31
30
29
28
27
26
25
24
23
22
21
20
19
18
2
17
1
16
0
Reserved
TFWMH
15
14
13
12
11
10
9
8
7
6
5
4
3
Reserved
TFDWL
Bit
Name
Function
Default
31:29
−
Reserved
Write 0.
−
28:16
TFWMH
Transmit full level
1200H
If the amount of data in transmit FIFO is less than or equal to this value, the
µPD98433 makes the TXFBA[n] signal high level to show the host system that
there is space in transmit FIFO. If the amount of data in transmit FIFO
exceeds this value, it makes the TXFBA[n] signal low level.
Set this value in the range from 0040H to 17FFH.
15:13
12:0
−
Reserved
Write 0.
−
TFDWL
Transmit drain level
0600H
If the amount of data in transmit FIFO exceeds this value, packet transmission
begins.
Set this value above collision window (HDREG:COLW+9) in the range from
0040H to 17FFH.
Caution Since TFWMH and TFDWL are handled in word units, the lower 4 bits are ignored.
Consequently, the setting values must be the values after the lower 4 bits are ignored and the
above range of settings.
TFIC2 - Transmit FIFO configuration register 2 (Register address HA[7:0] = 34H) R/W
31
30
29
28
27
26
25
24
23
22
21
20
19
18
2
17
1
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
0
Reserved
DPAR
Bit
Name
Function
Default
31:1
0
−
Reserved
Write 0.
−
DPAR
Transmit suspended due to transmit FIFO parity error
0
If this bit is 1, transmission of a packet in which a parity error occurs is
suspended.
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UFCR - User field configuration register (Register address HA[7:0] = 35H) R/W
31
30
29
28
27
26
25
24
23
22
21
20
19
3
18
2
17
1
16
0
UFCR[31:16]
15
14
13
12
11
10
9
8
7
6
5
4
UFCR[15:0]
Bit
Name
UFCR
Function
Default
0000 0000H
31:0
User field
The value written in this register is output in RXFD[95:64] on output of status
and RBYT fields. Set it to transmit user-defined information to a higher layer
device.
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4.3 Global Registers
Global registers are registers that are used to make settings and check status for all ports. When accessing a
global register, only HA[7:0] of the address bus HA[10:0] is valid and HA[10:8] is ignored.
STIR - Status information register (Register address HA[7:0] = FBH) Read only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
P7TS
P7RS
P7FS
P7CA
P6TS
P6RS
P6FS
P6CA
P5TS
P5RS
P5FS
P5CA
P4TS
P4RS
P4FS
P4CA
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
P3TS
P3RS
P3FS
P3CA
P2TS
P2RS
P2FS
P2CA
P1TS
P1RS
P1FS
P1CA
P0TS
P0RS
P0FS
P0CA
If any bit of the registers TSVREG, RSVREG, FSVREG, CAR1, and CAR2 established for each port is set to 1, the
corresponding bit of this register is 1. Since this register shows the current state of each status register, when each
status register is cleared, the corresponding bit of this register also is cleared. Reading this register does not clear
each status register and does not deassert the INT# signal.
(1/2)
Bit
Name
P7TS
Function
Default
31
30
29
28
Port 7 TSVREG status
0
0
0
0
When any bit in the TSVREG register of port 7 is set to 1, this bit is set to 1.
P7RS
P7FS
P7CA
Port 7 RSVREG status
When any bit in the RSVREG register of port 7 is set to 1, this bit is set to 1.
Port 7 FSVREG status
When any bit in the FSVREG register of port 7 is set to 1, this bit is set to 1.
Port 7 CAR status
When any bit in the CAR1 or CAR2 register of port 7 is set to 1, this bit is set
to 1.
27
26
25
24
P6TS
P6RS
P6FS
P6CA
Port 6 TSVREG status
0
0
0
0
When any bit in the TSVREG register of port 6 is set to 1, this bit is set to 1.
Port 6 RSVREG status
When any bit in the RSVREG register of port 6 is set to 1, this bit is set to 1.
Port 6 FSVREG status
When any bit in the FSVREG register of port 6 is set to 1, this bit is set to 1.
Port 6 CAR status
When any bit in the CAR1 or CAR2 register of port 6 is set to 1, this bit is set
to 1.
23
22
21
20
P5TS
P5RS
P5FS
P5CA
Port 5 TSVREG status
0
0
0
0
When any bit in the TSVREG register of port 5 is set to 1, this bit is set to 1.
Port 5 RSVREG status
When any bit in the RSVREG register of port 5 is set to 1, this bit is set to 1.
Port 5 FSVREG status
When any bit in the FSVREG register of port 5 is set to 1, this bit is set to 1.
Port 5 CAR status
When any bit in the CAR1 or CAR2 register of port 5 is set to 1, this bit is set
to 1.
19
P4TS
Port 4 TSVREG status
0
When any bit in the TSVREG register of port 4 is set to 1, this bit is set to 1.
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(2/2)
Bit
Name
P4RS
Function
Default
18
17
16
Port 4 RSVREG status
0
0
0
When any bit in the RSVREG register of port 4 is set to 1, this bit is set to 1.
P4FS
P4CA
Port 4 FSVREG status
When any bit in the FSVREG register of port 4 is set to 1, this bit is set to 1.
Port 4 CAR status
When any bit in the CAR1 or CAR2 register of port 4 is set to 1, this bit is set
to 1.
15
14
13
12
P3TS
P3RS
P3FS
P3CA
Port 3 TSVREG status
0
0
0
0
When any bit in the TSVREG register of port 3 is set to 1, this bit is set to 1.
Port 3 RSVREG status
When any bit in the RSVREG register of port 3 is set to 1, this bit is set to 1.
Port 3 FSVREG status
When any bit in the FSVREG register of port 3 is set to 1, this bit is set to 1.
Port 3 CAR status
When any bit in the CAR1 or CAR2 register of port 3 is set to 1, this bit is set
to 1.
11
10
9
P2TS
P2RS
P2FS
P2CA
Port 2 TSVREG status
0
0
0
0
When any bit in the TSVREG register of port 2 is set to 1, this bit is set to 1.
Port 2 RSVREG status
When any bit in the RSVREG register of port 2 is set to 1, this bit is set to 1.
Port 2 FSVREG status
When any bit in the FSVREG register of port 2 is set to 1, this bit is set to 1.
8
Port 2 CAR status
When any bit in the CAR1 or CAR2 register of port 2 is set to 1, this bit is set
to 1.
7
6
5
4
P1TS
P1RS
P1FS
P1CA
Port 1 TSVREG status
0
0
0
0
When any bit in the TSVREG register of port 1 is set to 1, this bit is set to 1.
Port 1 RSVREG status
When any bit in the RSVREG register of port 1 is set to 1, this bit is set to 1.
Port 1 FSVREG status
When any bit in the FSVREG register of port 1 is set to 1, this bit is set to 1.
Port 1 CAR status
When any bit in the CAR1 or CAR2 register of port 1 is set to 1, this bit is set
to 1.
3
2
1
0
P0TS
P0RS
P0FS
P0CA
Port 0 TSVREG status
0
0
0
0
When any bit in the TSVREG register of port 0 is set to 1, this bit is set to 1.
Port 0 RSVREG status
When any bit in the RSVREG register of port 0 is set to 1, this bit is set to 1.
Port 0 FSVREG status
When any bit in the FSVREG register of port 0 is set to 1, this bit is set to 1.
Port 0 CAR status
When any bit in the CAR1 or CAR2 register of port 0 is set to 1, this bit is set
to 1.
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MISCR - FIFO configuration register (Register address HA[7:0] = FCH) R/W
31
30
29
28
27
26
25
24
23
22
21
20
19
3
18
2
17
1
16
Reserved
BUSMODE PSEL
PEN
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
0
Reserved
INTEN
Reserved
SRRC
Bit
Name
Function
Default
31:27
−
Reserved
Write 0.
−
26
BUSMODE
PSEL
FIFO I/F little endian/big endian selection
If this bit is 0, it specifies little endian.
If this bit is 1, it specifies big endian.
0
0
25
FIFO bus parity type selection
If this bit is 1, it specifies odd parity.
If this bit is 0, it specifies even parity.
If the number of ‘1’ bits among the data bits and parity bits transferred in 1
clock is an odd number, it is odd parity and if the number of ‘1’ bits is an even
number, it is even parity. TXFDQ and RXFDQ are not an object.
24
23:9
8
PEN
FIFO bus parity enable
0
0
0
If this bit is 1, parity is enabled.
−
Reserved
Write 0.
−
−
INTEN
−
Interrupt enable
If 1, this enables the function of the INT# signal.
7:1
0
Reserved
Write 0.
SRRC
Status register read clear configuration
If 1, each status register is cleared by a read operation.
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CLKCHK – Clock Check register (Register address HA[7:0] = FDH) R/W
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
TXFCK RXFCK GTX_REF_CLK TX_CLK7 TX_CLK6 TX_CLK5 TX_CLK4 TX_CLK3 TX_CLK2 TX_CLK1 TX_CLK0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RX_CLK71 RX_CLK61 RX_CLK51 RX_CLK41 RX_CLK31 RX_CLK21 RX_CLK11 RX_CLK01 RX_CLK70 RX_CLK60 RX_CLK50 RX_CLK40 RX_CLK30 RX_CLK20 RX_CLK10 RX_CLK00
This register shows the input status of each clock. First, write FFFFFFFH to reset this register. Then, create an
interval that is at least one cycle of the slowest clock signal. Subsequently, if 1 is read out when this register is read, it
indicates that the clock corresponding to that bit is stopped.
Note, however, that short-period clock stoppage, skipped clocks, and frequency abnormalities cannot be detected.
Also, the bit corresponding to the clock of a port set to power-down mode is 1.
Bit
31:27
Name
Function
Default
−
Reserved
−
Write 1 to these bits.
26
TXFCK
Transmit FIFO bus clock
1
1
1
1
1
1
When this bit is 1, the transmit FIFO bus clock is stopped.
25
RXFCK
Receive FIFO bus clock
When this bit is 1, the receive FIFO bus clock is stopped.
24
GTX_REF_CLK 1000 Mbps transmit clock
When this bit is 1, the 1000 Mbps transmit clock is stopped.
23:16
15:8
7:0
TX_CLK[7:0]
MII transmit clock
When this bit is 1, the MII transmit clock is stopped.
RX_CLK[7:0]1 Receive clock 1
When this bit is 1, the receive clock is stopped.
RX_CLK[7:0]0 Receive clock 0
When this bit is 1, the receive clock 0 is stopped.
VERID - Version register (Register address HA[7:0] = FEH) Read only
31
30
29
28
27
26
25
24
23
22
21
5
20
4
19
3
18
2
17
16
0
Reserved
15
14
13
12
11
10
9
8
7
6
1
Reserved
VER
Bit
Name
Function
Default
31:8
7:0
−
Reserved
Write 0.
−
VER
Version number
Consult an
NEC
This shows the version of the µPD98433.
Electronics
sales
representative.
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POWD - Power down control register (Register address HA[7:0] = FFH) R/W
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
P7
P6
P5
P4
P3
P2
P1
P0
Bit
Name
Function
Default
31:8
7
−
Reserved
Write 0.
−
P7
P6
P5
P4
P3
P2
P1
P0
Port 7 power down
0
0
0
0
0
0
0
0
This sets power down mode. Making this bit 1 cuts clock supply to the port
block in the device.
6
5
4
3
2
1
0
Port 6 power down
This sets power down mode. Making this bit 1 cuts clock supply to the port
block in the device.
Port 5 power down
This sets power down mode. Making this bit 1 cuts clock supply to the port
block in the device.
Port 4 power down
This sets power down mode. Making this bit 1 cuts clock supply to the port
block in the device.
Port 3 power down
This sets power down mode. Making this bit 1 cuts clock supply to the port
block in the device.
Port 2 power down
This sets power down mode. Making this bit 1 cuts clock supply to the port
block in the device.
Port 1 power down
This sets power down mode. Making this bit 1 cuts clock supply to the port
block in the device.
Port 0 power down
This sets power down mode. Making this bit 1 cuts clock supply to the port
block in the device.
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4.4 PCS Configuration Registers
The PCS configuration registers are a set of 16-bit wide registers that can be accessed via MII serial management.
PYCNT - Control register (Register address RGAD[4:0] = 00H) R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RST Reserved SP0
ANE
Reserved
RAN
DM
Reserved
SP1
Reserved
Bit
Name
RST
Function
Default
15
PHY reset
0
0
Setting this bit to 1 resets the “control register” and “status register” to default
values. This bit is cleared automatically after a reset.
14
13
−
Reserved
Write 0.
−
SP0
Speed selection
The combination of SP0 and SP1 selects the speed when operating in TBI
mode. This is ignored when operating in MII or GMII mode.
SP0 SP1
Maximum operation frequency
0
1
X
1
1
0
1000 Mbps
Reserved
Reserved
12
ANE
Auto-negotiation enable
0
Setting this bit to 1 enables auto-negotiation processing.
11:10
9
−
Reserved
Write 0.
−
RAN
DM
Auto-negotiation reset
0
0
Setting this bit to 1 restarts auto-negotiation. However, auto-negotiation must
be enabled. This bit is cleared automatically after a restart.
8
Duplex mode
Setting this bit to 1 makes operation full-duplex. A setting of 0 is designed for
half-duplex operation, but at present a setting of 0 cannot be used.
7
−
−
Reserved
Write 0.
−
−
6
SP1
Speed selection
See SP0
0
5:0
Reserved
Write 0.
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PYSTS - Status register (Register address RGAD[4:0] = 01H) Read only
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
EXS Reserved NPRE
AND
RF
ANA
LKS Reserved EXA
Bit
Name
Function
Default
15:9
8
−
Reserved
Write 0.
−
EXS
Extension status
1
This bit shows that register 15 (extension status) contains further PHY status
information. This bit is fixed to 1.
7
6
−
Reserved
Write 0.
−
NPRE
AND
Management frame preamble suppression enable
1
0
This bit shows that PHY can handle an MII management frame without a 32-
bit preamble field. This bit is fixed to 1.
5
4
Auto-negotiation complete
If this bit is 1, it shows that auto-negotiation processing completed. If this bit is
0, it shows that auto-negotiation is in processing or auto-negotiation function is
disabled.
RF
Remote fault
0
If this bit is 1, it shows that a remote fault was detected. When a remote fault
is detected, this bit maintains 1 until a register read. This bit is cleared when
the status register is read.
3
2
ANA
LKS
Auto-negotiation ability
1
0
This bit shows that the system has the ability to execute auto-negotiation. This
bit is fixed to 1.
Link status
If this bit is 1, it shows that a valid link was established. If this bit is 0, it shows
that a valid link could not be established. This bit maintains 0 until a register
read if a link could not be established.
1
0
−
Reserved
Write 0.
−
EXA
Extended function
1
This bit indicates that PHY has registers other than a control register (register
0) and a status register (register 1). This bit is fixed to 1.
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CHAPTER 4 REGISTER DESCRIPTION
PYANA - Auto-Negotiation Advertisement register (Register address RGAD[4:0] = 04H) R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NP
Reserved RF2
RF1
Reserved
ASD
PUS
HD
FD
Reserved
Bit
Name
Function
Default
15
NP
Next page
0
If this bit is 1, it requests transmission of the next page or reports to the link
partner that it has the ability to swap the next page. This bit can be set even if
the local device does not have next page data if it wants to enable a next page
receive. If there is no next page data on the local device and the link partner
wants to transmit the next page, the local device must transmit a null message
code as defined in Annex 28C. (A null message code is a message page that
has the value 000_0000_0001B) Clear this bit when the local device does not
want to swap the next page.
14
13
−
Reserved
Write 0.
−
RF2
RF1
Remote fault
00
The remote fault conditions of the local device are encoded in bits 13:12 of the
base page. Setting a remote fault to a value other than 00B and re-negotiating
shows a link failure.
Remote fault codes are as follows.
12
RF2 RF1
Definition
0
0
1
1
0
1
0
1
No errors, link OK
Off-line
Link failure
Auto-negotiation error
11:9
8
−
Reserved
Write 0.
−
ASD
PUS
Pause
00
The pause ability of the local device is set in bits 8:7.
The pause ability codes are as follows.
ASD PUS
Ability
0
1
0
1
0
0
1
1
No pauses
7
Asymmetrical pause for link partner
Symmetrical pause
Both symmetrical pause and asymmetrical pause for local
device
See Table 4-1 for information about resolving the order of precedence with a
link partner.
6
HD
FD
Half-duplex
0
1
Always write 0 in this bit.
5
Full duplex
Always write 1 in this bit.
4:0
−
Reserved
Write 0.
−
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CHAPTER 4 REGISTER DESCRIPTION
Table 4-1. Pause Order of Precedence Resolution Table
Local Device
Link Partner
Local Resolution
Link Partner Resolution
PAUSE
ASM_DIR
0
PAUSE
ASM_DIR
X
0
0
0
0
1
1
1
1
1
X
0
1
1
0
1
0
0
1
Pause transmit disabled
Pause receive disabled
Pause transmit disabled
Pause receive disabled
1
1
1
0
0
1
1
1
X
0
1
X
X
0
1
X
Pause transmit disabled
Pause receive disabled
Pause transmit disabled
Pause receive disabled
Pause transmit disabled
Pause receive disabled
Pause transmit disabled
Pause receive disabled
Pause transmit enabled
Pause receive disabled
Pause transmit disabled
Pause receive enabled
Pause transmit disabled
Pause receive disabled
Pause transmit disabled
Pause receive disabled
Pause transmit enabled
Pause receive enabled
Pause transmit enabled
Pause receive enabled
Pause transmit disabled
Pause receive disabled
Pause transmit disabled
Pause receive disabled
Pause transmit disabled
Pause receive enabled
Pause transmit enabled
Pause receive disabled
Pause transmit enabled
Pause receive enabled
Pause transmit enabled
Pause receive enabled
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CHAPTER 4 REGISTER DESCRIPTION
PYANBP - Auto-Negotiation Link Partner Base Page Ability register (Register address RGAD[4:0] = 05H)
Read only
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NP
Reserved RF1
RF0
Reserved
ASD
PUS
HD
FD
Reserved
Bit
Name
Function
Default
15
NP
Next page
0
A link partner asserts this bit to perform a next page transmit or to show its
ability to receive the next page. If this bit is 0, the link partner does not have
the next page or cannot receive the next page.
14
13
−
Reserved
Write 0.
−
RF1
RF0
Remote fault
00
The remote fault conditions of a link partner are encoded in bits 13:12 of the
base page. Remote fault codes are as follows.
RF1 RF0
Definition
12
0
1
0
1
0
0
1
1
No errors, link OK
Off-line
Link failure
Auto-negotiation error
11:9
8
−
Reserved
Write 0.
−
ASD
PUS
Pause
00
The pause ability of a link partner is encoded in bits 8:7 of the base page.
Pause ability codes are as follows.
ASD PUS
Ability
7
0
1
0
1
0
0
1
1
No pause
Asymmetrical pause for link partner
Symmetrical pause
Both symmetrical pause and asymmetrical pause for local
device
See Table 4-1 for information about resolving the order of precedence with a
link partner.
6
HD
FD
Half-duplex
0
0
If this bit is 1, it shows that the link partner can operate in half-duplex mode. If
this bit is 0, it shows that the link partner cannot operate in half-duplex mode.
5
Full-duplex
If this bit is 1, it shows that the link partner can operate in full-duplex mode. If
this bit is 0, it shows that the link partner cannot operate in full-duplex mode.
4:0
−
Reserved
Write 0.
−
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CHAPTER 4 REGISTER DESCRIPTION
PYANEX - Auto-Negotiation extension register (Register address RGAD[4:0] = 06H) Read only
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
NPA
PRX Reserved
Bit
Name
−
Function
Default
15:3
2
Reserved
Write 0.
−
NPA
PRX
Next page available
1
If this bit is 1, it shows that the local device supports the next page function.
This bit is fixed to 1.
1
0
Page receive
0
If this bit is 1, it shows that a new page was received and its value was written
to the PYANBP register or PYANLPN register appropriately. After a page
receive, this bit maintains 1 until it is read. This bit is cleared by a register
read.
−
Reserved
Write 0.
−
PYANNP - Auto-Negotiation Next Page Transmit register (Register address RGAD[4:0] = 07H) R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NP
Reserved
MP
AK2
TGL
MSGUFC
Bit
Name
Function
Default
15
NP
Next page
0
If this bit is 1, it shows that there is an additional next page. Clear it to show
that this page is the last page.
14
13
−
Reserved
Write 0.
−
MP
Message page
0
0
If this bit is 1, it shows a message page. Clear the bit to show an unformatted
page.
12
11
AK2
Acknowledge 2
This is used by the next page function to show that a device has the ability to
reply to messages. If this bit is 1, the local device replies to messages. Clear
the bit if the local device cannot reply to messages.
TGL
Toggle
0
This is used for page synchronization with a link partner between next page
swaps. This bit always takes the inverse of the value of the toggle bit of the
link code swapped immediately before. The initial value of the next page that
is transmitted first is the inverse of bit 11 of the base link code.
10:0
MSGUFC
Message/Unformat code field
000H
A message page is a formatted page that carries defined message codes.
Message types are enumerated in IEEE 802.3 Annex 28C. The unformat code
field takes arbitrary values.
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CHAPTER 4 REGISTER DESCRIPTION
PYANLPN - Auto-Negotiation Link Partner Ability Next Page register (Register address RGAD[4:0] = 08H)
Read only
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NP
Reserved
MP
AK2
TGL
MSGUFC
Bit
Name
Function
Default
15
NP
Next page
If this bit is 1, a link partner set this bit to show that there continues to be an
0
additional next page. If this bit is 0, it shows that this is the last next page from
the link partner.
14
13
−
Reserved
Write 0.
−
MP
Message page
0
0
If this bit is 1, it shows a message page. If this bit is 0, it shows an
unformatted page.
12
11
AK2
Acknowledge 2
This shows the ability of the link partner to reply to messages. If this bit is 1, it
shows that the link partner has the ability to reply to massages. If this bit is 0,
it shows that the link partner cannot reply to messages.
TGL
Toggle
0
This is used for page synchronization with a link partner between next page
swaps. This bit always takes the inverse of the value of the toggle bit of the
link code swapped immediately before. The initial value of the next page that
is transmitted first is the inverse of bit 11 of the base link code.
10:0
MSGUFC
Message/Unformat code field
000H
A message page is a formatted page that carries defined message codes.
Message types are enumerated in IEEE 802.3 Annex 28C. The unformat code
field takes arbitrary values.
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CHAPTER 4 REGISTER DESCRIPTION
PYEX - Extension status register (Register address RGAD[4:0] = 0FH) Read only
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GXF
GXH
GTF
GTH
Reserved
Bit
Name
Function
Default
15
GXF
GXH
GTF
GTH
1000BASE-X full-duplex
This bit is fixed to 1.
1
0
1
0
1: Shows that PHY can operate in 1000BASE-X full-duplex mode.
0: Shows that PHY cannot operate in 1000BASE-X full-duplex mode.
14
1000BASE-X half-duplex
This bit is fixed to 0.
1: Shows that PHY can operate in 1000BASE-X half-duplex mode.
0: Shows that PHY cannot operate in 1000BASE-X half-duplex mode.
13
1000BASE-T full-duplex
This bit is fixed to 1.
1: Shows that PHY can operate in 1000BASE-T full-duplex mode.
0: Shows that PHY cannot operate in 1000BASE-T full-duplex mode.
12
1000BASE-T half-duplex
This bit is fixed to 0.
1: Shows that PHY can operate in 1000BASE-T half-duplex mode.
0: Shows that PHY cannot operate in 1000BASE-T half-duplex mode.
11:0
−
Reserved
Write 0.
−
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CHAPTER 4 REGISTER DESCRIPTION
PYJTR - Jitter diagnosis register (Register address RGAD[4:0] = 10H) R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
JDE
JPS
Reserved
CJP
Bit
Name
Function
Default
15
JDE
JPS
Jitter diagnosis enable
If this bit is 1, the function that transmits jitter test patterns defined in IEEE
0
802.3 Annex 36A can be used. Clear this bit to make it possible to use normal
transmit operations. The default value is 0.
14:12
Jitter pattern selection
00
This selects the jitter pattern to transmit in jitter diagnosis mode.
JPS14 JPS13 JPS12
Jitter Pattern
Jitter pattern defined in CJP[9:0]
1010101010......
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
01011111001010000011......
1111100000......
0101111100001100100100111001011010100011......
0001111100......
None
None
11:10
9:0
−
Reserved
Write 0.
−
CJP
Custom jitter pattern
000H
This is used with jitter pattern selection and jitter diagnosis enable. A custom
pattern that is transmitted continuously is set in this field.
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CHAPTER 4 REGISTER DESCRIPTION
PYTBIC - TBI control register (Register address RGAD[4:0] = 11H) R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRT Reserved DRD
DTD
DEF
Reserved
ANS
Reserved
RCKSEL GMII/MII
Reserved
ERAP CDET
Bit
Name
Function
Default
0
15
SRT
Software reset
This bit resets the function module in the TBI. Clear this bit to perform normal
operations. The default value is 0.
14
13
−
Reserved
Write 0.
−
DRD
DTD
DEF
Receive running disparity invalid
0
If this bit is 1, it prohibits use of running disparity calculation and checking in a
receive. For normal operation, clear this bit.
12
11
Running disparity invalid
0
0
If this bit is 1, it prohibits use of running disparity calculation and checking in a
transmit. For normal operation, clear this bit.
Elastic FIFO error status
This bit is set to 1 if an error occurs in the elastic FIFO. After the error occurs,
this bit remains 1 until it is read. This bit is cleared when the register is read.
Write 0 to this bit when PYTBIC is set. This bit is a read-only bit.
10:9
8
−
Reserved
Write 0.
−
ANS
Auto-negotiation sense
0
Set this bit in order to enable the auto-negotiation function to detect gigabit
MAC operating in auto-negotiation bypass mode or gigabit MAC without the
foregoing auto-negotiation ability. Auto-negotiation complete becomes 1 when
this is detected. However, page receive becomes 0, which shows that pages
are not being swapped. Clear this bit if IEEE 802.3 Clause 37 operation is
requested. Doing so terminates without establishing a link.
7:6
5
−
Reserved
Write 0.
−
RCKSEL
Receive clock selection
0
If this bit is 1, it is set so that a 125 MHz clock can be input from
SERDES/PHY. In GMII mode, the 125 MHz clock must be physically
connected to PMA_RX_CLK[0] (RX_CLKn[0]). Clear this bit in order to input a
two-phase 62.5 MHz receive clock in the TBI.
4
GMII/MII
GMII/MII mode
0
If this bit is 1, it connects to GMII PHY or MII PHY and sets the TBI to GMII/MII
mode. Clear this bit when connecting to 1000BASE-X SERDES.
3
2
1
−
−
Reserved
Write 0.
−
Reserved
Write 1.
−
ERAP
WRAP enable
0
This sets SERDES to loopback mode. Clear this bit to perform normal
operation.
0
CDET
Comma detection enable
0
If this bit is 1, it enables SERDES to execute code alignment detection based
on comma detection.
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CHAPTER 5 STATISTICS COUNTERS
Statistics counter map
(1/2)
Register Address
HA[7:0]
Name
Function
R/W
Default
80H
81H
82H
83H
84H
85H
86H
87H
88H
89H
8AH
8BH
8CH
8DH
8EH
8FH
90H
91H
92H
93H
94H
95H
96H
97H to 9FH
A0H
A1H
A2H
A3H
A4H
A5H
A6H
A7H
A8H
R64
64-byte frame receive counter
65- to 127-byte frame receive counter
128- to 255-byte frame receive counter
256- to 511-byte frame receive counter
512- to 1023-byte frame receive counter
1024- to 1518-byte frame receive counter
1519- to LMAX frame receive counter
Byte receive counter
R/W
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
−
R127
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R255
R511
R1K
RMAX
REXD
RBYT
RPKT
RFCS
RMCA
RBCA
RXCF
RXPF
RXUO
RALN
RFLR
RCDE
RCSE
RUND
ROVR
RFRG
RJBR
Packet receive counter
FCS error receive counter
Multicast packet receive counter
Broadcast packet receive counter
Control frame receive counter
Pause frame receive counter
Undefined control frame receive counter
Alignment error receive counter
Data length mismatch receive counter
Code error receive counter
False Carrier receive counter
Short packet receive counter
Oversize packet receive counter
Error short packet receive counter
Jabber packet receive counter
Reserved
−
T64
64-byte frame transmit counter
65- to 127-byte frame transmit counter
128- to 255-byte frame transmit counter
256- to 511-byte frame transmit counter
512- to 1023-byte frame transmit counter
1024- to 1518-byte frame transmit counter
1519- to LMAX frame transmit counter
Byte transmit counter
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
T127
T255
T511
T1K
TMAX
TEXD
TBYT
TPKT
Packet transmit counter
Caution Do not access addresses that are “Reserved”.
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CHAPTER 5 STATISTICS COUNTERS
(2/2)
Register Address
HA[7:0]
Name
Function
R/W
Default
A9H
TMCA
Multicast packet transmit counter
Broadcast packet transmit counter
Pause control frame transmit counter
Transmit delay counter
R/W
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
−
AAH
ABH
ACH
ADH
AEH
AFH
TBCA
TXPF
TDFR
TEDF
TSCL
TMCL
TLCL
TXCL
TNCL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Transmit excessive delay counter
Single collision packet transmit counter
Multiple collision packet transmit counter
Late collision counter
B0H
B1H
Excessive collisions counter
Total collisions counter
B2H
B3H
Reserved
−
B4H
TDRP
TJBR
TFCS
TXCF
TOVR
TUND
TFRG
Transmit discard frame (transmit FIFO underrun) counter
Jabber frame transmit counter
FCS error frame transmit counter
Control frame transmit counter
Oversize frame transmit counter
Short packet transmit counter
Error short packet transmit counter
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
0000 0000H
−
B5H
B6H
B7H
B8H
B9H
BAH
BB to BF
C0H
−
−
RDRP
TFPE
Receive discard counter (Receive FIFO overflow)
Transmit FIFO bus parity error counter
Reserved
R/W
R/W
0000 0000H
0000 0000H
−
C1H
C2H to CBH
Caution Do not access addresses that are “Reserved”.
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CHAPTER 5 STATISTICS COUNTERS
R64 - 64-byte frame receive counter (Register address HA[7:0] = 80H) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
3
18
2
17
1
16
0
R64(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
R64(15:0)
R64 counts the number of 64-byte long receive frames. Receive frames include normal receive frames and receive
frames that have errors. (Preamble and SFD are excluded from the frame length, but the FCS field is included.)
R127 - 65- to 127-byte frame receive counter (Register address HA[7:0] = 81H) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
2
17
1
16
0
R127(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
3
R127(15:0)
R127 counts the number of 65-byte to 127-byte long receive frames. Receive frames include normal receive
frames and receive frames that have errors. (Preamble and SFD are excluded from the frame length, but the FCS
field is included.)
R255 - 128- to 255-byte frame receive counter (Register address HA[7:0] = 82H) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
2
17
1
16
0
R255(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
3
R255(15:0)
R255 counts the number of 128-byte to 255-byte long receive frames. Receive frames include normal receive
frames and receive frames that have errors. (Preamble and SFD are excluded from the frame length, but the FCS
field is included.)
R511 - 256- to 511-byte frame receive counter (Register address HA[7:0] = 83H) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
2
17
1
16
0
R511(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
3
R511(15:0)
R511 counts the number of 256-byte to 511-byte long receive frames. Receive frames include normal receive
frames and receive frames that have errors. (Preamble and SFD are excluded from the frame length, but the FCS
field is included.)
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CHAPTER 5 STATISTICS COUNTERS
R1K - 512- to 1023-byte frame receive counter (Register address HA[7:0] = 84H) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
2
17
1
16
0
R1K(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
3
R1K(15:0)
R1K counts the number of 512-byte to 1023-byte long receive frames. Receive frames include normal receive
frames and receive frames that have errors. (Preamble and SFD are excluded from the frame length, but the FCS
field is included.)
RMAX - 1024- to 1518-byte frame receive counter (Register address HA[7:0] = 85H) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
16
0
RMAX(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
RMAX(15:0)
RMAX counts the number of 1024-byte to 1518-byte long receive frames. Receive frames include normal receive
frames and receive frames that have errors. (Preamble and SFD are excluded from the frame length, but the FCS
field is included.)
REXD - 1519- to LMAX frame receive counter (Register address HA[7:0] = 86H) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
2
17
1
16
0
REXD(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
3
REXD(15:0)
When HUGEN of the MACC2 register is cleared to 0, this counter counts 1519 bytes to the maximum frame length
set to the LMAX register. When HUGEN of the MACC2 register is set to 1, this counter counts the number of receive
frames of 1519 bytes or more. This counter also counts receive frames that contain an error.
RBYT - Byte receive counter (Register address HA[7:0] = 87H) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
4
19
3
18
2
17
1
16
0
RBYT(31:16)
15
14
13
12
11
10
9
8
7
6
5
RBYT(15:0)
RBYT counts the number of receive bytes of a received frame. This counter also counts incorrect packets. The
count value does not include Preamble and SFD. However, the FCS byte is included.
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CHAPTER 5 STATISTICS COUNTERS
RPKT - Packet receive counter (Register address HA[7:0] = 88H) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
4
19
3
18
2
17
1
16
0
RPKT(31:16)
15
14
13
12
11
10
9
8
7
6
5
RPKT(15:0)
RPKT counts the number of packets received. This counter also counts incorrect packets. In addition, it counts all
unicast, multicast, and broadcast packets.
RFCS - FCS error receive counter (Register address HA[7:0] = 89H) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
3
18
2
17
1
16
0
RFCS(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
RFCS(15:0)
RFCS counts the number of complete 64-octet to 1518-octet long packets received that contain frame check
sequence errors.
RMCA - Multicast packet receive counter (Register address HA[7:0] = 8AH) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
2
17
1
16
0
RMCA(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
3
RMCA(15:0)
RMCA counts the number of 64-octet to 1518-octet long (non-VLAN) frames or 64-octet to 1522-octet long (VLAN)
normal multicast frames received. Broadcast frames are not included.
RBCA - Broadcast packet receive counter (Register address HA[7:0] = 8BH) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
2
17
1
16
0
RBCA(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
3
RBCA(15:0)
RBCA counts the number of 64-octet to 1518-octet long (non-VLAN) or 64-octet to 1522-octet long (VLAN) normal
broadcast frames received. Multicast frames are not included.
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CHAPTER 5 STATISTICS COUNTERS
RXCF - Control frame receive counter (Register address HA[7:0] = 8CH) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
3
18
2
17
1
16
0
RXCF(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
RXCF(15:0)
RXCF counts the number of MAC control frames (length/type field is 8808H) received. Unsupported commands
except for pause frame are included.
RXPF - Pause frame receive counter (Register address HA[7:0] = 8DH) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
3
18
2
17
1
16
0
RXPF(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
RXPF(15:0)
RXPF counts the number of valid pause MAC control frames (valid destination address, length/type field is 8808H,
correct pause opcode is 0001H) received.
RXUO - Undefined control frame receive counter (Register address HA[7:0] = 8EH) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
16
0
RXUO(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
RXUO(15:0)
RXUO counts the number of MAC control frames (length/type field is 8808H, correct pause opcode is not 0001H)
received.
RALN - Alignment error receive counter (Register address HA[7:0] = 8FH) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
2
17
1
16
0
RALN(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
3
RALN(15:0)
RALN counts the number of 64-octet to 1518-octet long receive frames that have an invalid FCS and octet unit
fractions.
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RFLR - Data length mismatch receive counter (Register address HA[7:0] = 90H) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
2
17
1
16
0
RFLR(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
3
RFLR(15:0)
RFLR counts the number of cases in which the data length of frames actually received does not match the length
field value. Invalid IEEE802.3 length field values (non-VLAN: except 46-1500 byte, VLAN: except 42-1500 byte) are
not counted. It checks data length when the LENCK bit of the MACC2 register is 1.
RCDE - Code error receive counter (Register address HA[7:0] = 91H) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
3
18
2
17
1
16
0
RCDE(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
RCDE(15:0)
RCDE is counted if an illegal data symbol is detected at least once while carrier is detected.
RCSE - False Carrier receive counter (Register address HA[7:0] = 92H) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
3
18
2
17
1
16
0
RCSE(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
RCSE(15:0)
RCSE is counted after receiving the next packet when False Carrier occurs while idle. False Carrier is counted only
once even if it occurs multiple times while idle.
RUND - Short packet receive counter (Register address HA[7:0] = 93H) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
3
18
2
17
1
16
0
RUND(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
RUND(15:0)
RUND is counted when a receive packet is less than 64-byte long and includes a valid FCS field.
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CHAPTER 5 STATISTICS COUNTERS
ROVR - Oversize packet receive counter (Register address HA[7:0] = 94H) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
2
17
1
16
0
ROVR(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
3
ROVR(15:0)
When HUGEN of the MACC2 register is cleared to 0, this counter counts the number of frames that exceeds the
maximum frame length set to the LMAX register. It also counts receive frames that contain an error.
When HUGEN of the MACC2 register is set to 1, this counter counts nothing.
RFRG - Error short packet receive counter (Register address HA[7:0] = 95H) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
2
17
1
16
0
RFRG(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
3
RFRG(15:0)
RFRG is counted when a receive packet is less than 64-byte long and contains an FCS error.
RJBR - Jabber packet receive counter (Register address HA[7:0] = 96H) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
3
18
2
17
1
16
0
RJBR(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
RJBR(15:0)
RJBR counts when a receive packet exceeds 1518 octets in length and contains an FCS error.
T64 - 64-byte frame transmit counter (Register address HA[7:0] = A0H) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
3
18
2
17
1
16
0
T64(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
T64(15:0)
T64 counts the number of 64-byte long transmit frames. Transmit frames include normal transmit frames and
transmit frames that have errors. (Preamble and SFD are excluded from the frame length, but the FCS field is
included.)
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CHAPTER 5 STATISTICS COUNTERS
T127 - 65- to 127-byte frame transmit counter (Register address HA[7:0] = A1H) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
2
17
1
16
0
T127(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
3
T127(15:0)
T127 counts the number of 65-byte to 127-byte long transmit frames. Transmit frames include normal transmit
frames and transmit frames that have errors. (Preamble and SFD are excluded from the frame length, but the FCS
field is included.)
T255 - 128- to 255-byte frame transmit counter (Register address HA[7:0] = A2H) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
16
0
T255(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
T255(15:0)
T255 counts the number of 128-byte to 255-byte long transmit frames. Transmit frames include normal transmit
frames and transmit frames that have errors. (Preamble and SFD are excluded from the frame length, but the FCS
field is included.)
T511 - 256- to 511-byte frame transmit counter (Register address HA[7:0] = A3H) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
16
0
T511(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
T511(15:0)
T511 counts the number of 256-byte to 511-byte long transmit frames. Transmit frames include normal transmit
frames and transmit frames that have errors. (Preamble and SFD are excluded from the frame length, but the FCS
field is included.)
T1K - 512- to 1023-byte frame transmit counter (Register address HA[7:0] = A4H) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
16
0
T1K(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
T1K(15:0)
T1K counts the number of 512-byte to 1023-byte long transmit frames. Transmit frames include normal transmit
frames and transmit frames that have errors. (Preamble and SFD are excluded from the frame length, but the FCS
field is included.)
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CHAPTER 5 STATISTICS COUNTERS
TMAX - 1024- to 1518-byte frame transmit counter (Register address HA[7:0] = A5H) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
16
0
TMAX(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
TMAX(15:0)
TMAX counts the number of 1024-byte to 1518-byte long transmit frames. Transmit frames include normal transmit
frames and transmit frames that have errors. (Preamble and SFD are excluded from the frame length, but the FCS
field is included.)
TEXD - 1519- to LMAX frame transmit counter (Register address HA[7:0] = A6H) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
16
0
TEXD(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
TEXD(15:0)
When HUGEN of the MACC2 register is cleared to 0, this counter counts the number of frames from 1519 bytes to
the maximum frame length set to the LMAX register. If an attempt is made to transmit a packet exceeding the
maximum frame length, this counter counts nothing, but TOVR counts the packet.
When HUGEN of the MACC2 register is set to 1, this counter counts the number of transmit frames of 1591 bytes
or more. This counter also counts transmit frames that contain an error.
TBYT - Byte transmit counter (Register address HA[7:0] = A7H) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
4
19
3
18
2
17
1
16
0
TBYT(31:16)
15
14
13
12
11
10
9
8
7
6
5
TBYT(15:0)
TBYT counts the number of bytes of transmit packets. When a collision occurs before transmission completes or
aborts, the number of transmit bytes when the collision occurs also is counted. Those of the preamble and SFD are
not counted.
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CHAPTER 5 STATISTICS COUNTERS
TPKT - Packet transmit counter (Register address HA[7:0] = A8H) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
3
18
2
17
1
16
0
TPKT(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
TPKT(15:0)
TPKT is counted for every packet transmission. It includes packets in which errors occur, all unicast packets, all
multicast packets, and broadcast packets.
TMCA - Multicast packet transmit counter (Register address HA[7:0] = A9H) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
2
17
1
16
0
TMCA(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
3
TMCA(15:0)
TMCA is counted when a multicast packet is transmitted. Broadcast packets are not included. Aborted frames and
frames that have CRC errors are not counted.
TBCA - Broadcast packet transmit counter (Register address HA[7:0] = AAH) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
2
17
1
16
0
TBCA(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
3
TBCA(15:0)
TBCA is counted when a broadcast packet is transmitted. Aborted frames and frames that have CRC errors are
not counted.
TXPF - Pause control frame transmit counter (Register address HA[7:0] = ABH) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
2
17
1
16
0
TXPF(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
3
TXPF(15:0)
TXPF is counted whenever a pause control frame is transmitted by the µPD98433 pause control frame transmit
function or FCn input.
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CHAPTER 5 STATISTICS COUNTERS
TDFR - Transmit delay counter (Register address HA[7:0] = ACH) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
4
19
3
18
2
17
1
16
0
TDFR(31:16)
15
14
13
12
11
10
9
8
7
6
5
TDFR(15:0)
TDFR is counted when a transmit delay occurs due to carrier detection when trying to start transmission. This
counter is not counted if a collision occurs during a transmit started after a delay occurs. This counter is counted only
when the transmit succeeds.
TEDF - Transmit excessive delay counter (Register address HA[7:0] = ADH) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
2
17
1
16
0
TEDF(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
3
TEDF(15:0)
TEDF is counted when transmission is aborted due to excessive delay (transmit delay exceeds 3036 byte time).
TSCL - Single collision packet transmit counter (Register address HA[7:0] = AEH) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
16
0
TSCL(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
TSCL(15:0)
TSCL is counted when transmission succeeds after one collision occurs during transmission.
TMCL - Multiple collision packet transmit counter (Register address HA[7:0] = AFH) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
16
0
TMCL(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
TMCL(15:0)
TMCL is counted when transmission succeeds after collisions (including late collisions) occur multiple times (2 to
15 times) within a range specified by the RTMAX field of the HDREG register during transmission.
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CHAPTER 5 STATISTICS COUNTERS
TLCL - Late collisions counter (Register address HA[7:0] = B0H) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
4
19
3
18
2
17
1
16
0
TLCL(31:16)
15
14
13
12
11
10
9
8
7
6
5
TLCL(15:0)
TLCL is counted when a late collision occurs on transfer.
TXCL - Excessive collisions counter (Register address HA[7:0] = B1H) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
3
18
2
17
1
16
0
TXCL(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
TXCL(15:0)
TXCL is counted when more collisions than the RTMAX field of the HDREG register occur during transmission and
transmission is aborted.
TNCL - Total collisions counter (Register address HA[7:0] = B2H) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
4
19
3
18
2
17
1
16
0
TNCL(31:16)
15
14
13
12
11
10
9
8
7
6
5
TNCL(15:0)
TNCL counts the total number of times that collisions occur when transmission succeeds after collisions occur.
This counter does not include excessive collision conditions.
TDRP - Transmit discard frame (Transmit FIFO underrun) counter (Register address HA[7:0] = B4H)
Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
TDRP(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
TDRP(15:0)
TDRP counts the number of packets discarded on transmission.
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CHAPTER 5 STATISTICS COUNTERS
TJBR - Jabber frame transmit counter (Register address HA[7:0] = B5H) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
3
18
2
17
1
16
0
TJBR(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
TJBR(15:0)
TJBR counts when a packet that exceeds 1518 octets and has an incorrect FCS is transmitted.
TFCS - FCS error packet transmit counter (Register address HA[7:0] = B6H) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
2
17
1
16
0
TFCS(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
3
TFCS(15:0)
TFCS counts when a valid sized packet (non-VLAN: 64-1518 byte, VLAN: 64-1522 byte) that has an incorrect FCS
value is transmitted.
TXCF - Control frame transmit counter (Register address HA[7:0] = B7H) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
2
17
1
16
0
TXCF(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
3
TXCF(15:0)
TXCF counts valid length control frames that have a type field indicating a control frame.
TOVR - Oversize frame transmit counter (Register address HA[7:0] = B8H) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
2
17
1
16
0
TOVR(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
3
TOVR(15:0)
When HUGEN of the MACC2 register is cleared to 0, this counter counts the number of transmit frames exceeding
the maximum frame length set to the IMAX register. It also counts transmit frames that contain an error.
When HUGEN of the MACC2 register is set to 1, it counts nothing.
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CHAPTER 5 STATISTICS COUNTERS
TUND - Short packet transmit counter (Register address HA[7:0] = B9H) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
3
18
2
17
1
16
0
TUND(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
TUND(15:0)
TUND counts the number of frames of less than 64 bytes that have a correct FCS.
TFRG - Error short packet transmit counter (Register address HA[7:0] = BAH) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
2
17
1
16
0
TFRG(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
3
TFRG(15:0)
TFRG counts the number of frames of less than 64 bytes that have an incorrect FCS.
RDRP - Receive discard (Receive FIFO overflow) counter (Register address HA[7:0] = C0H) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
RDRP(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RDRP(15:0)
This counter counts the number of frames by which an overflow occurs in the receive FIFO, or the number of
frames discarded by the filtering condition.
TFPE - Transmit FIFO bus parity error counter (Register address HA[7:0] = C1H) Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
16
0
TFPE(31:16)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
TFPE(15:0)
TFPE counts the number of frames in which parity errors occur in transmit data given by the transmit FIFO bus.
This counter also counts the number of frames in which a parity error occurs because of transmit FIFO overrun.
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CHAPTER 6 JTAG BOUNDARY SCAN
The µPD98433 has a JTAG boundary scan circuit.
6.1 Features
• Conforms to IEEE1149.1 JTAG Boundary Scan Standard.
• Three registers dedicated to boundary scan
• Instruction register
• Bypass register
• Boundary scan register
• Three instructions supported
• BYPASS instruction
• EXTEST instruction
• SAMPLE/PRELOAD instruction
• Five pins dedicated to boundary scan
• TCK (JTAG Test Clock)
• TMS (JTAG Test Mode Select)
• TDI (JTAG Test Data Input)
• TDO (JTAG Test Data Output)
• TRST# (JTAG Reset)
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6.2 Internal Configuration of Boundary Scan Circuit
Figure 6-1 shows the block diagram of the internal JTAG boundary scan circuit of the µPD98433.
Figure 6-1. Block Diagram of Boundary Scan Circuit
Boundary scan register
Bypass register
MUX
TDO
Output buffer
TDI
Instruction decoder
Instruction register
TMS
TCK
TAP
controller
TRST#
6.2.1 Instruction register
The instruction register consists of a 2-bit shift register and writes instruction data from the TDI pin. The register
and instruction are selected by this instruction data.
6.2.2 TAP (Test Access Port) controller
The TAP controller changes operating state by latching the signal of the TMS pin at the rising edge of the clock
input to the TCK pin.
6.2.3 Bypass register
The bypass register consists of a 1-bit shift register connected between the TDI and TDO pins when the TAP
controller is in Shift-DR state. If this register is selected while the TAP controller is in Shift-DR state, data is shifted to
the TDO pin at the rising edge of the clock input to the TCK pin.
When this register is selected, the operation of the JTAG boundary circuit does not influence on the operation of
the µPD98433.
6.2.4 Boundary scan register
The boundary scan register is located between an external pin of the µPD98433 and internal logic circuit. When
this register is selected, data is latched or loaded by the instruction of the TAP controller.
If this register is selected while the TAP controller is in Shift-DR state, data is output to the TDO pin starting from
the LSB at the falling edge of the clock input to the TCK pin.
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6.3 Pin Function
6.3.1 TCK (JTAG Test Clock) pin
The TCK pin is used to supply a clock signal to the JTAG boundary scan circuit (such as the bypass register,
instruction register, and TAP controller. This clock signal is isolated so as not to be supplied to the other internal
circuits of the µPD98433.
6.3.2 TMS (JTAG Test Mode Select) pin
Input to the TMS signal is latched at the rising edge of the clock input to the TCK pin and defines the operation of
the TAP controller.
6.3.3 TDI (JTAG Test Data Input) pin
The TDI pin is an input pin that inputs data to the JTAG boundary scan circuit register.
6.3.4 TDO (JTAG Test Data Output) pin
The TDO pin is an output pin that outputs data from the JTAG boundary scan circuit.
This pin changes its output at the falling edge of the clock input to the TCK pin. This pin is a three-state output pin
and is controlled by the TAP controller.
6.3.5 TRST# (JTAG Reset) pin
This pin asynchronously initializes the TAP controller. This reset signal sets the µPD98433 in the normal operating
mode and the boundary register in non-operating state.
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6.4 Operation Description
6.4.1 TAP controller
The TAP controller is a circuit having 16 states synchronized with changes of the TMS and TCK pins. Its operation
is specified by IEEE Standard 1149.1.
6.4.2 TAP controller state
Figure 6-2 shows the state transition of the TAP controller. The state of the TAP controller is determined
depending on the state of the TMS pin signal input at the rising edge of the clock input to the TCK pin. The operations
of the instruction register, boundary scan register, and bypass register change at the rising or falling edge of the clock
input to the TCK pin. (Refer to Figure 6-3).
Figure 6-2. State Transition of TAP Controller
(1) Test-Logic-Reset
H
L
H
H
H
(2) Run-Test/Idle
L
(3) Select-DR-Scan
(4) Select-IR-Scan
L
L
(11) Capture-IR
L
H
H
(5) Capture-DR
L
(6) Shift-DR
(12) Shift-IR
L
H
L
H
H
H
(7) Exit1-DR
(13) Exit1-IR
L
L
(8) Pause-DR
(14) Pause-IR
H
H
L
L
L
L
(9) Exit2-DR
(15) Exit2-IR
H
H
(10) Update-DR
H
(16) Update-IR
L
L
H
Remarks 1. “H” and “L” of the arrows indicating state transition in the above figure indicate the state of the TMS
pin at the rising edge of the clock input to the TCK pin.
2. Numbers in parentheses in the above figure correspond to the explanation below.
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Figure 6-3. Operation Timing in Controller State
TCK
Controller state
Enters state
Starts in state
Starts in state
at falling edge of TCK pin
at rising edge of TCK pin
(1) Test-Logic-Reset
The JTAG boundary scan circuit does not affect the normal operation of the µPD98433 in this controller status.
This is because the bypass instruction is stored to the instruction register and executed on initialization. The
TAP controller enters the Test-Logic-Reset state if the TMS pin holds the high level for the duration of at least
five rising edges of the TCK pin signal, regardless of the current state of the controller. The TAP controller
holds this state for the duration in which the TMS pin signal high.
If the TAP controller must be in the Test-Logic-Reset state, the controller returns to the original Test-Logic-
Reset state even if a low-level signal is input once to the TMS pin by mistake (due to, for example, the influence
of the external interface), if the TMS pin signal holds its high level status for the duration of three rising edges
of the TCK pin signal.
The operation of the test logic does not hinder the logic operation of the µPD98433 due to the above error.
When the TAP controller exits from the Test-Logic-Reset state, the controller enters the Run-Test/Idle state. In
this state, no operation is performed because the current instruction is set by the operation of the bypass
register. The logic operation of the JTAG boundary scan circuit is inactive even in the Select-DR-Scan and
Select-IR-Scan states.
(2) Run-Test/Idle
The TAP controller is in this state during scan operation (in Select-DR-Scan or Select-IR-Scan state). Once the
controller has entered this state and if the TMS pin signal holds the low level, the controller remains in this
state. The controller enters the Select-DR-Scan state if the TMS pin signal holds high level at one rising edge
of the TCK pin signal.
All the test data registers (boundary register and bypass register) selected by the current instruction hold the
previous status (Idle). While the TAP controller is in this state, the instruction does not change.
(3) Select-DR-Scan
This is a temporary boundary scan state. The boundary scan register and bypass register selected by the
current instruction hold the previous state.
If the TMS pin signal is held low at the rising edge of the TCK pin signal while the TAP controller is in this state,
the controller enters the Capture-DR state, and scan sequence to the selected registers is started.
If the TMS pin signal is held high at the rising edge of the TCK pin signal, the TAP controller enters the Select-
IR-Scan state. While the controller is in this state, the instruction does not change.
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(4) Select-IR-Scan
This is a temporary boundary scan state. The boundary scan register and bypass register selected by the
current instruction hold the previous state.
If the TMS pin signal is held low at the rising edge of the TCK pin signal while the TAP controller is in this state,
the controller enters the Capture-IR state, and scan sequence to the selected registers is started.
If the TMS pin signal is held high at the rising edge of the TCK pin signal, the TAP controller enters the Test-
Logic-Reset state. While the controller is in this state, the instruction does not change.
(5) Capture-DR
In this controller state, data is loaded to the boundary scan register selected by the current instruction in
parallel at the rising edge of the TCK pin signal. (In this case, load the data from the input pin of each device to
the corresponding boundary scan register at the same time.) While the TAP controller is in this state, the
instruction does not change.
If the TAP controller is in this state at the rising edge of the TCK pin signal, the controller enters the following
state:
• If the TMS pin signal is held high: Exit1-DR state
• If the TMS pin signal is held low: Shift-DR state
(6) Shift-DR
In this controller state, TDI and TDO are connected (at either of the boundary scan register of bypass register)
by the current instruction. The shift data is shifted one state at a time toward the serial output direction at each
rising edge of the TCK pin signal.
The boundary scan register or bypass register selected by the current instruction holds the previous status
without change if the controller is not on the serial bus (not in the Shift-DR state). While the controller is in this
state, the instruction does not change.
If the TAP controller is in this state at the rising edge of the TCK pin signal, the controller enters the following
state:
• If the TMS pin signal is held high: Exit1-DR state
• If the TMS pin signal is held low: Shift-DR state
(7) Exit1-DR
This is a temporary controller state. If the TMS pin signal is held high at the rising edge of the TCK pin signal
with the TAP controller in this state, the controller enters the Update-DR state. This ends the scan process.
If the TMS pin signal is held low at the rising edge of the TCK pin signal, the TAP controller enters the Pause-
DR state.
Both the bypass register and boundary scan register selected by the current instruction hold the previous
status without change. While the TAP controller is in this state, the instruction does not change.
(8) Pause-DR
In this controller state, shifting between TDI and TDO connected by either the bypass register or boundary
scan register is temporarily stopped. These registers selected by the current instruction hold the previous state
without change.
The TAP controller remains in this state while the TMS pin signal is low. If the TMS pin signal is held high at
the rising edge of the TCK pin signal, the TAP controller enters the Exit2-DR state. While the TAP controller is
in this state, the instruction does not change.
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CHAPTER 6 JTAG BOUNDARY SCAN
(9) Exit2-DR
This is a temporary controller state. If the TMS pin signal is held high at the rising edge of the TCK pin signal
with the TAP controller in this state, the controller enters the Update-DR state. This ends the scan process.
If the TMS pin signal is held low at the rising edge of the TCK pin signal, the TAP controller enters the Shift-DR
state.
Both the bypass register and boundary scan register selected by the current instruction hold the previous
status without change. While the TAP controller is in this state, the instruction does not change.
(10) Update-DR
The boundary scan register has a parallel output latch to prevent changes in parallel output (while shifted to
the shift register path concatenated) by certain instructions (for example, EXTEST instruction).
In the Update-DR controller state, data is latched from the shift register path to the parallel output of this
register at the falling edge of the TCK pin signal.
The data retained latched to the parallel output changes depending on this controller state (the data does not
change with the other controller states).
The previous states of all the shift register of the boundary scan register selected by the current instruction are
retained.
While the TAP controller is in this state, the instruction does not change.
If the TMS pin signal is held high at the rising edge of the TCK pin signal with the TAP controller in this state,
the controller enters the Select-DR-Scan state.
If the TMS pin signal is held low at the rising edge of the TCK pin signal, the TAP controller enters the Run-
Test/Idle state.
(11) Capture-IR
In this controller state, the shift register loads the pattern of a fixed logic value “01(binary)” to the instruction
register at the rising edge of the TCK pin signal.
The previous states of both the bypass register and boundary scan register selected by the current instruction
are retained without change.
While the TAP controller is in this state, the instruction does not change.
If the TMS pin signal is held high at the rising edge of the TCK pin signal while the controller is in this state,
the controller enters the Exit1-IR state.
If the TMS pin signal is held low at the rising edge of the TCK pin signal, the TAP controller enters the Shift-IR
state.
(12) Shift-IR
In this controller state, TDI and TDO are connected by the shift register in the instruction register. The shift
data is shift one state toward the serial output direction at each rising edge of the TCK pin signal.
The boundary scan register or bypass register selected by the current instruction holds the previous state
without change.
While the TAP controller is in this state, the instruction does not change.
If the TMS pin signal is held high at the rising edge of the TCK pin signal with the TAP controller in this state,
the controller enters the Exit1-IR state. If the TMS pin signal is held low, the controller remains the Shift-IR
state.
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CHAPTER 6 JTAG BOUNDARY SCAN
(13) Exit1-IR
This is a temporary controller state. If the TMS pin signal is held high at the rising edge of the TCK pin signal,
the TAP controller enters the Update-IR state. This ends the scan process.
If the TMS pin signal is held low at the rising edge of the TCK pin signal, the TAP controller enters the Pause-
IR state.
Both the bypass register and boundary scan register selected by the current instruction retain their states
without change.
While the TAP controller is in this state, the instruction does not change.
(14) Pause-IR
In this controller state, shift of the instruction register is temporarily stopped. The bypass register and
boundary scan register selected by the current instruction hold the previous state without change.
While the TAP controller is in this state, the instruction does not change. The instruction register holds the
current state.
While the TMS pin signal is low, the TAP controller remains in this state. If the TMS pin signal is held high at
the rising edge of the TCK pin signal, the TAP controller enters the Exit2-IR state.
(15) Exit2-IR
This is a temporary controller state. If the TMS pin signal is held high at the rising edge of the TCK pin signal,
the TAP controller enters the Update-IR state. This ends the scan process.
If the TMS pin signal is held low at the rising edge of the TCK pin, the TAP controller enters the Shift-IR state.
Both the bypass register and boundary scan register selected by the current instruction retain their states
without change.
While the TAP controller is in this state, or while the instruction register holds the current state, the instruction
does not change.
(16) Update-IR
In this controller state, the instruction shifted to the instruction register is latched to the parallel output from the
shift register path at the falling edge of the TCK pin signal. Once a new instruction has been latched, it is used
as the current instruction.
The bypass register or boundary scan register selected by the current instruction holds the previous state.
If the TMS pin signal is held high at the rising edge of the TCK pin signal while the TAP controller is in this
state, the TAP controller enters the Select-DR-Scan state.
If the TMS pin signal is held low at the rising edge of the TCK pin signal, the TAP controller enters the Run-
Test/Idle state.
The Pause-DR controller state in (8) and Pause-IR controller state in (14) temporarily stop shifting of data in
the bypass register, the boundary scan register, or instruction register.
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CHAPTER 6 JTAG BOUNDARY SCAN
6.5 TAP Controller Operation
The TAP controller operates as follows.
The state of the controller is changed by either of (1) and (2) below.
(1) Rising edge of TCK pin signal
(2) TRST# pin input
The TAP controller generates signals that control the operations of the bypass register, boundary scan register,
and instruction register defined by the IEEE1149.1 JTAG Boundary Scan Standard (refer to Figures 6-4 and 6-5).
The TDO pin output buffer and the peripheral circuit that selects a register whose contents are to be output to the
TDO pin are controlled as shown in Table 6-1. The TDO pin defined in this table changes at the falling edge of the
TCK pin signal after it has entered each state.
Table 6-1. Operation in Each Controller State
Controller State
Test-Logic-Reset
Selected Register to Be Driven to TDO Pin
Undefined
TDO Pin Driver
High impedance
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
Capture-IR
Shift-IR
Instruction register
Undefined
Active
Exit1-IR
High impedance
Pause-IR
Exit2-IR
Update-IR
Capture-DR
Shift-DR
Data register (boundary scan register,
bypass register)
Active
Exit1-DR
Undefined
High impedance
Pause-DR
Exit2-DR
Update-DR
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Figure 6-4. Operation of Test Logic (Instruction Scan)
TCK pin signal
TMS pin signal
Controller state
TDI pin signal
Input data to IR
IR shift register
Parallel output of IR
Input data to TDRNote
Bypass
New instruction
Old data
TDR shift register
Parallel output of TDR
Selected register
Instruction register
TDO enable signal
TDO pin signal
Inactive
Active
Inactive
Active
Inactive
Note TDR (Test Data Register): Boundary scan register and bypass register
Remark : don’t care or undefined
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Figure 6-5. Operation of Test Logic (Data Scan)
TCK pin signal
TMS pin signal
Controller state
TDI pin signal
Input data to IR
IR shift register
Instruction
Old data
Bypass
Parallel output of IR
Input data to TDRNote
TDR shift register
New instruction
Inactive
Parallel output of TDR
Selected register
TDO enable signal
TDO pin signal
Inactive
Active
Inactive
Active
Note TDR (Test Data Register): Boundary scan register and bypass register
Remark : don’t care or undefined
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6.6 Initializing TAP Controller
The TAP controller is initialized as follows:
(1) The TAP controller is not initialized by the operation of system input such as system reset.
(2) The TAP controller enters the Test-Logic-Reset controller state at the fifth rising edge of the TCK pin signal
(while the TMS pin signal is held high).
(3) The TAP controller asynchronously enters the Test-Logic-Reset state when the TRST# signal is input.
6.7 Instruction Register
This register is defined as follows (refer to 6.2 Internal Configuration of Boundary Scan Circuit).
(1) The instruction shifted and input to the instruction register is latched so that it changes only in the Update-IR
and Test-Logic-Reset controller states.
(2) Data is not inverted since it has been serially input to the instruction register until it is serially output.
(3) A fixed binary pattern data “01” (with LSB (Least Significant Bit) being “1”) is loaded to this register cell in the
Capture-IR controller state.
(4) A fixed binary pattern data “01” (with LSB being “1”) is loaded to this register cell in the Test-Logic-Reset
controller state.
(5) While this register is read, data is output from the TDO pin, starting from the LSB to the MSB (Most Significant
Bit), at each falling edge of the TCK pin signal.
The JTAG boundary scan circuit of the µPD98433 can support only the following three instructions depending on
the data set to the instruction register.
• BYPASS instruction
• EXTEST instruction
• SAMPLE/PRELOAD instruction
Instruction Register
Supported Instruction
D1
D0
0
0
0
1
1
EXTEST instruction
1
SAMPLE/PRELOAD instruction
Reserved
0
1
BYPASS instruction
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CHAPTER 6 JTAG BOUNDARY SCAN
6.7.1 BYPASS instruction
This instruction is specified by instruction data “11”. This instruction is used to select only the bypass register (to
access between the TDI and TDO pins serially) in the Shift-DR controller state.
While this instruction is selected, the operation of the JTAG boundary scan circuit does not affect the operation of
the µPD98433.
This bypass instruction is selected while the TAP controller is in the Test-Logic-Reset state.
6.7.2 EXTEST instruction
This instruction is specified by instruction data “00”. In the Shift-DR controller state, this instruction is used to
select the boundary scan register of serial access between the TDI and TDO instructions.
• While this instruction is selected:
The states of all the signals driven from the system output pins are completely defined by the data shifted to the
boundary scan register. In the Update-DR controller state, the states of all the signals are changed only by the
falling edge of the TCK pin signal.
The states of all the signals input from the system input pins are loaded to the boundary scan register at the
rising edge of the TCK pin signal while the TAP controller is in the Capture-DR state.
6.7.3 SAMPLE/PRELOAD instruction
This instruction is specified by instruction data “01”. This instruction is used to implement two functions: SAMPLE
and PRELOAD.
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Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:
•
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•
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Device availability
Ordering information
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Availability of related technical literature
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components, host computers, power plugs, AC supply voltages, and so forth)
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In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
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J03.4
相关型号：
UPD98501N7-F6-A
3 CHANNEL(S), 100Mbps, LOCAL AREA NETWORK CONTROLLER, PBGA352, 35 X 35 MM, BGA-352
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