74ALVT162821DGG [NEXPERIA]
20-bit bus interface D-type flip-flop; positive-edge trigger with 30 Ohm termination resistors; 3-stateProduction;型号: | 74ALVT162821DGG |
厂家: | Nexperia |
描述: | 20-bit bus interface D-type flip-flop; positive-edge trigger with 30 Ohm termination resistors; 3-stateProduction 驱动 信息通信管理 光电二极管 逻辑集成电路 |
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74ALVT162821
20-bit bus interface D-type flip-flop; positive-edge trigger with
30 Ω termination resistors; 3-state
Rev. 5 — 19 October 2020
Product data sheet
1. General description
The 74ALVT162821 is a 20-bit positive-edge triggered D-type flip-flop with 30 Ω termination
resistors and 3-state outputs
The device can be used as two 10-bit flip-flops or one 20-bit flip-flop. The device features
two clocks (1CP and 2CP) and two output enables (1OE and 2OE), each controlling 10-bits.
The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time
requirements on the LOW-to-HIGH clock (nCP) transition. A HIGH on nOE causes the outputs to
assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the
flip-flops. Bus hold data inputs eliminate the need for external pull-up resistors to define unused
inputs
2. Features and benefits
•
Wide supply voltage range from 2.3 V to 3.6 V
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Overvoltage tolerant inputs to 5.5 V
BiCMOS high speed and output drive
Outputs include series resistance of 30 Ω making external termination resistors unnecessary
No bus current loading when output is tied to 5 V bus
Direct interface with TTL levels
IOFF circuitry provides partial Power-down mode operation
20-bit positive-edge triggered register
5 V I/O compatible
Multiple VCC and GND pins minimize switching noise
Bus hold on data inputs
Live insertion and extraction permitted
Power-up reset
Power-up 3-state
Output capability: +12 mA and -12 mA
Latch-up protection:
•
JESD17: exceeds 500 mA
•
•
ESD protection:
•
•
MIL STD 883, method 3015: exceeds 2000 V
MM: exceeds 200 V
Specified from -40 °C to 85 °C
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
Name
Description
Version
74ALVT162821DGG -40 °C to +85 °C
TSSOP56 plastic thin shrink small outline package; 56 leads; SOT364-1
body width 6.1 mm
Nexperia
74ALVT162821
20-bit bus interface D-type flip-flop; positive-edge trigger with 30 Ω termination resistors; 3-state
4. Functional diagram
1
1OE
1CP
EN2
C1
56
28
29
EN4
C3
2OE
2CP
2
3
5
55
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
30
1D
2
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
1D9
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2D9
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
1Q9
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
2Q9
55 54 52 51 49 48 47 45 44 43
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9
6
8
9
56
1
1CP
1OE
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9
10
12
13
14
15
16
17
19
20
21
23
24
26
27
2
3
5
6
8
9
10 12 13 14
4
3D
42 41 40 38 37 36 34 33 31 30
2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D9
29
28
2CP
2OE
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9
15 16 17 19 20 21 23 24 26 27
001aad153
001aad155
Fig. 1. Logic symbol
Fig. 2. IEC logic symbol
nD0
nD1
nD2
nD3
nD4
nD5
nD6
nD7
nD8
nD9
D
D
D
D
D
D
D
D
D
D
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP Q
nCP
nOE
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
nQ8
nQ9
001aad156
Fig. 3. Logic diagram
V
V
CC
CC
27 Ω
output
27 Ω
001aac372
Fig. 4. Schematic of each output
©
74ALVT162821
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 5 — 19 October 2020
2 / 15
Nexperia
74ALVT162821
20-bit bus interface D-type flip-flop; positive-edge trigger with 30 Ω termination resistors; 3-state
5. Pinning information
5.1. Pinning
74ALVT162821
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OE
1Q0
1Q1
GND
1Q2
1Q3
1CP
1D0
1D1
GND
1D2
1D3
2
3
4
5
6
7
V
V
CC
CC
8
1Q4
1Q5
1Q6
GND
1Q7
1Q8
1Q9
2Q0
2Q1
2Q2
GND
2Q3
2Q4
2Q5
1D4
1D5
1D6
GND
1D7
1D8
1D9
2D0
2D1
2D2
GND
2D3
2D4
2D5
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
V
V
CC
CC
2Q6
2Q7
GND
2Q8
2Q9
2OE
2D6
2D7
GND
2D8
2D9
2CP
aaa-028101
Fig. 5. Pin configuration SOT364-1 (TSSOP56)
©
74ALVT162821
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 5 — 19 October 2020
3 / 15
Nexperia
74ALVT162821
20-bit bus interface D-type flip-flop; positive-edge trigger with 30 Ω termination resistors; 3-state
5.2. Pin description
Table 2. Pin description
Symbol
Pin
Description
1D0, 1D1, 1D2, 1D3, 1D4,
1D5, 1D6, 1D7, 1D8, 1D9
55, 54, 52, 51, 49,
48, 47, 45, 44, 43
data inputs
1Q0, 1Q1, 1Q2, 1Q3, 1Q4,
1Q5, 1Q6, 1Q7, 1Q8, 1Q9
2, 3, 5, 6, 8,
9, 10, 12, 13, 14
data outputs
data inputs
data outputs
2D0, 2D1, 2D2, 2D3, 2D4,
2D5, 2D6, 2D7, 2D8, 2D9
42, 41, 40, 38, 37,
36, 34, 33, 31, 30
2Q0, 2Q1, 2Q2, 2Q3, 2Q4,
2Q5, 2Q6, 2Q7, 2Q8, 2Q9
15, 16, 17, 19, 20,
21, 23, 24, 26, 27
1OE, 2OE
1CP, 2CP
GND
1, 28
output enable inputs (active LOW)
clock pulse inputs (active rising edge)
ground (0 V)
56, 29
4, 11, 18, 25,
32, 39, 46, 53
VCC
7, 22, 35, 50
supply voltage
6. Functional description
Table 3. Function table
H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level; I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
NC = no change; X = don’t care;
Z = high-impedance OFF-state; ↑ = LOW-to-HIGH clock transition.
Operating mode
Input
Internal register Output
nQn
nOE
L
nCP
↑
nDn
Load and read register
l
L
L
L
↑
h
H
H
NC
Z
Hold
L
NC
NC
↑
X
NC
NC
nDn
Disable outputs
H
X
H
nDn
Z
©
74ALVT162821
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 5 — 19 October 2020
4 / 15
Nexperia
74ALVT162821
20-bit bus interface D-type flip-flop; positive-edge trigger with 30 Ω termination resistors; 3-state
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
+4.6
+7.0
+7.0
-50
Unit
V
VCC
VI
supply voltage
-0.5
input voltage
[1]
[1]
-1.2
V
VO
IIK
output voltage
output in OFF-state or HIGH-state
VI < 0 V
-0.5
V
input clamping current
output clamping current
output current
-
mA
mA
mA
mA
°C
°C
IOK
IO
VO < 0 V
-
-50
output in LOW-state
output in HIGH-state
-
-
128
-64
Tstg
Tj
storage temperature
junction temperature
-65
-
+150
150
[2]
[1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability.
8. Recommended operating conditions
Table 5. Recommended operating conditions
Symbol Parameter
Conditions
VCC = 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V Unit
Min
Max
2.7
5.5
-8
Min
Max
3.6
5.5
-12
12
VCC
VI
supply voltage
2.3
3.0
V
input voltage
0
0
V
IOH
HIGH-level output current
LOW-level output current
input transition rise and fall rate
ambient temperature
-
-
-
-
mA
mA
ns/V
°C
IOL
none
12
Δt/ΔV
Tamb
outputs enabled
free-air
-
10
-
10
-40
+85
-40
+85
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; Tamb = -40 °C to +85 °C; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VCC = 2.5 V ± 0.2 V
Conditions
Min
Typ[1]
Max Unit
VIK
VIH
VIL
input clamping voltage
VCC = 2.3 V; IIK = -18 mA
-
-0.85
-1.2
-
V
V
V
V
V
V
V
V
V
HIGH-level input voltage
LOW-level input voltage
1.7
-
-
-
0.7
-
VOH
HIGH-level output voltage VCC = 2.3 V to 3.6 V; IO = -100 μA
VCC = 2.3 V; IO = -8 mA
VCC - 0.2
VCC
2.1
0.07
0.3
-
1.8
-
VOL
LOW-level output voltage VCC = 2.3 V; IO = 100 μA
VCC = 2.3 V; IO = 24 mA
-
-
-
-
0.2
0.5
0.4
0.55
VCC = 2.3 V; IO = 8 mA
VOL(pu) power-up LOW-level
output voltage
VCC = 2.7 V; IO = 1 mA; VI = VCC or GND
[2]
-
©
74ALVT162821
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 5 — 19 October 2020
5 / 15
Nexperia
74ALVT162821
20-bit bus interface D-type flip-flop; positive-edge trigger with 30 Ω termination resistors; 3-state
Symbol Parameter
Conditions
Min
Typ[1]
0.1
Max Unit
II
input leakage current
all input pins
VCC = 0 V or 2.7 V; VI = 5.5 V
control pins
VCC = 2.7 V; VI = VCC or GND
data pins;
VCC = 2.7 V; VI = VCC
-
-
10
±1
μA
μA
0.1
[3]
-
-
-
-
-
-
0.1
0.1
0.1
90
1
μA
μA
VCC = 2.7 V; VI = 0 V
-5
IOFF
IBHL
IBHH
IEX
power-off leakage current VCC = 0 V; VI or VO = 0 V to 4.5 V
±100 μA
bus hold LOW current
bus hold HIGH current
external current
data inputs; VCC = 2.3 V; VI = 0.7 V
data inputs; VCC = 2.3 V; VI = 1.7 V
-
-
μA
μA
μA
-10
10
output in HIGH-state when VO > VCC
;
125
VO = 5.5 V; VCC = 2.3 V
IO(pu/pd) power-up/power-down
output current
VCC ≤ 1.2 V; VO = 0.5 V to VCC
VI = GND or VCC; nOE = don’t care
;
[4]
-
1
±100 μA
IOZ
OFF-state output current VCC = 2.7 V; VI = VIL or VIH
output HIGH-state; VO = 2.3 V
-
-
0.5
0.5
5
μA
μA
output LOW-state; VO = 0.5 V
-5
ICC
supply current
VCC = 2.7 V; VI = GND or VCC; IO = 0 A
outputs HIGH-state
-
-
0.04
2.3
0.1
4.5
0.1
0.4
mA
mA
mA
mA
outputs LOW-state
outputs disabled
[5]
[6]
0.04
0.04
ΔICC
additional supply current per input pin; VCC = 2.3 V to 2.7 V;
one input at VCC - 0.6 V;
-
other inputs at VCC or GND
CI
input capacitance
output capacitance
VI = 0 V or VCC
VO = 0 V or VCC
-
-
3
9
-
-
pF
pF
CO
VCC = 3.3 V ± 0.3 V
VIK
VIH
VIL
input clamping voltage
VCC = 3.0 V; IIK = -18 mA
-
-0.85
-
-1.2
V
V
V
V
V
HIGH-level input voltage
LOW-level input voltage
2.0
-
0.8
-
-
-
VOH
HIGH-level output voltage VCC = 3.0 V to 3.6 V; IO = -100 μA
VCC - 0.2
2.0
VCC
2.3
VCC = 3.0 V; IO = -32 mA
-
VOL
LOW-level output voltage VCC = 3.0 V
IO = 100 μA
IO = 16 mA
IO = 32 mA
IO = 64 mA
-
-
-
-
-
0.07
0.25
0.3
0.4
-
0.2
0.4
V
V
V
V
V
0.5
0.55
0.55
VOL(pu) power-up LOW-level
output voltage
VCC = 3.6 V; IO = 1 mA; VI = VCC or GND
[2]
©
74ALVT162821
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 5 — 19 October 2020
6 / 15
Nexperia
74ALVT162821
20-bit bus interface D-type flip-flop; positive-edge trigger with 30 Ω termination resistors; 3-state
Symbol Parameter
Conditions
Min
Typ[1]
0.1
Max Unit
II
input leakage current
all input pins;
VCC = 0 V or 3.6 V; VI = 5.5V
control pins
VCC = 3.6 V; VI = VCC or GND
data pins;
VCC = 3.6 V; VI = VCC
-
-
10
±1
μA
μA
0.1
[3]
-
-
0.5
0.1
0.1
130
-140
-
1
μA
μA
VCC = 3.6 V; VI = 0 V
-5
IOFF
IBHL
IBHH
IBHLO
power-off leakage current VCC = 0 V; VI or VO = 0 V to 4.5 V
-
±100 μA
bus hold LOW current
bus hold HIGH current
data inputs; VCC = 3 V; VI = 0.8 V
data inputs; VCC = 3 V; VI = 2.0 V
data inputs; VCC = 3.6 V; VI = 0 V to 3.6 V
75
-75
500
-
-
-
μA
μA
μA
bus hold LOW
[7]
[7]
overdrive current
IBHHO
IEX
bus hold HIGH
overdrive current
data inputs; VCC = 3.6 V; VI = 0 V to 3.6 V
-500
-
-
μA
μA
external current
output in HIGH-state when VO > VCC
VO = 5.5 V; VCC = 3.0 V
;
-
-
10
1
125
IO(pu/pd) power-up/power-down
output current
VCC ≤ 1.2 V; VO = 0.5 V to VCC
VI = GND or VCC; nOE = don’t care
;
[8]
±100 μA
IOZ
OFF-state output current VCC = 3.6 V; VI = VIL or VIH
output HIGH-state; VO = 3.0 V
-
-
0.5
0.5
5
μA
μA
output LOW-state; VO = 0.5 V
-5
ICC
supply current
VCC = 3.6 V; VI = GND or VCC; IO = 0 A
outputs HIGH-state
-
-
-
-
0.07
5.1
0.1
7
mA
mA
mA
mA
outputs LOW-state
outputs disabled
[5]
[6]
0.07
0.04
0.1
0.4
ΔICC
additional supply current per input pin; VCC = 3 V to 3.6 V;
one input at VCC - 0.6 V;
other inputs at VCC or GND
CI
input capacitance
output capacitance
VI = 0 V or VCC
VO = 0 V or VCC
-
-
3
9
-
-
pF
pF
CO
[1] All typical values for VCC = 2.5 V ± 0.2 V are measured at VCC = 2.5 V and Tamb = 25 °C.
All typical values for VCC = 3.3 V ± 0.3 V are measured at VCC = 3.3 V and Tamb = 25 °C.
[2] For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
[3] Unused pins at VCC or GND.
[4] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms.
From VCC = 1.2 V to (2.5 ± 0.2) V a transition time of 100 μs is permitted. This parameter is valid for Tamb = 25 °C only.
[5] ICC with outputs disabled is measured with outputs pulled to VCC or GND.
[6] This is the increase in supply current for each input at the specified voltage level other than VCC or GND.
[7] This is the bus hold overdrive current required to force the input to the opposite logic state.
[8] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms.
From VCC = 1,2 V to (3.3 ± 0.3) V a transition time of 100 μs is permitted. This parameter is valid for Tamb = 25 °C only.
©
74ALVT162821
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 5 — 19 October 2020
7 / 15
Nexperia
74ALVT162821
20-bit bus interface D-type flip-flop; positive-edge trigger with 30 Ω termination resistors; 3-state
10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); Tamb = -40 °C to +85 °C; for test circuit see Fig. 9.
Symbol Parameter
VCC = 2.5 V ± 0.2 V
Conditions
Min
Typ[1]
Max Unit
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tsu
LOW to HIGH propagation delay
HIGH to LOW propagation delay
nCP to nQn; see Fig. 6
nCP to nQn; see Fig. 6
1.0
1.0
1.5
1.0
1.5
1.0
1.5
2.0
0.3
0.5
1.5
150
4.4
3.8
4.6
2.8
3.5
3.7
0.1
0.5
-0.5
-0.1
-
7.0
6.4
7.5
4.6
5.5
5.7
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
OFF-state to HIGH propagation delay nOE to nQn; see Fig. 8
OFF-state to LOW propagation delay nOE to nQn; see Fig. 8
HIGH to OFF-state propagation delay nOE to nQn; see Fig. 8
LOW to OFF-state propagation delay nOE to nQn; see Fig. 8
set-up time
nDn to nCP HIGH; see Fig. 7
nDn to nCP LOW; see Fig. 7
nDn to nCP HIGH; see Fig. 7
nDn to nCP LOW; see Fig. 7
nCP HIGH or LOW; see Fig. 6
nCP; see Fig. 6
-
th
hold time
-
tW
pulse width
-
-
fmax
maximum frequency
-
VCC = 3.3 V ± 0.3 V
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tsu
LOW to HIGH propagation delay
HIGH to LOW propagation delay
nCP to nQn; see Fig. 6
nCP to nQn; see Fig. 6
1.0
1.0
1.0
0.5
1.5
1.5
1.5
0.5
1.5
150
3.2
3.2
3.4
2.3
3.7
3.0
0.1
0.1
-
5.0
4.7
5.6
3.7
5.4
4.3
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
OFF-state to HIGH propagation delay nOE to nQn; see Fig. 8
OFF-state to LOW propagation delay nOE to nQn; see Fig. 8
HIGH to OFF-state propagation delay nOE to nQn; see Fig. 8
LOW to OFF-state propagation delay nOE to nQn; see Fig. 8
set-up time
nDn to nCP HIGH or LOW; see Fig. 7
th
hold time HIGH
pulse width
nDn to nCP HIGH or LOW; see Fig. 7
nCP HIGH or LOW; see Fig. 6
nCP; see Fig. 6
-
tW
-
fmax
maximum frequency
-
-
[1] All typical values for VCC = 2.5 V ± 0.2 V are measured at VCC = 2.5 V and Tamb = 25 °C.
All typical values for VCC = 3.3 V ± 0.3 V are measured at VCC = 3.3 V and Tamb = 25 °C.
©
74ALVT162821
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 5 — 19 October 2020
8 / 15
Nexperia
74ALVT162821
20-bit bus interface D-type flip-flop; positive-edge trigger with 30 Ω termination resistors; 3-state
10.1. Waveforms and test circuit
1/f
max
V
I
nCP input
V
V
M
M
GND
t
W
t
t
PHL
PLH
V
OH
V
nQn output
M
001aaa256
V
OL
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 6. Propagation delay clock input (nCP) to output (nQn), clock pulse (nCP) width and maximum clock
frequency
V
I
V
nCP input
M
GND
t
t
su
su
t
t
h
h
V
I
V
nDn input
M
GND
V
OH
V
nQn output
M
V
OL
001aaa257
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig. 7. Set-up times and hold times from input (nDn) to clock (nCP)
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Product data sheet
Rev. 5 — 19 October 2020
9 / 15
Nexperia
74ALVT162821
20-bit bus interface D-type flip-flop; positive-edge trigger with 30 Ω termination resistors; 3-state
V
I
nOE input
V
V
M
M
t
GND
t
PLZ
PZL
V
CC
nQn output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
nQn output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aal795
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 8. OFF-state to HIGH and LOW propagation delays and LOW and HIGH to OFF-state propagation delays
Table 8. Measurement points
VCC
Input
VI
Output
VM
VM
VX
VY
VCC ≤ 2.7 V
VCC ≥ 3.0 V
VCC
3.0 V
0.5 x VCC
1.5 V
0.5 x VCC
1.5 V
VOL + 0.15 V
VOL + 0.3 V
VOH - 0.15 V
VOH - 0.3 V
©
74ALVT162821
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 5 — 19 October 2020
10 / 15
Nexperia
74ALVT162821
20-bit bus interface D-type flip-flop; positive-edge trigger with 30 Ω termination resistors; 3-state
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
R
V
CC
L
V
V
O
I
G
DUT
R
T
C
L
R
L
001aae331
Test data is given in Table 9.
Definitions test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = Test voltage for switching times.
Fig. 9. Test circuit for measuring switching times
Table 9. Test data
Input
VI
Load
CL
VEXT
fi
tW
tr, tf
RL
tPHZ, tPZH tPLZ, tPZL
tPLH, tPHL
3.0 V or VCC
≤ 10 MHz 500 ns
≤ 2.5 ns
50 pF
500 Ω
GND
6 V or VCC x 2 open
whichever is less
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74ALVT162821
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Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 5 — 19 October 2020
11 / 15
Nexperia
74ALVT162821
20-bit bus interface D-type flip-flop; positive-edge trigger with 30 Ω termination resistors; 3-state
11. Package outline
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm
SOT364-1
E
D
A
X
c
H
v
M
A
y
E
Z
56
29
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
detail X
1
28
w
M
b
e
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions).
A
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
E
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
max.
8o
0o
0.15
0.05
1.05
0.85
0.28
0.17
0.2
0.1
14.1
13.9
6.2
6.0
8.3
7.9
0.8
0.4
0.50
0.35
0.5
0.1
mm
1.2
0.5
1
0.25
0.08
0.1
0.25
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT364-1
MO-153
Fig. 10. Package outline SOT364-1 (TSSOP56)
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74ALVT162821
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Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 5 — 19 October 2020
12 / 15
Nexperia
74ALVT162821
20-bit bus interface D-type flip-flop; positive-edge trigger with 30 Ω termination resistors; 3-state
12. Abbreviations
Table 10. Abbreviations
Acronym
Description
BiCMOS
DUT
Bipolar Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Military
MIL
MM
Machine Model
MOS
Metal Oxide Semiconductor
13. Revision history
Table 11. Revision history
Document ID
Release date Data sheet status
20201019 Product data sheet
Change notice Supersedes
- 74ALVT162821 v.4
74ALVT162821 v.5
Modifications:
•
•
•
Type number 74ALVT162821DGG (SOT371-1 / SSOP56) removed.
Section 1 and Section 2 updated.
Table 4: Derating values for Ptot total power dissipation updated.
74ALVT162821 v.4
Modifications:
20180124
Product data sheet
-
74ALVT162821 v.3
•
•
The format of this data sheet has been redesigned to comply with the identity
guidelines of Nexperia.
Legal texts have been adapted to the new company name where appropriate.
74ALVT162821 v.3
74ALVT162821 v.2
74ALVT162821 v.1
19981002
19980213
19971117
Product data sheet
Product specification
Product specification
-
-
-
74ALVT162821 v.2
74ALVT162821 v.1
-
©
74ALVT162821
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 5 — 19 October 2020
13 / 15
Nexperia
74ALVT162821
20-bit bus interface D-type flip-flop; positive-edge trigger with 30 Ω termination resistors; 3-state
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
14. Legal information
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Data sheet status
Document status Product
Definition
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
[1][2]
status [3]
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Nexperia product is suitable
and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Preliminary [short]
data sheet
Qualification
Production
This document contains data from
the preliminary specification.
Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Nexperia products in order to
avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Definitions
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of commercial sale — Nexperia products are
sold subject to the general terms and conditions of commercial sale, as
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
in a valid written individual agreement. In case an individual agreement is
concluded only the terms and conditions of the respective agreement shall
apply. Nexperia hereby expressly objects to applying the customer’s general
terms and conditions with regard to the purchase of Nexperia products by
customer.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outside
of Nexperia.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified, the
product is not suitable for automotive use. It is neither qualified nor tested in
accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of non-automotive qualified
products in automotive equipment or applications.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards,
customer (a) shall use the product without Nexperia’s warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
Nexperia’s specifications such use shall be solely at customer’s own risk,
and (c) customer fully indemnifies Nexperia for any liability, damages or failed
product claims resulting from customer design and use of the product for
automotive applications beyond Nexperia’s standard warranty and Nexperia’s
product specifications.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with the
Terms and conditions of commercial sale of Nexperia.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Trademarks
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-critical
systems or equipment, nor in applications where failure or malfunction
of an Nexperia product can reasonably be expected to result in personal
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
©
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Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 5 — 19 October 2020
14 / 15
Nexperia
74ALVT162821
20-bit bus interface D-type flip-flop; positive-edge trigger with 30 Ω termination resistors; 3-state
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Ordering information....................................................1
4. Functional diagram.......................................................2
5. Pinning information......................................................3
5.1. Pinning.........................................................................3
5.2. Pin description.............................................................4
6. Functional description................................................. 4
7. Limiting values............................................................. 5
8. Recommended operating conditions..........................5
9. Static characteristics....................................................5
10. Dynamic characteristics............................................ 8
10.1. Waveforms and test circuit........................................ 9
11. Package outline........................................................ 12
12. Abbreviations............................................................13
13. Revision history........................................................13
14. Legal information......................................................14
© Nexperia B.V. 2020. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 19 October 2020
©
74ALVT162821
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 5 — 19 October 2020
15 / 15
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