74ALVT162823DGG [NEXPERIA]
18-bit bus-interface D-type flip-flop with reset and enable with 30 Ohm termination resistors; 3-stateProduction;
| 型号： | 74ALVT162823DGG |
| 厂家： | 
Nexperia |
| 描述： | 18-bit bus-interface D-type flip-flop with reset and enable with 30 Ohm termination resistors; 3-stateProduction 驱动 信息通信管理 光电二极管 逻辑集成电路 |
| 文件： | 总18页 (文件大小：221K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74ALVT162823
18-bit bus-interface D-type flip-flop with reset and enable with
30 Ω termination resistors; 3-state
Rev. 3 — 23 January 2018
Product data sheet
1 General description
The 74ALVT162823 18-bit bus interface register is designed to eliminate the extra
packages required to buffer existing registers and provide extra data width for wider data
or address paths of buses carrying parity.
The 74ALVT162823 has two 9-bit wide buffered registers with clock enable (nCE) and
master reset (nMR) which are ideal for parity bus interfacing in high microprogrammed
systems.
The registers are fully edge-triggered. The state of each D input, one set-up time before
the LOW-to-HIGH clock transition is transferred to the corresponding Q output of the
flip-flop.
The 74ALVT162823 is designed with 30 Ω series resistance in both the pull-up and
pull-down output structures. This design reduces line noise in applications such as
memory address drivers, clock drivers, and bus receivers or transmitters.
2 Features and benefits
• Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops
• 5 V I/O compatible
• Ideal where high speed, light loading or increased fan-in are required with MOS
microprocessors
• Bus hold data inputs eliminate the need for external pull-up resistors to hold unused
inputs
• Live insertion and extraction permitted
• Power-up 3-state
• Power-up reset
• Output capability: +12 mA to −12 mA
• Outputs include series resistance of 30 Ω making external termination resistors
unnecessary
• Latch-up protection:
– JESD78: exceeds 500 mA
• ESD protection:
– MIL STD 883, method 3015: exceeds 2000 V
– MM: exceeds 200 V
Nexperia
74ALVT162823
18-bit bus-interface D-type flip-flop with reset and enable with 30 Ω termination resistors; 3-state
3 Ordering information
Table 1.ꢀOrdering information
Type number
Package
Temperature range Name
Description
Version
74ALVT162823DGG −40 °C to +85 °C
TSSOP56 plastic thin shrink small outline package; 56 leads;
body width 6.1 mm
SOT364-1
4 Functional diagram
2
V
CC
EN1
R2
1OE
1MR
1CE
1CP
2OE
2MR
2CE
2CP
1
55
56
27
28
30
29
G3
3C4
EN5
R6
G7
data input
to internal circuit
7C8
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
3
5
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
4D
1,2
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
6
001aad245
8
Figure 2.ꢀBus hold circuit
9
10
12
13
14
15
16
17
19
20
21
23
24
26
V
CC
V
CC
8D
5,6
27 Ω
output
27 Ω
001aad242
001aad244
Figure 1.ꢀIEC logic symbol
Figure 3.ꢀSchematic of each output
74ALVT162823
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 23 January 2018
2 / 18
Nexperia
74ALVT162823
18-bit bus-interface D-type flip-flop with reset and enable with 30 Ω termination resistors; 3-state
nCE
nCP
nD0
nD1
nD2
nD3
nD4
nD5
nD6
nD7
nD8
CP
nD
CP
nD
CP
nD
CP
nD
CP
nD
CP
nD
CP
nD
CP
nD
CP
nD
Q
Q
Q
Q
Q
Q
Q
Q
Q
R
R
R
R
R
R
R
R
R
nMR
nOE
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
nQ8
001aad243
Figure 4.ꢀLogic diagram
74ALVT162823
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 23 January 2018
3 / 18
Nexperia
74ALVT162823
18-bit bus-interface D-type flip-flop with reset and enable with 30 Ω termination resistors; 3-state
5 Pinning information
5.1 Pinning
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1MR
1OE
1Q0
GND
1Q1
1Q2
1CP
1CE
1D0
GND
1D1
1D2
2
3
4
5
6
7
V
V
CC
CC
8
1Q3
1Q4
1Q5
GND
1Q6
1Q7
1Q8
2Q0
2Q1
2Q2
GND
2Q3
2Q4
2Q5
1D3
1D4
1D5
GND
1D6
1D7
1D8
2D0
2D1
2D2
GND
2D3
2D4
2D5
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
74ALVT162823
V
V
CC
CC
2Q6
2Q7
GND
2Q8
2OE
2MR
2D6
2D7
GND
2D8
2CE
2CP
001aab433
Figure 5.ꢀPin configuration
74ALVT162823
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 23 January 2018
4 / 18
Nexperia
74ALVT162823
18-bit bus-interface D-type flip-flop with reset and enable with 30 Ω termination resistors; 3-state
5.2 Pin description
Table 2.ꢀPin description
Symbol
Pin
Description
1D0, 1D1, 1D2, 1D3, 1D4,
1D5, 1D6, 1D7, 1D8
54, 52, 51, 49, 48,
47, 45, 44, 43
data inputs
1Q0, 1Q1, 1Q2, 1Q3, 1Q4,
1Q5, 1Q6, 1Q7, 1Q8
3, 5, 6, 8, 9,
10, 12, 13, 14
data outputs
data inputs
data outputs
2D0, 2D1, 2D2, 2D3, 2D4,
2D5, 2D6, 2D7, 2D8
42, 41, 40, 38, 37,
36, 34, 33, 31
2Q0, 2Q1, 2Q2, 2Q3, 2Q4,
2Q5, 2Q6, 2Q7, 2Q8
15, 16, 17, 19, 20,
21, 23, 24, 26
1MR, 2MR
1OE, 2OE
1CP, 2CP
1CE, 2CE
GND
1, 28
master reset input (active-LOW)
output enable inputs (active LOW)
clock pulse inputs (active rising edge)
clock enable input (active-LOW)
ground (0 V)
2, 27
56, 29
55, 30
4, 11, 18, 25,
32, 39, 46, 53
VCC
7, 22, 35, 50
supply voltage
6 Functional description
Table 3.ꢀFunction table [1]
Operating mode
Input
nOE
L
Output
nMR
L
nCE
X
nCP
X
nDn
nQn
L
Clear
X
h
l
Load and read data
L
H
L
↑
H
L
Hold
L
H
X
H
X
NC
X
X
X
NC
Z
High-impedance
H
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
NC = no change;
X = don’t care;
Z = high-impedance OFF-state;
↑ = LOW-to-HIGH clock transition;
74ALVT162823
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 23 January 2018
5 / 18
Nexperia
74ALVT162823
18-bit bus-interface D-type flip-flop with reset and enable with 30 Ω termination resistors; 3-state
7 Limiting values
Table 4.ꢀLimiting values
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max
+4.6
+7.0
+7.0
−50
Unit
V
VCC
VI
supply voltage
−0.5
[1]
[1]
input voltage
−0.5
V
VO
IIK
output voltage
output in OFF-state or HIGH-state
VI < 0 V
−0.5
V
input clamping current
-
mA
mA
mA
mA
°C
°C
IOK
IO
output clamping current VO < 0 V
-
−50
output current
output in LOW-state
output in HIGH-state
-
128
-
−65
-
−64
Tstg
Tj
storage temperature
junction temperature
+150
150
[2]
[1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are
detrimental to reliability.
8 Recommended operating conditions
Table 5.ꢀRecommended operating conditions
Symbol Parameter
VCC = 2.5 V
Conditions
Min
Typ
Max
Unit
VCC
VI
supply voltage
2.3
-
-
-
-
-
-
2.7
5.5
−8
V
input voltage
0
V
IOH
HIGH-level output current
LOW-level output current
-
mA
mA
ns/V
°C
IOL
-
-
12
Δt/Δv
Tamb
input transition rise or fall rate outputs enabled
ambient temperature in free air
10
−40
+85
VCC = 3.3 V
VCC
VI
supply voltage
3.0
-
-
-
-
-
-
3.6
5.5
−12
12
V
input voltage
0
V
IOH
HIGH-level output current
LOW-level output current
-
mA
mA
ns/V
°C
IOL
-
-
Δt/Δv
Tamb
input transition rise or fall rate outputs enabled
10
ambient temperature
in free air
−40
+85
74ALVT162823
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 23 January 2018
6 / 18
Nexperia
74ALVT162823
18-bit bus-interface D-type flip-flop with reset and enable with 30 Ω termination resistors; 3-state
9 Static characteristics
Table 6.ꢀStatic characteristics
At recommended operating conditions; Tamb = −40 °C to +85 °C; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VCC = 2.5 V ± 0.2 V
Conditions
Min
Typ[1]
Max
Unit
VIK
VIH
VIL
input clamping voltage
VCC = 2.3 V; IIK = -18 mA
-
1.7
-
-0.85
-
-1.2
-
V
V
V
V
V
V
HIGH-level input voltage
LOW-level input voltage
-
0.7
-
VOH
VOL
HIGH-level output voltage VCC = 2.3 V; IO = -8 mA
LOW-level output voltage VCC = 2.3 V; IO = 12 mA
1.7
-
2.5
0.3
0.2
0.5
0.55
[2]
VOL(pu) power-up LOW-level
output voltage
VCC = 2.7 V; IO = 1 mA; VI = VCC or GND
-
II
input leakage current
control pins
VCC = 2.7 V; VI = GND
VCC = 2.7 V; VI = 5.5 V
I/O data pins
-
-
0.1
0.1
±1
10
μA
μA
[3]
VCC = 2.7 V; VI = 5.5 V
VCC = 2.7 V; VI = VCC
VCC = 2.7 V; VI = 0 V
-
-
-
-
-
-
-
0.1
0.5
0.1
0.1
100
-70
10
10
1
μA
μA
μA
μA
μA
μA
μA
-5
IOFF
IBHL
IBHH
IEX
power-off leakage current VCC = 0 V; VI or VO = 0 V to 4.5 V
±100
-
[4]
[4]
bus hold LOW current
bus hold HIGH current
external current
data inputs; VCC = 2.5 V; VI = 0.7 V
data inputs; VCC = 2.5 V; VI = 1.7 V
-
output HIGH-state when VO > VCC
;
125
VO = 5.5 V; VCC = 2.5 V
[5]
IO(pu\pd) power-up/power-down
output current
VCC ≤ 1.2 V; VO = 0.5 V to VCC
VI = GND or VCC
;
-
1
±100
μA
IOZ
OFF-state output current
VCC = 2.7 V; VI = VIL or VIH
output HIGH state; VO = 2.3 V
output LOW-state; VO = 0.5 V
-
-
0.5
0.5
5
μA
μA
-5
ICC
supply current
VCC = 2.7 V; VI = GND or VCC; IO = 0 A
outputs HIGH-state
-
-
-
0.04
2.7
0.1
4.5
0.1
mA
mA
mA
outputs LOW-state
[6]
outputs disabled
0.04
74ALVT162823
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 23 January 2018
7 / 18
Nexperia
74ALVT162823
18-bit bus-interface D-type flip-flop with reset and enable with 30 Ω termination resistors; 3-state
Symbol Parameter
Conditions
Min
Typ[1]
Max
Unit
[7]
ΔICC
additional supply current
per input pin; VCC = 2.3 V to 2.7 V;
one input at VCC - 0.6 V,
-
0.04
0.4
mA
other inputs at VCC or GND
CI
input capacitance
output capacitance
VI = 0 V or VCC
-
-
3
9
-
-
pF
pF
CO
VI/O = 0 V or 3.0 V
VCC = 3.3 V ± 0.3 V
VIK
VIH
VIL
input clamping voltage
VCC = 3.0 V; IIK = -18 mA
-
2.0
-
-0.85
-1.2
-
V
V
V
V
V
V
HIGH-level input voltage
LOW-level input voltage
-
-
0.8
-
VOH
VOL
HIGH-level output voltage VCC = 3.0 V; IO = −12 mA
LOW-level output voltage VCC = 3.0 V; IO = 12 mA
2.0
-
2.3
0.5
-
0.8
0.55
[2]
VOL(pu) power-up LOW-level
output voltage
VCC = 3.6 V; IO = 1 mA; VI = VCC or GND
-
II
input leakage current
control pins
VCC = 3.6 V; VI = VCC or GND
VCC = 0 V or 3.6 V; VI = 5.5 V
I/O data pins
-
-
0.1
0.1
±1
10
μA
μA
[3]
VCC = 3.6 V; VI = 5.5 V
VCC = 3.6 V; VI = VCC
VCC = 3.6 V; VI = 0 V
-
-
0.1
0.5
0.1
0.1
130
-140
-
10
μA
μA
μA
μA
μA
μA
μA
1
-
−5
IOFF
IBHL
IBHH
IBHLO
power-off leakage current VCC = 0 V; VI or VO = 0 V to 4.5 V
-
±100
bus hold LOW current
bus hold HIGH current
data inputs; VCC = 3 V; VI = 0.8 V
data inputs; VCC = 3 V; VI = 2.0 V
data inputs; VCC = 3.6 V; VI = 0 V to 3.6 V
75
-75
500
-
-
-
[8]
[8]
bus hold LOW overdrive
current
IBHHO
IEX
bus hold HIGH overdrive
current
data inputs; VCC = 3.6 V; VI = 0 V to 3.6 V
−500
-
-
μA
μA
μA
external current
output HIGH-state when VO > VCC
VO = 5.5 V; VCC = 3.0 V
;
-
-
10
1
125
±100
[9]
IO(pu\pd) power-up/power-down
output current
VCC ≤ 1.2 V; VO = 0.5 V to VCC
VI = GND or VCC
;
IOZ
OFF-state output current
VCC = 3.6 V; VI = VIL or VIH
output HIGH state; VO = 3.0 V
output LOW-state; VO = 0.5 V
-
-
0.5
0.5
5
μA
μA
−5
ICC
supply current
VCC = 3.6 V; VI = GND or VCC; IO = 0 A
outputs HIGH-state
-
-
-
0.05
3.9
0.1
5.5
0.1
mA
mA
mA
outputs LOW-state
[6]
outputs disabled
0.06
74ALVT162823
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 23 January 2018
8 / 18
Nexperia
74ALVT162823
18-bit bus-interface D-type flip-flop with reset and enable with 30 Ω termination resistors; 3-state
Symbol Parameter
Conditions
Min
Typ[1]
Max
Unit
[7]
ΔICC
additional supply current
per input pin; VCC = 3 V to 3.6 V;
one input at VCC - 0.6 V,
-
0.04
0.4
mA
other inputs at VCC or GND
CI
input capacitance
output capacitance
VI = 0 V or VCC
-
-
3
9
-
-
pF
pF
CO
VI/O = 0 V or 3.0 V
[1] All typical values for VCC = 2.5 V ± 0.2 V are measured at VCC = 2.5 V and Tamb = 25 °C.
All typical values for VCC = 3.3 V ± 0.3 V are measured at VCC = 3.3 V and Tamb = 25 °C.
[2] For valid test results, data must not be loaded into the flip-flops after applying power.
[3] Unused pins at VCC or GND.
[4] Not guaranteed.
[5] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 2.5 V ± 0.2 V a transition time of
100 μs is permitted. This parameter is valid for Tamb = 25 °C only.
[6] ICC is measured with outputs pulled up to VCC or pulled down to ground.
[7] This is the increase in supply current for each input at the specified voltage level other than VCC or GND.
[8] This is the bus hold overdrive current required to force the input to the opposite logic state.
[9] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V ± 0.3 V a transition time of
100 μs is permitted. This parameter is valid for Tamb = 25 °C only.
10 Dynamic characteristics
Table 7.ꢀDynamic characteristics
Voltages are referenced to GND (ground = 0 V); Tamb = −40 °C to +85 °C; for test circuit see Figure 10.
Symbol Parameter
VCC = 2.5 V ± 0.2 V
Conditions
Min
Typ[1]
Max
Unit
tPLH
tPHL
LOW to HIGH propagation delay
nCP to nQn; see Figure 6
nCP to nQn; see Figure 6
nMR to nQn; see Figure 8
nOE to nQn; see Figure 9
nOE to nQn; see Figure 9
nOE to nQn; see Figure 9
nOE to nQn; see Figure 9
nDn to nCP; see Figure 7
nCE to nCP; see Figure 7
nDn to nCP; see Figure 7
nCE to nCP; see Figure 7
nDn to nCP; see Figure 7
nCE to nCP; see Figure 7
nDn to nCP; see Figure 7
nCE to nCP; see Figure 7
nCP HIGH; see Figure 6
nCP LOW
2.1
2.0
2.0
2.8
2.0
2.3
2.0
1.0
1.0
2.0
0.5
0.1
1.0
0.1
1.0
2.0
3.0
2.0
2.3
3.7
2.8
3.0
4.4
3.4
3.2
2.5
0.5
0.2
1.3
−0.1
−1.4
0.2
−0.5
−0.1
0.8
2.1
0.8
1.3
5.8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
HIGH-to-LOW propagation delay
4.6
4.6
tPZH
tPZL
tPHZ
tPLZ
tsu(H)
OFF-state to HIGH propagation delay
OFF-state to LOW propagation delay
HIGH to OFF-state propagation delay
LOW to OFF-state propagation delay
set-up time HIGH
6.6
5.2
4.6
3.5
-
-
-
-
-
-
-
-
-
-
-
-
tsu(L)
th(H)
th(L)
tW
set-up time LOW
hold time HIGH
hold time LOW
pulse width
nMR LOW; see Figure 8
nMR to nCP; see Figure 8
trec
recovery time
74ALVT162823
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 23 January 2018
9 / 18
Nexperia
74ALVT162823
18-bit bus-interface D-type flip-flop with reset and enable with 30 Ω termination resistors; 3-state
Symbol Parameter
VCC = 3.3 V ± 0.3 V
Conditions
Min
Typ[1]
Max
Unit
tPLH
tPHL
LOW to HIGH propagation delay
nCP to nQn; see Figure 6
nCP to nQn; see Figure 6
nMR to nQn; see Figure 8
nOE to nQn; see Figure 9
nOE to nQn; see Figure 9
nOE to nQn; see Figure 9
nOE to nQn; see Figure 9
nDn to nCP; see Figure 7
nCE to nCP; see Figure 7
nDn to nCP; see Figure 7
nCE to nCP; see Figure 7
nDn to nCP; see Figure 7
nCE to nCP; see Figure 7
nDn to nCP; see Figure 7
nCE to nCP; see Figure 7
nCP HIGH; see Figure 6
nCP LOW
1.8
1.6
1.8
2.0
1.7
2.4
1.9
1.0
1.0
1.6
0.5
0.1
1.0
0.1
1.0
1.5
2.5
2.0
2.0
2.9
2.3
2.5
3.5
2.8
3.5
2.8
0.5
0.1
1.1
−0.5
−0.5
−0.1
−0.7
0.5
0.7
1.4
1.5
1.1
4.4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
HIGH-to-LOW propagation delay
3.6
3.7
tPZH
tPZL
tPHZ
tPLZ
tsu(H)
OFF-state to HIGH propagation delay
OFF-state to LOW propagation delay
HIGH to OFF-state propagation delay
LOW to OFF-state propagation delay
set-up time HIGH
5.2
3.8
4.7
3.8
-
-
-
-
-
-
-
-
-
-
-
-
tsu(L)
th(H)
th(L)
tW
set-up time LOW
hold time HIGH
hold time LOW
pulse width
nMR LOW; see Figure 8
nMR to nCP; see Figure 8
trec
recovery time
[1] All typical values for VCC = 2.5 V ± 0.2 V are measured at VCC = 2.5 V and Tamb = 25 °C.
All typical values for VCC = 3.3 V ± 0.3 V are measured at VCC = 3.3 V and Tamb = 25 °C.
74ALVT162823
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 23 January 2018
10 / 18
Nexperia
74ALVT162823
18-bit bus-interface D-type flip-flop with reset and enable with 30 Ω termination resistors; 3-state
10.1 Waveforms and test circuit
1/f
max
V
I
nCP input
V
V
M
M
GND
t
W
t
t
PHL
PLH
V
OH
V
nQn output
M
001aaa256
V
OL
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Figure 6.ꢀPropagation delay clock input (nCP) to output (nQn), clock pulse (nCP) width HIGH and maximum clock
frequency
V
I
input nDn,
nCE
V
V
V
V
M
M
M
M
GND
t
t
t
t
h(L)
su(H)
h(H)
su(L)
V
I
input nCP
V
V
M
M
GND
001aad401
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Figure 7.ꢀData set-up and hold times
V
I
V
V
t
input nMR
GND
M
M
t
WL
rec
V
I
input nCP
GND
V
M
t
PHL
V
OH
V
output nQn
M
V
OL
001aad400
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Figure 8.ꢀMaster reset (nMR) pulse width, master reset (nMR) to output (nQn) propagation delay and master reset
(nMR) to clock (nCP) recovery time
74ALVT162823
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 23 January 2018
11 / 18
Nexperia
74ALVT162823
18-bit bus-interface D-type flip-flop with reset and enable with 30 Ω termination resistors; 3-state
V
I
nOE input
V
V
M
M
t
GND
t
PLZ
PZL
V
CC
nQn output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
nQn output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aal795
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Figure 9.ꢀOFF-state to HIGH and LOW propagation delays and LOW and HIGH to OFF-state propagation delays
Table 8.ꢀMeasurement points
VCC
Input
VM
Output
VM
VX
VY
≤ 2.7 V
≥ 3.0 V
0.5 x VCC
1.5 V
0.5 x VCC
1.5 V
VOL + 0.15 V
VOL + 0.3 V
VOH - 0.15 V
VOH - 0.3 V
74ALVT162823
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 23 January 2018
12 / 18
Nexperia
74ALVT162823
18-bit bus-interface D-type flip-flop with reset and enable with 30 Ω termination resistors; 3-state
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
R
V
CC
L
V
V
O
I
G
DUT
R
T
C
L
R
L
001aae331
Test data is given in Table 9.
Definitions test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = Test voltage for switching times.
Figure 10.ꢀTest circuit for measuring switching times
Table 9.ꢀTest data
Input
VI
Load
CL
VEXT
fi
tW
tr, tf
RL
tPHZ, tPZH tPLZ, tPZL
tPLH, tPHL
3.0 V or VCC
≤ 10 MHz 500 ns
≤ 2.5 ns
50 pF
500 Ω
GND
6 V or VCC x 2 open
whichever is less
74ALVT162823
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 23 January 2018
13 / 18
Nexperia
74ALVT162823
18-bit bus-interface D-type flip-flop with reset and enable with 30 Ω termination resistors; 3-state
11 Package outline
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm
SOT364-1
E
D
A
X
c
H
v
M
A
y
E
Z
56
29
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
detail X
1
28
w
M
b
e
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions).
A
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
E
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
max.
8o
0o
0.15
0.05
1.05
0.85
0.28
0.17
0.2
0.1
14.1
13.9
6.2
6.0
8.3
7.9
0.8
0.4
0.50
0.35
0.5
0.1
mm
1.2
0.5
1
0.25
0.08
0.1
0.25
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT364-1
MO-153
Figure 11.ꢀPackage outline SOT364-1 (TSSOP56)
74ALVT162823
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 23 January 2018
14 / 18
Nexperia
74ALVT162823
18-bit bus-interface D-type flip-flop with reset and enable with 30 Ω termination resistors; 3-state
12 Abbreviations
Table 10.ꢀAbbreviations
Acronym
Description
DUT
ESD
MIL
Device Under Test
ElectroStatic Discharge
Military
MM
Machine Model
MOS
Metal-Oxide Semiconductor
13 Revision history
Table 11.ꢀRevision history
Document ID
Release date
20180123
Data sheet status
Change notice
Supersedes
74ALVT162823 v.3
Modifications:
Product data sheet
-
74ALVT162823 v.2
• The format of this data sheet has been redesigned to comply with the identity guidelines of
Nexperia.
• Legal texts have been adapted to the new company name where appropriate.
• Type number 74ALVT162823DL (SOT371-1 / SSOP56) removed.
74ALVT162823 v.2
Modifications:
20050811
Product data sheet
-
74ALVT162823 v.1
• The format of this data sheet has been redesigned to comply with the new presentation and
information standard of Philips Semiconductors.
• Section 2: modified ‘Jedec Std 17’ into ‘JESD78’
• Section 10: changed propagation delays.
74ALVT162823 v.1
19980827
Product specification
-
-
74ALVT162823
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 23 January 2018
15 / 18
Nexperia
74ALVT162823
18-bit bus-interface D-type flip-flop with reset and enable with 30 Ω termination resistors; 3-state
14 Legal information
14.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Product [short] data sheet
Qualification
Production
This document contains data from the preliminary specification.
This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nexperia.com.
systems or equipment, nor in applications where failure or malfunction
of an Nexperia product can reasonably be expected to result in personal
14.2 Definitions
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
Draft — The document is a draft version only. The content is still under
such equipment or applications and therefore such inclusion and/or use is at
internal review and subject to formal approval, which may result in
the customer’s own risk.
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
Short data sheet — A short data sheet is an extract from a full data sheet
without further testing or modification. Customers are responsible for the
with the same product type number(s) and title. A short data sheet is
design and operation of their applications and products using Nexperia
intended for quick reference only and should not be relied upon to contain
products, and Nexperia accepts no liability for any assistance with
detailed and full information. For detailed and full information see the
applications or customer product design. It is customer’s sole responsibility
relevant full data sheet, which is available on request via the local Nexperia
to determine whether the Nexperia product is suitable and fit for the
sales office. In case of any inconsistency or conflict with the short data sheet,
customer’s applications and products planned, as well as for the planned
the full data sheet shall prevail.
application and use of customer’s third party customer(s). Customers should
provide appropriate design and operating safeguards to minimize the risks
associated with their applications and products. Nexperia does not accept
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
any liability related to any default, damage, costs or problem which is based
Nexperia and its customer, unless Nexperia and customer have explicitly
on any weakness or default in the customer’s applications or products, or
agreed otherwise in writing. In no event however, shall an agreement be
the application or use by customer’s third party customer(s). Customer is
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
responsible for doing all necessary testing for the customer’s applications
and products using Nexperia products in order to avoid a default of the
applications and the products or of the application or use by customer’s third
party customer(s). Nexperia does not accept any liability in this respect.
14.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
Limited warranty and liability — Information in this document is believed
damage to the device. Limiting values are stress ratings only and (proper)
to be accurate and reliable. However, Nexperia does not give any
operation of the device at these or any other conditions above those
representations or warranties, expressed or implied, as to the accuracy
given in the Recommended operating conditions section (if present) or the
or completeness of such information and shall have no liability for the
Characteristics sections of this document is not warranted. Constant or
consequences of use of such information. Nexperia takes no responsibility
repeated exposure to limiting values will permanently and irreversibly affect
for the content in this document if provided by an information source outside
the quality and reliability of the device.
of Nexperia. In no event shall Nexperia be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation -
lost profits, lost savings, business interruption, costs related to the removal
Terms and conditions of commercial sale — Nexperia products are
sold subject to the general terms and conditions of commercial sale, as
or replacement of any products or rework charges) whether or not such
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
damages are based on tort (including negligence), warranty, breach of
in a valid written individual agreement. In case an individual agreement is
contract or any other legal theory. Notwithstanding any damages that
concluded only the terms and conditions of the respective agreement shall
customer might incur for any reason whatsoever, Nexperia's aggregate and
apply. Nexperia hereby expressly objects to applying the customer’s general
cumulative liability towards customer for the products described herein shall
terms and conditions with regard to the purchase of Nexperia products by
customer.
be limited in accordance with the Terms and conditions of commercial sale of
Nexperia.
No offer to sell or license — Nothing in this document may be interpreted
Right to make changes — Nexperia reserves the right to make changes
or construed as an offer to sell products that is open for acceptance or
to information published in this document, including without limitation
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-critical
74ALVT162823
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 23 January 2018
16 / 18
Nexperia
74ALVT162823
18-bit bus-interface D-type flip-flop with reset and enable with 30 Ω termination resistors; 3-state
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified, the
product is not suitable for automotive use. It is neither qualified nor tested in
accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of non-automotive qualified
products in automotive equipment or applications. In the event that customer
uses the product for design-in and use in automotive applications to
automotive specifications and standards, customer (a) shall use the product
without Nexperia's warranty of the product for such automotive applications,
use and specifications, and (b) whenever customer uses the product for
automotive applications beyond Nexperia's specifications such use shall be
solely at customer’s own risk, and (c) customer fully indemnifies Nexperia
for any liability, damages or failed product claims resulting from customer
design and use of the product for automotive applications beyond Nexperia's
standard warranty and Nexperia's product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
14.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
74ALVT162823
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 23 January 2018
17 / 18
Nexperia
74ALVT162823
18-bit bus-interface D-type flip-flop with reset and enable with 30 Ω termination resistors; 3-state
Contents
1
2
3
4
General description ............................................ 1
Features and benefits .........................................1
Ordering information .......................................... 2
Functional diagram .............................................2
Pinning information ............................................ 4
Pinning ...............................................................4
Pin description ...................................................5
Functional description ........................................5
Limiting values ....................................................6
Recommended operating conditions ................6
Static characteristics ..........................................7
Dynamic characteristics .....................................9
Waveforms and test circuit .............................. 11
Package outline .................................................14
Abbreviations .................................................... 15
Revision history ................................................ 15
Legal information ..............................................16
5
5.1
5.2
6
7
8
9
10
10.1
11
12
13
14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© Nexperia B.V. 2018.
All rights reserved.
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 23 January 2018
Document identifier: 74ALVT162823
相关型号：
74ALVT162823DL
18-bit bus-interface D-type flip-flop with reset and enable with 30ohm termination resistors (3-State)
NXP
74ALVT162827DGG
20-bit buffer/line driver, non-inverting, with 30ohm termination resistors 3-State
NXP
74ALVT162827DGG
20-bit buffer/line driver, non-inverting,with 30Ohm termination resistors (3-State)Production
NEXPERIA
74ALVT162827DGG-T
IC ALVT SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, PDSO56, Bus Driver/Transceiver
NXP
©2020 ICPDF网 联系我们和版权申明