74AUP2G98DP [NEXPERIA]
Low-power dual PCB configurable multiple function gate;型号: | 74AUP2G98DP |
厂家: | Nexperia |
描述: | Low-power dual PCB configurable multiple function gate PC |
文件: | 总21页 (文件大小:871K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74AUP2G98
Low-power dual PCB configurable multiple function gate
Rev. 2 — 2 December 2015
Product data sheet
1. General description
The 74AUP2G98 is a dual configurable multiple function gate with Schmitt-trigger inputs.
Each gate within the device can be configured as any of the following logic functions
MUX, AND, OR, NAND, NOR, inverter and buffer; using the 3-bit input. All inputs can be
connected directly to VCC or GND.
This device ensures very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power down applications using IOFF. The IOFF
circuitry disables the output, preventing the potentially damaging backflow current through
the device when it is powered down.
2. Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
ESD protection:
HBM JESD22-A114F exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; ICC = 0.9 A (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial power-down mode operation
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
74AUP2G98
Nexperia
Low-power dual PCB configurable multiple function gate
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74AUP2G98DP 40 C to +125 C
74AUP2G98GU 40 C to +125 C
74AUP2G98GF 40 C to +125 C
TSSOP10 plastic thin shrink small outline package; 10 leads;
body width 3 mm
SOT552-1
XQFN10
plastic, extremely thin quad flat package; no leads;
SOT1160-1
10 terminals; body 1.40 1.80 0.50 mm
XSON10
plastic extremely thin small outline package; no leads; SOT1081-2
10 terminals; body 1.0 1.7 0.5 mm
4. Marking
Table 2.
Marking
Type number
Marking code[1]
74AUP2G98DP
74AUP2G98GU
74AUP2G98GF
a9
a9
a9
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Q$
Q<
Q%
Q&
DDDꢀꢁꢂꢃꢄꢁꢅ
Fig 1. Logic diagram (one gate)
74AUP2G98
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 2 December 2015
2 of 21
74AUP2G98
Nexperia
Low-power dual PCB configurable multiple function gate
6. Pinning information
6.1 Pinning
ꢀꢁ$83ꢂ*ꢃꢄ
ꢀꢈ
ꢉ
9
&&
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢀ$
ꢀ%
ꢀ<
ꢁ&
ꢁ%
ꢁ$
ꢆ
ꢀ&
ꢇ
ꢁ<
ꢅ
*1'
DDDꢀꢁꢂꢃꢄꢁꢆ
Fig 2. Pin configuration SOT552-1 (TSSOP10)
ꢀꢁ$83ꢂ*ꢃꢄ
ꢀꢁ$83ꢂ*ꢃꢄ
ꢀ$
ꢀ%
ꢀ
ꢀꢈ
ꢉ
9
&&
WHUPLQDOꢊꢀ
LQGH[ꢊDUHD
ꢁ
ꢂ
ꢃ
ꢄ
ꢀ<
ꢁ&
ꢁ%
ꢁ$
ꢁ&
ꢁ%
ꢀ%
ꢀ&
ꢀ
ꢁ
ꢇ
ꢅ
ꢀ&
ꢆ
ꢁ<
ꢇ
*1'
ꢅ
7UDQVSDUHQWꢊWRSꢊYLHZ
7UDQVSDUHQWꢊWRSꢊYLHZ
DDDꢀꢁꢂꢃꢄꢂꢂ
DDDꢀꢁꢂꢃꢄꢂꢇ
Fig 3. Pin configuration SOT1160-1 (XQFN10)
Fig 4. Pin configuration SOT1081-2 (XSON10)
74AUP2G98
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 2 December 2015
3 of 21
74AUP2G98
Nexperia
Low-power dual PCB configurable multiple function gate
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
SOT552-1 and SOT1081-2 SOT1160-1
Description
1A, 2A
1B, 2B
1C, 2C
1Y, 2Y
GND
1, 6
2, 7
3, 8
9, 4
5
10, 5
1, 6
2, 7
8, 3
4
data input
data input
data input
data output
ground (0 V)
supply voltage
VCC
10
9
7. Functional description
Table 4.
Function table[1]
Input
nC
L
Output
nB
L
nA
L
nY
H
H
L
L
L
H
L
L
H
H
L
L
H
L
L
H
H
L
H
L
H
L
H
H
H
H
L
H
H
[1] H = HIGH voltage level; L = LOW voltage level.
7.1 Logic configurations
Table 5.
Function selection table
Logic function
Figure
2-input MUX with inverted output
2-input NAND
see Figure 5
see Figure 6
see Figure 7
see Figure 7
see Figure 8
see Figure 8
see Figure 9
see Figure 10
see Figure 11
2-input NOR with one input inverted
2-input AND with one input inverted
2-input NAND with one input inverted
2-input OR with one input inverted
2-input NOR
Buffer
Inverter
74AUP2G98
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 2 December 2015
4 of 21
74AUP2G98
Nexperia
Low-power dual PCB configurable multiple function gate
9
9
&&
&&
Q%
Q$
ꢁꢋꢊꢇꢊ
ꢄ
ꢂꢋꢊꢆ
ꢀꢈ
Q&
ꢁꢋꢊꢇꢊ
ꢄ
ꢂꢋꢊꢆ
ꢀꢈ
Q&
Q%
Q$
Q&
Q$
Q&
Q<
Q<
Q<
Q$
Q<
ꢀꢋꢊꢅ
ꢉꢋꢊꢃ
ꢀꢋꢊꢅ
ꢉꢋꢊꢃ
DDDꢀꢁꢂꢃꢄꢂꢈ
DDDꢀꢁꢂꢃꢄꢂꢄ
Pin numbers are not valid for SOT1160-1 package
Pin numbers are not valid for SOT1160-1 package
Fig 5. 2-input MUX with inverted output
Fig 6. 2-input NAND gate
9
&&
9
&&
Q$
Q&
Q%
Q&
Q<
Q<
Q<
Q<
Q&
ꢁꢋꢊꢇꢊ
ꢄ
ꢂꢋꢊꢆ
ꢀꢈ
Q&
Q%
ꢁꢋꢊꢇꢊ
ꢄ
ꢂꢋꢊꢆ
ꢀꢈ
Q$
Q&
Q$
Q<
Q%
Q&
Q<
ꢀꢋꢊꢅ
ꢉꢋꢊꢃ
ꢀꢋꢊꢅ
ꢉꢋꢊꢃ
DDDꢀꢁꢂꢃꢄꢂꢃ
DDDꢀꢁꢂꢃꢄꢂꢉ
Pin numbers are not valid for SOT1160-1 package
Pin numbers are not valid for SOT1160-1 package
Fig 7. 2-input AND gate with input A inverted or
2-input NOR gate with inverted C input
Fig 8. 2-input OR gate with input B inverted or
2-input NAND gate with input C inverted
9
&&
9
&&
Q%
Q&
ꢁꢋꢊꢇꢊ
ꢄ
ꢂꢋꢊꢆ
ꢀꢈ
Q&
ꢁꢋꢊꢇꢊ
ꢄ
ꢂꢋꢊꢆ
ꢀꢈ
Q%
Q&
Q<
Q&
Q<
Q<
ꢀꢋꢊꢅ
ꢉꢋꢊꢃ
Q<
DDDꢀꢁꢂꢃꢄꢂꢅ
ꢀꢋꢊꢅ
ꢉꢋꢊꢃ
DDDꢀꢁꢂꢃꢄꢂꢊ
Pin numbers are not valid for SOT1160-1 package
Pin numbers are not valid for SOT1160-1 package
Fig 9. 2-input NOR gate
Fig 10. Buffer
9
&&
Q%
ꢁꢋꢊꢇꢊ
ꢄ
ꢂꢋꢊꢆ
ꢀꢈ
Q%
Q<
Q<
ꢀꢋꢊꢅ
ꢉꢋꢊꢃ
DDDꢀꢁꢂꢃꢄꢂꢆ
Pin numbers are not valid for SOT1160-1 package
Fig 11. Inverter
74AUP2G98
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 2 December 2015
5 of 21
74AUP2G98
Nexperia
Low-power dual PCB configurable multiple function gate
8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
0.5
50
0.5
50
0.5
Max
+4.6
-
Unit
V
supply voltage
input clamping current
input voltage
VI < 0 V
mA
V
[1]
[1]
VI
+4.6
-
IOK
output clamping current VO < 0 V
mA
V
VO
output voltage
Active mode and Power-down
+4.6
mode
IO
output current
VO = 0 V to VCC
-
20
50
mA
mA
mA
C
ICC
IGND
Tstg
Ptot
supply current
-
ground current
50
65
-
-
storage temperature
total power dissipation
+150
250
[2]
Tamb = 40 C to +125 C
mW
[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP10 package: above 125C the value of Ptot derates linearly with 8.33 mW/K.
For XQFN10 (SOT1160-1) package: above 128 C the value of Ptot derates linearly with 11.5 mW/K.
For XSON10 package: above 45 C the value of Ptot derates linearly with 2.4 mW/K.
9. Recommended operating conditions
Table 7.
Symbol
VCC
Recommended operating conditions
Parameter
Conditions
Min
0.8
0
Max
3.6
Unit
supply voltage
V
VI
input voltage
3.6
V
VO
output voltage
Active mode
0
VCC
3.6
V
Power-down mode; VCC = 0 V
0
V
Tamb
ambient temperature
40
+125
C
74AUP2G98
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 2 December 2015
6 of 21
74AUP2G98
Nexperia
Low-power dual PCB configurable multiple function gate
10. Static characteristics
Table 8.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 C
VOH
HIGH-level output voltage VI = VT+ or VT
IO = 20 A; VCC = 0.8 V to 3.6 V
VCC 0.1
0.75 VCC
1.11
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = VT+ or VT
1.32
2.05
1.9
2.72
2.6
VOL
LOW-level output voltage
IO = 20 A; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
0.3 VCC
0.31
0.31
0.31
0.44
0.31
0.44
0.1
0.2
0.2
V
V
V
V
V
V
V
II
input leakage current
A
A
A
IOFF
IOFF
power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
-
-
-
-
0.5
40
A
A
[1]
ICC
additional supply current
VI = VCC 0.6 V; IO = 0 A;
VCC = 3.3 V
CI
input capacitance
output capacitance
VCC = 0 V to 3.6 V; VI = GND or VCC
VO = GND; VCC = 0 V
-
-
1.1
1.7
-
-
pF
pF
CO
74AUP2G98
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 2 December 2015
7 of 21
74AUP2G98
Nexperia
Low-power dual PCB configurable multiple function gate
Table 8.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 40 C to +85 C
VOH
HIGH-level output voltage VI = VT+ or VT
IO = 20 A; VCC = 0.8 V to 3.6 V
VCC 0.1
0.7 VCC
1.03
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = VT+ or VT
1.30
1.97
1.85
2.67
2.55
VOL
LOW-level output voltage
IO = 20 A; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
0.3 VCC
0.37
0.35
0.33
0.45
0.33
0.45
0.5
0.5
0.6
V
V
V
V
V
V
V
II
input leakage current
A
A
A
IOFF
IOFF
power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
-
-
-
-
0.9
50
A
A
[1]
ICC
additional supply current
VI = VCC 0.6 V; IO = 0 A;
VCC = 3.3 V
74AUP2G98
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 2 December 2015
8 of 21
74AUP2G98
Nexperia
Low-power dual PCB configurable multiple function gate
Table 8.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 40 C to +125 C
VOH
HIGH-level output voltage VI = VT+ or VT
IO = 20 A; VCC = 0.8 V to 3.6 V
VCC 0.11 -
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = VT+ or VT
0.6 VCC
0.93
-
-
-
-
-
-
-
1.17
1.77
1.67
2.40
2.30
VOL
LOW-level output voltage
IO = 20 A; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.11
V
0.33 VCC
0.41
V
V
0.39
V
0.36
V
0.50
V
0.36
V
0.50
V
II
input leakage current
0.75
0.75
0.75
A
A
A
IOFF
IOFF
power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
-
-
-
-
1.4
75
A
A
[1]
ICC
additional supply current
VI = VCC 0.6 V; IO = 0 A;
VCC = 3.3 V
[1] One input at VCC 0.6 V, other input at VCC or GND.
74AUP2G98
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 2 December 2015
9 of 21
74AUP2G98
Nexperia
Low-power dual PCB configurable multiple function gate
11. Dynamic characteristics
Table 9.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 13.
Symbol Parameter
Conditions
Tamb = 25 C
Tamb = 40 C to +125 C Unit
Min Typ[1] Max
Min
Max
Max
(85 C) (125 C)
CL = 5 pF
[2]
[2]
[2]
[2]
tpd
propagation delay nA, nB, nC to nY; see Figure 12
VCC = 0.8 V
-
23.3
6.7
4.8
4.0
3.2
2.9
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
2.9
2.4
2.2
2.0
1.9
12.9
7.7
6.3
4.6
4.0
2.7
2.4
1.9
1.8
1.6
13.2
8.3
7.0
5.2
4.2
13.4
8.7
7.4
5.4
4.4
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
CL = 10 pF
tpd
propagation delay nA, nB, nC to nY; see Figure 12
VCC = 0.8 V
-
27.1
7.6
5.4
4.6
3.8
3.5
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
3.3
2.7
2.5
2.4
2.3
14.5
8.8
7.2
5.3
4.7
3.0
2.8
2.3
2.2
2.0
15.1
9.5
8.0
5.9
4.9
15.3
9.9
8.4
6.2
5.2
CL = 15 pF
tpd
propagation delay nA, nB, nC to nY; see Figure 12
VCC = 0.8 V
-
30.6
8.4
6.0
5.1
4.2
3.9
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
3.6
3.0
2.8
2.7
2.5
16.1
9.7
7.9
5.9
5.2
3.3
3.1
2.5
2.5
2.2
16.9
10.5
8.9
17.2
11.0
9.3
7.0
5.8
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
6.6
VCC = 3.0 V to 3.6 V
5.5
CL = 30 pF
tpd
propagation delay nA, nB, nC to nY; see Figure 12
VCC = 0.8 V
-
38.7
10.7
7.6
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
4.5
3.8
3.5
3.4
3.2
21.1
12.3
10.1
7.5
4.1
3.8
3.1
3.2
2.9
22.0
13.5
11.3
8.4
22.4
14.2
11.9
8.9
6.3
5.3
5.0
6.7
7.1
7.5
74AUP2G98
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 2 December 2015
10 of 21
74AUP2G98
Nexperia
Low-power dual PCB configurable multiple function gate
Table 9.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 13.
Symbol Parameter
Conditions
Tamb = 25 C
Tamb = 40 C to +125 C Unit
Min Typ[1] Max
Min
Max
Max
(85 C) (125 C)
CL = 5 pF, 10 pF, 15 pF and 30 pF
CPD power dissipation fi = 1 MHz; VI = GND to VCC
[3]
capacitance
VCC = 0.8 V
-
-
-
-
-
-
2.7
2.9
3.0
3.2
3.8
4.4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
pF
pF
pF
pF
pF
pF
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
[1] All typical values are measured at nominal VCC
.
[2] tpd is the same as tPLH and tPHL
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of the outputs.
12. Waveforms
9
,
Q$ꢋꢊQ%ꢋꢊQ&ꢊLQSXW
*1'
9
9
0
0
W
W
3/+
3+/
9
2+
9
9
9
0
Q<ꢊRXWSXW
0
9
2/
W
W
3+/
3/+
9
2+
Q<ꢊRXWSXW
9
0
0
9
2/
DDDꢀꢁꢂꢃꢈꢅꢈ
Measurement points are given in Table 10.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 12. Input nA, nB and nC to output nY propagation delay times.
74AUP2G98
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 2 December 2015
11 of 21
74AUP2G98
Nexperia
Low-power dual PCB configurable multiple function gate
Table 10. Measurement points
Supply voltage
VCC
Output
Input
VM
VM
VI
tr = tf
0.8 V to 3.6 V
0.5VCC
0.5 VCC
0.5 VCC
3.0 ns
9
9
&&
(;7
ꢄꢊNȍ
9
,
9
2
*
'87
5
7
&
/
5
/
ꢁꢁꢂDDFꢃꢇꢂ
Test data is given in Table 11.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
EXT = External voltage for measuring switching times.
V
Fig 13. Test circuit for measuring switching times
Table 11. Test data
Supply voltage
VCC
Load
CL
VEXT
[1]
RL
tPLH, tPHL
open
tPZH, tPHZ
GND
tPZL, tPLZ
0.8 V to 3.6 V
5 pF, 10 pF, 15 pF and 30 pF 5 k or 1 M
2VCC
[1] For measuring enable and disable times, RL = 5 k, for measuring propagation delays, setup and hold times and pulse width RL = 1
M.
74AUP2G98
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 2 December 2015
12 of 21
74AUP2G98
Nexperia
Low-power dual PCB configurable multiple function gate
13. Transfer characteristics
Table 12. Transfer characteristics
Voltages are referenced to GND (ground = 0 V; for test circuit, see Figure 13.
Symbol Parameter
Conditions
Tamb = 25 C
Min Typ Max
Tamb = 40 C to +125 C Unit
Min
Max
Max
(85 C) (125 C)
VT+
VT
VH
positive-going
threshold voltage
see Figure 14 and Figure 15
VCC = 0.8 V
0.30
0.53
0.74
0.91
1.37
1.88
-
-
-
-
-
-
0.60
0.90
1.11
1.29
1.77
2.29
0.30
0.53
0.74
0.91
1.37
1.88
0.60
0.90
1.11
1.29
1.77
2.29
0.62
0.92
1.13
1.31
1.80
2.32
V
V
V
V
V
V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
negative-going
threshold voltage
see Figure 14 and Figure 15
VCC = 0.8 V
0.10
0.26
0.39
0.47
0.69
0.88
-
-
-
-
-
-
0.60
0.65
0.75
0.84
1.04
1.24
0.10
0.26
0.39
0.47
0.69
0.88
0.60
0.65
0.75
0.84
1.04
1.24
0.60
0.65
0.75
0.84
1.04
1.24
V
V
V
V
V
V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
hysteresis
voltage
(VT+ VT); see Figure 14, Figure 15, Figure 16 and Figure 17
VCC = 0.8 V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
0.07
0.08
0.18
0.27
0.53
0.79
-
-
-
-
-
-
0.50
0.46
0.56
0.66
0.92
1.31
0.07
0.08
0.18
0.27
0.53
0.79
0.50
0.46
0.56
0.66
0.92
1.31
0.50
0.46
0.56
0.66
0.92
1.31
V
V
V
V
V
V
14. Waveforms transfer characteristics
9
7ꢌ
9
2
9
,
9
+
9
7ꢍ
9
2
9
,
PQDꢇꢁꢅ
9
+
9
9
7ꢌ
7ꢍ
PQDꢇꢁꢊ
VT+ and VT limits at 70 % and 20 %.
Fig 14. Transfer characteristic
Fig 15. Definition of VT+, VT and VH
74AUP2G98
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 2 December 2015
13 of 21
74AUP2G98
Nexperia
Low-power dual PCB configurable multiple function gate
001aad691
240
I
CC
(μA)
160
80
0
0
0.4
0.8
1.2
1.6
2.0
V (V)
I
Fig 16. Typical transfer characteristics; VCC = 1.8 V
001aad692
1200
I
CC
(μA)
800
400
0
0
1.0
2.0
3.0
V (V)
I
Fig 17. Typical transfer characteristics; VCC = 3.0 V
74AUP2G98
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 2 December 2015
14 of 21
74AUP2G98
Nexperia
Low-power dual PCB configurable multiple function gate
15. Package outline
76623ꢆꢋꢌꢅSODVWLFꢅWKLQꢅVKULQNꢅVPDOOꢅRXWOLQHꢅSDFNDJHꢍꢅꢆꢋꢅOHDGVꢍꢅERG\ꢅZLGWKꢅꢈꢅPPꢅ
627ꢎꢎꢂꢏꢆꢅ
'ꢊ
(ꢊ
$ꢊ
;ꢊ
Fꢊ
\ꢊ
+
Yꢊ 0ꢊ
$ꢊ
(ꢊ
=ꢊ
ꢅꢊ
ꢀꢈꢊ
$
ꢏ$ ꢐꢊ
ꢁꢊ
$ꢊ
ꢂ
$
ꢀꢊ
SLQꢊꢀꢊLQGH[ꢊ
șꢊ
/
Sꢊ
/ꢊ
GHWDLOꢊ;ꢊ
ꢀꢊ
ꢄꢊ
Hꢊ
Zꢊ 0ꢊ
E
Sꢊ
ꢈꢊ
ꢁꢎꢄꢊ
ꢄꢊPPꢊ
VFDOHꢊ
',0(16,216ꢅꢉPPꢅDUHꢅWKHꢅRULJLQDOꢅGLPHQVLRQVꢊꢅ
$ꢅ
ꢉꢆꢊꢅ
ꢉꢂꢊꢅ
ꢉꢆꢊꢅ
$
$
$
E
Fꢅ
'
(
Hꢅ
+
/ꢅ
/
81,7ꢅ
PPꢊ
Yꢅ
Zꢅ
\ꢅ
=
șꢊ
ꢆꢅ
ꢂꢅ
ꢈꢅ
Sꢅ
(ꢅ
Sꢅ
PD[ꢇꢅ
ꢈꢎꢀꢄꢊ ꢈꢎꢉꢄꢊ
ꢈꢎꢈꢄꢊ ꢈꢎꢆꢈꢊ
ꢈꢎꢂꢈꢊ ꢈꢎꢁꢂꢊ
ꢈꢎꢀꢄꢊ ꢈꢎꢀꢄꢊ
ꢂꢎꢀꢊ
ꢁꢎꢉꢊ
ꢂꢎꢀꢊ
ꢁꢎꢉꢊ
ꢄꢎꢈꢊ
ꢃꢎꢆꢊ
ꢈꢎꢇꢊ
ꢈꢎꢃꢊ
ꢈꢎꢅꢇꢊ
ꢈꢎꢂꢃꢊ
ꢅꢊ
ꢈꢊ
ꢀꢎꢀꢊ
ꢈꢎꢄꢊ
ꢈꢎꢉꢄꢊ
ꢈꢎꢀꢊ
ꢈꢎꢀꢊ
ꢈꢎꢀꢊ
ꢈꢎꢁꢄꢊ
1RWHVꢅ
ꢀꢎꢊ3ODVWLFꢊRUꢊPHWDOꢊSURWUXVLRQVꢊRIꢊꢈꢎꢀꢄꢊPPꢊPD[LPXPꢊSHUꢊVLGHꢊDUHꢊQRWꢊLQFOXGHGꢎꢊ
ꢁꢎꢊ3ODVWLFꢊRUꢊPHWDOꢊSURWUXVLRQVꢊRIꢊꢈꢎꢁꢄꢊPPꢊPD[LPXPꢊSHUꢊVLGHꢊDUHꢊQRWꢊLQFOXGHGꢎꢊ
ꢅ5()(5(1&(6ꢅ
ꢅ-('(&ꢅ ꢅ-(,7$ꢅ
287/,1(ꢅ
9(56,21ꢅ
(8523($1ꢅ
352-(&7,21ꢅ
,668(ꢅ'$7(ꢅ
ꢅ,(&ꢅ
ꢉꢉꢍꢈꢇꢍꢁꢉꢊ
ꢈꢂꢍꢈꢁꢍꢀꢆꢊ
ꢊ627ꢄꢄꢁꢍꢀꢊ
ꢊ
Fig 18. Package outline SOT552-1 (TSSOP10)
74AUP2G98
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 2 December 2015
15 of 21
74AUP2G98
Nexperia
Low-power dual PCB configurable multiple function gate
;4)1ꢆꢋꢌꢅSODVWLFꢐꢅH[WUHPHO\ꢅWKLQꢅTXDGꢅIODWꢅSDFNDJHꢍꢅQRꢅOHDGVꢍꢅ
ꢆꢋꢅWHUPLQDOVꢍꢅERG\ꢅꢆꢇꢁꢋꢅ[ꢅꢆꢇꢄꢋꢅ[ꢅꢋꢇꢎꢋꢅPP
627ꢆꢆꢑꢋꢏꢆ
;
'
%
$
(
WHUPLQDOꢊꢀꢊ
LQGH[ꢊDUHD
$
$
ꢀ
$
ꢂ
GHWDLOꢊ;
H
ꢀ
H
&
Y
Z
& $ %
&
E
\
&
ꢀ
\
ꢂ
ꢄ
/
ꢁ
ꢀ
ꢅ
ꢇ
H
ꢁ
WHUPLQDOꢊꢀꢊ
LQGH[ꢊDUHD
ꢀꢈ
ꢆ
/
ꢀ
ꢈ
ꢀ
ꢁꢊPP
Z
VFDOH
'LPHQVLRQV
ꢏꢀꢐ
8QLW
$
$
$
E
'
(
H
H
ꢀ
H
ꢁ
/
/
ꢀ
Y
\
\
ꢀ
ꢀ
ꢂ
PD[ꢊ ꢈꢎꢄ ꢈꢎꢈꢄꢊ
ꢈꢎꢁꢄꢊ ꢀꢎꢄꢊ ꢀꢎꢉꢊ
ꢈꢎꢀꢁꢇ ꢈꢎꢁꢈꢊ ꢀꢎꢃꢊ ꢀꢎꢆꢊ ꢈꢎꢃ
ꢈꢎꢀꢄ ꢀꢎꢂ ꢀꢎꢇ
ꢈꢎꢃꢄꢊ ꢈꢎꢄꢄꢊ
ꢈꢎꢃ ꢈꢎꢃꢈꢊ ꢈꢎꢄꢈꢊ ꢈꢎꢀ ꢈꢎꢈꢄ ꢈꢎꢈꢄ ꢈꢎꢈꢄ
ꢈꢎꢂꢄ ꢈꢎꢃꢄ
PP QRPꢊ
PLQ
ꢊ
ꢈꢎꢆ
ꢈꢎꢈꢈ
1RWHꢊ
ꢀꢎꢊ3ODVWLFꢊRUꢊPHWDOꢊSURWUXVLRQVꢊRIꢊꢈꢎꢈꢇꢄꢊPPꢊPD[LPXPꢊSHUꢊVLGHꢊDUHꢊQRWꢊLQFOXGHGꢎ
VRWꢂꢂꢉꢁꢀꢂBSR
5HIHUHQFHV
2XWOLQHꢊ
YHUVLRQ
(XURSHDQꢊ
SURMHFWLRQ
,VVXHꢊGDWH
,(&
ꢍꢊꢍꢊꢍ
-('(&
ꢍꢊꢍꢊꢍ
-(,7$
ꢍꢊꢍꢊꢍ
ꢈꢉꢍꢀꢁꢍꢁꢆꢊ
ꢈꢉꢍꢀꢁꢍꢁꢉ
627ꢀꢀꢅꢈꢍꢀ
Fig 19. Package outline SOT1160-1 (XQFN10)
74AUP2G98
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 2 December 2015
16 of 21
74AUP2G98
Nexperia
Low-power dual PCB configurable multiple function gate
;621ꢆꢋꢌꢅSODVWLFꢅH[WUHPHO\ꢅWKLQꢅVPDOOꢅRXWOLQHꢅSDFNDJHꢍꢅQRꢅOHDGVꢍ
ꢆꢋꢅWHUPLQDOVꢍꢅERG\ꢅꢆꢇꢋꢅ[ꢅꢆꢇꢀꢅ[ꢅꢋꢇꢎꢅPP
627ꢆꢋꢄꢆꢏꢂ
;
'
%
$
(
$
$
ꢀ
F
WHUPLQDOꢊꢀ
LQGH[ꢊDUHD
GHWDLOꢊ;
H
ꢀ
&
Y
Z
&
&
$ %
H
E
WHUPLQDOꢊꢀ
LQGH[ꢊDUHD
\
\
&
ꢀ
ꢀ
ꢄ
/
ꢀ
N
/
ꢀꢈ
ꢄ
ꢈ
ꢀ
ꢁꢊPP
\
VFDOH
'LPHQVLRQV
ꢏꢀꢐ
8QLW
$
$
E
F
'
(
H
H
ꢀ
N
/
/
ꢀ
Y
Z
\
ꢀ
ꢀ
PD[ ꢈꢎꢄ ꢈꢎꢈꢄ ꢈꢎꢁꢈ
ꢀꢎꢆ ꢀꢎꢀ
ꢀꢎꢇ ꢀꢎꢈ
ꢀꢎꢅ ꢈꢎꢉ
ꢈꢎꢃꢈ ꢈꢎꢃꢄ
ꢈꢎꢂꢄ ꢈꢎꢃꢈ
ꢈꢎꢂꢈ ꢈꢎꢂꢄ
QRP
PLQ
ꢈꢎꢀꢄ
PP
ꢈꢎꢀꢁꢇ
ꢈꢎꢂꢄ ꢀꢎꢃ
ꢈꢎꢀ ꢈꢎꢈꢄ ꢈꢎꢈꢄ ꢈꢎꢈꢄ
ꢈꢎꢈꢈ ꢈꢎꢀꢈ
ꢈꢎꢁ
1RWH
ꢀꢎꢊ3ODVWLFꢊRUꢊPHWDOꢊSURWUXVLRQVꢊRIꢊꢈꢎꢈꢇꢄꢊPPꢊPD[LPXPꢊSHUꢊVLGHꢊDUHꢊQRWꢊLQFOXGHGꢎ
VRWꢂꢁꢅꢂꢀꢇBSR
5HIHUHQFHV
2XWOLQH
YHUVLRQ
(XURSHDQ
SURMHFWLRQ
,VVXHꢊGDWH
,(&
ꢍꢊꢍꢊꢍ
-('(&
ꢍꢊꢍꢊꢍ
-(,7$
ꢍꢊꢍꢊꢍ
ꢀꢈꢍꢀꢀꢍꢈꢆ
ꢀꢀꢍꢈꢂꢍꢂꢈ
627ꢀꢈꢆꢀꢍꢁ
Fig 20. Package outline SOT1081-2 (XSON10)
74AUP2G98
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 2 December 2015
17 of 21
74AUP2G98
Nexperia
Low-power dual PCB configurable multiple function gate
16. Abbreviations
Table 13. Abbreviations
Acronym
CDM
DUT
Description
Charged Device Model
Device Under Test
ElectroStatic Discharge
Human Body Model
Machine Model
ESD
HBM
MM
PCB
Printed-Circuit Board
17. Revision history
Table 14. Revision history
Document ID
74AUP2G98 v.2
Modifications:
Release date
Data sheet status
Change notice
Supersedes
20151202
Product data sheet
-
74AUP2G98 v.1
• Maximum value temperature range TSSOP10 (74AUP2G98DP) changed from 85 C to 125 C.
• Removed 74AUP2G98GM (SOT1049-3).
74AUP2G98 v.1
20141104
Product data sheet
-
-
74AUP2G98
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 2 December 2015
18 of 21
74AUP2G98
Nexperia
Low-power dual PCB configurable multiple function gate
18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nexperia.com.
Suitability for use — Nexperia products are not designed,
18.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of a Nexperia product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. Nexperia and its suppliers accept no liability for
inclusion and/or use of Nexperia products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the Nexperia
product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the Nexperia product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
Nexperia does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using Nexperia
products in order to avoid a default of the applications and
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no
responsibility for the content in this document if provided by an information
source outside of Nexperia.
the products or of the application or use by customer’s third party
customer(s). Nexperia does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall Nexperia be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — Nexperia
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nexperia.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. Nexperia hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of Nexperia products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
74AUP2G98
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 2 December 2015
19 of 21
74AUP2G98
Nexperia
Low-power dual PCB configurable multiple function gate
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Nexperia’s specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies Nexperia for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond Nexperia’s
standard warranty and Nexperia’s product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without Nexperia’s warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
19. Contact information
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
74AUP2G98
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 2 December 2015
20 of 21
74AUP2G98
Nexperia
Low-power dual PCB configurable multiple function gate
20. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
7.1
8
Functional description . . . . . . . . . . . . . . . . . . . 4
Logic configurations . . . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . 10
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Transfer characteristics . . . . . . . . . . . . . . . . . 13
Waveforms transfer characteristics. . . . . . . . 13
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 18
9
10
11
12
13
14
15
16
17
18
Legal information. . . . . . . . . . . . . . . . . . . . . . . 19
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
18.1
18.2
18.3
18.4
19
20
Contact information. . . . . . . . . . . . . . . . . . . . . 20
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
© Nexperia B.V. 2017. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 02 December 2015
相关型号:
©2020 ICPDF网 联系我们和版权申明