74HCT594D-Q100 [NEXPERIA]
8-bit shift register with output registerProduction;
| 型号： | 74HCT594D-Q100 |
| 厂家： | 
Nexperia |
| 描述： | 8-bit shift register with output registerProduction 逻辑集成电路 |
| 文件： | 总25页 (文件大小：873K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74HC594-Q100; 74HCT594-Q100
8-bit shift register with output register
Rev. 2 — 13 June 2016
Product data sheet
1. General description
The 74HC594-Q100; 74HCT594-Q100 is a high-speed Si-gate CMOS device and is pin
compatible with Low-Power Schottky TTL (LSTTL).
The 74HC594-Q100; 74HCT594-Q100 is an 8-bit, non-inverting, serial-in, parallel-out shift
register that feeds an 8-bit D-type storage register. Separate clocks (SHCP and STCP)
and direct overriding clears (SHR and STR) are provided on both the shift and storage
registers. A serial output (Q7S) is provided for cascading purposes.
Both the shift and storage register clocks are positive-edge triggered. If both clocks are
connected together, the shift register is always one count pulse ahead of the storage
register.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Synchronous serial input and output
Complies with JEDEC standard No.7A
8-bit parallel output
Shift and storage registers have independent direct clear and clocks
Independent clocks for shift and storage registers
100 MHz (typical)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
3. Applications
Serial-to parallel data conversion
Remote control holding register
74HC594-Q100; 74HCT594-Q100
Nexperia
8-bit shift register with output register
4. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74HC594D-Q100
74HCT594D-Q100
40 C to +125 C
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74HC594PW-Q100 40 C to +125 C
TSSOP16
plastic thin shrink small outline package;
16 leads; body width 4.4 mm
SOT403-1
5. Functional diagram
ꢂꢅ
ꢂꢂ
ꢂꢁ
'6
6+&3
6+5
ꢉꢊ67$*(ꢋ6+,)7ꢋ5(*,67(5
ꢈ
4ꢀ6
ꢂꢃ
ꢂꢄ
67&3
675
ꢉꢊ%,7ꢋ6725$*(ꢋ5(*,67(5
ꢂꢆ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢀ
4ꢁ 4ꢂ 4ꢃ 4ꢄ 4ꢅ 4ꢆ 4ꢇ 4ꢀ
PEFꢀꢁꢂ
Fig 1. Functional diagram
6+&3 67&3
ꢂꢄ
ꢂꢃ
ꢂꢁ
ꢂꢂ
675
5ꢃ
&ꢃ
ꢂꢂ
ꢂꢃ
67&3
6+5
4ꢀ6
ꢈ
ꢂꢆ
ꢂ
5ꢂ 65*ꢉ
&ꢂꢌ
4ꢁ
4ꢂ
4ꢃ
4ꢄ
4ꢅ
4ꢆ
4ꢇ
4ꢀ
6+&3
ꢂꢅ
ꢂꢆ
ꢂ
'6
4ꢁ
4ꢂ
4ꢃ
4ꢄ
4ꢅ
4ꢆ
4ꢇ
4ꢀ
ꢂ'
ꢃ'
ꢃ
'6
ꢂꢅ
ꢄ
ꢃ
ꢄ
ꢅ
ꢅ
ꢆ
ꢆ
ꢇ
ꢇ
ꢀ
ꢀ
ꢂꢁ
ꢂꢄ
ꢈ
4ꢀ6
6+5 675
PEFꢀꢃꢄ
PEFꢀꢁꢁ
Fig 2. Logic symbol
Fig 3. IEC logic symbol
74HC_HCT594_Q100
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©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 13 June 2016
2 of 25
74HC594-Q100; 74HCT594-Q100
Nexperia
8-bit shift register with output register
67$*(ꢋꢁ
67$*(6ꢋꢂꢋ72ꢋꢇ
67$*(ꢋꢀ
'6
4ꢀ6
'
4
))6+ꢁ
&3
'
4
'
4
))6+ꢀ
&3
5
5
6+&3
6+5
'
))67ꢁ
&3
'
))67ꢀ
&3
4
4
5
5
67&3
675
PEFꢀꢁꢃ
4ꢁ
4ꢂ 4ꢃ 4ꢄ 4ꢅ 4ꢆ 4ꢇ
4ꢀ
Fig 4. Logic diagram
6+&3
'6
67&3
6+5
675
4ꢁ
4ꢂ
4ꢇ
4ꢀ
4ꢀ6
PEFꢀꢁꢀ
Fig 5. Timing diagram
74HC_HCT594_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 13 June 2016
3 of 25
74HC594-Q100; 74HCT594-Q100
Nexperia
8-bit shift register with output register
6. Pinning information
6.1 Pinning
ꢀꢁ+&ꢂꢃꢁꢄ4ꢅꢆꢆ
ꢀꢁ+&7ꢂꢃꢁꢄ4ꢅꢆꢆ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢀ
ꢉ
ꢂꢇ
ꢂꢆ
ꢂꢅ
ꢂꢄ
ꢂꢃ
ꢂꢂ
ꢂꢁ
ꢈ
4ꢂ
4ꢃ
9
&&
4ꢁ
ꢀꢁ+&ꢂꢃꢁꢄ4ꢅꢆꢆ
4ꢄ
'6
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢀ
ꢉ
ꢂꢇ
ꢂꢆ
ꢂꢅ
ꢂꢄ
ꢂꢃ
ꢂꢂ
ꢂꢁ
ꢈ
4ꢂ
4ꢃ
9
&&
4ꢁ
4ꢅ
675
67&3
6+&3
6+5
4ꢀ6
4ꢄ
'6
4ꢆ
4ꢅ
675
67&3
6+&3
6+5
4ꢀ6
4ꢇ
4ꢆ
4ꢇ
4ꢀ
4ꢀ
*1'
*1'
DDDꢅꢂꢂꢀꢆꢇꢈ
DDDꢅꢂꢁꢀꢀꢉꢈ
Fig 6. Pin configuration SO16
Fig 7. Pin configuration TSSOP16
6.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
15, 1, 2, 3, 4, 5, 6, 7
parallel data output
ground (0 V)
GND
Q7S
SHR
SHCP
STCP
STR
DS
8
9
serial data output
10
11
12
13
14
16
shift register reset (active LOW)
shift register clock input
storage register clock input
storage register reset (active LOW)
serial data input
VCC
supply voltage
74HC_HCT594_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 13 June 2016
4 of 25
74HC594-Q100; 74HCT594-Q100
Nexperia
8-bit shift register with output register
7. Functional description
Table 3.
Function table[1]
Function
Input
SHR STR SHCP STCP DS
Clear shift register
L
X
L
X
X
X
X
X
X
X
Clear storage register
X
H
X
H
X
Load DS into shift register stage 0, advance previous stage data to the next stage
Transfer shift register data to storage register and outputs Qn
Shift register one count pulse ahead of storage register
X
H
H
H or L
X
X
[1] H = HIGH voltage level; L = LOW voltage level; = LOW-to-HIGH transition; X = don’t care.
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7.0
20
20
Unit
V
supply voltage
0.5
[1]
[1]
input clamping current
output clamping current
output current
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
VO = 0.5 V to VCC + 0.5 V
Serial data output Q7S
Parallel data output
-
-
mA
mA
IOK
IO
-
25
35
50
mA
mA
mA
mA
mA
mA
C
-
ICC
supply current
ground current
Serial data output Q7S
Parallel data output
-
-
70
IGND
Serial data output Q7S
Parallel data output
-
50
70
+150
500
-
65
-
Tstg
Ptot
storage temperature
total power dissipation
[2]
Tamb = 40 C to +125 C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO16 package: above 70 C the value of Ptot derates linearly with 8 mW/K.
For TSSOP16 package: Ptot derates linearly with 5.5 mW/K above 60 C.
74HC_HCT594_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 13 June 2016
5 of 25
74HC594-Q100; 74HCT594-Q100
Nexperia
8-bit shift register with output register
9. Recommended operating conditions
Table 5.
Symbol
Recommended operating conditions
Parameter Conditions
Min
Typ
Max Unit
Type 74HC594-Q100
VCC
VI
supply voltage
2.0
5.0
6.0
VCC
VCC
V
V
V
input voltage
0
-
VO
Tamb
tr
output voltage
ambient temperature
rise time
0
-
+25
-
40
+125 C
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
-
-
-
1000 ns
6.0
-
500
400
ns
ns
tf
fall time
-
1000 ns
6.0
-
500
400
ns
ns
Type 74HCT594-Q100
VCC
VI
supply voltage
4.5
5.0
-
5.5
VCC
VCC
V
V
V
input voltage
output voltage
ambient temperature
rise time
0
0
VO
Tamb
tr
-
40
-
+25
6.0
6.0
+125 C
VCC = 4.5 V
VCC = 4.5 V
500
500
ns
ns
tf
fall time
-
10. Static characteristics
Table 6.
Static characteristics type 74HC594-Q100
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Tamb = 25 C
VIH
Parameter
Conditions
Min
Typ
Max
Unit
HIGH-level input voltage
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
1.5
1.2
2.4
3.2
0.8
2.1
2.8
-
-
V
V
V
V
V
V
3.15
4.2
-
VIL
LOW-level input voltage
-
-
-
0.5
1.35
1.8
VOH
HIGH-level output voltage VI = VIH or VIL
Serial data output Q7S
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
Parallel data outputs
3.98
5.48
4.32
5.81
-
-
V
V
IO = 6.0 mA; VCC = 4.5 V
IO = 7.8 mA; VCC = 6.0 V
3.98
5.48
4.32
5.81
-
-
V
V
74HC_HCT594_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 13 June 2016
6 of 25
74HC594-Q100; 74HCT594-Q100
Nexperia
8-bit shift register with output register
Table 6.
Static characteristics type 74HC594-Q100 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOL
LOW-level output voltage
VI = VIH or VIL
Serial data output Q7S
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
Parallel data outputs
IO = 6.0 mA; VCC = 4.5 V
IO = 7.8 mA; VCC = 6.0 V
VI = VCC or GND; VCC = 6.0 V
-
-
0.15
0.16
0.26
0.26
V
V
-
-
-
-
0.15
0.26
0.26
0.1
8.0
V
0.16
V
II
input leakage current
supply current
-
-
A
A
ICC
VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
Ci
input capacitance
-
3.5
-
pF
Tamb = 40 C to +85 C
VIH HIGH-level input voltage
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
1.5
-
-
-
-
-
-
-
-
V
V
V
V
V
V
3.15
4.2
-
VIL
LOW-level input voltage
-
-
-
0.5
1.35
1.8
VOH
HIGH-level output voltage VI = VIH or VIL
Serial data output Q7S
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
Parallel data outputs
3.84
5.34
-
-
-
-
V
V
IO = 6.0 mA; VCC = 4.5 V
IO = 7.8 mA; VCC = 6.0 V
VI = VIH or VIL
3.84
5.34
-
-
-
-
V
V
VOL
LOW-level output voltage
Serial data output Q7S
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
Parallel data outputs
-
-
-
-
0.33
0.33
V
V
IO = 6.0 mA; VCC = 4.5 V
IO = 7.8 mA; VCC = 6.0 V
VI = VCC or GND; VCC = 6.0 V
-
-
-
-
-
-
-
-
0.33
0.33
1.0
80
V
V
II
input leakage current
supply current
A
A
ICC
VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
74HC_HCT594_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 13 June 2016
7 of 25
74HC594-Q100; 74HCT594-Q100
Nexperia
8-bit shift register with output register
Table 6.
Static characteristics type 74HC594-Q100 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Tamb = 40 C to +125 C
VIH HIGH-level input voltage
Parameter
Conditions
Min
Typ
Max
Unit
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
1.5
-
-
-
-
-
-
-
-
V
V
V
V
V
V
3.15
4.2
-
VIL
LOW-level input voltage
-
-
-
0.5
1.35
1.8
VOH
HIGH-level output voltage VI = VIH or VIL
Serial data output Q7S
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
Parallel data outputs
3.7
5.2
-
-
-
-
V
V
IO = 6.0 mA; VCC = 4.5 V
IO = 7.8 mA; VCC = 6.0 V
VI = VIH or VIL
3.7
5.2
-
-
-
-
V
V
VOL
LOW-level output voltage
Serial data output Q7S
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
Parallel data outputs
-
-
-
-
0.4
0.4
V
V
IO = 6.0 mA; VCC = 4.5 V
IO = 7.8 mA; VCC = 6.0 V
VI = VCC or GND; VCC = 6.0 V
-
-
-
-
-
-
-
-
0.4
0.4
V
V
II
input leakage current
supply current
1.0
160
A
A
ICC
VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
74HC_HCT594_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 13 June 2016
8 of 25
74HC594-Q100; 74HCT594-Q100
Nexperia
8-bit shift register with output register
Table 7.
Static characteristics type 74HCT594-Q100
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Tamb = 25 C
VIH
Parameter
Conditions
Min
Typ
Max
Unit
HIGH-level input voltage
LOW-level input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
1.6
1.2
-
V
V
VIL
0.8
VOH
HIGH-level output voltage VI = VIH or VIL
Serial data output Q7S
IO = 4.0 mA; VCC = 4.5 V
Parallel data outputs
IO = 6.0 mA; VCC = 4.5 V
VI = VIH or VIL
3.98
3.98
4.32
4.32
-
-
V
V
VOL
LOW-level output voltage
Serial data output Q7S
IO = 4.0 mA; VCC = 4.5 V
Parallel data outputs
IO = 6.0 mA; VCC = 4.5 V
VI = VCC or GND; VCC = 5.5 V
-
0.15
0.26
V
-
-
-
0.16
0.26
0.1
8.0
V
II
input leakage current
supply current
-
-
A
A
ICC
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
ICC
additional supply current
per input pin; VI = VCC 2.1 V and
other inputs at VCC or GND;
IO = 0 A; VCC = 4.5 V to 5.5 V
pins SHR, SHCP, STCP, STR
pin DS
-
-
-
150
25
540
90
-
A
A
pF
Ci
input capacitance
3.5
Tamb = 40 C to +85 C
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
-
-
-
V
V
0.8
VOH
HIGH-level output voltage VI = VIH or VIL
Serial data output Q7S
IO = 4.0 mA; VCC = 4.5 V
Parallel data outputs
IO = 6.0 mA; VCC = 4.5 V
VI = VIH or VIL
3.84
3.84
-
-
-
-
V
V
VOL
LOW-level output voltage
Serial data output
IO = 4.0 mA; VCC = 4.5 V
Parallel data outputs
IO = 6.0 mA; VCC = 4.5 V
VI = VCC or GND; VCC = 5.5 V
-
-
0.33
V
-
-
-
-
-
-
0.33
1.0
80
V
II
input leakage current
supply current
A
A
ICC
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
74HC_HCT594_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 13 June 2016
9 of 25
74HC594-Q100; 74HCT594-Q100
Nexperia
8-bit shift register with output register
Table 7.
Static characteristics type 74HCT594-Q100 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ICC
additional supply current
per input pin; VI = VCC 2.1 V and
other inputs at VCC or GND;
IO = 0 A; VCC = 4.5 V to 5.5 V
pins SHR, SHCP, STCP, STR
pin DS
-
-
-
-
675
A
112.5 A
Tamb = 40 C to +125 C
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
-
-
-
V
V
0.8
VOH
HIGH-level output voltage VI = VIH or VIL
Serial data output Q7S
IO = 4.0 mA; VCC = 4.5 V
Parallel data outputs
IO = 6.0 mA; VCC = 4.5 V
VI = VIH or VIL
3.7
3.7
-
-
-
-
V
V
VOL
LOW-level output voltage
Serial data output Q7S
IO = 4.0 mA; VCC = 4.5 V
Parallel data outputs
IO = 6.0 mA; VCC = 4.5 V
VI = VCC or GND; VCC = 5.5 V
-
-
0.4
V
-
-
-
-
-
-
0.4
1.0
160
V
II
input leakage current
supply current
A
A
ICC
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
ICC
additional supply current
per input pin; VI = VCC 2.1 V and
other inputs at VCC or GND;
IO = 0 A; VCC = 4.5 V to 5.5 V
pins SHR, SHCP, STCP, STR
pin DS
-
-
-
-
735
A
122.5 A
74HC_HCT594_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 13 June 2016
10 of 25
74HC594-Q100; 74HCT594-Q100
Nexperia
8-bit shift register with output register
11. Dynamic characteristics
Table 8.
Dynamic characteristics type 74HC594-Q100
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 14.
Symbol Parameter Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
[1]
tpd
propagation d SHCP to Q7S;
elay
see Figure 8
VCC = 2.0 V
VCC = 4.5 V
-
-
-
44
16
13
150
30
-
-
-
-
185
37
-
-
-
-
225
45
-
ns
ns
ns
VCC = 5.0 V;
CL = 15 pF
VCC = 6.0 V
-
14
26
-
31
-
38
ns
STCP to Qn;
see Figure 9
VCC = 2.0 V
VCC = 4.5 V
-
-
-
44
16
13
150
30
-
-
-
-
185
37
-
-
-
-
225
45
-
ns
ns
ns
VCC = 5.0 V;
CL = 15 pF
VCC = 6.0 V
-
14
26
-
31
-
38
ns
tPHL
HIGH to LOW SHR to Q7S;
propagation
delay
see Figure 12
VCC = 2.0 V
VCC = 4.5 V
-
-
-
39
14
11
150
30
-
-
-
-
185
37
-
-
-
-
225
45
-
ns
ns
ns
VCC = 5.0 V;
CL = 15 pF
VCC = 6.0 V
-
12
26
-
31
-
38
ns
STR to Qn;
see Figure 13
VCC = 2.0 V
VCC = 4.5 V
-
-
-
39
14
11
125
25
-
-
-
-
155
31
-
-
-
-
185
37
-
ns
ns
ns
VCC = 5.0 V;
CL = 15 pF
VCC = 6.0 V
-
12
21
-
26
-
31
ns
tTHL
HIGH to LOW see Figure 8
output
Serial data output Q7S
transition
time
VCC = 2.0 V
VCC = 4.5 V
-
-
-
19
7
75
15
13
-
-
-
95
19
16
-
-
-
110
22
ns
ns
ns
VCC = 6.0 V
6
19
Parallel data outputs
VCC = 2.0 V
-
-
-
14
5
60
12
10
-
-
-
75
15
13
-
-
-
90
18
15
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
4
74HC_HCT594_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 13 June 2016
11 of 25
74HC594-Q100; 74HCT594-Q100
Nexperia
8-bit shift register with output register
Table 8.
Dynamic characteristics type 74HC594-Q100 …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 14.
Symbol Parameter Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
tTLH
LOW to HIGH see Figure 8
output
Serial data output Q7S
transition
time
VCC = 2.0 V
VCC = 4.5 V
-
-
-
19
7
75
15
13
-
-
-
95
19
16
-
-
-
110
22
ns
ns
ns
VCC = 6.0 V
6
19
Parallel data outputs
VCC = 2.0 V
-
-
-
14
5
60
12
10
-
-
-
75
15
13
-
-
-
90
18
15
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
4
tW
pulse width
SHCP (HIGH or
LOW); see Figure 8
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
80
16
14
10
4
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
3
17
20
STCP (HIGH or
LOW); see Figure 9
VCC = 2.0 V
80
16
14
10
4
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
V
CC = 4.5 V
VCC = 6.0 V
3
17
20
SHR and STR (HIGH
or LOW);
see Figure 12 and
Figure 13
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
80
16
14
14
5
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
4
17
20
tsu
set-up time
DS to SHCP;
see Figure 10
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
100
20
10
4
-
-
-
125
25
-
-
-
150
30
-
-
-
ns
ns
ns
17
3
21
26
SHR to STCP;
see Figure 11
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
100
20
14
5
-
-
-
125
25
-
-
-
150
30
-
-
-
ns
ns
ns
17
4
21
26
SHCP to STCP;
see Figure 9
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
100
20
17
6
-
-
-
125
25
-
-
-
150
30
-
-
-
ns
ns
ns
17
5
21
26
74HC_HCT594_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 13 June 2016
12 of 25
74HC594-Q100; 74HCT594-Q100
Nexperia
8-bit shift register with output register
Table 8.
Dynamic characteristics type 74HC594-Q100 …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 14.
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
th
hold time
DS to SHCP;
see Figure 10
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
25
5
8
3
2
-
-
-
30
6
-
-
-
35
7
-
-
-
ns
ns
ns
4
5
6
trec
recovery time SHR to SHCP and
STR to STCP;
see Figure 12 and
Figure 13
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
50
10
9
14
5
-
-
-
65
13
11
-
-
-
75
15
13
-
-
-
ns
ns
ns
4
fmax
maximum
frequency
SHCP or STCP;
see Figure 8 and
Figure 9
VCC = 2.0 V
VCC = 4.5 V
6.0
30
-
30
92
-
-
-
4.8
24
-
-
-
-
4.0
20
-
-
-
-
MHz
MHz
MHz
VCC = 5.0 V;
CL = 15 pF
100
VCC = 6.0 V
35
-
109
84
-
-
28
-
-
-
24
-
-
-
MHz
pF
[2]
CPD
power
VI = GND to VCC;
dissipation
capacitance
VCC = 5 V; fi = 1 MHz
[1] tpd is the same as tPHL and tPLH
.
[2] CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
74HC_HCT594_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 13 June 2016
13 of 25
74HC594-Q100; 74HCT594-Q100
Nexperia
8-bit shift register with output register
Table 9.
Dynamic characteristics type 74HCT594-Q100
GND = 0 V; VCC = 4.5 V; tr = tf = 6 ns; CL = 50 pF; see Figure 14.
Symbol Parameter
Conditions
25 C
Typ
18
40 C to +85 C 40 C to +125 C Unit
Min
Max
Min
Max
Min
Max
[1]
tpd
propagation
delay
SHCP to Q7S;
see Figure 8
-
32
-
40
-
48
ns
ns
ns
ns
ns
ns
ns
ns
VCC = 5.0 V;
CL = 15 pF
-
-
-
-
-
-
-
15
18
15
17
14
17
14
-
32
-
-
-
-
-
-
-
-
-
40
-
-
-
-
-
-
-
-
-
48
-
STCP to Qn;
see Figure 9
VCC = 5.0 V;
CL = 15 pF
tPHL
HIGH to LOW SHR to Q7S;
30
-
38
-
45
-
propagation
delay
see Figure 12
V
CC = 5.0 V;
CL = 15 pF
STR to Qn;
see Figure 13
30
-
38
-
45
-
VCC = 5.0 V;
CL = 15 pF
tTHL
tTLH
tW
HIGH to LOW see Figure 8
output
Serial data output Q7S
transition time
VCC = 4.5 V
-
-
7
5
15
12
-
-
19
15
-
-
22
18
ns
ns
Parallel data outputs
VCC = 4.5 V
LOW to HIGH see Figure 8
output
Serial data output Q7S
transition time
VCC = 4.5 V
-
7
15
-
19
-
22
ns
Parallel data outputs
VCC = 4.5 V
-
5
4
12
-
-
15
-
-
18
-
ns
ns
pulse width
SHCP (HIGH or LOW);
see Figure 8
16
20
24
STCP (HIGH or LOW);
see Figure 9
16
16
4
6
-
-
20
20
-
-
24
24
-
-
ns
ns
SHR and STR (HIGH or
LOW); see Figure 12
and Figure 13
tsu
set-up time
DS to SHCP;
see Figure 10
20
20
20
5
4
6
-
-
-
-
25
25
25
6
-
-
-
-
30
30
30
7
-
-
-
-
ns
ns
ns
ns
SHR to STCP;
see Figure 11
SHCP to STCP;
see Figure 9
7
th
hold time
DS to SHCP;
see Figure 10
3
74HC_HCT594_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 13 June 2016
14 of 25
74HC594-Q100; 74HCT594-Q100
Nexperia
8-bit shift register with output register
Table 9.
Dynamic characteristics type 74HCT594-Q100 …continued
GND = 0 V; VCC = 4.5 V; tr = tf = 6 ns; CL = 50 pF; see Figure 14.
Symbol Parameter
Conditions
25 C
Typ
5
40 C to +85 C 40 C to +125 C Unit
Min
Max
Min
Max
Min
Max
trec
recovery time SHR to SHCP and
STR to STCP;
10
-
13
-
15
-
ns
see Figure 12 and
Figure 13
fmax
maximum
frequency
SHCP or STCP;
see Figure 8 and
Figure 9
30
92
-
24
-
20
-
MHz
VCC = 5.0 V;
CL = 15 pF
-
-
100
89
-
-
-
-
-
-
-
-
-
-
MHz
pF
[2]
CPD
power
VI = GND to VCC
1.5 V; VCC = 5 V;
fi = 1 MHz
dissipation
capacitance
[1] tpd is the same as tPHL and tPLH
.
[2] PD is used to determine the dynamic power dissipation (PD in W):
C
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
12. Waveforms
ꢂꢌI
PD[
6+&3ꢋLQSXW
4ꢀ6ꢋRXWSXW
9
0
W
:
W
W
3+/
3/+
9
0
W
W
7/+
7+/
ꢂꢂꢃDDHꢀꢆꢃ
Measurement points are given in Table 10.
tPLH and tPHL are the same as tpd
TLH = LOW to HIGH output transition time; tTHL = HIGH to LOW output transition time.
.
t
Fig 8. The shift clock (SHCP) to output (Q7S) propagation delays, the shift clock pulse width, the maximum shift
clock frequency, and output transition times
74HC_HCT594_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 13 June 2016
15 of 25
74HC594-Q100; 74HCT594-Q100
Nexperia
8-bit shift register with output register
9
6+&3ꢋLQSXW
0
W
VX
ꢂꢌI
PD[
9
W
0
67&3ꢋLQSXW
4QꢋRXWSXWV
W
:
W
3+/
3/+
9
0
PODꢈꢃꢁ
Measurement points are given in Table 10.
tPLH and tPHL are the same as tpd
.
Fig 9. The storage clock (STCP) to output (Qn), propagation delays, the storage clock pulse width, the
maximum storage clock pulse frequency and the shift clock to storage clock set-up time
9
6+&3ꢋLQSXW
'6ꢋLQSXW
0
W
W
VX
VX
W
W
K
K
9
0
9
4ꢀꢋRXWSXW
0
ꢂꢂꢃDDHꢀꢆꢁ
Measurement points are given in Table 10.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 10. The data set-up time and hold times for DS input to SHCP
74HC_HCT594_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 13 June 2016
16 of 25
74HC594-Q100; 74HCT594-Q100
Nexperia
8-bit shift register with output register
9
0
6+5ꢋLQSXW
67&3ꢋLQSXW
4QꢋRXWSXWV
W
VX
9
0
9
0
PEFꢀꢁꢉ
Measurement points are given in Table 10.
Fig 11. The set-up time shift reset (SHR) to storage clock (STCP)
9
0
6+5ꢋLQSXW
W
:
W
UHF
9
0
6+&3ꢋLQSXW
W
3+/
9
4ꢀ6ꢋRXWSXW
0
PEFꢀꢁꢆ
Measurement points are given in Table 10.
tPLH and tPHL are the same as tpd.
Fig 12. The shift reset (SHR) pulse width, the shift reset to output (Q7S) propagation delay and the shift reset to
shift clock (SHCP) recovery time
74HC_HCT594_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 13 June 2016
17 of 25
74HC594-Q100; 74HCT594-Q100
Nexperia
8-bit shift register with output register
9
0
675ꢋLQSXW
67&3ꢋLQSXW
4QꢋRXWSXWV
W
:
W
UHF
9
0
W
3+/
9
0
PEFꢀꢁꢈ
Measurement points are given in Table 10.
tPLH and tPHL are the same as tpd
.
Fig 13. The storage reset (STR) pulse width, the storage reset to output (Qn) propagation delay and the storage
reset to storage clock (STCP) recovery time
Table 10. Measurement points
Type
Input
VM
Output
VM
74HC594-Q100
74HCT594-Q100
0.5 VCC
1.3 V
0.5 VCC
1.3 V
74HC_HCT594_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 13 June 2016
18 of 25
74HC594-Q100; 74HCT594-Q100
Nexperia
8-bit shift register with output register
W
:
9
,
ꢈꢁꢋꢍ
QHJDWLYHꢋ
SXOVH
9
9
9
0
0
0
ꢂꢁꢋꢍ
ꢁꢋ9
W
W
U
I
W
W
U
I
9
,
ꢈꢁꢋꢍ
SRVLWLYHꢋ
SXOVH
9
0
ꢂꢁꢋꢍ
ꢁꢋ9
W
:
9
9
&&
&&
9
,
9
2
ꢋ
5
/
6ꢂ
*
RSHQ
'87
5
7
&
/
ꢂꢂꢃDDGꢄꢊꢀ
Test data is given in Table 11.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator
CL = Load capacitance including jig and probe capacitance
RL = Load resistor
S1 = Test selection switch
Fig 14. Test circuit for measuring switching times
Table 11. Test data
Type
Input
VI
Load
S1 position
tPHL, tPLH
open
tr, tf
6 ns
6 ns
CL
RL
tPZH, tPHZ
GND
tPZL, tPLZ
VCC
74HC594-Q100
VCC
15 pF, 50 pF
15 pF, 50 pF
1 k
1 k
74HCT594-Q100 3 V
open
GND
VCC
74HC_HCT594_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 13 June 2016
19 of 25
74HC594-Q100; 74HCT594-Q100
Nexperia
8-bit shift register with output register
13. Package outline
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Fig 15. Package outline SOT109-1 (SO16)
74HC_HCT594_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 13 June 2016
20 of 25
74HC594-Q100; 74HCT594-Q100
Nexperia
8-bit shift register with output register
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Fig 16. Package outline SOT403-1 (TSSOP16)
74HC_HCT594_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 13 June 2016
21 of 25
74HC594-Q100; 74HCT594-Q100
Nexperia
8-bit shift register with output register
14. Abbreviations
Table 12. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
LSTTL
MM
Low-Power Schottky Transistor-Transistor Logic
Machine Model
TTL
Transistor-Transistor Logic
15. Revision history
Table 13. Revision history
Document ID
Release date
20160613
Data sheet status
Change notice
Supersedes
74HC_HCT594_Q100 v.2
Modifications:
Product data sheet
-
74HC_HCT594_Q100 v.1
• Added type number 74HC594PW-Q100 (SOT403-1).
20120802 Product data sheet
74HC_HCT594_Q100 v.1
-
-
74HC_HCT594_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 13 June 2016
22 of 25
74HC594-Q100; 74HCT594-Q100
Nexperia
8-bit shift register with output register
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nexperia.com.
Suitability for use in automotive applications — This Nexperia
product has been qualified for use in automotive
16.2 Definitions
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of a Nexperia product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. Nexperia and its suppliers accept no liability for
inclusion and/or use of Nexperia products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the Nexperia product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the Nexperia
product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Nexperia does not accept any liability related to any default,
16.3 Disclaimers
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using Nexperia
products in order to avoid a default of the applications and
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no
responsibility for the content in this document if provided by an information
source outside of Nexperia.
the products or of the application or use by customer’s third party
customer(s). Nexperia does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall Nexperia be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of Nexperia.
Terms and conditions of commercial sale — Nexperia
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nexperia.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. Nexperia hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of Nexperia products by customer.
Right to make changes — Nexperia reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74HC_HCT594_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 13 June 2016
23 of 25
74HC594-Q100; 74HCT594-Q100
Nexperia
8-bit shift register with output register
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
74HC_HCT594_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 13 June 2016
24 of 25
74HC594-Q100; 74HCT594-Q100
Nexperia
8-bit shift register with output register
18. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . 11
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 20
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 22
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 22
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 23
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 24
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 24
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
© Nexperia B.V. 2017. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 13 June 2016
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