74LV03D [NEXPERIA]
Quad 2-input NAND gateProduction;型号: | 74LV03D |
厂家: | Nexperia |
描述: | Quad 2-input NAND gateProduction 光电二极管 逻辑集成电路 |
文件: | 总12页 (文件大小:169K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74LV03
Quad 2-input NAND gate
Rev. 4 — 31 August 2017
Product data sheet
1 General description
The 74LV03 is a low-voltage Si-gate CMOS device and is pin and function compatible
with 74HC/HCT03.
The 74LV03 provides the 2-input NAND function.
The 74LV03 has open-drain N-transistor outputs, which are not clamped by a diode
connected to VCC. In the OFF-state, i.e., when one input is LOW, the output may be
pulled to any voltage between GND and VO(max). This allows the device to be used as
a LOW-to-HIGH or HIGH-to-LOW level shifter. For digital operation and OR-tied output
applications, these devices must have a pull-up resistor to establish a logic HIGH level.
2 Features and benefits
• Wide operating voltage: 1.0 V to 5.5 V
• Optimized for low voltage applications: 1.0 V to 3.6 V
• Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
• Typical VOLP (output ground bounce) < 0.8 V @ VCC = 3.3 V, Tamb = 25 °C
• Typical VOHV (output VOH undershoot) > 2 V @ VCC = 3.3 V, Tamb = 25 °C
• Level shifter capability
• ESD protection:
– HBM JESD22-A114F exceeds 2000 V
– MM JESD22-A115-A exceeds 200 V
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C
3 Ordering information
Table 1.ꢀOrdering information
Type number Package
Temperature range Name
Description
Version
74LV03D
-40 °C to + 125 °C
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
Nexperia
74LV03
Quad 2-input NAND gate
4 Functional diagram
1
2
3
&
&
&
&
1
2
1A
1B
1Y
2Y
3Y
3
6
8
4
5
4
5
2A
2B
6
Y
9
9
3A
8
10
10 3B
A
B
12 4A
13 4B
12
13
4Y 11
11
GND
mna212
aaa-008083
001aab715
Figure 1.ꢀLogic symbol
Figure 2.ꢀIEC logic symbol
Figure 3.ꢀLogic diagram (one gate)
5 Pinning information
5.1 Pinning
74LV03
1
2
3
4
5
6
7
14
13
12
11
10
9
1A
1B
V
CC
4B
4A
4Y
3B
3A
3Y
1Y
2A
2B
2Y
8
GND
aaa-027324
Figure 4.ꢀPin configuration SO14
5.2 Pin description
Table 2.ꢀPin description
Symbol
Pin
Description
data input
1A, 2A, 3A, 4A
1B, 2B, 3B, 4B
1Y, 2Y, 3Y, 4Y
GND
1, 4, 9, 12
2, 5, 10, 13
data input
3, 6, 8, 11
data output
ground (0 V)
supply voltage
7
VCC
14
74LV03
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© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 4 — 31 August 2017
2 / 12
Nexperia
74LV03
Quad 2-input NAND gate
6 Functional description
Table 3.ꢀFunction table [1]
Input
Output
nA
L
nB
nY
Z
L
L
H
L
Z
H
Z
H
H
L
[1] H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF-state.
7 Limiting values
Table 4.ꢀLimiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max
+7.0
±20
±50
±25
50
Unit
V
VCC
IIK
supply voltage
-0.5
[1]
[1]
input clamping current
output clamping current
output current
VI < -0.5 V or VI > VCC + 0.5 V
VO < -0.5 V or VO > VCC + 0.5 V
VO = -0.5 V to (VCC + 0.5 V)
-
mA
mA
mA
mA
mA
°C
IOK
IO
-
-
ICC
IGND
Tstg
Ptot
supply current
-
ground current
-50
-65
-
-
storage temperature
total power dissipation
+150
500
[2]
Tamb = -40 °C to +125 °C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Ptot derates linearly with 8 mW/K above 70 °C.
74LV03
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© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 4 — 31 August 2017
3 / 12
Nexperia
74LV03
Quad 2-input NAND gate
8 Recommended operating conditions
Table 5.ꢀRecommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
5.5
Unit
V
[1]
VCC
VI
supply voltage
1.0
3.3
input voltage
0
-
VCC
VCC
+125
500
200
100
50
V
VO
output voltage
0
-
V
Tamb
Δt/ΔV
ambient temperature
input transition rise and fall rate
-40
+25
°C
VCC = 1.0 V to 2.0 V
VCC = 2.0 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 3.6 V to 5.5 V
-
-
-
-
-
-
-
-
ns/V
ns/V
ns/V
ns/V
[1] The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V, but LV devices are guaranteed to function down to VCC = 1.0 V (with input
levels GND or VCC).
9 Static characteristics
Table 6.ꢀStatic characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
-40 °C to +85 °C
Min
Typ [1] Max
-40 °C to +125 °C Unit
Min
Max
VIH
HIGH-level
input voltage
VCC = 1.2 V
0.9
-
-
-
-
-
-
-
-
-
0.9
-
V
V
V
V
V
V
V
V
VCC = 2.0 V
1.4
-
-
1.4
-
-
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 1.2 V
2.0
2.0
0.7VCC
-
0.7VCC
-
VIL
LOW-level
input voltage
-
-
-
-
0.3
0.6
0.8
0.3VCC
-
-
-
-
0.3
0.6
0.8
0.3VCC
VCC = 2.0 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VI = VIH or VIL
VOL
LOW-level
output voltage
IO = 100 μA; VCC = 1.2 V
IO = 100 μA; VCC = 2.0 V
IO = 100 μA; VCC = 2.7 V
IO = 100 μA; VCC = 3.0 V
IO = 100 μA; VCC = 4.5 V
IO = 6 mA; VCC = 3.0 V
IO = 12 mA; VCC = 4.5 V
-
-
-
-
-
-
-
-
0
0
-
-
-
-
-
-
-
-
-
-
V
0.2
0.2
0.2
0.2
0.40
0.55
1.0
0.2
0.2
0.2
0.2
0.50
0.65
1.0
V
0
V
0
V
0
V
0.25
0.35
-
V
V
II
input leakage VI = VCC or GND; VCC = 5.5 V
current
μA
74LV03
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© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 4 — 31 August 2017
4 / 12
Nexperia
74LV03
Quad 2-input NAND gate
Symbol Parameter
Conditions
-40 °C to +85 °C
Min
Typ [1] Max
-40 °C to +125 °C Unit
Min
Max
IOZ
OFF-state
per input pin; VCC = 2.0 V to 3.6 V;
-
-
±5.0
-
±10
μA
μA
output current VI = VIL; VO = VCC or GND;
other inputs at VCC or GND
[2]
per input pin; VCC = 2.0 V to 3.6 V;
VI = VIL; VO = 6.0 V;
-
-
±10.0
-
±20
other inputs at VCC or GND
ICC
ΔICC
CI
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
-
-
-
20.0
500
-
-
-
-
40
850
-
μA
μA
pF
additional
per input; VI = VCC - 0.6 V;
supply current VCC = 2.7 V to 3.6 V
input
3.5
capacitance
[1] Typical values are measured at Tamb = 25 °C.
[2] The maximum operating output voltage (VO(max)) is 6.0 V.
10 Dynamic characteristics
Table 7.ꢀDynamic characteristics
GND = 0 V; For test circuit see Figure 6.
Symbol Parameter
Conditions
-40 °C to +85 °C
Min Typ [1] Max
-40 °C to +125 °C Unit
Min
Max
[2]
tpd
propagation
delay
nA, nB to nY; see Figure 5
VCC = 1.2 V
-
-
-
-
-
-
-
50
17
13
8
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
pF
VCC = 2.0 V
26
19
-
31
23
-
VCC = 2.7 V
VCC = 3.3 V; CL = 15 pF
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
[3]
[4]
10
-
16
13
-
19
16
-
CPD
power dissipation CL = 0 pF; RL = ∞ Ω;
capacitance VI = GND to VCC
4
[1] All typical values are measured at Tamb = 25 °C.
[2] tpd is the same as tPLZ and tPZL
.
[3] Typical values are measured at nominal supply voltage (VCC = 3.3 V).
[4] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz,
fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in V
N = number of inputs switching
Σ(CL × VCC2 × fo) = sum of the outputs.
74LV03
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© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 4 — 31 August 2017
5 / 12
Nexperia
74LV03
Quad 2-input NAND gate
10.1 Waveforms and test circuit
V
I
nA, nB input
V
t
M
GND
t
PLZ
PZL
V
CC
nY output
V
M
V
V
X
OL
mnb132
Measurement points are given in Table 8
VOL is a typical voltage output level that occurs with the output load.
Figure 5.ꢀInputs nA and nB to output nY propagation delay times
Table 8.ꢀMeasurement points
Supply voltage
VCC
Input
Output
VX
VM
VM
≤ 2.7 V
0.5 × VCC
1.5 V
VOL + 0.1 V
VOL + 0.3 V
VOL + 0.1 V
0.5 × VCC
1.5 V
2.7 V to 3.6 V
≥ 4.5 V
0.5 × VCC
0.5 × VCC
74LV03
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© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 4 — 31 August 2017
6 / 12
Nexperia
74LV03
Quad 2-input NAND gate
t
W
V
I
90 %
negative
pulse
V
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
M
M
10 %
0 V
t
W
V
EXT
V
CC
R
L
V
V
O
I
PULSE
GENERATOR
DUT
R
T
C
L
R
L
001aae235
Test data is given in Table 9
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Figure 6.ꢀTest circuit for measuring switching times
Table 9.ꢀTest data
Supply voltage Input
Load
CL
VEXT
VCC
VI
tr, tf
RL
tPLZ, tPZL
2 × VCC
2 × VCC
2 × VCC
≤ 2.7 V
VCC
2.7 V
VCC
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
50 pF
50 pF
50 pF
1 kΩ
1 kΩ
1 kΩ
2.7 V to 3.6 V
≥ 4.5 V
74LV03
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 4 — 31 August 2017
7 / 12
Nexperia
74LV03
Quad 2-input NAND gate
11 Package outline
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.05
1.05
0.25
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT108-1
076E06
MS-012
Figure 7.ꢀPackage outline SOT108-1 (SO14)
74LV03
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© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 4 — 31 August 2017
8 / 12
Nexperia
74LV03
Quad 2-input NAND gate
12 Abbreviations
Table 10.ꢀAbbreviations
Acronym
CMOS
DUT
Description
Complementary Metal-Oxide Semiconductor
Device Under Test
TTL
Transistor-Transistor Logic
13 Revision history
Table 11.ꢀRevision history
Document ID
74LV03 v.4
Release date
Data sheet status
Change notice
Supersedes
20170831
Product data sheet
-
74LV03 v.3
Modifications:
• The format of this data sheet has been redesigned to comply with the identity guidelines of
Nexperia.
• Legal texts have been adapted to the new company name where appropriate.
74LV03 v.3
20030303
Product data sheet
ECN 853-1963 29494 74LV03 v.2
Modifications:
• Deleted DIL, SSOP and TSSOP package ordering and package outlines (discontinued options).
• Corrected power dissipation formula.
74LV03 v.2
74LV03 v.1
19980420
19970328
Product specification
Product specification
ECN 853-1963 19257 74LV03 v.1
-
-
74LV03
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 4 — 31 August 2017
9 / 12
Nexperia
74LV03
Quad 2-input NAND gate
14 Legal information
14.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Product [short] data sheet
Qualification
Production
This document contains data from the preliminary specification.
This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nexperia.com.
systems or equipment, nor in applications where failure or malfunction
of an Nexperia product can reasonably be expected to result in personal
14.2 Definitions
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
Draft — The document is a draft version only. The content is still under
such equipment or applications and therefore such inclusion and/or use is at
internal review and subject to formal approval, which may result in
the customer’s own risk.
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
Short data sheet — A short data sheet is an extract from a full data sheet
without further testing or modification. Customers are responsible for the
with the same product type number(s) and title. A short data sheet is
design and operation of their applications and products using Nexperia
intended for quick reference only and should not be relied upon to contain
products, and Nexperia accepts no liability for any assistance with
detailed and full information. For detailed and full information see the
applications or customer product design. It is customer’s sole responsibility
relevant full data sheet, which is available on request via the local Nexperia
to determine whether the Nexperia product is suitable and fit for the
sales office. In case of any inconsistency or conflict with the short data sheet,
customer’s applications and products planned, as well as for the planned
the full data sheet shall prevail.
application and use of customer’s third party customer(s). Customers should
provide appropriate design and operating safeguards to minimize the risks
associated with their applications and products. Nexperia does not accept
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
any liability related to any default, damage, costs or problem which is based
Nexperia and its customer, unless Nexperia and customer have explicitly
on any weakness or default in the customer’s applications or products, or
agreed otherwise in writing. In no event however, shall an agreement be
the application or use by customer’s third party customer(s). Customer is
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
responsible for doing all necessary testing for the customer’s applications
and products using Nexperia products in order to avoid a default of the
applications and the products or of the application or use by customer’s third
party customer(s). Nexperia does not accept any liability in this respect.
14.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
Limited warranty and liability — Information in this document is believed
damage to the device. Limiting values are stress ratings only and (proper)
to be accurate and reliable. However, Nexperia does not give any
operation of the device at these or any other conditions above those
representations or warranties, expressed or implied, as to the accuracy
given in the Recommended operating conditions section (if present) or the
or completeness of such information and shall have no liability for the
Characteristics sections of this document is not warranted. Constant or
consequences of use of such information. Nexperia takes no responsibility
repeated exposure to limiting values will permanently and irreversibly affect
for the content in this document if provided by an information source outside
the quality and reliability of the device.
of Nexperia. In no event shall Nexperia be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation -
lost profits, lost savings, business interruption, costs related to the removal
Terms and conditions of commercial sale — Nexperia products are
sold subject to the general terms and conditions of commercial sale, as
or replacement of any products or rework charges) whether or not such
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
damages are based on tort (including negligence), warranty, breach of
in a valid written individual agreement. In case an individual agreement is
contract or any other legal theory. Notwithstanding any damages that
concluded only the terms and conditions of the respective agreement shall
customer might incur for any reason whatsoever, Nexperia's aggregate and
apply. Nexperia hereby expressly objects to applying the customer’s general
cumulative liability towards customer for the products described herein shall
terms and conditions with regard to the purchase of Nexperia products by
customer.
be limited in accordance with the Terms and conditions of commercial sale of
Nexperia.
No offer to sell or license — Nothing in this document may be interpreted
Right to make changes — Nexperia reserves the right to make changes
or construed as an offer to sell products that is open for acceptance or
to information published in this document, including without limitation
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-critical
74LV03
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 4 — 31 August 2017
10 / 12
Nexperia
74LV03
Quad 2-input NAND gate
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified, the
product is not suitable for automotive use. It is neither qualified nor tested in
accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of non-automotive qualified
products in automotive equipment or applications. In the event that customer
uses the product for design-in and use in automotive applications to
automotive specifications and standards, customer (a) shall use the product
without Nexperia's warranty of the product for such automotive applications,
use and specifications, and (b) whenever customer uses the product for
automotive applications beyond Nexperia's specifications such use shall be
solely at customer’s own risk, and (c) customer fully indemnifies Nexperia
for any liability, damages or failed product claims resulting from customer
design and use of the product for automotive applications beyond Nexperia's
standard warranty and Nexperia's product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
14.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
74LV03
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© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 4 — 31 August 2017
11 / 12
Nexperia
74LV03
Quad 2-input NAND gate
Contents
1
General description ............................................ 1
2
3
4
5
5.1
5.2
6
7
8
Features and benefits .........................................1
Ordering information .......................................... 1
Functional diagram .............................................2
Pinning information ............................................ 2
Pinning ...............................................................2
Pin description ...................................................2
Functional description ........................................3
Limiting values ....................................................3
Recommended operating conditions ................4
Static characteristics ..........................................4
Dynamic characteristics .....................................5
Waveforms and test circuit ................................6
Package outline ...................................................8
Abbreviations ...................................................... 9
Revision history .................................................. 9
Legal information ..............................................10
9
10
10.1
11
12
13
14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© Nexperia B.V. 2017.
All rights reserved.
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 31 August 2017
Document identifier: 74LV03
相关型号:
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