74LVC3G07DP-Q100 [NEXPERIA]
Triple buffer with open-drain outputProduction;型号: | 74LVC3G07DP-Q100 |
厂家: | Nexperia |
描述: | Triple buffer with open-drain outputProduction 光电二极管 逻辑集成电路 |
文件: | 总11页 (文件大小:196K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74LVC3G07-Q100
Triple buffer with open-drain output
Rev. 3 — 23 October 2018
Product data sheet
1. General description
The 74LVC3G07-Q100 provides three non-inverting buffers.
The output of the device is an open-drain and can be connected to other open-drain outputs to
implement active-LOW wired-OR or active-HIGH wired-AND functions.
Input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a
mixed 3.3 V and 5 V environment.
Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall time.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry
disables the output, preventing the damaging backflow current through the device when it is
powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
•
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
•
•
•
•
•
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
•
•
•
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V).
•
•
•
•
•
•
-24 mA output drive (VCC = 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
ESD protection:
•
•
•
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
Nexperia
74LVC3G07-Q100
Triple buffer with open-drain output
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVC3G07DP-Q100 -40 °C to +125 °C
TSSOP8
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
SOT505-2
74LVC3G07DC-Q100 -40 °C to +125 °C
VSSOP8
plastic very thin shrink small outline package;
8 leads; body width 2.3 mm
SOT765-1
4. Marking
Table 2. Marking codes
Type number
Marking code [1]
74LVC3G07DP-Q100
74LVC3G07DC-Q100
V07
V07
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
1
1A
2A
3A
1Y
2Y
3Y
1A
2A
3A
1Y
2Y
1
Y
3Y
1
A
GND mna591
001aah762
001aah763
Fig. 1. Logic symbol
Fig. 2. IEC logic symbol
Fig. 3. Logic diagram (one driver)
6. Pinning information
6.1. Pinning
74LVC3G07-Q100
1
2
3
4
8
7
6
5
1A
3Y
V
CC
1Y
3A
2Y
2A
GND
aaa-006019
Fig. 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8)
©
74LVC3G07_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 3 — 23 October 2018
2 / 11
Nexperia
74LVC3G07-Q100
Triple buffer with open-drain output
6.2. Pin description
Table 3. Pin description
Symbol
Pin
1, 3, 6
4
Description
data input
1A, 2A, 3A
GND
ground (0 V)
data output
supply voltage
1Y, 2Y, 3Y
VCC
7, 5, 2
8
7. Functional description
Table 4. Function table
H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.
Input nA
Output nY
L
L
Z
H
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
-0.5
-50
-0.5
-50
-0.5
-0.5
-
Max
+6.5
-
Unit
V
VCC
IIK
supply voltage
input clamping current
input voltage
VI < 0 V
mA
V
VI
[1]
+6.5
-
IOK
VO
output clamping current
output voltage
VO < 0 V
mA
V
Active mode
[1]
[1]
+6.5
+6.5
50
Power-down mode; VCC = 0 V
VO = 0 V to 6.5 V
V
IO
output current
mA
mA
mA
°C
ICC
IGND
Tstg
Ptot
supply current
-
100
-
ground current
-100
-65
-
storage temperature
total power dissipation
+150
250
Tamb = -40 °C to +125 °C
[2]
mW
[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP8 package: above 55 °C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 °C the value of Ptot derates linearly with 8 mW/K.
©
74LVC3G07_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 3 — 23 October 2018
3 / 11
Nexperia
74LVC3G07-Q100
Triple buffer with open-drain output
9. Recommended operating conditions
Table 6. Operating conditions
Symbol Parameter
Conditions
Min
Max
5.5
5.5
5.5
5.5
+125
20
Unit
V
VCC
VI
supply voltage
input voltage
output voltage
1.65
0
0
V
VO
Active mode
V
Power-down mode; VCC = 0 V
0
V
Tamb
ambient temperature
-40
-
°C
ns/V
ns/V
Δt/ΔV
input transition rise and fall rate
VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 5.5 V
-
10
10. Static characteristics
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Tamb = -40 °C to +85 °C
Tamb
=
Unit
-40 °C to +125 °C
Min
Typ [1]
Max
Min
Max
VIH
HIGH-level input
voltage
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
0.65VCC
-
-
-
-
-
-
-
-
-
0.65VCC
-
V
V
V
V
V
V
V
V
1.7
-
1.7
-
2.0
-
-
2.0
-
-
0.7VCC
0.7VCC
VIL
LOW-level input
voltage
-
-
-
-
0.35VCC
0.7
-
-
-
-
0.35VCC
0.7
0.8
0.8
0.3VCC
0.3VCC
VOL
LOW-level output VI = VIH or VIL
voltage
IO = 100 μA;
-
-
0.1
-
0.1
V
VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
-
-
-
-
-
-
-
-
-
-
0.45
0.3
-
-
-
-
-
0.70
0.45
0.60
0.80
0.80
V
V
V
V
V
0.4
0.55
0.55
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74LVC3G07_Q100
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Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 3 — 23 October 2018
4 / 11
Nexperia
74LVC3G07-Q100
Triple buffer with open-drain output
Symbol Parameter
Conditions
Tamb = -40 °C to +85 °C
Tamb
=
Unit
-40 °C to +125 °C
Min
Typ [1]
Max
Min
Max
II
input leakage
current
VI = 5.5 V or GND;
VCC = 0 V to 5.5 V
-
±0.1
±1
-
±1
μA
μA
IOZ
OFF-state output VI = VIH or VIL;
-
±0.1
±2
-
±2
current
VO = VCC or GND;
VCC = 5.5 V
IOFF
ICC
power-off leakage VI or VO = 5.5 V; VCC = 0 V
current
-
-
-
-
±0.1
0.1
5
±2
4
-
-
-
-
±2
4
μA
μA
μA
pF
supply current
VI = 5.5 V or GND; IO = 0 A;
VCC = 1.65 V to 5.5 V
ΔICC
CI
additional supply
current
per pin; VCC = 2.3 V to 5.5 V;
VI = VCC - 0.6 V; IO = 0 A
500
-
500
-
input capacitance
2.5
[1] All typical values are measured at VCC = 3.3 V and at Tamb = 25 °C.
11. Dynamic characteristics
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Fig. 6.
Symbol Parameter
Conditions
Tamb = -40 °C to +85 °C
Tamb
=
Unit
-40 °C to +125 °C
Min
Typ [1]
Max
Min
Max
tpd
propagation
delay
nA to nY; see Fig. 5
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
[2]
1.0
0.5
1.0
0.5
0.5
-
2.9
1.7
2.3
2.1
1.5
6.5
6.7
4.3
4.2
3.7
2.9
-
1.0
0.5
1.0
0.5
0.5
-
8.4
5.5
5.3
4.7
3.7
-
ns
ns
ns
ns
ns
pF
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
CPD
power
VI = GND to VCC; VCC = 3.3 V [3]
dissipation
capacitance
[1] Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2] tpd is the same as tPLZ and tPZL
.
[3] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of outputs.
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74LVC3G07_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 3 — 23 October 2018
5 / 11
Nexperia
74LVC3G07-Q100
Triple buffer with open-drain output
11.1. Waveforms and test circuit
V
I
V
V
M
nA input
M
GND
t
t
PZL
PLZ
V
CC
nY output
V
M
V
X
V
OL
mna528
Measurement points are given in Table 9.
VOL is the typical output voltage level that occurs with the output load.
Fig. 5. The input (nA) to output (nY) propagation delays
Table 9. Measurement points
Supply voltage
VCC
Input
Output
VM
VM
VX
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
0.5 × VCC
0.5 × VCC
1.5 V
0.5 × VCC
0.5 × VCC
1.5 V
VOL + 0.15 V
VOL + 0.15 V
VOL + 0.3 V
VOL + 0.3 V
VOL + 0.3 V
3.0 V to 3.6 V
4.5 V to 5.5 V
1.5 V
1.5 V
0.5 × VCC
0.5 × VCC
V
EXT
V
CC
R
L
L
V
V
O
I
G
DUT
R
T
C
L
R
mna616
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig. 6. Test circuit for measuring switching times
Table 10. Test data
Supply voltage
VCC
Input
VI
Load
CL
VEXT
tr = tf
RL
tPZL, tPLZ
2 × VCC
2 × VCC
6 V
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
VCC
VCC
2.7 V
2.7 V
VCC
≤ 2.0 ns
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
30 pF
30 pF
50 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
500 Ω
3.0 V to 3.6 V
4.5 V to 5.5 V
6 V
2 × VCC
©
74LVC3G07_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 3 — 23 October 2018
6 / 11
Nexperia
74LVC3G07-Q100
Triple buffer with open-drain output
12. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
SOT505-2
D
E
A
X
c
H
v
M
y
A
E
Z
5
8
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
A
A
A
b
c
D
E
e
H
E
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
max.
0.15
0.00
0.95
0.75
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
4.1
3.9
0.47
0.33
0.70
0.35
8°
0°
mm
1.1
0.65
0.5
0.2
0.13
0.1
0.25
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-01-16
SOT505-2
- - -
Fig. 7. Package outline SOT505-2 (TSSOP8)
©
74LVC3G07_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 3 — 23 October 2018
7 / 11
Nexperia
74LVC3G07-Q100
Triple buffer with open-drain output
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
E
A
X
c
y
H
E
v
A
Z
5
8
Q
A
2
A
A
(A )
3
1
pin 1 index
θ
L
p
detail X
1
4
L
e
w
b
p
0
5 mm
scale
Dimensions (mm are the original dimensions)
A
(1)
(2)
(1)
Unit
A
A
A
b
c
D
E
e
H
E
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
max.
max
mm nom
min
0.15 0.85
0.00 0.60
0.27 0.23 2.1 2.4
0.17 0.08 1.9 2.2
3.2
3.0
0.40 0.21
0.15 0.19
0.4
8°
0°
1
0.12
0.5
0.4
0.2 0.08 0.1
0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
sot765-1_po
Issue date
References
Outline
version
European
projection
IEC
JEDEC
JEITA
07-06-02
16-05-31
SOT765-1
MO-187
Fig. 8. Package outline SOT765-1 (VSSOP8)
©
74LVC3G07_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 3 — 23 October 2018
8 / 11
Nexperia
74LVC3G07-Q100
Triple buffer with open-drain output
13. Abbreviations
Table 11. Abbreviations
Acronym
Description
CMOS
DUT
ESD
HBM
MIL
Complementary Metal-Oxide Semiconductor
Device Under Test
ElectroStatic Discharge
Human Body Model
Military
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 12. Revision history
Document ID
Release date
20181023
Data sheet status
Change notice Supersedes
74LVC3G07_Q100 v.3
Modifications:
Product data sheet
-
74LVC3G07_Q100 v.2
•
•
The format of this data sheet has been redesigned to comply with the identity guidelines
of Nexperia.
Legal texts have been adapted to the new company name where appropriate.
74LVC3G07_Q100 v.2
Modifications:
20161214
Table 7: The maximum limits for leakage current and supply current have changed.
20130129 Product data sheet
Product data sheet
-
74LVC3G07_Q100 v.1
•
74LVC3G07_Q100 v.1
-
-
©
74LVC3G07_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 3 — 23 October 2018
9 / 11
Nexperia
74LVC3G07-Q100
Triple buffer with open-drain output
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Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
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Definition
[1][2]
status [3]
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data sheet
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the objective specification for
product development.
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the preliminary specification.
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data sheet
This document contains the product
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74LVC3G07_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 3 — 23 October 2018
10 / 11
Nexperia
74LVC3G07-Q100
Triple buffer with open-drain output
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Ordering information....................................................2
4. Marking..........................................................................2
5. Functional diagram.......................................................2
6. Pinning information......................................................2
6.1. Pinning.........................................................................2
6.2. Pin description.............................................................3
7. Functional description................................................. 3
8. Limiting values............................................................. 3
9. Recommended operating conditions..........................4
10. Static characteristics..................................................4
11. Dynamic characteristics.............................................5
11.1. Waveforms and test circuit........................................ 6
12. Package outline.......................................................... 7
13. Abbreviations..............................................................9
14. Revision history..........................................................9
15. Legal information......................................................10
© Nexperia B.V. 2018. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 23 October 2018
©
74LVC3G07_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 3 — 23 October 2018
11 / 11
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