74LVC3G07GT_技术文档

74LVC3G07

Triple buffer with open-drain output

Rev. 03 — 01 February 2005

Product data sheet

1. General description

The 74LVC3G07 is a high-performance, low-power, low-voltage, Si-gate CMOS device

and superior to most advanced CMOS compatible TTL families.

Input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this

device in a mixed 3.3 V and 5 V environment.

Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall

time.

This device is fully speciﬁed for partial power-down applications using I_off. The I_offcircuitry

disables the output, preventing the damaging backﬂow current through the device when it

is powered down.

The 74LVC3G07 provides three non-inverting buffers.

The output of the device is an open drain and can be connected to other open-drain

outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.

2. Features

■ Wide supply voltage range from 1.65 V to 5.5 V

■ 5 V tolerant input/output for interfacing with 5 V logic

■ High noise immunity

■ Complies with JEDEC standard:

◆ JESD8-7 (1.65 V to 1.95 V)

◆ JESD8-5 (2.3 V to 2.7 V)

◆ JESD8-B/JESD36 (2.7 V to 3.6 V).

■ ESD protection:

◆ HBM EIA/JESD22-A114-B exceeds 2000 V

◆ MM EIA/JESD22-A115-A exceeds 200 V.

■ −24 mA output drive (V_CC= 3.0 V)

■ CMOS low power consumption

■ Latch-up performance exceeds 250 mA

■ Direct interface with TTL levels

■ Inputs accept voltages up to 5 V

■ Multiple package options

■ Speciﬁed from −40 °C to +85 °C and −40 °C to +125 °C.

74LVC3G07

Philips Semiconductors

Triple buffer with open-drain output

3. Quick reference data

Table 1:

Quick reference data

GND = 0 V; T_amb= 25 °C.

Symbol

Parameter

Conditions

Min

Typ

Max Unit

t_PLZ, t_PZL

propagation delay

input nA to output nY C_L= 30 pF; R_L= 1 kΩ

V_CC= 1.8 V;

-

2.9

-

ns

V_CC= 2.5 V;

C_L= 30 pF; R_L= 500 Ω

-

1.7

2.3

2.1

1.5

V_CC= 2.7 V;

C_L= 50 pF; R_L= 500 Ω

V_CC= 3.3 V;

C_L= 50 pF; R_L= 500 Ω

V_CC= 5.0 V;

C_L= 50 pF; R_L= 500 Ω

C_I

input capacitance

-

2.5

6.5

-

pF

[1] [2]

C_PD

power dissipation

V_CC= 3.3 V

capacitance per gate

[1] C_PDis used to determine the dynamic power dissipation (P_Din µW).

P_D= C_PD× V_CC²× f_i× N + ∑(C_L× V_CC²× f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in Volts;

N = number of inputs switching;

∑(C_L× V_CC²× f_o) = sum of outputs.

[2] The condition is V_I= GND to V_CC

.

4. Ordering information

Table 2:

Ordering information

Type number

Package

Temperature range Name

Description

Version

74LVC3G07DP −40 °C to +125 °C

74LVC3G07DC −40 °C to +125 °C

74LVC3G07GT −40 °C to +125 °C

TSSOP8 plastic thin shrink small outline package; 8 leads; body

width 3 mm; lead length 0.5 mm

SOT505-2

VSSOP8 plastic very thin shrink small outline package; 8 leads;

body width 2.3 mm

SOT765-1

SOT833-1

XSON8

plastic extremely thin small outline package; no leads;

8 terminals; body 1 × 1.95 × 0.5 mm

5. Marking

Table 3:

Marking codes

Type number

74LVC3G07DP

74LVC3G07DC

74LVC3G07GT

Marking code

V07

9397 750 14542

Product data sheet

Rev. 03 — 01 February 2005

2 of 14

74LVC3G07

Philips Semiconductors

Triple buffer with open-drain output

6. Functional diagram

1

3

6

7

5

2

1Y

2Y

3Y

1A

2A

3A

1Y

2Y

7

5

2

1A

2A

3A

1

3

6

3Y

mnb136

mnb137

Fig 1. Logic symbol

Fig 2. IEC logic symbol

Y

A

GND mna591

Fig 3. Logic diagram (one driver)

7. Pinning information

7.1 Pinning

07

1A

3Y

1

2

3

4

8

7

6

5

V

CC

1

2

3

4

8

7

6

5

1A

V

CC

1Y

3A

2Y

3Y

2A

1Y

3A

2Y

07

2A

GND

001aab022

GND

001aac022

Transparent top view

Fig 4. Pin conﬁguration VSSOP8 and

TSSOP8

Fig 5. Pin conﬁguration XSON8

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74LVC3G07

Philips Semiconductors

Triple buffer with open-drain output

7.2 Pin description

reserved

Table 4:

Pin description

Symbol

1A

1

Description

data input

3Y

2

data output

data input

2A

3

GND

2Y

4

ground (0 V)

data output

data input

5

3A

6

1Y

7

data output

supply voltage

V_CC

8

8. Functional description

8.1 Function table

Table 5:

Function table^[1]

Input nA

Output nY

L

Z

H

[1] H = HIGH voltage level;

L = LOW voltage level;

Z = high-impedance OFF-state.

9. Limiting values

Table 6:

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to

GND (ground = 0 V).

Symbol Parameter

Conditions

Min

Max

+6.5

−50

Unit

V

V_CC

V_I

supply voltage

input voltage

output voltage

−0.5

[1]

−0.5

V

V_O

active mode

Power-down mode

V_I< 0 V

−0.5

V

[1] [2]

−0.5

V

I_IK

I_OK

I_O

input diode current

-

mA

°C

mW

output diode current V_O< 0 V

output sink current V_O= 0 V to 6.5 V

-

−50

-

50

I_CC, I_GNDV_CCor GND current

-

±100

+150

300

T_stg

P_tot

storage temperature

power dissipation

−65

T_amb= −40 °C to +125 °C

-

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] When V_CC= 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.

9397 750 14542

Product data sheet

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74LVC3G07

Philips Semiconductors

Triple buffer with open-drain output

10. Recommended operating conditions

Table 7:

Recommended operating conditions

Symbol Parameter

Conditions

Min

1.65

0

Typ

Max Unit

V_CC

V_I

supply voltage

input voltage

output voltage

-

5.5

V_CC

5.5

V

V_O

active mode

0

Power-down mode; V_CC= 0 V

0

T_amb

t_r, t_f

ambient temperature

−40

0

+125 °C

input rise and fall

times

V_CC= 1.65 V to 2.7 V

V_CC= 2.7 V to 5.5 V

20

10

ns/V

0

ns/V

11. Static characteristics

Table 8:

Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

T_amb= −40 °C to +85 °C^[1]

V_IH

HIGH-level input

voltage

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V to 3.6 V

V_CC= 4.5 V to 5.5 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V to 3.6 V

V_CC= 4.5 V to 5.5 V

V_I= V_IHor V_IL

0.65 × V_CC

-

V

1.7

2.0

0.7 × V_CC

V_IL

LOW-level input

voltage

-

0.35 × V_CC

0.7

0.8

0.3 × V_CC

V_OL

LOW-level output

voltage

I_O= 100 µA;

-

0.1

V

V_CC= 1.65 V to 5.5 V

I_O= 4 mA; V_CC= 1.65 V

I_O= 8 mA; V_CC= 2.3 V

I_O= 12 mA; V_CC= 2.7 V

I_O= 24 mA; V_CC= 3.0 V

I_O= 32 mA; V_CC= 4.5 V

-

0.45

0.3

V

-

V

-

0.4

V

-

0.55

±5

V

-

V

I_LI

input leakage current V_I= 5.5 V or GND;

_CC= 1.65 V to 5.5 V

±0.1

µA

V

I_OZ

I_off

I_CC

∆I_CC

3-state output

OFF-state current

V_I= V_IHor V_IL; V_O= V_CCor GND;

_CC= 5.5 V

-

±0.1

0.1

5

±10

10

µA

pF

V

power-off leakage

current

V_Ior V_O= 5.5 V; V_CC= 0 V

quiescent supply

current

V_I= V_CCor GND; I_O= 0 A;

V_CC= 5.5 V

additional quiescent

supply current per pin V_CC= 2.3 V to 5.5 V

V_I= V_CC− 0.6 V; I_O= 0 A;

500

-

C_I

input capacitance

2.5

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74LVC3G07

Philips Semiconductors

Triple buffer with open-drain output

Table 8:

Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

T_amb= −40 °C to +125 °C

V_IH

HIGH-level input

voltage

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V to 3.6 V

V_CC= 4.5 V to 5.5 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V to 3.6 V

V_CC= 4.5 V to 5.5 V

V_I= V_IHor V_IL

0.65 × V_CC

-

V

1.7

-

2.0

-

0.7 × V_CC

-

V_IL

LOW-level input

voltage

-

0.35 × V_CC

0.7

0.8

0.3 × V_CC

V_OL

LOW-level output

voltage

I_O= 100 µA;

-

0.1

V

V_CC= 1.65 V to 5.5 V

I_O= 4 mA; V_CC= 1.65 V

I_O= 8 mA; V_CC= 2.3 V

I_O= 12 mA; V_CC= 2.7 V

I_O= 24 mA; V_CC= 3.0 V

I_O= 32 mA; V_CC= 4.5 V

-

0.70

0.45

0.60

0.80

±20

V

I_LI

input leakage current V_I= 5.5 V or GND;

_CC= 1.65 V to 5.5 V

µA

V

I_OZ

I_off

I_CC

∆I_CC

3-state output

OFF-state current

V_I= V_IHor V_IL; V_O= V_CCor GND;

_CC= 5.5 V

-

±10

±20

40

µA

V

power-off leakage

current

V_Ior V_O= 5.5 V; V_CC= 0 V

quiescent supply

current

V_I= V_CCor GND; I_O= 0 A;

V_CC= 5.5 V

additional quiescent

V_I= V_CC− 0.6 V; I_O= 0 A;

5000

supply current per pin V_CC= 2.3 V to 5.5 V

[1] All typical values are measured at nominal V_CCand T_amb= 25 °C.

12. Dynamic characteristics

Table 9:

Dynamic characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

T_amb= −40 °C to +85 °C^[1]

t_PLZ, t_PZL

propagation delay

input nA to output nY

see Figure 6 and 7

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.0

0.5

1.0

0.5

2.9

1.7

2.3

2.1

1.5

6.7

4.3

4.2

3.7

2.9

ns

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

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74LVC3G07

Philips Semiconductors

Triple buffer with open-drain output

Table 9:

Dynamic characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

[2] [3]

C_PD

power dissipation

V_CC= 3.3 V

-

6.5

-

pF

capacitance per gate

T_amb= −40 °C to +125 °C

t_PLZ, t_PZLpropagation delay

input nA to output nY

see Figure 6 and 7

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.0

0.5

1.0

0.5

-

8.4

5.5

5.3

4.7

3.7

ns

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

[1] All typical values are measured at nominal V_CCand T_amb= 25 °C.

[2] C_PDis used to determine the dynamic power dissipation (P_Din µW).

P_D= C_PD× V_CC²× f_i× N + ∑(C_L× V_CC²× f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in Volts;

N = number of inputs switching;

∑(C_L× V_CC²× f_o) = sum of outputs.

[3] The condition is V_I= GND to V_CC

.

13. Waveforms

V

I

V

nA input

M

GND

t

PZL

PLZ

V

CC

nY output

V

M

V

X

V

OL

mna528

Measurement points are given in Table 10.

V_OLis typical output voltage drop that occurs with the output load.

Fig 6. The input (nA) to output (nY) propagation delays

9397 750 14542

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74LVC3G07

Philips Semiconductors

Triple buffer with open-drain output

Table 10: Measurement points

Supply voltage

Input

Output

V_CC

V_M

V_I

V_M

V_X

1.65 V to 1.95 V

2.3 V to 2.7 V

2.7 V

0.5 × V_CC

1.5 V

V_CC

2.7 V

V_CC

0.5 × V_CC

1.5 V

V_OL+ 0.15 V

V_OL+ 0.3 V

3.0 V to 3.6 V

4.5 V to 5.5 V

1.5 V

0.5 × V_CC

V

EXT

V

CC

R

L

V

I

V

O

PULSE

GENERATOR

D.U.T.

C

L

R

L

R

T

mna616

Test data are given in Table 11.

Deﬁnitions for test circuit:

R_L= Load resistor.

C_L= Load capacitance including jig and probe capacitance.

R_T= Termination resistance should be equal to the output impedance Z_oof the pulse

generator.

Fig 7. Load circuitry for switching times

Table 11: Test data

Supply voltage

V_CC

Input

V_I

Load

C_L

V_EXT

t_r= t_f

R_L

t_PZL, t_PLZ

2 × V_CC

6 V

1.65 V to 1.95 V

2.3 V to 2.7 V

2.7 V

V_CC

2.7 V

V_CC

≤ 2.0 ns

≤ 2.5 ns

30 pF

50 pF

1 kΩ

500 Ω

3.0 V to 3.6 V

4.5 V to 5.5 V

6 V

2 × V_CC

9397 750 14542

Product data sheet

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74LVC3G07

Philips Semiconductors

Triple buffer with open-drain output

14. Package outline

TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm

SOT505-2

D

E

A

X

c

H

v

M

y

A

E

Z

5

8

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

detail X

1

4

e

w

M

b

p

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

A

b

c

D

E

e

H

E

L

p

UNIT

v

w

y

Z

θ

1

2

3

p

max.

0.15

0.00

0.95

0.75

0.38

0.22

0.18

0.08

3.1

2.9

3.1

2.9

4.1

3.9

0.47

0.33

0.70

0.35

8°

0°

mm

1.1

0.65

0.25

0.5

0.2

0.13

0.1

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

02-01-16

SOT505-2

- - -

Fig 8. Package outline SOT505-2 (TSSOP8)

9397 750 14542

Product data sheet

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74LVC3G07

Philips Semiconductors

Triple buffer with open-drain output

VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm

SOT765-1

D

E

A

X

c

y

H

v

M

A

E

Z

5

8

Q

A

2

A

1

(A )

3

pin 1 index

θ

L

p

L

detail X

1

4

e

w

M

b

p

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

A

b

c

D

E

e

H

L

p

Q

UNIT

v

w

y

Z

θ

1

2

3

p

E

max.

0.15

0.00

0.85

0.60

0.27

0.17

0.23

0.08

2.1

1.9

2.4

2.2

3.2

3.0

0.40

0.15

0.21

0.19

0.4

0.1

8°

0°

mm

1

0.5

0.12

0.4

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

02-06-07

SOT765-1

MO-187

Fig 9. Package outline SOT765-1 (VSSOP8)

9397 750 14542

Product data sheet

Rev. 03 — 01 February 2005

10 of 14

74LVC3G07

Philips Semiconductors

Triple buffer with open-drain output

XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm

SOT833-1

b

1

2

3

4

4×

(2)

L

1

e

8

7

6

5

e

1

e

1

e

1

8×

(2)

A

1

D

E

terminal 1

index area

0

1

2 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

1

UNIT

b

D

E

e

L

1

max max

0.25

0.17

2.0

1.9

1.05

0.95

0.35 0.40

0.27 0.32

mm

0.5 0.04

0.6

0.5

Notes

1. Including plating thickness.

2. Can be visible in some manufacturing processes.

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

- - -

04-07-22

04-11-09

SOT833-1

- - -

MO-252

Fig 10. Package outline SOT833-1 (XSON8)

9397 750 14542

Product data sheet

Rev. 03 — 01 February 2005

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74LVC3G07

Philips Semiconductors

Triple buffer with open-drain output

15. Revision history

Table 12: Revision history

Document ID

74LVC3G07_3

Modiﬁcations:

74LVC3G07_2

74LVC3G07_1

Release date Data sheet status

20050201 Product data sheet

Change notice Doc. number

Supersedes

-

9397 750 14542 74LVC3G07_2

• Changed: type number 74LVC3G07GT (XSON8 package).

20041027

Product data sheet

-

9397 750 13791 74LVC3G07_1

20040608

Product data sheet

-

9397 750 13267

-

9397 750 14542

Product data sheet

Rev. 03 — 01 February 2005

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74LVC3G07

Philips Semiconductors

Triple buffer with open-drain output

16. Data sheet status

Level Data sheet status^[1]Product status^{[2] [3]}

Deﬁnition

I

Objective data

Development

This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II

Preliminary data

Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

[1]

[2]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

17. Deﬁnitions

18. Disclaimers

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

19. Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales ofﬁce addresses, send an email to: sales.addresses@www.semiconductors.philips.com

9397 750 14542

Product data sheet

Rev. 03 — 01 February 2005

13 of 14

74LVC3G07

Philips Semiconductors

Triple buffer with open-drain output

20. Contents

1

2

3

4

5

6

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Quick reference data . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3

7

7.1

7.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

8

8.1

9

Functional description . . . . . . . . . . . . . . . . . . . 4

Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4

Recommended operating conditions. . . . . . . . 5

Static characteristics. . . . . . . . . . . . . . . . . . . . . 5

Dynamic characteristics . . . . . . . . . . . . . . . . . . 6

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12

Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 13

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Contact information . . . . . . . . . . . . . . . . . . . . 13

10

11

12

13

14

15

16

17

18

19

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner. The information presented in this document does

not form part of any quotation or contract, is believed to be accurate and reliable and may

be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under

patent- or other industrial or intellectual property rights.

Date of release: 01 February 2005

Document number: 9397 750 14542

Published in The Netherlands


型号：	74LVC3G07GT
厂家：	NXP
描述：	Triple buffer with open-drain output 开漏输出三重缓冲触发器逻辑集成电路光电二极管栅
文件：	总14页 (文件大小：79K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74LVC3G07GT [NXP]

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