PSMN1R1-50SLH [NEXPERIA]
N-channel 50 V, 1.18 mOhm, 280 A logic level MOSFET in LFPAK88 using NextPower-S3 Schottky-Plus technologyDevelopment;![PSMN1R1-50SLH](http://pdffile.icpdf.com/pdf2/p00364/img/icpdf/PSMN1R1-50SL_2227002_icpdf.jpg)
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描述: | N-channel 50 V, 1.18 mOhm, 280 A logic level MOSFET in LFPAK88 using NextPower-S3 Schottky-Plus technologyDevelopment |
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PSMN1R1-50SLH
N-channel 50 V, 1.18 mOhm, 280 A logic level MOSFET in
LFPAK88 using NextPower-S3 Schottky-Plus technology
8 January 2021
Objective data sheet
1. General description
280 Amp, logic level gate drive N-channel enhancement mode MOSFET in 175 °C LFPAK88
package using advanced TrenchMOS Superjunction technology. This product has been designed
and qualified for high performance industrial applications.
2. Features and benefits
•
280 Amp continuous current capability
•
•
LFPAK88 (8 x 8 mm) LFPAK-style low-stress exposed lead-frame for ultimate reliability,
optimum soldering and easy solder-joint inspection
Copper-clip and solder die attach for low package inductance and resistance, and high ID(max)
rating
•
•
•
•
•
Ideal replacement for D2PAK and 10 x 12 mm leadless package types
Qualified to 175 °C
Avalanche rated, 100 % tested
Low QG, QGD and QOSS for high efficiency, especially at higher switching frequencies
Superfast switching with soft body-diode recovery for low-spiking and ringing, recommended for
low EMI designs
•
•
•
Unique “SchottkyPlus” technology for Schottky-like switching performance and low IDSS leakage
Narrow VGS(th) rating for easy paralleling and improved current sharing
Very strong linear-mode / safe operating area characteristics for safe and reliable switching at
high-current conditions
3. Applications
•
•
•
•
•
Brushless DC motor control
Synchronous rectifier in high-power AC-to-DC applications, e.g. server power supplies
Battery protection and Battery Management Systems (BMS)
Load switch
10 cell lithium-ion battery applications (36 V ‒ 42 V)
4. Quick reference data
Table 1. Quick reference data
Symbol
VDS
ID
Parameter
Conditions
Min
Typ
Max
50
Unit
V
drain-source voltage
drain current
25 °C ≤ Tj ≤ 175 °C
VGS = 10 V; Tmb = 25 °C
-
-
-
-
-
-
280
375
175
A
Ptot
total power dissipation Tmb = 25 °C; Fig. 1
junction temperature
-
W
Tj
-55
°C
Static characteristics
RDSon drain-source on-state
resistance
VGS = 10 V; ID = 25 A; Tj = 25 °C
VGS = 4.5 V; ID = 25 A; Tj = 25 °C
-
-
0.97
[tbd]
1.18
[tbd]
mΩ
mΩ
Nexperia
PSMN1R1-50SLH
N-channel 50 V, 1.18 mOhm, 280 A logic level MOSFET in LFPAK88 using NextPower-S3 Schottky-Plus
technology
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Dynamic characteristics
QGD
gate-drain charge
total gate charge
ID = 25 A; VDS = 25 V; VGS = 4.5 V;
Fig. 4
-
-
20
86
[tbd]
[tbd]
nC
nC
QG(tot)
5. Pinning information
Table 2. Pinning information
Pin
1
Symbol
Description
gate
Simplified outline
Graphic symbol
G
S
S
S
D
D
S
2
source
source
source
G
3
4
mbb076
mb
mounting base; connected
to drain
1
2
3
4
LFPAK88 (SOT1235)
6. Ordering information
Table 3. Ordering information
Type number
Package
Name
Description
Version
PSMN1R1-50SLH
LFPAK88
plastic, single-ended surface-mounted package (LFPAK88); 4
leads; 2 mm pitch; 8 mm x 8 mm x 1.6 mm body
SOT1235
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDS
Parameter
Conditions
Min
Max
Unit
drain-source voltage
drain-gate voltage
gate-source voltage
total power dissipation
drain current
25 °C ≤ Tj ≤ 175 °C
25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ
-
50
V
VDGR
VGS
-
50
V
-20
20
V
Ptot
Tmb = 25 °C; Fig. 1
-
375
280
269
1524
175
175
260
W
A
ID
VGS = 10 V; Tmb = 25 °C
VGS = 10 V; Tmb = 100 °C
pulsed; tp ≤ 10 µs; Tmb = 25 °C
-
-
A
IDM
peak drain current
storage temperature
junction temperature
-
A
Tstg
Tj
-55
-55
-
°C
°C
°C
Tsld(M)
peak soldering
temperature
Source-drain diode
IS
source current
peak source current
Tmb = 25 °C
-
-
280
A
A
ISM
pulsed; tp ≤ 10 µs; Tmb = 25 °C
1524
©
PSMN1R1-50SLH
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Objective data sheet
8 January 2021
2 / 9
Nexperia
PSMN1R1-50SLH
N-channel 50 V, 1.18 mOhm, 280 A logic level MOSFET in LFPAK88 using NextPower-S3 Schottky-Plus
technology
Symbol
Avalanche ruggedness
EDS(AL)S
Parameter
Conditions
Min
Max
Unit
non-repetitive drain-
ID = 25 A; Vsup ≤ 50 V; RGS = 50 Ω;
source avalanche energy VGS = 10 V; Tj(init) = 25 °C; unclamped;
tp = 6.1 ms
[1]
[1]
-
4.9
J
IAS
non-repetitive avalanche Vsup ≤ 50 V; VGS = 10 V; Tj(init) = 25 °C;
-
[tbd]
A
current
RGS = 50 Ω
[1] Protected by 100% test
03aa16
120
P
der
(%)
80
40
0
0
50
100
150
200
T
(°C)
mb
Fig. 1. Normalized total power dissipation as a function of mounting base temperature
8. Thermal characteristics
Table 5. Thermal characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rth(j-mb)
thermal resistance from
junction to mounting
base
-
0.35
0.4
K/W
Rth(j-a)
thermal resistance from Fig. 2
-
-
35
70
-
-
K/W
K/W
junction to ambient
Fig. 3
©
PSMN1R1-50SLH
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Objective data sheet
8 January 2021
3 / 9
Nexperia
PSMN1R1-50SLH
N-channel 50 V, 1.18 mOhm, 280 A logic level MOSFET in LFPAK88 using NextPower-S3 Schottky-Plus
technology
aaa-029383
aaa-029384
Copper square 25.4 mm x 25.4 mm; 70 μm thick on
FR4 board
70 μm thick copper on FR4 board
Fig. 3. PCB layout with minimum footprint for thermal
resistance from junction to ambient
Fig. 2. PCB layout for resistance from junction to
ambient
9. Characteristics
Table 6. Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
V(BR)DSS
drain-source
breakdown voltage
ID = 250 µA; VGS = 0 V; Tj = 25 °C
ID = 250 µA; VGS = 0 V; Tj = -55 °C
50
45
1.2
-
-
V
V
V
-
-
VGS(th)
gate-source threshold ID = 1 mA; VDS=VGS; Tj = 25 °C
voltage
1.78
2.2
ΔVGS(th)/ΔT
gate-source threshold 25 °C ≤ Tj ≤ 150 °C
voltage variation with
-
[tbd]
-
mV/K
temperature
IDSS
drain leakage current
gate leakage current
VDS = 40 V; VGS = 0 V; Tj = 25 °C
VDS = 40 V; VGS = 0 V; Tj = 125 °C
VGS = 16 V; VDS = 0 V; Tj = 25 °C
VGS = -16 V; VDS = 0 V; Tj = 25 °C
VGS = 10 V; ID = 25 A; Tj = 25 °C
VGS = 10 V; ID = 25 A; Tj = 150 °C
VGS = 4.5 V; ID = 25 A; Tj = 25 °C
VGS = 4.5 V; ID = 25 A; Tj = 150 °C
f = 1 MHz; Tj = 25 °C
-
-
1
µA
µA
nA
nA
mΩ
mΩ
mΩ
mΩ
Ω
-
[tbd]
-
IGSS
-
-
100
100
1.18
[tbd]
[tbd]
[tbd]
[tbd]
-
-
RDSon
drain-source on-state
resistance
-
0.97
-
-
-
[tbd]
-
-
RG
gate resistance
[tbd]
[tbd]
Dynamic characteristics
QG(tot)
total gate charge
ID = 25 A; VDS = 25 V; VGS = 4.5 V;
Fig. 4
-
-
86
[tbd]
[tbd]
nC
nC
ID = 25 A; VDS = 25 V; VGS = 10 V;
Fig. 4
190
ID = 0 A; VDS = 0 V; VGS = 10 V
-
-
-
101
28
-
nC
nC
nC
QGS
gate-source charge
ID = 25 A; VDS = 25 V; VGS = 4.5 V;
Fig. 4
[tbd]
[tbd]
QGS(th)
pre-threshold gate-
source charge
19
QGS(th-pl)
QGD
post-threshold gate-
source charge
-
-
9
[tbd]
[tbd]
nC
nC
gate-drain charge
20
©
PSMN1R1-50SLH
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Objective data sheet
8 January 2021
4 / 9
Nexperia
PSMN1R1-50SLH
N-channel 50 V, 1.18 mOhm, 280 A logic level MOSFET in LFPAK88 using NextPower-S3 Schottky-Plus
technology
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VGS(pl)
gate-source plateau
voltage
ID = 25 A; VDS = 25 V; Fig. 4
-
[tbd]
-
V
Ciss
Coss
Crss
input capacitance
output capacitance
VDS = 25 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C
-
-
-
13338 [tbd]
1276 [tbd]
pF
pF
pF
reverse transfer
capacitance
337
[tbd]
td(on)
tr
td(off)
tf
turn-on delay time
rise time
VDS = 25 V; RL = 1 Ω; VGS = 4.5 V;
RG(ext) = 5 Ω
-
-
-
-
-
[tbd]
[tbd]
[tbd]
[tbd]
68
-
-
-
-
-
ns
ns
ns
ns
nC
turn-off delay time
fall time
Qoss
output charge
VGS = 0 V; VDS = 25 V; f = 1 MHz;
Tj = 25 °C
Source-drain diode
VSD
trr
source-drain voltage
IS = 25 A; VGS = 0 V; Tj = 25 °C
-
-
-
-
0.75
[tbd]
[tbd]
[tbd]
1
-
V
reverse recovery time IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V;
ns
nC
ns
VDS = 25 V; Fig. 5
Qr
ta
recovered charge
[1]
-
reverse recovery rise
time
-
tb
reverse recovery fall
time
-
[tbd]
-
ns
[1] includes capacitive recovery
003aal160
I
D
V
DS
(A)
I
D
t
rr
t
t
b
a
V
V
GS(pl)
GS(th)
0
0.25 I
RM
V
GS
I
Q
RM
GS2
Q
GS1
Q
Q
t (s)
GS
GD
Q
G(tot)
Fig. 5. Reverse recovery timing definition
003aaa508
Fig. 4. Gate charge waveform definitions
©
PSMN1R1-50SLH
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Objective data sheet
8 January 2021
5 / 9
Nexperia
PSMN1R1-50SLH
N-channel 50 V, 1.18 mOhm, 280 A logic level MOSFET in LFPAK88 using NextPower-S3 Schottky-Plus
technology
10. Package outline
Plastic single-ended surface-mounted package (LFPAK88); 4 leads
SOT1235
b
2
E
1
D
1
A
C
1
A
3
θ
L
y
C
detail X
A
2
A
E
c
2
mounting
base
D
H
L
2
1
2
3
4
X
e
e
e
c
b
w
A
(4x)
0
4
8 mm
scale
Dimensions (mm are the original dimensions)
(1)
(1)
(1)
(1)
(1)
Unit
A
A
A
b
b
2
c
c
2
D
D
1
E
E
e
H
L
L
2
w
y
θ
1
2
3
1
°
max 0.15 1.7
nom
1.1
7.3 0.24 0.55 6.3
7.1 0.18 0.45 6.1
5.1
4.9
8.1
7.9
6.9
6.7
8.1
7.8
0.8
1.3
0.9
8
0
mm
0.25
2.0
0.25 0.10
°
0.00 1.5
0.9
0.6
min
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
sot1235_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
17-08-02
17-08-07
SOT1235
Fig. 6. Package outline LFPAK88 (SOT1235)
©
PSMN1R1-50SLH
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Objective data sheet
8 January 2021
6 / 9
Nexperia
PSMN1R1-50SLH
N-channel 50 V, 1.18 mOhm, 280 A logic level MOSFET in LFPAK88 using NextPower-S3 Schottky-Plus
technology
11. Soldering
Footprint information for reflow soldering of LFPAK88 package
SOT1235
9.2
8.8
8.6
0.3
0.2
1.85
2.05
1.7
2.1
0.2
1.2
0.7
0.7
0.1
0.2
1.25
1.76
4.275
2.925
5.7
1.15
7.8
3.74
9.4
0.2
1.225
1.9
1.6 1.4 1.3
1.6
6.55
6.8
7
1.2
1.4
1.1
2
7.8
recommended stencil thickness: 0.125 mm
solder resist
occupied area
solder land
solder paste
Dimensions in mm
18-12-12
18-12-13
Issue date
sot1235_fr
Fig. 7. Reflow soldering footprint for LFPAK88 (SOT1235)
©
PSMN1R1-50SLH
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Objective data sheet
8 January 2021
7 / 9
Nexperia
PSMN1R1-50SLH
N-channel 50 V, 1.18 mOhm, 280 A logic level MOSFET in LFPAK88 using NextPower-S3 Schottky-Plus
technology
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
12. Legal information
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
Data sheet status
document, and as such is not complete, exhaustive or legally binding.
Document status Product
Definition
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
[1][2]
status [3]
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Nexperia product is suitable
and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Preliminary [short]
data sheet
Qualification
Production
This document contains data from
the preliminary specification.
Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Nexperia products in order to
avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Definitions
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
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Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
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Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
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Non-automotive qualified products — Unless this data sheet expressly
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In no event shall Nexperia be liable for any indirect, incidental, punitive,
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or replacement of any products or rework charges) whether or not such
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In the event that customer uses the product for design-in and use in
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customer (a) shall use the product without Nexperia’s warranty of the
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whenever customer uses the product for automotive applications beyond
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and (c) customer fully indemnifies Nexperia for any liability, damages or failed
product claims resulting from customer design and use of the product for
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Notwithstanding any damages that customer might incur for any reason
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©
PSMN1R1-50SLH
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Objective data sheet
8 January 2021
8 / 9
Nexperia
PSMN1R1-50SLH
N-channel 50 V, 1.18 mOhm, 280 A logic level MOSFET in LFPAK88 using NextPower-S3 Schottky-Plus
technology
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Applications.................................................................. 1
4. Quick reference data....................................................1
5. Pinning information......................................................2
6. Ordering information....................................................2
7. Limiting values............................................................. 2
8. Thermal characteristics............................................... 3
9. Characteristics..............................................................4
10. Package outline.......................................................... 6
11. Soldering..................................................................... 7
12. Legal information........................................................8
© Nexperia B.V. 2021. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 8 January 2021
©
PSMN1R1-50SLH
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Objective data sheet
8 January 2021
9 / 9
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PSMN1R2-25YLC - N-channel 25 V 1.3 mΩ logic level MOSFET in LFPAK using NextPower technology SOIC 4-Pin
NXP
![](http://pdffile.icpdf.com/pdf2/p00367/img/page/PSMN1R2-25YL_2243875_files/PSMN1R2-25YL_2243875_1.jpg)
![](http://pdffile.icpdf.com/pdf2/p00367/img/page/PSMN1R2-25YL_2243875_files/PSMN1R2-25YL_2243875_2.jpg)
PSMN1R2-25YLD
N-channel 25 V, 1.2 mΩ, 230 A logic level MOSFET in LFPAK56 using NextPowerS3 TechnologyProduction
NEXPERIA
![](http://pdffile.icpdf.com/pdf2/p00362/img/page/PSMN1R2-30YL_2218716_files/PSMN1R2-30YL_2218716_1.jpg)
![](http://pdffile.icpdf.com/pdf2/p00362/img/page/PSMN1R2-30YL_2218716_files/PSMN1R2-30YL_2218716_2.jpg)
PSMN1R2-30YLC
N-channel 30 V 1.25mΩ logic level MOSFET in LFPAK using NextPower technologyProduction
NEXPERIA
![](http://pdffile.icpdf.com/pdf2/p00302/img/page/PSMN1R2-30YL_1824156_files/PSMN1R2-30YL_1824156_1.jpg)
![](http://pdffile.icpdf.com/pdf2/p00302/img/page/PSMN1R2-30YL_1824156_files/PSMN1R2-30YL_1824156_2.jpg)
PSMN1R2-30YLC,115
PSMN1R2-30YLC - N-channel 30 V 1.25mΩ logic level MOSFET in LFPAK using NextPower technology SOIC 4-Pin
NXP
![](http://pdffile.icpdf.com/pdf2/p00368/img/page/PSMN1R2-30YL_2248180_files/PSMN1R2-30YL_2248180_1.jpg)
![](http://pdffile.icpdf.com/pdf2/p00368/img/page/PSMN1R2-30YL_2248180_files/PSMN1R2-30YL_2248180_2.jpg)
PSMN1R2-30YLD
N-channel 30 V, 1.2 mΩ, 250 A logic level MOSFET in LFPAK56 using NextPowerS3 TechnologyProduction
NEXPERIA
![](http://pdffile.icpdf.com/pdf2/p00364/img/page/PSMN1R2-55SL_2225884_files/PSMN1R2-55SL_2225884_1.jpg)
![](http://pdffile.icpdf.com/pdf2/p00364/img/page/PSMN1R2-55SL_2225884_files/PSMN1R2-55SL_2225884_2.jpg)
PSMN1R2-55SLH
N-channel 55 V, 1.03 mOhm, 330 A logic level Application Specific MOSFET in LFPAK88Production
NEXPERIA
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