PSMN1R2-30YLD [NEXPERIA]

N-channel 30 V, 1.2 mΩ, 250 A logic level MOSFET in LFPAK56 using NextPowerS3 TechnologyProduction;


型号：	PSMN1R2-30YLD
厂家：	Nexperia
描述：	N-channel 30 V, 1.2 mΩ, 250 A logic level MOSFET in LFPAK56 using NextPowerS3 TechnologyProduction
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PSMN1R2-30YLD

N-channel 30 V, 1.2 mΩ, 250 A logic level MOSFET in

LFPAK56 using NextPowerS3 Technology

21 December 2018

Product data sheet

1. General description

250 A logic level gate drive N-channel enhancement mode MOSFET in LFPAK56 package.

NextPowerS3 portfolio utilising Nexperia’s unique “SchottkyPlus” technology delivers high

efficiency, low spiking performance usually associated with MOSFETs with an integrated Schottky

or Schottky-like diode but without problematic high leakage current. NextPowerS3 is particularly

suited to high efficiency applications at high switching frequencies.

2. Features and benefits

•

250 A capability

•

Ultra low Q_G, Q_GDand Q_OSSfor high system efficiency, especially at higher switching

frequencies

•

Superfast switching with soft-recovery; s-factor > 1

Low spiking and ringing for low EMI designs

Unique “SchottkyPlus” technology; Schottky-like performance with < 1 µA leakage at 25 °C

Optimised for 4.5 V gate drive

Low parasitic inductance and resistance

High reliability clip bonded and solder die attach Power SO8 package; no glue, no wire bonds,

qualified to 175 °C

•

Wave solderable; exposed leads for optimal visual solder inspection

3. Applications

•

On-board DC-to-DC solutions for server and telecommunications

Secondary-side synchronous rectification in telecommunication applications

Voltage regulator modules (VRM)

Point-of-Load (POL) modules

Power delivery for V-core, ASIC, DDR, GPU, VGA and system components

Brushed and brushless motor control

Power OR-ing

4. Quick reference data

Table 1. Quick reference data

Symbol

V_DS

I_D

Parameter

Conditions

Min

Typ

Max

Unit

drain-source voltage

drain current

25 °C ≤ T_j≤ 175 °C

V_GS= 10 V; T_mb= 25 °C; Fig. 2

[1]

250

194

175

P_tot

total power dissipation T_mb= 25 °C; Fig. 1

junction temperature

T_j

-55

°C

Static characteristics

R_DSondrain-source on-state

resistance

V_GS= 4.5 V; I_D= 25 A; T_j= 25 °C;

Fig. 10

1.2

1.6

mΩ

Nexperia

PSMN1R2-30YLD

N-channel 30 V, 1.2 mΩ, 250 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_GS= 10 V; I_D= 25 A; T_j= 25 °C;

Fig. 10

0.96

1.24

mΩ

Dynamic characteristics

Q_GD

gate-drain charge

total gate charge

I_D= 25 A; V_DS= 15 V; V_GS= 4.5 V;

Fig. 12; Fig. 13

9.1

Q_G(tot)

Source-drain diode

softness factor

I_S= 25 A; dI_S/dt = -100 A/µs; V_GS= 0 V;

V_DS= 15 V; Fig. 16

0.95

[1] 250A continuous current has been successfully demonstrated during application test. Practically, the current will be limited by PCB,

thermal design and operating temperature.

5. Pinning information

Table 2. Pinning information

Symbol Description

Simplified outline

Graphic symbol

source

gate

mbb076

2 3 4

mounting base; connected to

drain

LFPAK56; Power-

SO8 (SOT669)

6. Ordering information

Table 3. Ordering information

Type number

Package

Name

Description

Version

PSMN1R2-30YLD

LFPAK56;

Power-SO8

Plastic single-ended surface-mounted package (LFPAK56;

Power-SO8); 4 leads

SOT669

7. Marking

Table 4. Marking codes

Type number

Marking code

PSMN1R2-30YLD

1D230L

8. Limiting values

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DS

Parameter

Conditions

Min

Max

Unit

drain-source voltage

drain-gate voltage

gate-source voltage

total power dissipation

25 °C ≤ T_j≤ 175 °C

25 °C ≤ T_j≤ 175 °C; R_GS= 20 kΩ

V_DGR

V_GS

-20

P_tot

T_mb= 25 °C; Fig. 1

194

PSMN1R2-30YLD

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Product data sheet

21 December 2018

2 / 13

Nexperia

PSMN1R2-30YLD

N-channel 30 V, 1.2 mΩ, 250 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology

Symbol

Parameter

Conditions

Min

Max

250

209

1181

175

260

Unit

I_D

drain current

V_GS= 10 V; T_mb= 25 °C; Fig. 2

V_GS= 10 V; T_mb= 100 °C; Fig. 2

pulsed; t_p≤ 10 µs; T_mb= 25 °C; Fig. 3

[1]

I_DM

peak drain current

storage temperature

junction temperature

T_stg

T_j

-55

°C

T_sld(M)

peak soldering

temperature

V_ESD

electrostatic discharge

voltage

HBM

1500

Source-drain diode

I_S

source current

peak source current

T_mb= 25 °C

162

I_SM

pulsed; t_p≤ 10 µs; T_mb= 25 °C

1181

Avalanche ruggedness

E_DS(AL)S

non-repetitive drain-

I_D= 25 A; V_sup≤ 30 V; R_GS= 50 Ω;

source avalanche energy V_GS= 10 V; T_j(init)= 25 °C; unclamped;

t_p= 1.97 ms

[2]

961

[1] 250A continuous current has been successfully demonstrated during application test. Practically, the current will be limited by PCB,

thermal design and operating temperature.

[2] Protected by 100% test

03na19

aaa-008639

120

300

250

200

150

100

(A)

der

(%)

(1)

100

150

200

75 100 125 150 175 200

(°C)

(1) 250A Continuous current has been successfully

demonstrate during application tests. Practically the

current will be limited by PCB, thermal design and

operation temperature.

Fig. 1. Normalized total power dissipation as a

function of mounting base temperature

Fig. 2. Continuous drain current as a function of

mounting base temperature

PSMN1R2-30YLD

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Product data sheet

21 December 2018

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Nexperia

PSMN1R2-30YLD

N-channel 30 V, 1.2 mΩ, 250 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology

aaa-011672

(A)

Limit R

= V / I

DSon

= 10 µs

100 µs

1 ms

10 ms

100 ms

-1

(V)

Fig. 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage

9. Thermal characteristics

Table 6. Thermal characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

R_th(j-mb)

thermal resistance from Fig. 4

junction to mounting

base

0.69

0.77

K/W

R_th(j-a)

thermal resistance from Fig. 5

K/W

junction to ambient

Fig. 6

125

aaa-008640

th(j-mb)

(K/W)

δ = 0.5

0.2

-1

-2

-3

0.1

0.05

0.02

single shot

δ =

-6

-5

-4

-3

-2

-1

(s)

Fig. 4. Transient thermal impedance from junction to mounting base as a function of pulse duration

PSMN1R2-30YLD

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Product data sheet

21 December 2018

4 / 13

Nexperia

PSMN1R2-30YLD

N-channel 30 V, 1.2 mΩ, 250 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology

aaa-005751

aaa-005750

Fig. 6. PCB layout for thermal resistance junction to

ambient minimum footprint;FR4 board; 2oz

copper

Fig. 5. PCB layout for thermal resistance junction to

ambient 1” square pad; FR4 Board; 2oz copper

10. Characteristics

Table 7. Characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Static characteristics

V_(BR)DSS

drain-source

breakdown voltage

I_D= 250 µA; V_GS= 0 V; T_j= 25 °C

I_D= 250 µA; V_GS= 0 V; T_j= -55 °C

1.2

V_GS(th)

gate-source threshold I_D= 2 mA; V_DS=V_GS; T_j= 25 °C

voltage

1.7

2.2

ΔV_GS(th)/ΔT

gate-source threshold 25 °C ≤ T_j≤ 150 °C

voltage variation with

-4.7

mV/K

temperature

I_DSS

drain leakage current

gate leakage current

V_DS= 24 V; V_GS= 0 V; T_j= 25 °C

V_DS= 24 V; V_GS= 0 V; T_j= 125 °C

V_GS= 16 V; V_DS= 0 V; T_j= 25 °C

V_GS= -16 V; V_DS= 0 V; T_j= 25 °C

µA

mΩ

1.9

I_GSS

100

1.6

R_DSon

drain-source on-state

resistance

V_GS= 4.5 V; I_D= 25 A; T_j= 25 °C;

Fig. 10

1.2

V_GS= 4.5 V; I_D= 25 A; T_j= 150 °C;

Fig. 10; Fig. 11

2.64

1.24

2.05

mΩ

V_GS= 10 V; I_D= 25 A; T_j= 25 °C;

Fig. 10

0.96

V_GS= 10 V; I_D= 25 A; T_j= 150 °C;

Fig. 10; Fig. 11

R_G

gate resistance

f = 1 MHz

1.15

Dynamic characteristics

Q_G(tot)

total gate charge

I_D= 25 A; V_DS= 15 V; V_GS= 10 V;

Fig. 12; Fig. 13

I_D= 25 A; V_DS= 15 V; V_GS= 4.5 V;

Fig. 12; Fig. 13

I_D= 0 A; V_DS= 0 V; V_GS= 10 V

Q_GS

gate-source charge

I_D= 25 A; V_DS= 15 V; V_GS= 4.5 V;

Fig. 12; Fig. 13

9.9

6.4

Q_GS(th)

pre-threshold gate-

source charge

PSMN1R2-30YLD

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Product data sheet

21 December 2018

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Nexperia

PSMN1R2-30YLD

N-channel 30 V, 1.2 mΩ, 250 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Q_GS(th-pl)

post-threshold gate-

source charge

3.5

Q_GD

gate-drain charge

9.1

2.5

V_GS(pl)

gate-source plateau

voltage

I_D= 25 A; V_DS= 15 V; Fig. 12; Fig. 13

C_iss

C_oss

C_rss

input capacitance

output capacitance

V_DS= 15 V; V_GS= 0 V; f = 1 MHz;

T_j= 25 °C; Fig. 14

4616

2079

293

reverse transfer

capacitance

t_d(on)

t_r

t_d(off)

t_f

turn-on delay time

rise time

V_DS= 15 V; R_L= 0.6 Ω; V_GS= 4.5 V;

R_G(ext)= 5 Ω

25.3

turn-off delay time

fall time

38.7

25.5

47.4

Q_oss

output charge

V_GS= 0 V; V_DS= 15 V; f = 1 MHz;

T_j= 25 °C

Source-drain diode

V_SD

t_rr

source-drain voltage

I_S= 25 A; V_GS= 0 V; T_j= 25 °C; Fig. 15

0.78

43.2

1.2

reverse recovery time I_S= 25 A; dI_S/dt = -100 A/µs; V_GS= 0 V;

V_DS= 15 V; Fig. 16

Q_r

t_a

recovered charge

[1]

reverse recovery rise

time

22.2

t_b

reverse recovery fall

time

softness factor

0.95

[1] includes capacitive recovery

aaa-011673

aaa-011674

200

10 V 3.5 V

DSon

(A)

(mΩ)

160

120

= 3 V

2.8 V

2.6 V

2.4 V

0.5

1.5

2.5

(V)

Fig. 7. Output characteristics; drain current as a

function of drain-source voltage; typical values

Fig. 8. Drain-source on-state resistance as a function

of gate-source voltage; typical values

PSMN1R2-30YLD

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Product data sheet

21 December 2018

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Nexperia

PSMN1R2-30YLD

N-channel 30 V, 1.2 mΩ, 250 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology

aaa-011675

aaa-011676

160

120

(mΩ)

DSon

2.8 V

3 V

(A)

3.5 V

4.5 V

150°C

T = 25°C

= 10 V

0.8

1.6

2.4

3.2

(V)

120

150

(A)

180

Fig. 9. Transfer characteristics; drain current as a

function of gate-source voltage; typical values

Fig. 10. Drain-source on-state resistance as a function

of drain current; typical values

003aal037

10 V

1.6

GS(pl)

1.2

GS(th)

= 4.5 V

0.8

0.4

GS2

GS1

G(tot)

003aaa508

Fig. 12. Gate charge waveform definitions

-60 -30

90 120 150 180

T (°C)

Fig. 11. Normalized drain-source on-state resistance

factor as a function of junction temperature

PSMN1R2-30YLD

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Product data sheet

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Nexperia

PSMN1R2-30YLD

N-channel 30 V, 1.2 mΩ, 250 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology

aaa-011677

aaa-011678

(V)

(pF)

iss

oss

24 V

15 V

= 6 V

rss

-1

(nC)

(V)

Fig. 14. Input, output and reverse transfer capacitances

as a function of drain-source voltage; typical

values

Fig. 13. Gate-source voltage as a function of gate

charge; typical values

003aal160

aaa-011679

(A)

0.25 I

150°C

T = 25°C

-1

t (s)

0.2

0.4

0.6

0.8

(V)

1.2

Fig. 16. Reverse recovery timing definition

Fig. 15. Source current as a function of source-drain

voltage; typical values

PSMN1R2-30YLD

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Product data sheet

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Nexperia

PSMN1R2-30YLD

N-channel 30 V, 1.2 mΩ, 250 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology

11. Package outline

Plastic single-ended surface-mounted package (LFPAK56; Power-SO8); 4 leads

SOT669

mounting

base

1/2 e

(A )

detail X

5 mm

scale

Dimensions (mm are the original dimensions)

(1)

Unit

max 1.20 0.15 1.10

nom

min 1.01 0.00 0.95

0.50 4.41 2.2 0.9 0.25 0.30 4.10 4.20 5.0 3.3

6.2 0.85 1.3 1.3

5.8 0.40 0.8 0.8

0.1

0.25

1.27

0.25

0.35 3.62 2.0 0.7 0.19 0.24 3.80

4.8 3.1

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

sot669_po

Issue date

11-03-25

References

Outline

version

European

projection

IEC

JEDEC

JEITA

SOT669

MO-235

13-02-27

Fig. 17. Package outline LFPAK56; Power-SO8 (SOT669)

PSMN1R2-30YLD

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Product data sheet

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Nexperia

PSMN1R2-30YLD

N-channel 30 V, 1.2 mΩ, 250 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology

12. Soldering

Footprint information for reflow soldering

SOT669

4.7

4.2

0.9

0.6

(3×)

(4×)

0.25

(2×)

0.25

(2×)

3.5

3.45

0.6

2.55

(3×)

0.25

(2×)

SR opening =

Cu + 0.075

1.1

2.15

3.3

SP opening =

Cu - 0.050

0.7

(4×)

1.27

3.81

solder paste

solder lands

125 µm stencil

occupied area

Dimensions in mm

solder resist

sot669_fr

Fig. 18. Reflow soldering footprint for LFPAK56; Power-SO8 (SOT669)

PSMN1R2-30YLD

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Product data sheet

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Nexperia

PSMN1R2-30YLD

N-channel 30 V, 1.2 mΩ, 250 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology

Wave soldering footprint information for LFPAK56 package

SOT669

4.826

1.78

1.72

2.1

1.4

0.6 (x4)

1.27

0.635

solder lands

Dimensions in mm

15-04-13

Issue date

15-04-16

sot669_fw

Fig. 19. Wave soldering footprint for LFPAK56; Power-SO8 (SOT669)

PSMN1R2-30YLD

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Product data sheet

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Nexperia

PSMN1R2-30YLD

N-channel 30 V, 1.2 mΩ, 250 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology

injury, death or severe property or environmental damage. Nexperia and its

suppliers accept no liability for inclusion and/or use of Nexperia products in

such equipment or applications and therefore such inclusion and/or use is at

the customer’s own risk.

13. Legal information

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Data sheet status

Document status Product

Definition

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. Nexperia makes no representation

or warranty that such applications will be suitable for the specified use

without further testing or modification.

[1][2]

status [3]

Objective [short]

data sheet

Development

This document contains data from

the objective specification for

product development.

Customers are responsible for the design and operation of their applications

and products using Nexperia products, and Nexperia accepts no liability for

any assistance with applications or customer product design. It is customer’s

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for the planned application and use of customer’s third party customer(s).

Customers should provide appropriate design and operating safeguards to

minimize the risks associated with their applications and products.

Preliminary [short]

data sheet

Qualification

Production

This document contains data from

the preliminary specification.

Product [short]

data sheet

This document contains the product

specification.

[1] Please consult the most recently issued document before initiating or

completing a design.

Nexperia does not accept any liability related to any default, damage, costs

or problem which is based on any weakness or default in the customer’s

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[2] The term 'short data sheet' is explained in section "Definitions".

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changed since this document was published and may differ in case of

multiple devices. The latest product status information is available on

the internet at https://www.nexperia.com.

Definitions

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

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PSMN1R2-30YLD

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Product data sheet

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Nexperia

PSMN1R2-30YLD

N-channel 30 V, 1.2 mΩ, 250 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology

Contents

1. General description......................................................1

2. Features and benefits.................................................. 1

3. Applications.................................................................. 1

4. Quick reference data....................................................1

5. Pinning information......................................................2

6. Ordering information....................................................2

7. Marking..........................................................................2

8. Limiting values............................................................. 2

9. Thermal characteristics............................................... 4

10. Characteristics............................................................5

11. Package outline.......................................................... 9

12. Soldering................................................................... 10

13. Legal information......................................................12

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 21 December 2018

PSMN1R2-30YLD

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Product data sheet

21 December 2018

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PSMN1R2-30YLD [NEXPERIA]

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PSMN1R3-80SSF

PSMN1R4-30YLD

PSMN1R4-40YLD

PSMN1R5-25MLH

PSMN1R5-25YL

PSMN1R5-25YL,115

PSMN1R5-30BLE

PSMN1R5-30BLE,118