NJU6678VAH [NJRC]
Liquid Crystal Driver, 236-Segment, CMOS, TCP;
| 型号： | NJU6678VAH |
| 厂家： | 
NEW JAPAN RADIO |
| 描述： | Liquid Crystal Driver, 236-Segment, CMOS, TCP 驱动器 CD |
| 文件： | 总45页 (文件大小：401K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NJU6678
PRELIMINARY
104-common x 132-segment
BIT MAP LCD DRIVER
GENERAL DESCRIPTION
PACKAGE OUTLINE
The NJU6678 is a bit map LCD driver to display graphics or charac-
ters. It contains 21,120 bits display data RAM, microprocessor inter-
face circuits, instruction decoder, 132-segment and 104-common driv-
ers.
The bit image display data is transferred to the display data RAM by
serial or 8-bit parallel interface.
The NJU6678 displays 104 x 132 dots graphics or 8-character 6-line
by 16 x 16 dots character.
NJU6678CL
It oscillates by built-in OSC circuit without any external components.
Furthermore, the NJU6678 features Partial Display Function which
creates up to 2 blocks of active display area and optimizes duty cycle
ratio. This function sets optimum boosted voltage by the combination
with both of programmable 5-time voltage booster circuit and 201-
step electrical variable resistor. As result, it reduces the operating cur-
rent.
The operating voltage from 2.5V to 3.3V and low operating current are
useful for small size battery operating items.
FEATURES
Direct Correspondence between Display Data RAM and LCD Pixel
Display Data RAM - 21,120 bits (1.5 times over than display size)
236 LCD Drivers - 104-common and 132-segment
Direct Microprocessor Interface for both of 68 and 80 type MPU
Serial Interface
Partial Display Function
(2 blocks of active display area and automatic duty cycle ratio selection)
Easy Vertical Scroll by the variable start line address and over size display data RAM
Programmable Bias selection ; 1/4,1/5,1/6,1/7,1/8,1/9,1/10,1/11 bias
Common Driver Order Assignment by mask option
Version
C0 to C103(Pin name)
NJU6678A Com0 to Com103
NJU6678B Com103 to Com0
Useful Instruction Set
Display Data Read/Write, Display ON/OFF Cont, Inverse Display, Page Address Set,
Display Start Line Set, Partial Display, Bias Select, Column Address Set, Status Read,
All On/Off, Voltage Booster Circuits Multiple Select(Maximum 5-time), n-Line Inverse,
Read Modify Write, Power Saving, ADC Select, etc.
Power Supply Circuits for LCD; Programmable Voltage Booster Circuits(5-time Maximum),
Regulator, Voltage Follower x 4
Precision Electrical Variable Resistance
Low Power Consumption
Operating Voltage
--- 2.5V to 3.3V
LCD Driving Voltage --- 6.0V to 17V
Mar.2000
Ver.2.1
Package Outline
--- COF / TCP / Bumped Chip
C-MOS Technology
NJU6678
PAD LOCATION
S27
S26
S104
S105
Y
S130
S131
C103
C102
S1
S0
C5 1
C5 0
X
C53
C52
C1
C0
Chip Center
Chip Size
Chip Thickness
Bump Size
Pad pitch
: X=0um,Y=0um
: X=5.36mm,Y=5.31mm
: 675um + 30um
: 45um x 83um
: 60um(Min)
Bump Height
Bump Material
: 15um TYP.
: Au
NJU6678
TERMINAL DESCRIPTION
Chip Size 5.36 x 5.31mm (Chip Center X=0um,Y=0um)
PAD No.
1
Terminal
DUMMY0
DUMMY1
DUMMY2
DUMMY3
DUMMY4
DUMMY5
DUMMY6
DUMMY7
V D D
X= um
-2250
-2190
-2130
-2070
-2010
-1950
-1890
-1830
-1747
-1666
-1596
-1487
-1417
-1347
-1238
-1168
-1049
-979
Y= um
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2497
-2370
-2310
-2250
-2190
PAD No.
5 1
5 2
5 3
5 4
5 5
5 6
5 7
5 8
5 9
6 0
6 1
6 2
6 3
6 4
6 5
6 6
6 7
6 8
6 9
7 0
7 1
7 2
7 3
7 4
7 5
7 6
7 7
7 8
7 9
8 0
8 1
8 2
8 3
8 4
8 5
8 6
8 7
8 8
8 9
9 0
9 1
9 2
9 3
9 4
9 5
9 6
9 7
9 8
9 9
100
Terminal
C 4
X= um
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
2523
Y= um
-2130
-2070
-2010
-1950
-1890
-1830
-1770
-1710
-1650
-1590
-1530
-1470
-1410
-1350
-1290
-1230
-1170
-1110
-1050
-990
-930
-870
-810
-750
-690
-630
-570
-510
-450
-390
-330
-270
-210
-150
-90
2
C 5
3
C 6
4
C 7
5
C 8
6
C 9
7
C 10
C 11
C 12
C 13
C 14
C 15
C 16
C 17
C 18
C 19
C 20
C 21
C 22
C 23
C 24
C 25
C 26
C 27
C 28
C 29
C 30
C 31
C 32
C 33
C 34
C 35
C 36
C 37
C 38
C 39
C 40
C 41
C 42
C 43
C 44
C 45
C 46
C 47
C 48
C 49
C 50
C 51
S 0
8
9
1 0
11
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 0
3 1
3 2
3 3
3 4
3 5
3 6
3 7
3 8
3 9
4 0
4 1
4 2
4 3
4 4
4 5
4 6
4 7
4 8
4 9
5 0
P/S
CEL68
RES
V SS
T2
T1
OSC 1
OSC2
C S
A0
-861
W R
-791
RD
-667
D 0
-510
D 1
-289
D 2
-69
D 3
152
D 4
372
D 5
592
D 6(SCL)
D 7(SI)
V SS
813
1033
1191
1261
1331
1401
1471
1541
1611
1681
1751
1821
1891
1961
2031
2101
2171
2241
2311
2523
2523
2523
2523
V OUT
C 4 +
C 4 -
C 3 +
C 3 -
C 2 +
C 2 -
C 1 +
C 1 -
-30
3 0
9 0
150
V R
210
V 5
270
V 4
330
V 3
390
V 2
450
V 1
510
V D D
570
C 0
630
C 1
690
C 2
750
C 3
S 1
810
NJU6678
P A D N o .
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
T erminal
X = u m
2 5 2 3
2 5 2 3
2 5 2 3
2 5 2 3
2 5 2 3
2 5 2 3
2 5 2 3
2 5 2 3
2 5 2 3
2 5 2 3
2 5 2 3
2 5 2 3
2 5 2 3
2 5 2 3
2 5 2 3
2 5 2 3
2 5 2 3
2 5 2 3
2 5 2 3
2 5 2 3
2 5 2 3
2 5 2 3
2 5 2 3
2 5 2 3
2 5 2 3
2 5 2 3
2 2 5 0
2 1 9 0
2 1 3 0
2 0 7 0
2 0 1 0
1 9 5 0
1 8 9 0
1 8 3 0
1 7 7 0
1 7 1 0
1 6 5 0
1 5 9 0
1 5 3 0
1 4 7 0
1 4 1 0
1 3 5 0
1 2 9 0
1 2 3 0
1170
1110
1 0 5 0
990
Y = u m
870
P A D N o .
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
T erminal
S 52
X = u m
Y = u m
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
S 2
S 3
S 4
S 5
S 6
S 7
810
750
930
S 53
990
S 54
690
1 0 5 0
1110
1170
1 2 3 0
1 2 9 0
1 3 5 0
1 4 1 0
1 4 7 0
1 5 3 0
1 5 9 0
1 6 5 0
1 7 1 0
1 7 7 0
1 8 3 0
1 8 9 0
1 9 5 0
2 0 1 0
2 0 7 0
2 1 3 0
2 1 9 0
2 2 5 0
2 3 1 0
2 3 7 0
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
2 4 9 7
S 55
630
S 56
570
S 57
510
8
58
S
S
450
S 9
S 59
S 60
S 61
S 62
S 63
S 64
S 65
S 66
S 67
S 68
S 69
S 70
S 71
S 72
S 73
S 74
S 75
S 76
S 77
S 78
S 79
S 80
S 81
S 82
S 83
S 84
S 85
S 86
S 87
S 88
S 89
S 90
S 91
S 92
S 93
S 94
S 95
S 96
S 97
S 98
S 99
S 100
S 101
390
S 10
S 11
S 12
S 13
S 14
S 15
S 16
S 17
S 18
S 19
S 20
S 21
S 22
S 23
S 24
S 25
S 26
S 27
S 28
S 29
S 30
S 31
S 32
S 33
S 34
S 35
S 36
S 37
S 38
S 39
S 40
S 41
S 42
S 43
S 44
S 45
S 46
S 47
S 48
S 49
S 50
S 51
330
270
210
150
9 0
3 0
- 3 0
- 9 0
-150
-210
-270
-330
-390
-450
-510
-570
-630
-690
-750
-810
-870
-930
-990
- 1 0 5 0
-1110
-1170
- 1 2 3 0
- 1 2 9 0
- 1 3 5 0
- 1 4 1 0
- 1 4 7 0
- 1 5 3 0
- 1 5 9 0
- 1 6 5 0
- 1 7 1 0
- 1 7 7 0
- 1 8 3 0
- 1 8 9 0
- 1 9 5 0
- 2 0 1 0
- 2 0 7 0
- 2 1 3 0
930
870
NJU6678
P A D N o .
201
202
203
204
205
206
207
208
209
210
211
T erminal
S 102
S 103
S 104
S 105
S 106
S 107
S 108
S 109
S 110
S 111
S 112
S 113
S 114
S 115
S 116
S 117
S 118
S 119
S 120
S 121
S 122
S 123
S 124
S 125
S 126
S 127
S 128
S 129
S 130
S 131
C 103
C 102
C 101
C 100
C 99
X = u m
- 2 1 9 0
- 2 2 5 0
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
Y = u m
2 4 9 7
2 4 9 7
2 3 7 0
2 3 1 0
2 2 5 0
2 1 9 0
2 1 3 0
2 0 7 0
2 0 1 0
1 9 5 0
1 8 9 0
1 8 3 0
1 7 7 0
1 7 1 0
1 6 5 0
1 5 9 0
1 5 3 0
1 4 7 0
1 4 1 0
1 3 5 0
1 2 9 0
1 2 3 0
1170
1110
1 0 5 0
990
P A D N o .
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
T erminal
C 83
C 82
C 81
C 80
C 79
C 78
C 77
C 76
C 75
C 74
C 73
C 72
C 71
C 70
C 69
C 68
C 67
C 66
C 65
C 64
C 63
C 62
C 61
C 60
C 59
C 58
C 57
C 56
C 55
C 54
C 53
C 52
X = u m
Y = u m
-510
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
- 2 5 2 4
-570
-630
-690
-750
-810
-870
-930
-990
- 1 0 5 0
-1110
-1170
- 1 2 3 0
- 1 2 9 0
- 1 3 5 0
- 1 4 1 0
- 1 4 7 0
- 1 5 3 0
- 1 5 9 0
- 1 6 5 0
- 1 7 1 0
- 1 7 7 0
- 1 8 3 0
- 1 8 9 0
- 1 9 5 0
- 2 0 1 0
- 2 0 7 0
- 2 1 3 0
- 2 1 9 0
- 2 2 5 0
- 2 3 1 0
- 2 3 7 0
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
930
870
810
750
690
630
570
510
450
C 98
390
C 97
330
C 96
270
C 95
210
C 94
150
C 93
9 0
C 92
3 0
C 91
- 3 0
C 90
- 9 0
C 89
-150
-210
-270
-330
-390
-450
C 88
C 87
C 86
C 85
C 84
NJU6678
BLOCK DIAGRAM
C0
C51 S0
S131 C103
C52
VSS
VDD
5
C O M
S E G
C O M
V1 to V5
D r i v e r
D r i v e r
D r i v e r
C1+
C1-
C2+
C2-
C3+
C3-
C4+
C4-
S h i f t
S h i f t
R e g i s t e r
R e g i s t e r
COM SEG
Voltage
Timing
Generator
Generator
D i s p l a y D a t a L a t c h
VR
T1,T2
Display Data RAM
160 x 132
Culumn Address Decoder
Culumn Address Counter
Display
Timing
Generator
Culumn Address Register
M u l t i p l e x e r
OSC1
OSC2
OSC.
Instruction Decoder
B F
B u s H o l d e r
S t a t u s
I n t e r n a l B u s
R e s e t
M P U I n t e r f a c e
CEL68
RD
RES
D0 to D7 (SI,SCL)
CS
WR
A0
P/S
NJU6678
TERMINAL DESCRIPTION
No.
Symbol I/O
F u n c t i o n
DUMMY0
to
1 to 8
Dummy Terminals.
These terminals are insulated.
DUMMY7
Power
VDD
9,46
VDD=+3V
13,30
VSS
GND VSS=0V
Power
45
44
43
42
41
V1
V2
V3
V4
V5
LCD Driving Voltage Supplying Terminal. When the internal voltage booster is
not used, supply each level of LCD driving voltage from outside with following
relation.
VDD>V1>V2>V3>V4>V5
When the internal power supply is on, the internal circuits generate and supply
following LCD bias voltage from V1 to V4 terminals.
Bias
V1
V2
V3
V4
1/4Bias
1/5Bias
1/6Bias
1/7Bias
1/8Bias
1/9Bias
1/10Bias
1/11Bias
V5+3/4VLCD
V5+4/5VLCD
V5+5/6VLCD
V5+6/7VLCD
V5+7/8VLCD
V5+8/9VLCD
V5+9/10V LCD
V5+2/4VLCD
V5+3/5VLCD
V5+4/6VLCD
V5+5/7VLCD
V5+6/8VLCD
V5+7/9VLCD
V5+2/4VLCD
V5+2/5VLCD
V5+2/6VLCD
V5+2/7VLCD
V5+2/8VLCD
V5+2/9VLCD
V5 +1/4VLCD
V5 +1/5VLCD
V5 +1/6VLCD
V5 +1/7VLCD
V5 +1/8VLCD
V5 +1/9VLCD
V5+8/10V LCD V5 +2/10V LCD V5+1/10V LCD
V5+2/11V LCD V5 +1/11V LCD
V5+10/11VLCD V5+9/11V LCD
(VLCD=VDD-V5)
38,39
36,37
34,35
32,33
C1+,C1-
C2+,C2-
C3+,C3-
C4+,C4-
O
Step up capacitor connecting terminals.
Voltage booster circuit (Maximum 5-time)
31
VOUT
O
I
Step up voltage output terminal. Connect the step up capacitor between this
terminal and VSS.
40
VR
Voltage adjust terminal. V5 level is adjusted by external bleeder resistance
connecting between VDD and V5 terminal.
15
14
T1
T2
I
LCD bias voltage control terminals. ( *:Don't Care)
V o l t a g e
T 1
T 2
V o l t a g e A d j .
V / F C i r .
b o o s t e r C i r .
L
H
H
*
L
A v a i l a b l e
A v a i l a b l e
A v a i l a b l e
N o t A v a i l .
A v a i l a b l e
A v a i l a b l e
A v a i l a b l e
N o t A v a i l .
N o t A v a i l .
H
22 to 29
D0 to
D7
I/O P/S="H" : Tri-state bi-directional Data I/O terminal in 8-bit parallel operation.
P/S="L" : D7=Serial data input terminal. D 6=Serial data clock signal input
(SI)
terminal.
(SCL)
Data from SI is loaded at the rising edge of SCL and latched as the
parallel
data at 8th rising edge of SCL.
19
A0
I
Connect to the Address bus of MPU. The data on the D 0 to D7 is
distinguished between Display data and Instruction by status of A0.
A0
H
L
Distin.
Display Data
Instruction
12
18
RES
CS
I
I
Reset terminal. When the RES terminal goes to "L", the initialization is
performed. Reset operation is executing during "L" state of RES.
Chip select terminal. Data Input/Output are available during CS ="L".
NJU6678
No
Symbol
RD(E)
I/O
I
F u n c t i o n
21
20
<In case of 80 Type MPU>
RD signal of 80 type MPU input terminal. Active "L"
During this signal is "L" , D0 to D7 terminals are output.
<In case of 68 Type MPU>
Enable signal of 68 type MPU input terminal. Active "H"
WR(RW)
I
<In case of 80 Type MPU>
Connect to the 80 type MPU WR signal. Actie "L".
The data on the data bus input syncronizing the rise edge of this signal.
<In case of 68 Type MPU>
The read/write control signal of 68 type MPU input terminal.
R/W
H
L
State
Read
Write
11
10
CEL68
I
I
MPU interface type selection terminal.
CEL68
State
H
L
68 Type
80 Type
P/S
serial or parallel interface selection terminal.
Chip Select Data/Command
Read/Write
serial Clock
P/S
"H"
"L"
Data
CS
CS
A
D 0 to D 7
SI(D7)
RD,WR
-
A0
Write Only SCL(D6)
RAM data and status read operation do not work in mode of
the serial interface.
In case of the serial interface (P/S="L"),RD and WR must be fixed
"H" or "L", and D0 to D5 are high impedance.
16
17
OSC1
OSC2
I
System clock input terminal for Maker testing.(This terminal should be Open)
For external clock operation, the clock shoud be input to OSC1 terminal.
47 to 98
C0 to C51
O
LCD driving signal output terminals.
Segmet output terminals:S 0 to S131
Common output terminals:C 0 to C103
Segment output terminal
The following output voltages are selected by the combination of FR and data in the
RAM.(non of the n-line inverse functions)
Output Voltage
R A M
F R
D a t a
N o r m a l
V DD
V 5
R e v e r s e
99 to 230
S0 toS131
O
H
L
V 2
H
L
V 3
H
L
V 2
V DD
V 5
V 3
Common output terminal
The following output voltages are selected by the combination of FR and status of
282 to 231
C52 to
C103
O
common.
Scan data
H
F R
H
Output Voltage
V 5
VDD
V 1
L
H
L
L
V 4
NJU6678
Functional Description
(1) Description for each blocks
(1-1) Busy Flag (BF)
While the internal circuits are operating, the busy flag (BF) is "1" and any instruction excepting for the status
read are inhibited .
The busy flag goes to “1” from D7 terminal when status read instruction is executed.
When enough cycle time over than tCYC indicated in “ BUS TIMING CHARACTERISTICS” is ensured, no
need to check the busy flag for reduction of the MPU loads.
(1-2)Display Start Line Register
The Display start Line Register is a pointer register which indicates the address in the Display Data RAM
corresponding with COM0(normally it display the top line in the LCD Panel). This register also operates for
vertical display scroll, the display page change and so on. The Display Start Line Set instruction sets the
display start address of the Display Data RAM represented in 8-bit to this register.
(1-3) Line Counter
The Line Counter generates the line address of display data RAM by the count up operation synchronizing the
common cycle after the reset operation at the status change of internal FR signal.
(1-4) Column Address Counter
The column address counter is 8-bit pre-settable counter addressing the column address of display data RAM
as shown in Fig. 1. It is incremented (+1) up to (84)H by the Display Data Read/Write instruction execution.
It stops the count up operation at (84)H, and it does not count up non existing address area over than (84)H by
the count lock function. This count lock is released by new column address set.
The column address counter is independent of the Page Register.
By the Address Inverse Instruction, the column address decoder inverse the column address of Display Data
RAM corresponding to the Segment Driver.
(1-5) Page Register
The page register gives a page address of Display Data RAM as shown in Fig. 1. When the MPU accesses
the data with the page change, the page address set instruction is required.
(1-6) Display Data RAM
Display Data RAM is the bit map RAM consisting of 21,120 bits to memorize the display data corresponding to
each pixel of LCD panel. The each bit in the Display Data RAM corresponds to the each pixel of the LCD
panel and controls the display by following bit data.
When Normal Display : On="1" , Off="0"
When Inverse Display : On="0" , Off="1"
The Display Data RAM outputs 132-bit parallel data in the area addressed by the line counter, and these data
are set into the Display Data Latch.
The access operation from MPU to the display data RAM and the data output from the display data RAM are
so controlled to operate independently that the data rewriting does not influence with any malfunctions to the
display.The relation between column address and segment output can inverse by the Address Inverse Instruc-
tion ADC as shown in Fig.1.
(1-7) Common Driver Assignment
The scanning order can be assigned by mask option as shown on Table 1.
Table 1
C O M O u t p u t s T e r m i n a l s
47
98
2 3 1
2 8 2
P A D N o .
P i n n a m e
Ver.A
C 0
C 5 1
C O M 5 1
C O M 5 2
C 1 0 3
C 5 2
C O M 5 2
C O M 5 1
C O M 0
C O M 1 0 3
C O M 1 0 3
C O M 0
Ver.B
NJU6678
F o r e x a m p l e t h e
Line
P a g e A d d r e s s
D A T A
Display Pattern
Display start line
Address
is 10 H
D 0
D 1
D 2
D 3
D 4
D 5
D 6
D 7
D 0
D 1
D 2
D 3
D 4
D 5
D 6
D 7
D 0
D 1
D 2
D 3
D 4
D 5
D 6
D 7
D 0
D 1
00
01
02
03
04
05
06
07
08
09
0 A
0 B
0C
0D
0 E
D 4 , D 3 , D 2 , D 1 , D 0
(0,0,0,0,0)
P e g e
P e g e
P e g e
0
1
2
D 4 , D 3 , D 2 , D 1 , D 0
(0,0,0,0,1)
0F
10
11
12
13
14
15
16
17
18
19
C n O u t
C 0
C 1
C 2
D 4 , D 3 , D 2 , D 1 , D 0
(0,0,0,1,0)
C 3
C 4
C 5
C 6
C 7
C 8
C 9
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
D 6
D 7
D 0
D 1
D 2
D 3
D 4
D 5
D 6
D 7
D 0
D 1
D 2
D 3
D 4
D 5
D 6
D 7
D 0
D 1
6 E
6F
70
71
72
73
74
75
76
77
78
79
7 A
7 B
7C
7D
7 E
7F
80
81
C 9 4
C 6 5
C 9 6
C 9 7
C 9 8
D 4 , D 3 , D 2 , D 1 , D 0
(0,1,1,1,0)
C 9 9
P e g e 1 4
C 1 0 0
C 1 0 1
C 1 0 2
C 1 0 3
D 4 , D 3 , D 2 , D 1 , D 0
(0,1,1,1,1)
P e g e 1 5
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
D 6
D 7
D 0
D 1
D 2
D 3
D 4
D 5
D 6
D 7
96
97
98
99
9 A
9 B
9C
9D
9 E
9F
D 4 , D 3 , D 2 , D 1 , D 0
(1,0,0,1,1)
P e g e 1 9
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
D 0= " 0 "
D 0= " 1 "
00 01 02 03 04 05 06 07 08 09
83 82 81 80 7F 7E 7D 7C 7B 7A
7A 7B 7C 7D 7E 7F 80 81 82 83
09 08 07 06 05 04 03 02 01 00
A
D
C
Column
Address
1 2 2
1 2 3
1 2 4
1 2 5
1 2 6
1 2 7
1 2 8
1 2 9
1 3 0
1 3 1
0
1
2
3
4
5
6
7
8
9
S e g m e n t O u t p u t
Fig.1 Correspondence with Display Data RAM Address
NJU6678
(1-8) Reset Circuit
Reset circuit operates the following initializations when the condition of RES terminal goes to "L" level.
Initialization
1
2
3
Display Off
Normal Display (Non-inverse display)
ADC Select : Normal (ADC Instruction D0 =”0”)
Read Modify Write Mode Off
4
5
6
Internal Power supply (Voltage Booster) circuits Off
Static Drive Off
7
Driver Output Off
8
Clear the serial interface register
9
Set the address(00)H to the Column Address Counter
Set the 1st Line in the Display Start Line Register.page (00)H to the Page Address Register
Set the page “0” to the Page Address Register
Set the EVR register to (FF)H
Set the All display(1/104 duty)
Set the Bias select(1/11 Bias)
10
11
12
13
14
15
16
Set the 5-Time Voltage Booster
Set the n line turn over register (0)H
The RES terminal should be connected to the Reset terminal of MPU for the initialization at the mean time
with MPU as shown in "MPU Interface Example". The period of reset signal requires over than 10us RES="L"
level input as shown in "Electrical Characteristics". After 1us from the rise edge of RES signal, the operation
goes to normal.
When the internal LCD power supply is not used, the external LCD power supply into the NJU6678 must be
turned on during RES = "L". Although the condition of RES="L" clear each registers and initialize as above, the
oscillation circuit and the output terminal conditions (D0 to D7) are not influenced. The initialization must be
performed using RES terminal at the power on, to prevent hung up or any incorrect operations. The reset
Instruction performs the initialization procedures from No.8 to No.16 as shown in above.
Note) The noise into the RES terminal should be eliminated to avoid the error on the application with the
careful design.
(1-9) LCD Driving
(a) LCD Driving Circuits
LCD driving circuits are consisted of 236 multiplexers which operate as 132 Segment drivers and 104 Com-
mon drivers. 104 Common drivers with the shift register scan the common display signal. The combination of
the Display data, COM scan signal and FR signal form into the LCD driving output voltage. The output wave
form is shown in the Fig. 7.
(b) Display Data Latch Circuits
Display Data Latch stores 132-bit display data temporarily which is output to LCD driver circuits at a common
cycle from Display Data RAM addressed by Line Counter. The instructions of Display On/Off, Display inverse
ON/OFF and Static Drive On/Off control only the data in Display Data Latch, therefore, the data in the Display
Data RAM is not changed.
(c) Line Counter and Latch signal of Latch Circuits
The clock to Line Counter and latch signal to the Latch Circuits are generated from the internal display clock
(CL). The line address of Display Data RAM is renewed synchronizing with display clock(CL). 132 bits display
data are latched in display latch circuits synchronizing with display clock, and then output to the LCD driving
circuits. The display data transfer to the LCD driving circuits is executed independently with RAM access by
the MPU.
(d) Display Timing Generator
Display Timing Generator generates the timing signal for the display system by combination of the master
clock CL and Driving Signal FR ( refer to Fig.2 ). The Frame Signal FR and LCD alternative signal generate
LCD driving waveform of the two frame alternative driving method or n-Line inverse driving method.
NJU6678
(e)Common Timing Generation
The common timing is generated by display clock.
-Waveform of Display Timing(without the n-line inverse functions, the line inverse register in set to 0)
103 104 1
2
3
4
5
6
7
8
101 102 103 104 1
2
3
4
5
CL
FR
VDD
V
1
C0
C1
V4
V5
VDD
V1
V4
V5
AMDATA
Sn
VDD
V
2
V
3
V
5
Fig.2
-Waveform of Display Timing(with the n-line inverse function, n=7, the line inverse register in set to 6)
103 104 1 101 102 103 104 1
2
3
4
5
6
7
8
2
3
4
5
CL
FR
VDD
V
1
C0
C1
V4
V5
VDD
V1
V4
V5
RAMDATA
Sn
VDD
V
2
V
3
V
5
Fig.3
NJU6678
(f) Oscillation Circuit
The Oscillation Circuit is a low power CR oscillator incorporating with Resistor and Capacitor. It generates
clocks for display timing signal source and voltage booster circuits. The oscillation circuit output frequency is
divided as shown in below for display clock CL.
-The relation between duty and divide
Duty
1/8
1/16
1/25
1/24
1/16
1/32
1/12
1/40
1/10
1/48,56
1/8
1/64,72
1/6
1/80,88
1/5
1/96,104
1/4
Divide
1/50
(g) Power Supply Circuit
Internal Power Supply Circuit generate the High voltage and Bias voltage for the LCD. The power Supply
Circuit consists of Voltage Booster (5-Time maximum) Circuits, Regulator Circuits, and Voltage Followers.
The internal Power Supply is designed for small size LCD panel, therefore it is not suitable for the large size
LCD panel application. If the contrast is not good in the large size LCD panel application, please supply the
external.
The suitable values of the capacitors connecting to the V1 to V5 terminals and the voltage booster circuit, and
the feedback resistors for V5 operational amplifier depend on the LCD panel. And the power consumption with
the LCD panel is depending on the display pattern. Please evaluate with actual LCD module.
The operation of internal Power Supply Circuits is controlled by the Internal Power Supply On/Off Instruction.
When the Internal Power Supply Off Instruction is executed, all of the voltage booster circuits, regulator
circuits, voltage follower circuits are turned off. In this time, the bias voltage of V1, V2, V3, V4, and V5 for the
LCD should be supplied from outside, terminals C1+, C1-, C2+, C2-, and VR should be open. The status of
internal power supply is selected by T1 and T2 terminal. Furthermore the external power supply operates with
some of internal power supply function.
Voltage
Booster
C1+,C1- to
T1
T2
Voltage Adj.
Buffer(V/F)
Ext.Pow Supply
VR Term.
4
4-
C +,C
L
H
H
L/H
L
ON
ON
ON
ON
ON
ON
-
OFF
OFF
VOUT
Open
Open
H
OFF
V5,VOUT
Open
When (T1, T2)=(H, L), C1+, C1-, C2+, C2-,C3+, C3-, C4+, C4- terminals for voltage booster circuits are open
because the voltage booster circuits doesn't operate. Therefore LCD driving voltage to the VOUT terminal
should be supplied from outside.
When (T1, T2)=(H, H), terminals for voltage booster circuits and VR are open, because the voltage booster
circuits and Voltage adjust circuits do not operate.
NJU6678
Power Supply applications
(1)External power supply operation.
(2)Internal power supply operation.
(Voltage Booster, Voltage Adj., Buffer(V/F))
Internal power supply ON (instruction) (T1,T2)=(L,L)
V
DD
V
DD
T1
T2
T1
T2
+
+
+
+
+
+
V1
V1
V2
V3
V2
V3
C1+
C1-
C2+
V4
V4
C2-
C3+
V5
V5
C3-
C4+
VOUT
VOUT
C4-
VSS
VSS
V
DD
VR
V
5
(3)External power supply operation with
Voltage Adjustment,3 Buffer(V/F)
(4)External power supply operation adjusted
Voltage to V5.
Internal power supply ON (Instruction) (T1,T2) = (H,L)
Internal power supply (Instruction) (T1,T2) =(H,H)
VDD
VDD
T1
T2
T1
T2
+
+
+
+
+
+
+
+
+
V
1
V
1
V2
V3
V
2
V
3
V4
V4
V5
V5
VOUT
VOUT
VSS
VSS
V
DD
VR
V5
: These switches should be open during the power save mode.
NJU6678
(2) Instruction
The NJU6678 distinguishes the signal on the data bus by combination of A0, RD and WR. The decode of the
instruction and execution performs depending on the internal timing only neither the external clock. In case of
serial interface, the data input as MSB first serially.
The Table. 4 shows the instruction codes of the NJU6678.
(*:Don't Care)
Table 4. Instruction Code
C o d e
I n s t r u c t i o n
D e s c r i p t i o n
A 0
0
R D
1
W R
0
D 7
1
D 6
0
D 5
1
D 4
0
D 3
1
D 2
1
D 1
1
D 0
( 1 )
( 2 )
D i s p l a y O N / O F F
0
1
L C D D i s p l a y O N / O F F
0 : O F F 1 : O N
D i s p l a y S t a r t L i n e S e t
H i g h O r d e r 4 b i t s
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
0
1
0
0
0
H i g h O r d e r
A d d r e s s
D e t e r m i n e t h e D i s p l a y L i n e o f
R A M t o t h e C O M 0 .
( S e t t h e H i g h e r o r d e r 4 b i t s )
D i s p l a y S t a r t L i n e S e t
L o w e r O r d e r 4 b i t s
L o w e r O r d e r
A d d r e s s
D e t e r m i n e t h e D i s p l a y L i n e o f
R A M t o t h e C O M 0 .
( S e t t h e L o w e r o r d e r 4 b i t s )
Hi.
( 3 )
P a g e A d d r e s s S e t
H i g h O r d e r 1 b i t s
*
*
*
S e t t h e H i g h e r o r d e r 1 b i t p a g e o f
D D R A M t o t h e P a g e A d d r e s s
R e g i s t e r
P a g e A d d r e s s S e t
L o w e r O r d e r 4 b i t s
L o w e r O r d e r
S e t t h e L o w e r o r d e r
4 b i t p a g e o f
P a g e A d d r e s s
D D R A M t o t h e P a g e A d d r e s s
R e g i s t e r
( 4 )
C o l u m n A d d r e s s S e t
H i g h O r d e r 4 b i t s
0
0
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
1
0
H i g h O r d e r
S e t t h e H i g h e r o r d e r
C o l u m n A d d r e s s t o t h e R e g .
S e t t h e L o w e r o r d e r b i t s
4 b i t s
C o l u m n A d d .
C o l u m n A d d r e s s S e t
L o w e r O r d e r 4 b i t s
L o w e r O r d e r
C o l u m n A d d .
4
C o l u m n A d d r e s s t o t h e R e g .
( 5 )
S t a t u s R e a d
S t a t u s
0
0
0
0
R e a d o u t t h e i n t e r n a l S t a t u s
( 6 )
W r i t e D i s p l a y D a t a
R e a d D i s p l a y D a t a
W r i t e D a t a
R e a d D a t a
W r i t e t h e d a t a i n t o t h e D i s p l a y
D a t a R A M
( 7 )
R e a d t h e d a t a f r o m t h e D i s p l a y
D a t a R A M
( 8 )
N o r m a l o r I n v e r s e o f
O N / O F F S e t
1
1
0
0
0
1
1
1
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
I n v e r s e t h e O N a n d O F F D i s p l a y
0 : N o r m a l 1 : I n v e r s e
( 9 )
W h o l e D i s p l a y O N
/ N o r m a l D i s p l a y
0
1
W h o l e D i s p l a y T u r n s O N
0 : N o r m a l 1 : W h o l e D i s p . O N
( 1 0 )
( 1 1 )
S u b i n s t r u c t i o n t a b l e
m o d e
0
S e t t h e S u b i n s t r u c t i o n t a b l e .
P a r t i a l D i s p l a y
1 s t B l o c k , S e t S t a r t
d i s p l a y u n i t
0
0
1
1
0
0
0
0
0
0
0
0
0
1
S t a r t d i s p l a y u n i t
S e t t h e S t a r t d i s p l a y u n i t o f 1 s t
B l o c k .
1 s t B l o c k ,
S e t T h e n u m b e r o f
d i s p l a y u n i t s
n u m b e r o f
d i s p l a y u n i t s
S e t t h e n u m b e r o f d i s p l a y u n i t s o f
1 s t B l o c k .
2 n d B l o c k , S e t S t a r t
d i s p l a y u n i t
0
0
1
1
0
0
0
0
0
0
1
1
0
1
S t a r t d i s p l a y u n i t
S e t t h e S t a r t d i s p l a y u n i t o f 2 n d
B l o c k .
2 n d B l o c k ,
S e t T h e n u m b e r o f
d i s p l a y u n i t s
n u m b e r o f
d i s p l a y u n i t s
S e t t h e n u m b e r o f d i s p l a y u n i t s o f
2 n d B l o c k .
P a r t i a l d i s p l a y o n
0
1
0
0
1
0
0
0
*
0
*
0
0
I t c o m e s o f f t h e m o d e t o s e t a n d
d i s p l a y i s e x e c u t e d .
a
( 1 2 )
( 1 3 )
( 1 4 )
n - l i n e I n v e r s e D r i v e S e t
R e g i s t e r S e t
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
0
1
1
1
0
1
h i g h e r
o r d e r
S e t t h e n u m b e r o f i n v e r s e d r i v e
l i n e .
H i g h e r o r d e r
2
b i t s
R e g i s t e r S e t
L o w e r o r d e r
L o w e r o r d e r
S e t t h e n u m b e r o f i n v e r s e d r i v e
l i n e .
4
b i t s
n - l i n e I n v e r s e D r i v e
S e t i s e x e c u t e d .
0
0
0
0
T h e e x e c u t i o n o f t h e l i n e i n v e r s e
d r i v e .
E V R R e g i s t e r S e t
E V R R e g i s t e r S e t
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
0
0
1
1
0
1
0
1
E V R D a t a
S e t t h e V 5 o u t p u t l e v e l t o t h e E V R
H i g h e r o r d e r
E V R R e g i s t e r S e t
L o w e r o r d e r b i t s
4
b i t s
H i g h e r o r d e r
r e g i s t e r . ( H i g h e r o r d e r
S e t t h e V 5 o u t p u t l e v e l t o t h e E V R
r e g i s t e r . ( L o w e r o r d e r b i t s )
4 b i t s )
E V R D a t a
4
L o w e r o r d e r
4
E V R R e g i s t e r S e t i s
e x e c u t e d .
0
0
0
0
0
1
T h e e x e c u t i o n o f t h e E V R .
E n d o f s u b i n s t r u c t i o n
t a b l e m o d e
0
0
I t e n d s t h e s e t t i n g o f s u b
i n s t r u c t i o n t a b l e .
NJU6678
(*:Don't Care)
Code
Instruction
Description
A0 RD W R D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0
(15) Bias Select
0
0
0
1
1
1
0
0
0
1
0
1
0
0
1
1
1
1
1
1
0
*
Bias
Select the bias
(8 Patterns)
Voltage Booster Circuits
Multiple Select
Boost
Multiple
(16)
0
0
0
0
Set the Booster circuits
(17) Read Modify Write
/End
0
0
1
Read Modify Write mode
D 0=0:On D0=1:End
(18) Reset
0
0
1
1
0
0
1
0
1
0
1
1
0
0
0
0
0
0
1
0
Initialize the internal Circuits
(19) Internal Power Supply
ON/OFF
0
0
1
0:Int. Power Supply OFF
1:Int. Power Supply ON
(20) LCD Driving Voltage
Set
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
1
Set LCD Driving Voltage after
the internal (external) power
supply is turned on
(21) Power Save
(Dual Command)
Set the Power Save Mode
(LCD Display OFF
+Whole Display Turns
ON)
(22) ADC Select
1
0
0
1
Set the DD RAM vs Segment
D 0=0:Normal D0=1:Inverse
NJU6678
(3) Explanation of Instruction Code
(3-1) Display On/Off
This instruction executes whole display On/Off without relationship of the data in the Display Data RAM and
internal conditions.
R/W
A 0
0
R D
1
W R
D 7
1
D 6
0
D 5
1
D 4
0
D 3
1
D 2
1
D 1
1
D 0
D
0
D 0:Display Off
1:Display On
(3-2) Display Start Line
This instruction sets the line address of Display Data RAM corresponding the COM0 terminal (the highest
position line of display in normal application). The display area is fixed automatically by number of display line
which corresponds the display duty ratio from the pointed line address as the start line. This instruction realizes
the vertical smooth scroll with extra display RAM or the page address change by dynamic line addressing. In
this time, the contents of RAM are not changed.
R/W
A 0
0
R D
1
W R
D 7
0
D 6
1
D 5
0
D 4
1
D 3
A 7
D 2
A 6
D 1
A 5
D 0
A 4
0
0
1
0
0
1
1
0
A 3
A 2
A 1
A 0
A7
0
A6
A5
A4
0
A3
0
A2
0
A1
0
A0
Line Address(HEX)
0
0
0
0
0
0
1
0
0
0
0
0
1
:
:
:
:
1
0
0
1
1
1
1
1
9F
(3-3) Page Address Set
When MPU accesses the Display Data RAM, the page address must be selected before the data writing. The
access to the Display Data RAM is available by the page and column address set (Refer the Fig. 1). The page
address change does not influence with the display.
R/W
A 0
0
R D
1
W R
D 7
0
D 6
1
D 5
0
D 4
0
D 3
*
D 2
*
D 1
*
D 0
4
0
A
0
1
0
1
1
0
0
A 3
A 2
A 1
A 0
(*:Don't Care)
A4
A3
0
A2
0
A1
0
A0
0
Page
0
0
0
1
0
0
0
1
:
:
:
:
1
0
0
1
1
19
NJU6678
(3-4) Column Address
When MPU accesses the Display Data RAM, the page address (refer(3-3) ) and column address set are
required before the data writing. The column address set requires twice address set which are higher order 4
bits address set and lower order 4 bits. When the MPU accesses the Display Data RAM sequentially, the
column address is increase one by one automatically, therefore, the MPU can access only the data sequen-
tially without address set.
After writing 1page data, page address setting is required due to page address doesn't increase automatically.
The increment of the column address is stopped at the address of (83)H automatically, and the page address is
not changed even if the column address increase to (83)H and stop. In this time the page address is not
changed.
R/W
A 0
0
R D
1
W R
D 7
0
D 6
0
D 5
0
D 4
1
D 3
A 7
D 2
A 6
D 1
A 5
D 0
A 4
Higher Order
Lower Order
0
0
1
0
0
0
0
0
A 3
A 2
A 1
A 0
A7
A6
A5
0
A4
0
A3
A2
0
A1
A0
0
Column Address(HEX)
0
0
0
0
0
0
:
0
0
0
1
0
0
0
1
:
:
:
1
0
0
0
0
0
1
1
83
(3-5) Status Read
This instruction reads out the internal status of "BUSY", “ADC", "ON/OFF" and "RESET".
R/W
A 0
0
R D
0
W R
D 7
D 6
D 5
D 4
D 3
0
D 2
0
D 1
0
D 0
0
O N / O F F
R E S E T
1
B U S Y A D C
BUSY : BUSY=1 indicate the operating or the Reset cycle.
The instruction can be input after the BUSY status change to "0".
ADC
: Indicate the output correspondence of column (segment) address and segment driver.
0 :Counterclockwise Output (Inverse) Column Address 131-n <---> Segment Driver n
1 :Clockwise Output
(Normal) Column Address n
<---> Segment Driver n
(Note) The data "0=Inverse" and "1=Normal" of ADC is inverted with the ADC select
Instruction of "1=Inverse" and "0=Normal".
ON/OFF : Indicate the whole display On/Off status.
0 : Whole Display "On
1 : Whole Display "Off"
(Note) The data "0=On" and "1=Off" of Display On/Off status read out is inverted with the
Display On/Off instruction data of "1=On" and "0=Off".
RESET : Indicate the initializing by RES signal or reset instruction.
0 :
-
1 : Initialization Period
NJU6678
(3-6) Write Display Data
This instruction writes the 8-bit data on the data bus into the Display Data RAM. The column address in-
creases "1" automatically after data writing, therefore, the MPU can write the 8-bit data into the Display Data
RAM continuously without any address setting after the start address setting.
R/W
A 0
1
R D
1
W R
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
0
W R I T E D A T A
(3-7) Read Display Data
This instruction reads out the 8-bit data from Display Data RAM addressed by the column and page address.
The column address increase "1" automatically after data reading out, therefore, the MPU can read out the 8-
bit data from the Display Data RAM without any address setting after the start address setting. One time of
dummy read must operate after column address set as the explanation in "(5-4) Access to the Display Data
RAM and Internal Register". In the serial interface mode, the display data is not read out.
R/W
A 0
1
R D
0
W R
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
1
R E A D D A T A
(3-8) Normal or Inverse On/Off Set
This instruction changes the condition of display turn on and off as normal or inverse. The contents of Display
Data RAM is not changed by this instruction execution.
R/W
A 0
0
R D
1
W R
D 7
1
D 6
0
D 5
1
D 4
0
D 3
0
D 2
1
D 1
1
D 0
D
0
D 0 : Normal
1 : Inverse
RAM data "1" correspond to "On"
RAM data "0" correspond to "On"
(3-9) Whole Display On
This instruction turns on the all pixels independent of the contents of Display Data RAM. In this time, the
contents of Display Data RAM is not changed and kept. This instruction takes precedence over the "Normal or
Inverse On/Off Set Instruction".
R/W
A 0
0
R D
1
W R
D 7
1
D 6
0
D 5
1
D 4
0
D 3
0
D 2
1
D 1
0
D 0
D
0
D 0 : Normal Display
1 : Whole Display turn on
When Whole Display On Instruction is executed in the Display Off status, the internal circuits go
to the power save mode (refer to the (s) Power Save).
NJU6678
(3-10) Sub Instruction table mode
This instruction switches the instruction table from the main to the sub. The sub instruction table contains
instructions of partial display, n-line inverse drive set and EVR register set as mentioned in (11), (12) and (13).
The instruction of sub instruction table mode must be executed before above 3 sub instructions execution. The
instruction of end of sub instruction table mode (14) switches the instruction table from the sub to the main. If
any main instructions are written in the sub instruction mode, the NJU6678 will malfunction.
R/W
A 0
0
R D
1
W R
D 7
0
D 6
1
D 5
1
D 4
1
D 3
0
D 2
0
D 1
0
D 0
0
0
-Set sub Instruction table flow is shown below:
Sub Instruction table
mode
Switches to Sub instruction table mode.
Set sub instructions.
End of Sub Instruction
table mode.
Switches to Main instruction mode.
NJU6678
(3-11) Partial Display
This instruction divides the active display area in a LCD panel to 13 units consisting of 8 commons per unit
and displays one or two blocks of active display area consisting of a unit or more. In the partial display mode,
the display duty ratio is set automatically according to the number of unit in a block or two.
Therefore, the partial display function realizes to go down the LCD driving voltage according to the display
duty ratio. As a result, the operation current of display system is much saved against the full display mode.
The display units
UNIT
UNIT
UNIT
UNIT
UNIT
UNIT
UNIT
UNIT
UNIT
UNIT
UNIT
UNIT
UNIT
0
(8 commons)
1
2
3
4
5
6
104-common
7
8
9
10
11
12
(8 commons)
132-segment
Partial display instruction
The partial display operates by the combination of instructions which area unit number of start position start
unit block in the display area and a number of display unit from start position to end as a block. The number of
block is set up to two.
R/W
A 0
0
R D
1
W R
D 7
0
D 6
0
D 5
0
D 4
0
D 3
D
D 2
D
D 1
D
D 0
D
Start display
unit
0
1st Block
2nd Block
The number of
display units
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
D
D
D
D
D
D
D
D
D
D
D
D
Start display
unit
The number of
display units
After execution of the next instruction, the display mode is changed to the
partial display and the duty is changed automatically.
Partial display
on
0
1
0
0
1
0
0
0
0
0
0
D :unit number (Hex.)
In case of full display (1/104 duty), all of units on the display are selected when the first
start unit is set to “0” (0,0,0,0) and the second number of display unit is set to “13”
(1,1,0,1). In this time, the second block settings are ignored.
Note)
In case of only one block display, the second block settings are ignored when the
second start unit is set to “0” (0,0,0,0) and the second display unit number is set to “0”
(0,0,0,0).
Keep the order of partial display instruction sequence.
Do not set over “UNIT 12” the display data in DD RAM are assigned continuously from
page 0 for all of display block, even if non-display area is existed between the first
block and the second.
NJU6678
The example of partial display setting
UNIT 0
1st Block
UNIT 1
UNIT 2
UNIT 3
UNIT 4
UNIT 5
UNIT 6
UNIT 7
UNIT 8
UNIT 9
UNIT 10
UNIT 11
UNIT 12
2nd Block
active display-block
The above partial display condition is set as follows:
1)Set sub instruction mode
R/W
A 0
0
R D
1
W R
D 7
0
D 6
1
D 5
1
D 4
1
D 3
0
D 2
0
D 1
D 0
0
Set sub instruction
mode.
0
0
2)Set partial display conditions
R/W
A 0
0
R D
1
W R
D 7
0
D 6
0
D 5
0
D 4
0
D 3
0
D 2
0
D 1
0
D 0
0
1st Block, Set start
display unit to ”0”
0
1st Block, Set the number
of display units to ”2”
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
1
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
1
0
2nd Block, Set start
display unit to ”4”
2nd Block, Set the number
of display units to ”5”
Partial display on.
In this case, 1/56 duty. (Duty=1/(number of display units x 8))
3)End sub instruction mode
R/W
A 0
0
R D
1
W R
D 7
0
D 6
1
D 5
1
D 4
1
D 3
0
D 2
0
D 1
0
D 0
1
End sub instruction
mode. Back to main
instruction mode.
0
Although the partial display instruction changes duty cycle ratio automatically and display area, LCD driving
voltage, Bias and others are not changed. Therefore, the instruction of LCD driving voltage “OFF” (D=0) must
be set before partial display operation, and the other instructions such as the n-line inverse drive set, EVR
register set, bias select and voltage booster select should be set for optimum display-contrast. The “End of sub
instruction mode” is required before these instructions in order to prevent momentary flickering.
NJU6678
-Set Partial Display flow is shown below:
Internal Power Supply OFF
Sub Instruction Table Mode
Partial Display
n-line Inverse Drive Set
EVR Register Set
End Sub Instruction Table
Mode
Bias Select
Voltage Booster Times Select
Wait Time
Internal Power Supply ON
(3-12) n-line Inverse Drive Mode
This instruction sets a line number for inversion of LCD driving signal levels between “1” and “0”. It reduces
the stripe shadow(crosstalk) and stabilizes display quality. The n-line inverse number is set according to the
result of actual LCD panel display.
The instructions must be input in order of followings. These instructions are sub instruction sets and must be
set after (3-10)Sub instruction table mode.
R/W
A 0
0
R D
1
W R
D 7
0
D 6
1
D 5
0
D 4
1
D 3
*
D 2
*
D 1
A 5
D 0
A 4
Higher order
0
0
1
0
0
1
1
0
A 3
A 2
A 1
A 0
Low order
(*:Don't Care)
A5
0
0
A4
0
0
A3
0
0
A2
0
A1
0
A0
0
Inverse line
-
0
0
1
2
:
:
:
:
1
1
1
1
1
1
64
The actual operation starts after following instruction.
R/W
A 0
0
R D
1
W R
D 7
0
D 6
1
D 5
1
D 4
1
D 3
0
D 2
0
D 1
0
D 0
0
0
NJU6678
(3-13) EVR Register Set
This instruction controls voltage adjustment circuits of internal LCD power supply and changes LCD driving
voltage “V5”. Finally, it adjusts the contrast of LCD display. By setting a data into EVR register, V5 output
voltage selects one condition out of 201-voltage conditions. The range of V5 voltage is adjusted by setting
external resistors as mentioned in "(4)(b) Voltage Adjust Circuits".
This instruction is sub instruction and it must be set after (3-10) Sub instruction table mode.
R/W
A 0
0
R D
1
W R
D 7
1
D 6
0
D 5
0
D 4
0
D 3
A 7
D 2
A 6
D 1
A 5
D 0
A 4
0
0
1
0
1
0
0
1
A 3
A 2
A 1
A 0
A7
0
A6
0
A5
1
A4
1
A3
0
A2
1
A1
A0
VLCD
1
1
Low
:
:
:
:
1
1
1
1
1
1
1
1
High
VLCD=VDD-V5
When EVR doesn't use, set the EVR register to (1,1,1,1,1,1,1,1).
The actual operation starts after following instruction.
R/W
A 0
0
R D
1
W R
D 7
1
D 6
0
D 5
1
D 4
0
D 3
0
D 2
0
D 1
0
D 0
0
0
(3-14) End of Sub instruction table mode
"End of sub instruction table mode" instruction switches instruction table from sub to main.
(11)Partial display, (12)n-line inverse drive mode, and (13)EVR are sub instruction sets on the sub instruction
table. The instruction of “END of sub instruction mode” must be set after these sub instruction sets. The
NJU6678 may occur incorrect operation if any main instructions on the main instruction table are input in mode
of sub instruction table.
R/W
A 0
0
R D
1
W R
D 7
0
D 6
1
D 5
1
D 4
1
D 3
0
D 2
0
D 1
0
D 0
1
0
NJU6678
(3-15) Bias Select
This instruction decides the value of LCD driving voltage bias ratio.
Especially, the bias should be selected for display quality in partial mode.
R/W
A 0
0
R D
1
W R
0
D 7
1
D 6
0
D 5
1
D 4
1
D 3
*
D 2
A 2
D 1
A 1
D 0
A0
(*:Don't Care)
A2
A1
0
A0
Bias
1/4
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1/5
1
1/6
1
1/7
0
1/8
0
1/9
1
1/10
1/11
1
(3-16) Voltage Booster Circuit Multiple Select
This instruction Selects a voltage boost time.
The multiple must be selected the voltage boost times according to the maximum boost times by the external
capacitors connections or less. Especially, the multiple should be selected for display quality and saving
operation current in partial display mode.
R/W
A 0
0
R D
1
W R
0
D 7
0
D 6
0
D 5
1
D 4
1
D 3
0
D 2
0
D 1
A 1
D 0
A0
Command
Booster Multiple
5times external 4times external 3times external 2times external
A1
A0
capacitors
capacitors
capacitors
capacitors
connections
connections
connections
connections
0
0
1
1
0
1
0
1
2-time
3-time
4-time
5-time
2-time
3-time
4-time
2-time
3-time
2-time
NJU6678
(3-17) Read Modify Write/End
This instruction sets the Read Modify Write Mode for the column address increment control. In mode of the
Read Modify Write, the column address increases "1" automatically when the Display Data Write Instruction is
executed, but the address does not change when the Display Data Read Instruction is executed. This status is
continued until End instruction execution. When the End instruction (D=1) is input, the column address goes
back to the start address before the Read Modify Write instruction input. This function reduces the load of
MPU for repeating the display data change in the fixed area (ex. cursor blink).
D=”1” to release the Read Modify Write mode and the column address back to the address where the read
modify write mode setting.
R/W
A 0
0
R D
1
W R
D 7
1
D 6
1
D 5
1
D 4
0
D 3
0
D 2
0
D 1
0
D 0
D
0
D 0 : Read Modify Write On
1 : End
Note) In mode of the Read Modify Write, any instructions except for Column Address Set can
execute.
- Sequence of cursor blink display
P a g e A d d r e s s S e t
Set to the Start
Address of Cursor
Display
C o l u m n A d d r e s s S e t
Start the
Read Modify Write
Read Modify Write
D u m m y R e a d
D a t a R e a d
R e a d t h e D a t a a s d u m m y
D a t a i n v e r s e b y M P U
D a t a W r i t e
D u m m y R e a d
D a t a R e a d
D a t a W r i t e
End the
E n d
Read Modify Write
N O
Finish?
Y E S
NJU6678
(3-18) Reset
This instruction executes the following initialization.
Initialization
(1) Set the Address (00)H into the Column Address Counter.
(2) Set the Address (00)H into the Display Start Line Register.
(3) Set the page "0" into the Page Address Register.
(4) Set 0 to the EVR Register to (FF)H.
(5) Set the All display(1/104 duty)
(6) Set the Bias select(1/11 Bias)
(7) Set the 5-Time Voltage Booster.
(8) Set the n-line inverse register (0)H
In this time, the Display Data RAM is not influenced.
R/W
A 0
0
R D
1
W R
D 7
1
D 6
1
D 5
1
D 4
0
D 3
0
D 2
0
D 1
1
D 0
0
0
The reset signal input to the RES terminal (hardware reset) must be input for the power on initialization. Reset
instruction does not perform completely in stead of hardware reset using the RES terminal.
(3-19) Internal Power Supply ON/OFF
This instruction set the condition of internal Power Supply On/Off. Voltage Booster circuits, Voltage Regulator
and Voltage Follower operate at On. To operate the voltage booster circuits, the oscillation circuits must be
operating.
R/W
A 0
0
R D
1
W R
D 7
0
D 6
0
D 5
1
D 4
0
D 3
0
D 2
0
D 1
0
D 0
D
0
D 0 : Internal Power Supply Off
1 : Internal Power Supply On
The internal Power Supply must be Off when external power supply using.
*1 The set up period of internal power supply On depends on the step up capacitors, voltage stabilizer
capacitors, VDD and VLCD.
Therefore it requires the actual evaluation using the LCD module to get the correct time. (Refer to the
(4)(d) Fig.4)
NJU6678
(3-20) LCD Driving Voltage Set
This instruction controls LCD driving waveform output through the COM/SEG terminals.
R/W
A 0
0
R D
1
W R
D 7
0
D 6
0
D 5
1
D 4
0
D 3
0
D 2
0
D 1
1
D 0
0
D
D 0 : LCD driving waveform output Off
1 : LCD driving waveform output On
The NJU6678 contains low power LCD driving voltage generator circuit reducing own operation current.
Therefore, it requires the following sequence procedures at power on for the power source stabilized operation.
- LCD driving power supply ON/OFF sequences
The following sequences are required when the power supply is turned On/Off.
When the power supply is turned on again after the turn off (by the power save instruction), the power save
release sequence ((3-21) Power Save) is required.
Turn ON sequence
Turn OFF sequence
Display OFF
Output Assign. Register Set
EVR Register Set
Whole Display ON
Internal Power Supply OFF
or
Internal Power Supply ON
or
External Power Supply OFF
External Power supply ON
LCD Driving Voltage
Set to OFF
(Wait Time) *1
LCD Driving Voltage
Set to ON
*1 The wait time depends on the C1 to C9, COUT capacitors (refer (4) (d)Fig.4), VDD and VLCD voltage.
Therefore it requires the actual evaluation using the LCD module to get the correct time. (Refer to the
following graph.)
The wait time [Typical performance]
100
80
60
40
T.B.D.
20
Cout=1 to 4.7[uF]
0
0
0.2
0.4
0.6
0.8
1
1.2
C3 to C7[uF]
VDD=2.7V,VLCD=7V,Ta=25C
NJU6678
(3-21) Power Save(Dual Command)
When both of Display Off and Whole Display On are executed, the internal circuits go to the power save mode
and the operating current is reduced as some as the stand by current.
The internal status in the Power Save Mode is shown in follows;
(1) Stop the Oscillation Circuits and Internal Power Supply Circuits operation.
(2) Stop the LCD driving. Segment and Common drivers output VDD level.
(3) Keep the display data and operating mode just before the power save mode.
(4) All of LCD driving bias voltage fix to the VDD level.
The power save and its release perform according to the following sequences.
Power Save Sequence
Power Save Release Sequence
D i s p l a y O F F
Normal Display
(Whole Display OFF)
W h o l e D i s p l a y O N
Display ON
(Wait Time)
LCD Driving Voltage
Set to OFF
LCD Driving Voltage
Set to ON
*1 In the power save sequence, the power save mode is started after the second instruction "whole Display
ON".
*2 In the power save release sequence, the power save mode is released after the Normal Display instruction
(Whole display OFF).
The instruction of display ON is input at any timing after the instruction of normal display in power save
release sequence.
*3 Until "LCD driving voltage set to ON" execution, NJU6678 operating current is higher than usual state and
all COM/SEG terminals output VDD level continuously.
*4 In case of the external power supply for LCD driving, it should be turned off and made condition like as
unconnection or connected to VDD before the power save mode or at the same time. In this time, VOUT
terminal should be made condition like as disconnection or connected to the lowest voltage of the system
(V5 level from the external power supply).
(3-22) ADC Select
This instruction set the correspondence of column address in the Display Data RAM and segment driver
output. (See Fig. 1.) By this instruction, the order of segment output can be changed by the software, and no
restriction of the LSI placement against the LCD panel.
R/W
A 0
0
R D
1
W R
D 7
1
D 6
0
D 5
1
D 4
0
D 3
0
D 2
0
D 1
0
D 0
D
0
D 0 : Clockwise Output (Normal)
1 : Counterclockwise Output (Inverse)
NJU6678
(4) Internal Power Supply
(a) 5-time voltage booster circuits
5-time voltage booster circuits connecting five capacitors between C1+ and C1-, C2+ and C2-, C3+ and C3-, C4+
and C4-, VSS and VOUT boost the voltage of VDD - VSS to negative voltage (VDD Common) and output the
boosted voltage from the VOUT terminal. It selects one of boost time from 2 to 5 times by external capacitors
connection. Furthermore, it also selects one of boost time by ”Voltage Booster circuits multiple select” instruc-
tion. The boost voltage and the voltage booster circuits are shown in below. Voltage Booster circuits requires
the clock signals from internal oscillation circuit, therefore, the oscillation circuits must be operating when
voltage boost operation. The boost voltage times are shown in below. When 5-time voltage boost operation,
the operation voltage of VDD-VOUT should be less than 17V.
VDD=+3V
VSS=+0V
VOUT=-VDD=-3V
VOUT=-2VDD=-6V
VOUT=-3VDD=-9V
VOUT=-4VDD=-12V
2-time voltage
3-time voltage
4-time voltage
4-time voltage
5-time voltage
Examples for connecting the capacitors
5-time voltage
VSS
+
VSS
+
C1
C1
+
+
+
C1
+
+
+
C1
-
-
C2
C2
C3+
C3
C4
C4
+
C2
C2
C3+
C3
C4
C4
+
+
+
-
-
-
-
+
+
+
-
-
VOUT
VOUT
3-time voltage
2-time voltage
VSS
+
VSS
+
C1
C1
+
+
C1
+
C1
-
-
C2
C2
C3+
C3
C4
C4
+
C2
C2
C3+
C3
C4
C4
+
+
+
-
-
-
-
+
+
-
-
VOUT
VOUT
NJU6678
(b)Voltage Adjust Circuits
The boosted voltage of VOUT output from V5 through the voltage adjust circuits for LCD driving. The output
voltage of V5 is adjusted by changing the Ra and Rb within the range of | V5 | < | VOUT |. The output voltage
is calculated by the following formula.
VLCD = VDD-V5 = (1+Rb/Ra)VREG
(1)
VDD
VREG
Ra
R1
R2
VR
V
5
R3
Rb
Fig. 3
The voltage of VREG is a standard voltage produced from built-in bleeder resistance. VREG is possible to be
fine-adjusted by EVR functions mentioned in (c).
For fine-adjustment of V5, R2 as variable resistor, R1 and R3 as fixed constant should be connected to VDD
terminal, VR and V5, as shown in Fig.3.
[ Design example for R1, R2 and R3 / Reference ]
- R1+R2+R3=5MW• (Determined by the current flown between VDD-V5)
- Variable voltage range by the R2. -6V to -7.5V (VLCD=VDD-V5 --> 9.0V to 10.5V)
(Determined by the LCD electrical characteristics)
- VREG=3V(In case of EVR=(FF)H)
- R1, R2 and R3 are calculated by above conditions and the formula of (1) to below;
R1=2.0MW, R2=0.5MW, R3=2.5MW
* If the power supply voltage between VDD and VSS changes, V5 changes too. Therefore the power supply
voltage should be stabilized for V5 stable operation.
NJU6678
(c) Contrast Adjustment by the EVR function
The EVR controls voltage of VREG by instruction and changes voltage of V5.
As result, LCD display contrast is adjusted by V5. The EVR selects a voltage of VREG in the following 201
conditions by setting 6bits data into the EVR register.
In case of EVR operation, T1 terminal and T2 require to set couples of value as (L,L),(L,H) and (H,L) excepting
for (H,H) and the internal power supply must turn on by instruction.
(37)H to (4F)H available for use. If keeping 3% precision set EVR over (4F)H.
EVR register
V REG[V]
V LCD
Low
:
:
:
:
:
:
:
:
:
:
:
:
(4F)H
(0,1,0,0,1,1,1,1)
(124/300) x (VDD -VSS)
:
:
:
:
:
:
(FD)H
(FE)H
(FF)H
(1,1,1,1,1,1,0,1)
(1,1,1,1,1,1,1,0)
(1,1,1,1,1,1,1,1)
(298/300) x (VDD -VSS)
(299/300) x (VDD -VSS)
(300/300) x (VDD -VSS)
High
Adjustable range of the LCD driving voltage by EVR function
The adjustable range is decided by the power supply voltage VDD and the ratio of external resistors
Ra and Rb.
[ Design example for the adjustable range / Reference ]
- Condition VDD=3.0V, VSS=0V
Ra=1MW, Rb=4MW ( Ra:Rb=1:4 )
The adjustable range and the step voltage are calculated as follows in the above condition.
In case of setting (4F)H in the EVR register,
VLCD = ((Ra+Rb)/Ra)VREG
= (5/1) x [(124/300) x 3.0]
= 6.2V
In case of setting (FF)H in the EVR register,
VLCD = ((Ra+Rb)/Ra)VREG
= (5/1) x [(300/300) x 3.0]
= 15.0V
Min.(4F)H
6.2 - - - - - - - - - - - - - - - - - - -
50
Max.(FF)H
15.0 [V]
Adjustable Range
Step Voltagre
[mV]
* In case of VDD=3V
NJU6678
*) The VLCD operating temperature. Please refer to the following graphs.
(conditions) VDD = 3V
Ra=1MW, Rb=4MW ( Ra:Rb = 1:4 )
Five times voltage
VLCD vs. Temperature (Typical Performance)
16
14
12
VLCD
EVR=(FF)H
T.B.D.
10
8
6
4
2
0
VLCD
EVR=(4F)H
-30 -20 -10
0
10 20 30 40 50 60 70 80
o
Ta [ C]
NJU6678
(d) LCD Driving Voltage Generation Circuits
The LCD driving bias voltage of V1,V2,V3,V4 are generated internally by dividing the V5 voltage with the
internal bleeder resistance. And it is supplied to the LCD driving circuits after the impedance conversion with
voltage follower circuit.
As shown in Fig. 4, Five capacitors are required to connect to each LCD driving voltage terminal for voltage
stabilizing. And the value of capacitors C5, C6, C7, C8 and C9 are determined depending on the actual LCD
panel display evaluation.
Using the internal Power Supply
Using the external Power Supply
VSS
VSS
C1+
C1-
C1+
+
C1
C1-
C2+
C2-
C3+
C3-
C4+
+
C
OUT
C2+
+
C2
C2-
C3+
C3-
+
+
C3
C4+
C4
C4-
C4-
VOUT
VOUT
NJU6678
NJU6678
R3
V5
VR
V5
R2
VR
R1
VDD
VDD
V1
C5
C6
+
+
V1
V2
V3
V4
V5
External
V2
V3
V4
V5
C7
C8
+
+
+
Voltage
Generator
C9
Reference set up value
VLCD=VDD-V5 = 9.0 to 10.5V
COUT
C1 to C4, C9
C5 to C8
R1
to 1uF
to 1uF
0.1 to 0.47uF
2.0MW
R2
0.5MW
R3
2.5MW
Fig.4
*1 Short wiring or sealed wiring to the VR terminal is required due to the high impedance of VR terminal.
*2 Following connection of VOUT is required when external power supply using.
When VSS > V5 --- VOUT=V5
When VSS < V5 --- VOUT=VSS
NJU6678
(5) MPU Interface
(5-1) Interface type selection
NJU6678 interfaces with MPU by 8-bit bidirectional data bus (D7 to D0) or serial (SI:D7). The 8 bit parallel or
serial interface is determined by a condition of the P/S terminal connecting to "H" or "L" level as shown in
Table 5. In case of the serial interface, status and RAM data read out operation is impossible.
Table 5
P/S
H
Type
Parallel
Serial
CS
CS
CS
A0
A0
A0
RD
RD
-
WR
WR
-
CEL68
CEL68
-
D7
D7
SI
D6
D6
D0 to D5
D0 to D5
Hi-Z
L
SCL
(5-2) Parallel Interface
The NJU6678 interfaces to 68 or 80 type MPU directly when the parallel interface (P/S="H") is selected.
68 type MPU or 80 is determined by the condition of CEL68 terminal connecting to "H" or "L" as shown in
table 6.
Table 6
CEL68
Type
CS
CS
CS
A0
A0
A0
RD
E
WR
R/W
WR
D0 to D7
D0 to D7
D0 to D7
H
L
68 type MPU
80 type MPU
RD
(5-3) Discrimination of Data Bus Signal
The NJU6678 discriminates the mean of signal on the data bus by the combination of A0, E, R/W, and
(RD,WR) signals as shown in Table 7.
Table 7
Common
68 type
80 type
Function
Read Display Data
A0
1
R/W
RD
0
W R
1
1
0
1
0
1
1
0
Write Display Data
0
0
1
Status Read
0
1
0
Write into the Register(Instruction)
(5-4) Serial Interface.(P/S="L")
Serial interface circuits consist of 8 bits shift register and 3 bits counter. SI and SCL input are activated when
the chip select terminal CS set to "L"and P/S terminal set to "L". The 8 bits shift register and 3 bits counter are
reset to the initial condition when the chip is not selected. The data input from SI terminal is MSB first like as
the order of D7,D6,- - - - D0, and the data are entered into the shift register synchronizing with the rise edge of
the serial clock SCL. The data in the shift register are converted to parallel data at the 8th serial clock rise
edge input. Discrimination of the display data or instruction of the serial input data is executed by the condi-
tion of A0 at the 8th serial clock rise edge. A0="H" is display data and A0="L" is instruction. When RES
terminal becomes "L" or CS terminal becomes "H" before 8th serial clock rise edge, NJU6678 recognizes
them as a instruction data incorrectly. Therefore a unit of serial data must be structured by 8-bit. The time
chart for the serial interface is shown in Fig. 5. To avoid the noise trouble, the short wiring is required for the
SCL input.
Note) The read out function, such as the status or RAM data read out, is not supported in this serial interface
.CS
SI
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
1
2
3
4
5
6
7
8
9
10
SCL
A0
Fig. 5
NJU6678
(5-5) Access to the Display Data RAM and Internal Register.
The NJU6678 is operating as one of pipe-line processor by the bus-holder connecting to the internal data bus
to adjust the operation frequency between MPU and the Display Data RAM or Internal Register.
For example, when the MPU reads out the data from the Display Data RAM, the read out data in the data read
cycle (dummy read) is held in the bus-holder, then it is read out from the bus-holder to the system bus at the
next data read cycle. When the MPU writes the data into the Display Data RAM, the data is held in the bus-
holder, then it is written into the Display Data RAM by the next data write cycle.
Therefore high speed data transmission between MPU and NJU6678 is available because of it is not limited by
the tACC and tDS as display data RAM access time and is limited by the system cycle time (R) or (W).
If the cycle time is not be kept in the MPU operation, NOP should be inserted to the system instead of the
waiting operation.
The read out operation does not read out the data in the pointed address just after the address set operation.
And second read out operation can read out the data correctly from the pointed address.
Therefore, one dummy read operation is required after address setting or write cycle as shown in FIG. 6.
Write Operation
MPU
WR
DATA
N
N+1
N+2
N+3
Internal
Timing
I/OBuffer
WR
N+1
N+2
N+3
N
Read Operation
MPU
WR
RD
N
n
n+1
DATA
N
Address Set N
Data Read n
Data Read n+1
Dummy Read
Internal
Timing
WR
RD
Column Address
I/O Buffer
N+1
N+2
n+1
N
n
N
n+2
Fig.6
(5-6) Chip Select
CS is Chip Select terminal. In case of CS="L", the interface with MPU is available. In case of CS=”H”, the D0
to D7 are high impedance and A0, RD, WR, D7(SI) and D6(SCL) inputs are ignored. If the serial interface is
selected when CS=”H”,the shift register and the counter are reset. However, the reset is always operated in
any conditions of CS.
NJU6678
ABSOLUTE MAXIMUM RATINGS
P A R A M E T E R
(Ta=25°C)
SYMBOL
VDD
R A T I N G S
-0.3 to +5.0
UNIT
Supply Voltage (1)
V
Supply Voltage (2)
Supply Voltage (3)
Input Voltage
V5
V1 to V4
VIN
VDD-17.0 to VDD+0.3
V5 to VDD+0.3
V
V
-0.3 to VDD+0.3
-30 to +80
V
Operating Temperature
Topr
°C
-55 to +125 (Chip)
-55 to +100 (TCP)
Storage Temperature
T stg
°C
Note 1) If the LSI are used on condition above the absolute maximum ratings, the LSI may be destroyed.
Using the LSI within electrical characteristics is strongly recommended for normal operation. Use
beyond the electric characteristics conditions will cause malfunction and poor reliability.
Note 2) All voltage values are specified as VSS=0 V.
Note 3) The relation : VDD > V1 > V2 > V3 > V4 > V5 ; VDD > VSS > VOUT must be maintained.
Note 4) Decoupling capacitor should be connected between VDD and VSS due to the stabilized operation for
the voltage converter.
ELECTRICAL CHARACTERISTICS (1)
(VDD=2.5V to 3.3V, VSS=0V, Ta=-30 to +80°C)
SYMB-
Note
5
P A R A M E T E
OL
C O N D I T I O N S
MIN.
2.5
TYP.
MAX.
UNIT
V
Operating Voltage(1)
V DD
V5
3.3
VDD -17.0
VDD-0.5VLCD
V 5
VDD -6.0
OperatingVoltage(2)
V
V 1,V 2 VLCD = VDD -V5
V DD
VDD-0.5VLCD
V 3,V 4
High Level
Low Level
V IHC1 D0...D7,A0, CS,RES,RD,WR,CEL68,
0.8VDD
V SS
V DD
0.2VDD
V DD
V
V
V
V
Input
Voltage
P/S Terminals
VILC1
High Level VOHC11 D0...D7
Terminals
IOH=-0.5mA
IOL= 0.5mA
0.8VDD
V SS
Output
Voltage
Low Level VOLC11
0.2VDD
All Input terminals
Input Leakage
ILIO
- 1.0
1.0
uA
6
7
Current
RON1
RON2
IDDQ
VLCD =15.0V
VLCD =8.0V
2.0
3.0
0.05
15
3.0
4.5
5
Ta=25°C
Driver On-resistance
Stand-by Current
Operating Current
kW
uA
uA
during Power save Mode
8
9
IDD12 Display V LCD=12.0V
40
800
IDD21 Accessing f CYC =200kHz
600
NJU6678
SYMBOL
CIN
Note
P A R A M E T E R
C O N D I T I O N S
MIN
TYP
10
MAX
UNIT
A0,CS,RES,RD,WR,CEL68,
P/S,T1,T2,D 0...D 7
Input Terminal
Capacitance
pF
Ta=25°C
Oscillation Frequency
Output Volt.
fOSC
26
32
38
kHz
V
Ta=25°C
V SS-Vout, 5-time voltage booster,
V D D=3V
V OUT1
VD D-15.0V
V D D-14.5V
V D D=3V;COUT=4.7uF
5-time voltage booster
On-resistance
RTRI
VOUT2
V5
2000
4000
W
V
Adjustment
range of
LCD
Voltage Booster Circuit "OFF"
VD D-17.0V
VD D-17.0V
VD D-6.0V
Voltage
10
Driving Volt.
Booster
Voltage
Voltage Adjustment Circuit "OFF"
VD D-6.0V
V
Follower
V D D=3V, VLCD =12V
COM/SEG Terminals Open
No Access
IOUT1
IOUT2
160
35
320
70
50
3
Operating
Current
uA
%
11
12
IOUT3
25
Display Checkered pattern
Voltage Reg.
V REG%
V D D=3V,Ta=25°C, V REG=4F to FFH
Note 5) NJU6678 can operate wide operating range, but it is not guarantee immediate voltage changing during
the accessing of the MPU.
Note 6) Apply to the High-impedance state of the D0 to D7 terminals.
Note 7) RON is the resistance values between power supply terminals(V1, V2, V3, V4) and each output
terminals of common and segment supplied by 0.1V. This is specified within the range of supply
voltage (2).
Note 8,9,11) Apply to current after "LCD Driving Voltage Set".
Note 8) Apply to the external display clock operation in no access from the MPU and no use internal power
supply circuits.
Note 9) Apply to the condition of cyclic (tcyc) inverted data input continuously in no use internal power supply
circuits. The operating current during the accessing is proportionate to the access frequency. In the no
accessing period, it is as same as IDD1X.
Note 10) LCD driving voltage V5 can be adjusted within the voltage follower operating range.
Note 11) Each operating current of voltage supply circuits block is specified under below table conditions.
Status
Operating Condition
External
SYMBOL
Voltage Supply
(Input Terminal)
Internal
Voltage
Voltage
Voltage
T1
T2
Oscillator
Booster
Validity
Adjustment
Follower
IOUT1
IOUT2
IOUT3
L
*
L
Validity
Validity
Validity
Validity
Validity
Validity
Validity
Validity
Unuse
H
H
Invalidity
Invalidity
Use(V OUT)
Use(V OUT,V5)
H
Invalidity
(* = Don’t Care)
Note 12) Apply to the precision of the voltage between VDD and V5 with EVR function.
NJU6678
MEASUREMENT BLOCK DIAGRAM
:IOUT1
VR
V5
VDD
T1
A
NJU6678
T2
C1-C2+ C2- C3+ C3-C4+ C4- VOUT
VSS C1+
+
+
+
+
+
:IOUT2
VR
V5
VDD
T1
T2
A
NJU6678
VOUT
VSS C1+ C1- C2+ C2- C3+ C3-C4+ C4-
:IOUT3
VR
V5
VDD
T1
T2
A
NJU6678
VOUT
VSS C1+ C1- C2+ C2- C3+ C3-C4+ C4-
ELECTRICAL CHARACTERISTICS (2)
(VDD=2.5V to 3.3V, VSS=0V, Ta=-30 to +80°C)
P A R A M E T E R
Reset time
SYMBOL
tR
C O N D I T I O N S
RES Terminal
MIN
1.0
TYP
MAX
UNIT Note
us
13
Reset "L" Level Pulse
tRW
RES Terminal
10
us
14
Width
Note 13) Specified from the rising edge of RES to finish the internal circuit reset.
Note 14) Specified minimum pulse width of RES signal. Over than tRW "L" input should be required for correct
reset operation.
NJU6678
BUS TIMING CHARACTERISTICS
- Read/Write operation sequence (80 Type MPU)
tCYC8
A0,CS
t
AW8
tAH8
tCCL
WR,RD
tCCH
tDH8
tDS8
0 toD
(Write)
7
tf
tr
tACC
tCH8
D0 toD
(Read)
7
(VDD=2.5V to 3.3V,Ta=-30 to +80°C)
SYMBO-
L
P A R A M E T E R
MIN.
TYP.
MAX.
CONDITION UNIT
Address Hold Time
Address Set Up Time
System Cycle WR
tAH8
tAW8
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
A0,CS
Terminals
tCYC8 (W)
tCYC8 (R)
tCCL(W)
tCCL(R)
tCCH(W)
tCCH(R)
tDS8
270
350
50
200
220
150
35
220
Time
RD
WR,"L"
WR,RD
RD,"L" Terminals
WR,"H"
Control
Pulse Width
160
RD,"H"
Data Set Up Time
Data Hold Time
tDH8
15
D0 to D7
Terminals
RD Access Time
Output Disable Time
tACC8
120
50
ns
CL=100pF
ns
tCH8
0
CS, WR, RD,
A0, D0 to D7
Terminals
Rise Time, Fall Time
tr,tf
15
ns
Note 15) Rise time (tr) and fall time (tf) of input signal should be less than 15ns.
Note 16) Each timing is specified based on 0.2xVDD and 0.8xVDD.
NJU6678
- Read/Write operation sequence (68 Type MPU)
tCYC6
tEWL
E
tAW6
tEWH
t
f
R/W
tr
tAH6
A0,CS
tDH6
tDS6
D0 to D
(Write)
7
tOH6
tACC6
D0 toD7
(Read)
(VDD=2.5V to 3.3V,Ta=-30 to +80°C)
SYMBOL
CONDITION
P A R A M E T E R
MIN.
10
TYP.
MAX.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Hold Time
Address Set Up Time
System Cycle Time(W)
tAH6
tAW6
0
A0,CS,R/W
Terminals
tCYC6(W)
tCYC6(R)
270
350
200
50
220
System Cycle Time(R)
Read"H"
tEWH
tEWL
Write"H"
Enable
E Terminal
Pulse Width
Read"L"
Write"L"
220
150
35
160
Data Set Up Time
Data Hold Time
Access Time
tDS6
tDH6
15
D0 to D7
Terminals
tACC6
tOH6
200
50
CL=100pF
Output Disable Time
0
A0, CS, R/W,
E, D0 to D7
Terminals
Rise Time, Fall Time
tr,tf
15
ns
Note 17) tCYC6 indicates the E signal cycle during the CS activation period. The System Cycle Time must be
required after CS becomes active.
Note 18) Rise time (tr) and fall time (tf) of input signal should be less than 15ns.
Note 19) Each timing is specified based on 0.2xVDD and 0.8xVDD.
NJU6678
- Write operation sequence (Serial Interface)
t
CSS
tCSH
CS
A0
tSAS
tSAH
tSCYC
t
SLW
SCL
SI
t
SHW
tSDS
tSDH
tf
tr
(VDD=2.5V to 3.3V,Ta=-30 to +80°C)
P A R A M E T E R
SYMBOL
tSCYC
tSHW
tSLW
MIN.
120
40
TYP.
MAX.
CONDITION UNIT
Serial Clock cycle
SCL "H" pulse width
SCL "L" pulse width
Address Set Up Time
Address Hold Time
Data Set Up Time
Data Hold Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCL
Terminal
80
tSAS
0
A0 Terminal
SI Terminal
CS Terminal
tSAH
150
25
tSDS
tSDH
10
tCSS
10
CS-SCL Time
tCSH
300
SCL, A0,
CS, SI
Rise Time, Fall Time
tr,tf
15
ns
Terminals
Note 20) Rise time (tr) and fall time (tf) of input signal should be less than 15ns.
Note 21) Each timing is specified based on 0.2xVDD and 0.8xVDD.
Note 22) In case of instruction set continuously, it is required to wait more than 450ns between the instruction
and next as follows.
SCL 8th clock
SCL 1st clock
SCL
450 ns
SCL"L"pulse width
(Between the
Instruction N+1
Instruction N
instruction and next)
NJU6678
LCD DRIVING WAVEFORM
103
102
102
103
0
1
2
3
4
0
1 2 3 4 5
VDD
FR
VSS
VDD
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
V1
V2
V3
V4
V5
COM0
VDD
V1
V2
V3
V4
V5
COM1
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
VDD
V1
V2
V3
V4
V5
COM2
VDD
V1
V2
V3
V4
V5
SEG
0
VDD
V1
V2
V3
V4
V5
SEG
1
V5
V4
V3
V2
V1
VDD
V1
V2
V3
V4
V5
COM0-SEG
0
-
-
-
-
-
V5
V4
V3
V2
V1
COM0-SEG VDD
1
V
-
-
1
V2
V
-
-
3
V4
V5
-
Fig.7
NJU6678
APPLICATION CIRCUIT
- Microprocessor Interface Example
The NJU6678 interfaces to 80 type or 68 type MPU directly.
And the serial interface also communicate with MPU.
- 80 Type MPU
VDD
VCC
A0
A0
CS
CEL68
A0 to A7
IORQ
Decoder
MPU
NJU6678
D0 to D7
RD
D0 to D7
RD
WR
WR
P/S
RES
RES
GND
VSS
RESET
- 68 Type MPU
VCC
VDD
A0
A0
CS
CEL68
A0 to A15
VMA
Decoder
NJU6678
MPU
D0 to D7
D0 to D7
E
E
R/W
R/W
RES
P/S
RES
GND
VSS
RESET
- Serial Interface
VCC
VDD
A0
A0
CS
CEL68
A1 to A7
Decoder
VDD
OR GND
MPU
NJU6678
SI
Port1
Port2
SCL
P/S
RES
RES
GND
VSS
RESET
NJU6678
LCD Panel Interface Example
LCD Panel
(104 x 132)
NJU6678
BOTTOM VIEW
CAUTION
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
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