NJU6825CJ-Z_技术文档

NJU6825

Preliminary

128 X RGB Segment, 162-common 4096-Color

STN LCD DRIVER

ꢀꢀ GENERAL DESCRIPTION

ꢀ PACKAGE OUTLINE

The NJU6825 is a 128 x RGB segment, 162-common

4096-color STN LCD driver consisted of 384(128xRGB)-

segment and 162-common drivers, serial and parallel

MPU interface circuits, internal power supply circuits, color

palettes and 248,832-bit for graphic display data RAM.

Each of the 128-RGB segment drivers outputs 16

gradation levels out of 32-gradation level of color palette.

Since the NJU6825 provides a low operating voltage of

1.7V and low operating current, it is ideally suited for

battery-powered handheld applications.

NJU6825

ꢀꢀ FEATURES

ꢀꢀ 4096-color STN LCD driver

ꢀꢀ LCD drivers

ꢀꢀ Display data RAM (DDRAM)

ꢀꢀ Color display mode

128 x 3(RGB) segments, 162 commons

248,832-bit for graphic display

16 gradation levels out of 32-gradation level of color palette

ꢀꢀ Black & white display mode

ꢀꢀ 256-color driving mode

162 x 384 pixels 16 gradation levels or 162 x 384 pixels in B&W display

ꢀꢀ 8/16bit Parallel interface direct connection to 68/80 series MPU

ꢀꢀ Programmable 8- or 16-bit data bus length for display data

ꢀꢀ Serial interface 3-/4-line

ꢀꢀ Programmable duty and bias ratios

ꢀꢀ Programmable internal voltage booster (7-times maximum)

ꢀꢀ Programmable clock frequency for internal voltage booster operation (1/2, 1, 2, 4times)

ꢀꢀ Programmable contrast control using128-step EVR

ꢀꢀ Various instructions

Display data read/write, Display ON/OFF, Reverse display ON/OFF, All pixels ON/OFF,

column address, row address, N-line inversion, Initial display line, Initial COM line, Read-modify-write,

Gradation mode control, Increment control, Data bus length, Discharge ON/OFF,

Duty cycle ratio, LCD bias ratio, Boost level, EVR control, Power save ON/OFF, etc

ꢀꢀ Low operating current

ꢀꢀ Low logic supply voltage

ꢀꢀ LCD driving supply voltage

ꢀꢀ C-MOS technology

ꢀꢀ Package

1.7V to 3.3V

5.0V to 18.0V

Bumped chip / TCP

- 1 -

NJU6825

ꢀꢀ PAD LOCATION

DMY₁₁₄

COM₁₀₁

COM₁₄₉

DMY₁₁₅

1

Note1) The PADs of (L), (R) and (C) are shorted mutually in the LSI.

Note2) The DMY PADs are electrically open.

Chip Center

Chip Size

:X= 0µm, Y= 0µm

:20.00mm x 3.13mm

Chip Thickness

Bump Size

:625µm ± 25µm

:32µm x 68µm(COM/SEG Output), 47µm x 68µm(Interface),

68µm x 68µm(DMY₀,_{109 110 111 112 113 114,115}

,

)

Bump Pitch

:45µm(Min)

Bump Height

Bump Material

:14.0~22.5µm (Typical 18µm) <tolerance : ±3µm >

:Au

Alignment marks

a

a: 30µm

b: 6µm

d

c: 120µm

d: 27µm

d

b

Alignment mark coordinates

c

a

X=-9831µm, Y=-1396µm

X= 9831µm, Y=-1396µm

b

c

- 2 -

NJU6825

Y

X

- 3 -

NJU6825

DMY₁₁₁

COM₂₀

Y

X

COM₆₈

DMY₁₁₀

- 4 -

NJU6825

ꢀꢀ PAD COORDINATES 1

Chip Size 20000µm x 3130µm (Chip Center 0µm x 0µm )

PAD

No.

1

2

3

4

5

6

PAD

No.

PAD

Terminal

X(µm)

Y(µm)

Terminal

X (µm)

Y (µm)

Terminal

X (µm)

Y (µm)

No.

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

DMY₀

COM₁₅₀

COM₁₅₁

COM₁₅₂

COM₁₅₃

COM₁₅₄

COM₁₅₅

COM₁₅₆

COM₁₅₇

COM₁₅₈

COM₁₅₉

COM₁₆₀

COM₁₆₁

DMY₁

-9581

-9518

-9473

-9428

-9383

-9338

-9293

-9248

-9203

-9158

-9113

-9068

-9023

-8910

-8850

-8790

-8730

-8670

-8610

-8550

-8490

-8430

-8370

-8310

-8250

-8190

-8130

-8070

-8010

-7950

-7890

-7830

-7650

-7590

-7530

-7470

-7410

-7350

-7290

-7230

-7170

-7110

-7050

-6990

-6930

-6870

-6810

-6750

-6690

-6630

-6570

-1396

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

V_SS(R)

DMY₂₇

DMY₂₈

TEST₂

DMY₂₉

DMY₃₀

V_DDA(L)

V_DDA(C)

V_DDA(R)

DMY₃₁

DMY₃₂

P/S

DMY₃₃

DMY₃₄

DMY₃₅

SEL68

DMY₃₆

DMY₃₇

V_SSA(L)

V_SSA(C)

V_SSA(R)

DMY₃₈

DMY₃₉

WR

DMY₄₀

DMY₄₁

DMY₄₂

RD

DMY₄₃

DMY₄₄

DMY₄₅

V_DD(L)

V_DD(C)

V_DD(R)

DMY₄₆

DMY₄₇

D₀

-6510

-6330

-6270

-6210

-6150

-6090

-6030

-5970

-5910

-5850

-5790

-5730

-5670

-5610

-5550

-5490

-5430

-5370

-5310

-5250

-5190

-5130

-5070

-5010

-4950

-4890

-4830

-4770

-4710

-4650

-4590

-4530

-4470

-4410

-4230

-4170

-4050

-3930

-3810

-3690

-3570

-3450

-3330

-3210

-3090

-2970

-2850

-2730

-2610

-2490

-2370

-1396

DMY₅₅

D₈

DMY₅₆

D₉

DMY₅₇

D₁₀

DMY₅₈

D₁₁

DMY₅₉

D₁₂

DMY₆₀

D₁₃

DMY₆₁

D₁₄

DMY₆₂

D₁₅

DMY₆₃

V_SS(L)

V_SS(C)

V_SS(R)

DMY₆₄

CL

DMY₆₅

DMY₆₆

FLM

DMY₆₇

DMY₆₈

FR

DMY₆₉

DMY₇₀

CLK

DMY₇₁

DMY₇₂

DMY₇₃

OSC₁

DMY₇₄

DMY₇₅

OSC₂

DMY₇₆

DMY₇₇

V_SSH(L)

V_SSH(C)

V_SSH(R)

DMY₇₈

DMY₇₉

V_LCD(L)

V_LCD(C)

V_LCD(R)

V₁(L)

-2250

-2130

-2010

-1890

-1770

-1650

-1530

-1410

-1290

-1170

-1050

-930

-810

-690

-570

-450

-330

-270

-210

-150

30

-1396

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

DMY₂

V_SSA(L)

V_SSA(C)

V_SSA(R)

DMY₃

DMY₄

DMY₅

DMY₆

DMY₇

TEST₁

DMY₈

DMY₉

DMY₁₀

DMY₁₁

DMY₁₂

V_DD(L)

V_DD(C)

V_DD(R)

DMY₁₃

DMY₁₄

DMY₁₅

DMY₁₆

DMY₁₇

DMY₁₈

RES

DMY₁₉

DMY₂₀

DMY₂₁

CS

DMY₂₂

DMY₂₃

DMY₂₄

RS

150

270

330

450

570

630

750

870

930

1050

1170

1230

1290

1350

1410

1470

1650

1830

1890

1950

2010

2070

2250

2310

2370

2430

2490

2670

2730

2790

DMY₄₈

D₁

DMY₄₉

D₂

DMY₅₀

D₃

DMY₅₁

D₄

DMY₅₂

D₅

DMY₅₃

D₆

DMY₅₄

D₇

DMY₂₅

DMY₂₆

V_SS(L)

V_SS(C)

-1396 100

-1396 101

-1396 102

V₁(C)

V₁(R)

- 5 -

NJU6825

ꢀꢀ PAD COORDINATES 2

Chip Size 20000µm x 3130µm (Chip Center 0µm x 0µm )

PAD

No.

PAD

Terminal

X(µm)

Y(µm)

Terminal

X (µm)

Y (µm)

Terminal

X (µm)

Y (µm)

No.

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

No.

256

257

258

259

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

275

276

277

278

279

280

281

282

283

284

285

286

287

288

289

290

291

292

293

294

295

296

297

298

299

300

301

302

303

304

305

306

DMY₈₀

V₂(L)

V₂(C)

V₂(R)

V₃(L)

V₃(C)

V₃(R)

DMY₈₁

V₄(L)

V₄(C)

2850

2910

2970

3030

3210

3270

3330

3390

3450

3510

3570

3750

3810

3870

3930

3990

4050

4110

4170

4230

4290

4350

4410

4470

4530

4590

4650

4710

4770

4950

5010

5190

5250

5310

5370

5430

5490

5550

5610

5670

5730

5790

5850

5910

5970

6030

6090

6150

6210

6270

6330

-1396 205

-1396 206

-1396 207

-1396 208

-1396 209

-1396 210

DMY₉₅

C₃+(L)

C₃+(C)

C₃+(R)

DMY₉₆

C₃-(L)

C₃-(C)

C₃-(R)

DMY₉₇

C₄+(L)

C₄+(C)

C₄+(R)

DMY₉₈

C₄-(L)

C₄-(C)

C₄-(R)

DMY₉₉

C₅+(L)

C₅+(C)

C₅+(R)

DMY₁₀₀

C₅-(L)

C₅-(C)

C₅-(R)

DMY₁₀₁

C₆+(L)

C₆+(C)

C₆+(R)

DMY₁₀₂

C₆-(L)

C₆-(C)

C₆-(R)

DMY₁₀₃

DMY₁₀₄

DMY₁₀₅

DMY₁₀₆

DMY₁₀₇

V_OUT(L)

V_OUT(C)

V_OUT(R)

DMY₁₀₈

COM₈₀

COM₇₉

COM₇₈

COM₇₇

COM₇₆

COM₇₅

COM₇₄

COM₇₃

COM₇₂

COM₇₁

6390

6450

6510

6570

6630

6690

6750

6810

6870

6930

6990

7050

7110

7170

7230

7290

7350

7410

7470

7530

7590

7650

7710

7770

7830

7890

7950

8010

8070

8130

8190

8250

8310

8370

8430

8490

8550

8610

8670

8730

8910

9023

9068

9113

9158

9203

9248

9293

9338

9383

9428

-1396

COM₇₀

COM₆₉

DMY₁₀₉

DMY₁₁₀

COM₆₈

COM₆₇

COM₆₆

COM₆₅

COM₆₄

COM₆₃

COM₆₂

COM₆₁

COM₆₀

COM₅₉

COM₅₈

COM₅₇

COM₅₆

COM₅₅

COM₅₄

COM₅₃

COM₅₂

COM₅₁

COM₅₀

COM₄₉

COM₄₈

COM₄₇

COM₄₆

COM₄₅

COM₄₄

COM₄₃

COM₄₂

COM₄₁

COM₄₀

COM₃₉

COM₃₈

COM₃₇

COM₃₆

COM₃₅

COM₃₄

COM₃₃

COM₃₂

COM₃₁

COM₃₀

COM₂₉

COM₂₈

COM₂₇

COM₂₆

COM₂₅

COM₂₄

COM₂₃

COM₂₂

9473

9518

9581

9831

-1396

-1143

-1080

-1035

-990

-945

-900

-855

-810

-765

-720

-675

-630

-585

-540

-495

-450

-405

-360

-315

-270

-225

-180

-135

-90

-45

0

45

90

135

180

225

270

315

360

405

450

495

540

585

630

-1396

211

-1396 212

-1396 213

-1396 214

-1396 215

-1396 216

-1396 217

-1396 218

-1396 219

-1396 220

-1396 221

-1396 222

-1396 223

-1396 224

-1396 225

-1396 226

-1396 227

-1396 228

-1396 229

-1396 230

-1396 231

-1396 232

-1396 233

-1396 234

-1396 235

-1396 236

-1396 237

-1396 238

-1396 239

-1396 240

-1396 241

-1396 242

-1396 243

-1396 244

-1396 245

-1396 246

-1396 247

-1396 248

-1396 249

-1396 250

-1396 251

-1396 252

-1396 253

-1396 254

-1396 255

V₄(R)

V_REG(L)

V_REG(C)

V_REG(R)

DMY₈₂

DMY₈₃

V_REF(L)

V_REF(C)

V_REF(R)

DMY₈₄

V_BA(L)

V_BA(C)

V_BA(R)

DMY₈₅

DMY₈₆

DMY₈₇

V_EE(L)

V_EE(C)

V_EE(R)

DMY₈₈

DMY₈₉

V_SSH(L)

V_SSH(C)

V_SSH(R)

DMY₉₀

DMY₉₁

C₁+(L)

C₁+(C)

C₁+(R)

DMY₉₂

C₁-(L)

C₁-(C)

C₁-(R)

DMY₉₃

C₂+(L)

C₂+(C)

C₂+(R)

DMY₉₄

C₂-(L)

C₂-(C)

C₂-(R)

675

720

765

810

855

900

945

990

- 6 -

NJU6825

ꢀꢀ PAD COORDINATES 3

Chip Size 20000µm x 3130µm (Chip Center 0µm x 0µm )

PAD

No.

PAD

Terminal

X(µm)

Y(µm)

Terminal

X (µm)

Y (µm)

Terminal

X (µm)

Y (µm)

No.

307

308

309

310

311

312

313

314

315

316

317

318

319

320

321

322

323

324

325

326

327

328

329

330

331

332

333

334

335

336

337

338

339

340

341

342

343

344

345

346

347

348

349

350

351

352

353

354

355

356

357

No.

409

410

411

412

413

414

415

416

417

418

419

420

421

422

423

424

425

426

427

428

429

430

431

432

433

434

435

436

437

438

439

440

441

442

443

444

445

446

447

448

449

450

451

452

453

454

455

456

457

458

459

COM₂₁

COM₂₀

DMY₁₁₁

DMY₁₁₂

COM₁₉

COM₁₈

COM₁₇

COM₁₆

COM₁₅

COM₁₄

COM₁₃

COM₁₂

COM₁₁

COM₁₀

COM₉

COM₈

COM₇

COM₆

COM₅

COM₄

COM₃

COM₂

COM₁

9831

9581

9518

9473

9428

9383

9338

9293

9248

9203

9158

9113

9068

9023

8978

8933

8888

8843

8798

8753

8708

8663

8618

8573

8528

8483

8438

8393

8348

8303

8258

8213

8168

8123

8078

8033

7988

7943

7898

7853

7808

7763

7718

7673

7628

7583

7538

7493

7448

1035

1080

1144

1396

358

359

360

361

362

363

364

365

366

367

368

369

370

371

372

373

374

375

376

377

378

379

380

381

382

383

384

385

386

387

388

389

390

391

392

393

394

395

396

397

398

399

400

401

402

403

404

405

406

407

408

SEGA₉

SEGB₉

7403

7358

7313

7268

7223

7178

7133

7088

7043

6998

6953

6908

6863

6818

6773

6728

6683

6638

6593

6548

6503

6458

6413

6368

6323

6278

6233

6188

6143

6098

6053

6008

5963

5918

5873

5828

5783

5738

5693

5648

5603

5558

5513

5468

5423

5378

5333

5288

5243

5198

5153

1396

SEGA₂₆

SEGB₂₆

SEGC₂₆

SEGA₂₇

SEGB₂₇

SEGC₂₇

SEGA₂₈

SEGB₂₈

SEGC₂₈

SEGA₂₉

SEGB₂₉

SEGC₂₉

SEGA₃₀

SEGB₃₀

SEGC₃₀

SEGA₃₁

SEGB₃₁

SEGC₃₁

SEGA₃₂

SEGB₃₂

SEGC₃₂

SEGA₃₃

SEGB₃₃

SEGC₃₃

SEGA₃₄

SEGB₃₄

SEGC₃₄

SEGA₃₅

SEGB₃₅

SEGC₃₅

SEGA₃₆

SEGB₃₆

SEGC₃₆

SEGA₃₇

SEGB₃₇

SEGC₃₇

SEGA₃₈

SEGB₃₈

SEGC₃₈

SEGA₃₉

SEGB₃₉

SEGC₃₉

SEGA₄₀

SEGB₄₀

SEGC₄₀

SEGA₄₁

SEGB₄₁

SEGC₄₁

SEGA₄₂

SEGB₄₂

SEGC₄₂

5108

5063

5018

4973

4928

4883

4838

4793

4748

4703

4658

4613

4568

4523

4478

4433

4388

4343

4298

4253

4208

4163

4118

4073

4028

3983

3938

3893

3848

3803

3758

3713

3668

3623

3578

3533

3488

3443

3398

3353

3308

3263

3218

3173

3128

3083

3038

2993

2948

2903

2858

1396

SEGC₉

SEGA₁₀

SEGB₁₀

SEGC₁₀

SEGA₁₁

SEGB₁₁

SEGC₁₁

SEGA₁₂

SEGB₁₂

SEGC₁₂

SEGA₁₃

SEGB₁₃

SEGC₁₃

SEGA₁₄

SEGB₁₄

SEGC₁₄

SEGA₁₅

SEGB₁₅

SEGC₁₅

SEGA₁₆

SEGB₁₆

SEGC₁₆

SEGA₁₇

SEGB₁₇

SEGC₁₇

SEGA₁₈

SEGB₁₈

SEGC₁₈

SEGA₁₉

SEGB₁₉

SEGC₁₉

SEGA₂₀

SEGB₂₀

SEGC₂₀

SEGA₂₁

SEGB₂₁

SEGC₂₁

SEGA₂₂

SEGB₂₂

SEGC₂₂

SEGA₂₃

SEGB₂₃

SEGC₂₃

SEGA₂₄

SEGB₂₄

SEGC₂₄

SEGA₂₅

SEGB₂₅

SEGC₂₅

COM₀

SEGA₀

SEGB₀

SEGC₀

SEGA₁

SEGB₁

SEGC₁

SEGA₂

SEGB₂

SEGC₂

SEGA₂

SEGB₃

SEGC₃

SEGA₄

SEGB₄

SEGC₄

SEGA₅

SEGB₅

SEGC₅

SEGA₆

SEGB₆

SEGC₆

SEGA₇

SEGB₇

SEGC₇

SEGA₈

SEGB₈

SEGC₈

- 7 -

NJU6825

ꢀꢀ PAD COORDINATES 4

Chip Size 20000µm x 3130µm (Chip Center 0µm x 0µm )

PAD

No.

PAD

Terminal

X(µm)

Y(µm)

Terminal

X (µm)

Y (µm)

Terminal

X (µm)

Y (µm)

No.

460

461

462

463

464

465

466

467

468

469

470

471

472

473

474

475

476

477

478

479

480

481

482

483

484

485

486

487

488

489

490

491

492

493

494

495

496

497

498

499

500

501

502

503

504

505

506

507

508

509

510

No.

562

563

564

565

566

567

568

569

570

571

572

573

574

575

576

577

578

579

580

581

582

583

584

585

586

587

588

589

590

591

592

593

594

595

596

597

598

599

600

601

602

603

604

605

606

607

608

609

610

611

612

SEGA₄₃

SEGB₄₃

SEGC₄₃

SEGA₄₄

SEGB₄₄

SEGC₄₄

SEGA₄₅

SEGB₄₅

SEGC₄₅

SEGA₄₆

SEGB₄₆

SEGC₄₆

SEGA₄₇

SEGB₄₇

SEGC₄₇

SEGA₄₈

SEGB₄₈

SEGC₄₈

SEGA₄₉

SEGB₄₉

SEGC₄₉

SEGA₅₀

SEGB₅₀

SEGC₅₀

SEGA₅₁

SEGB₅₁

SEGC₅₁

SEGA₅₂

SEGB₅₂

SEGC₅₂

SEGA₅₃

SEGB₅₃

SEGC₅₃

SEGA₅₄

SEGB₅₄

SEGC₅₄

SEGA₅₅

SEGB₅₅

SEGC₅₅

SEGA₅₆

SEGB₅₆

SEGC₅₆

SEGA₅₇

SEGB₅₇

SEGC₅₇

SEGA₅₈

SEGB₅₈

SEGC₅₈

SEGA₅₉

SEGB₅₉

SEGC₅₉

2813

2768

2723

2678

2633

2588

2543

2498

2453

2408

2363

2318

2273

2228

2183

2138

2093

2048

2003

1958

1913

1868

1823

1778

1733

1688

1643

1598

1553

1508

1463

1418

1373

1328

1283

1238

1193

1148

1103

1058

1013

968

1396

511

512

513

514

515

516

517

518

519

520

521

522

523

524

525

526

527

528

529

530

531

532

533

534

535

536

537

538

539

540

541

542

543

544

545

546

547

548

549

550

551

552

553

554

555

556

557

558

559

560

561

SEGA₆₀

SEGB₆₀

SEGC₆₀

SEGA₆₁

SEGB₆₁

SEGC₆₁

SEGA₆₂

SEGB₆₂

SEGC₆₂

SEGA₆₃

SEGB₆₃

SEGC₆₃

SEGA₆₄

SEGB₆₄

SEGC₆₄

SEGA₆₅

SEGB₆₅

SEGC₆₅

SEGA₆₆

SEGB₆₆

SEGC₆₆

SEGA₆₇

SEGB₆₇

SEGC₆₇

SEGA₆₈

SEGB₆₈

SEGC₆₈

SEGA₆₉

SEGB₆₉

SEGC₆₉

SEGA₇₀

SEGB₇₀

SEGC₇₀

SEGA₇₁

SEGB₇₁

SEGC₇₁

SEGA₇₂

SEGB₇₂

SEGC₇₂

SEGA₇₃

SEGB₇₃

SEGC₇₃

SEGA₇₄

SEGB₇₄

SEGC₇₄

SEGA₇₅

SEGB₇₅

SEGC₇₅

SEGA₇₆

SEGB₇₆

SEGC₇₆

518

473

428

383

338

293

248

203

158

113

68

23

-23

1396

SEGA₇₇

SEGB₇₇

SEGC₇₇

SEGA₇₈

SEGB₇₈

SEGC₇₈

SEGA₇₉

SEGB₇₉

SEGC₇₉

SEGA₈₀

SEGB₈₀

SEGC₈₀

SEGA₈₁

SEGB₈₁

SEGC₈₁

SEGA₈₂

SEGB₈₂

SEGC₈₂

SEGA₈₃

SEGB₈₃

SEGC₈₃

SEGA₈₄

SEGB₈₄

SEGC₈₄

SEGA₈₅

SEGB₈₅

SEGC₈₅

SEGA₈₆

SEGB₈₆

SEGC₈₆

SEGA₈₇

SEGB₈₇

SEGC₈₇

SEGA₈₈

SEGB₈₈

SEGC₈₈

SEGA₈₉

SEGB₈₉

SEGC₈₉

SEGA₉₀

SEGB₉₀

SEGC₉₀

SEGA₉₁

SEGB₉₁

SEGC₉₁

SEGA₉₂

SEGB₉₂

SEGC₉₂

SEGA₉₃

SEGB₉₃

SEGC₉₃

-1778

-1823

-1868

-1913

-1958

-2003

-2048

-2093

-2138

-2183

-2228

-2273

-2318

-2363

-2408

-2453

-2498

-2543

-2588

-2633

-2678

-2723

-2768

-2813

-2858

-2903

-2948

-2993

-3038

-3083

-3128

-3173

-3218

-3263

-3308

-3353

-3398

-3443

-3488

-3533

-3578

-3623

-3668

-3713

-3758

-3803

-3848

-3893

-3938

-3983

-4028

1396

-68

-113

-158

-203

-248

-293

-338

-383

-428

-473

-518

-563

-608

-653

-698

-743

-788

-833

-878

-923

-968

-1013

-1058

-1103

-1148

-1193

-1238

-1283

-1328

-1373

-1418

-1463

-1508

-1553

-1598

-1643

-1688

-1733

923

878

833

788

743

698

653

608

563

- 8 -

NJU6825

ꢀꢀ PAD COORDINATES 5

Chip Size 20000µm x 3130µm (Chip Center 0µm x 0µm )

PAD

No.

PAD

Terminal

X(µm)

Y(µm)

Terminal

X (µm)

Y (µm)

Terminal

X (µm)

Y (µm)

No.

613

614

615

616

617

618

619

620

621

622

623

624

625

626

627

628

629

630

631

632

633

634

635

636

637

638

639

640

641

642

643

644

645

646

647

648

649

650

651

652

653

654

655

656

657

658

659

660

661

662

663

No.

715

716

717

718

719

720

721

722

723

724

725

726

727

728

729

730

731

732

733

734

735

736

737

738

739

740

741

742

743

744

745

746

747

748

749

750

751

752

753

754

755

756

757

758

759

760

761

762

763

764

765

SEGA₉₄

SEGB₉₄

SEGC₉₄

SEGA₉₅

SEGB₉₅

SEGC₉₅

SEGA₉₆

SEGB₉₆

SEGC₉₆

SEGA₉₇

SEGB₉₇

SEGC₉₇

SEGA₉₈

SEGB₉₈

SEGC₉₈

SEGA₉₉

SEGB₉₉

SEGC₉₉

SEGA₁₀₀

SEGB₁₀₀

SEGC₁₀₀

SEGA₁₀₁

SEGB₁₀₁

SEGC₁₀₁

SEGA₁₀₂

SEGB₁₀₂

SEGC₁₀₂

SEGA₁₀₃

SEGB₁₀₃

SEGC₁₀₃

SEGA₁₀₄

SEGB₁₀₄

SEGC₁₀₄

SEGA₁₀₅

SEGB₁₀₅

SEGC₁₀₅

SEGA₁₀₆

SEGB₁₀₆

SEGC₁₀₆

SEGA₁₀₇

SEGB₁₀₇

SEGC₁₀₇

SEGA₁₀₈

SEGB₁₀₈

SEGC₁₀₈

SEGA₁₀₉

SEGB₁₀₉

SEGC₁₀₉

SEGA₁₁₀

SEGB₁₁₀

SEGC₁₁₀

-4073

-4118

-4163

-4208

-4253

-4298

-4343

-4388

-4433

-4478

-4523

-4568

-4613

-4658

-4703

-4748

-4793

-4838

-4883

-4928

-4973

-5018

-5063

-5108

-5153

-5198

-5243

-5288

-5333

-5378

-5423

-5468

-5513

-5558

-5603

-5648

-5693

-5738

-5783

-5828

-5873

-5918

-5963

-6008

-6053

-6098

-6143

-6188

-6233

-6278

-6323

1396

664

665

666

667

668

669

670

671

672

673

674

675

676

677

678

679

680

681

682

683

684

685

686

687

688

689

690

691

692

693

694

695

696

697

698

699

700

701

702

703

704

705

706

707

708

709

710

711

712

713

714

SEGA₁₁₁

SEGB₁₁₁

SEGC₁₁₁

SEGA₁₁₂

SEGB₁₁₂

SEGC₁₁₂

SEGA₁₁₃

SEGB₁₁₃

SEGC₁₁₃

SEGA₁₁₄

SEGB₁₁₄

SEGC₁₁₄

SEGA₁₁₅

SEGB₁₁₅

SEGC₁₁₅

SEGA₁₁₆

SEGB₁₁₆

SEGC₁₁₆

SEGA₁₁₇

SEGB₁₁₇

SEGC₁₁₇

SEGA₁₁₈

SEGB₁₁₈

SEGC₁₁₈

SEGA₁₁₉

SEGB₁₁₉

SEGC₁₁₉

SEGA₁₂₀

SEGB₁₂₀

SEGC₁₂₀

SEGA₁₂₁

SEGB₁₂₁

SEGC₁₂₁

SEGA₁₂₂

SEGB₁₂₂

SEGC₁₂₂

SEGA₁₂₃

SEGB₁₂₃

SEGC₁₂₃

SEGA₁₂₄

SEGB₁₂₄

SEGC₁₂₄

SEGA₁₂₅

SEGB₁₂₅

SEGC₁₂₅

SEGA₁₂₆

SEGB₁₂₆

SEGC₁₂₆

SEGA₁₂₇

SEGB₁₂₇

SEGC₁₂₇

-6368

-6413

-6458

-6503

-6548

-6593

-6638

-6683

-6728

-6773

-6818

-6863

-6908

-6953

-6998

-7043

-7088

-7133

-7178

-7223

-7268

-7313

-7358

-7403

-7448

-7493

-7538

-7583

-7628

-7673

-7718

-7763

-7808

-7853

-7898

-7943

-7988

-8033

-8078

-8123

-8168

-8213

-8258

-8303

-8348

-8393

-8438

-8483

-8528

-8573

-8618

1396

COM₈₁

COM₈₂

COM₈₃

COM₈₄

COM₈₅

COM₈₆

COM₈₇

COM₈₈

COM₈₉

COM₉₀

COM₉₁

COM₉₂

COM₉₃

COM₉₄

COM₉₅

COM₉₆

COM₉₇

COM₉₈

COM₉₉

COM₁₀₀

DMY₁₁₃

DMY₁₁₄

COM₁₀₁

COM₁₀₂

COM₁₀₃

COM₁₀₄

COM₁₀₅

COM₁₀₆

COM₁₀₇

COM₁₀₈

COM₁₀₉

COM₁₁₀

COM₁₁₁

COM₁₁₂

COM₁₁₃

COM₁₁₄

COM₁₁₅

COM₁₁₆

COM₁₁₇

COM₁₁₈

COM₁₁₉

COM₁₂₀

COM₁₂₁

COM₁₂₂

COM₁₂₃

COM₁₂₄

COM₁₂₅

COM₁₂₆

COM₁₂₇

COM₁₂₈

COM₁₂₉

-8663

-8708

-8753

-8798

-8843

-8888

-8933

-8978

-9023

-9068

-9113

-9158

-9203

-9248

-9293

-9338

-9383

-9428

-9473

-9518

-9581

-9831

1396

1143

1080

1035

990

945

900

855

810

765

720

675

630

585

540

495

450

405

360

315

270

225

180

135

90

45

0

-45

-90

-135

-180

- 9 -

NJU6825

ꢀꢀ PAD COORDINATES 6

Chip Size 20000µm x 3130µm (Chip Center 0µm x 0µm )

PAD

Terminal

X(µm)

Y(µm)

No.

766

767

768

769

770

771

772

773

774

775

776

777

778

779

780

781

782

783

784

785

786

COM₁₃₀

COM₁₃₁

COM₁₃₂

COM₁₃₃

COM₁₃₄

COM₁₃₅

COM₁₃₆

COM₁₃₇

COM₁₃₈

COM₁₃₉

COM₁₄₀

COM₁₄₁

COM₁₄₂

COM₁₄₃

COM₁₄₄

COM₁₄₅

COM₁₄₆

COM₁₄₇

COM₁₄₈

COM₁₄₉

DMY₁₁₅

-9831

-225

-270

-315

-360

-405

-450

-495

-540

-585

-630

-675

-720

-765

-810

-855

-900

-945

-990

-1035

-1080

-1144

- 10 -

NJU6825

ꢀꢀ BLOCK DIAGRAM

V_SSH

V_SS

V_DD

Segment Driver

Common Driver

5

V

_LCD, V₁-V₄

Gradation Circuit

Data Latch Circuit

Shift Register

C₁+

C₁-

C₂+

C₂-

C₃+

C₃-

Voltage

booster

C₄+

C₄-

C₅+

C₅-

C₆+

C₆-

Voltage

regulator

V_OUT

V_EE

V_REF

V_BA

V_REG

Display Data RAM

(DD RAM)

128x162x(4+4+4)bit

D₁₅

Column Address Decoder

Column Address Counter

Column Address Register

D₁₄

FR

D₁₃

RAM

Interface

Display

Timing

Generator

FLM

CL

D₁₂

D₁₁

D₁₀

D₉

CLK

D₈

OSC₂

OSC₁

Oscillator

D₇

D₆

D₅

D₄/SPOL

D₃/SMODE

D₂

Instruction

Decoder

Register Read

Control

Bus Holder

Pole Control

Internal Bus

D₁/SDA

D₀/SCL

MPU Interface

CS

RS

RD

WR

P/S

SEL68 RES TEST₁TEST₂

- 11 -

NJU6825

ꢀPOWER SUPPLY CIRCUITS BLOCK DIAGRAM

+

-

Reference

Voltage

Generator

+

-

V_BA

V_LCD

+

-

Voltage regulator

V₁

V_REG

V_REF

+

-

+

-

V₂

Gain

Control

(1x-7x)

+

-

V₃

E.V.R

1/2V_REG

+

-

V₄

EVR register

Boost level register

C₁+

C₁-

C₂+

C₂-

C₃+

C₃-

C₄+

C₄-

C₅+

C₅-

C₆+

C₆-

V_EE

Voltage

Booster

V_OUT

- 12 -

NJU6825

ꢀꢀ TERMINAL DESCRIPTION 1

No.

30-32,

83-85

Symbol

V_DD

I/O

Function

Power supply for logic circuits

Power

50-52,

V_SS

Power

GND for logic circuits

120-122

143-145,

185-187

V_SSH

GND for high voltage circuits

This terminal is internally connected to the V_DDlevel.

•This terminal is used to fix the select-terminals of the SEL68,

P/S and TEST₂to the V_DDlevel.

Note) Do not use this terminal for a main power supply.

This terminal is internally connected to the V_SSlevel.

•This terminal is used to fix the select-terminals of the SEL68,

P/S and TEST₂to the V_SSlevel.

58-60

V_DDA

Power

16-18,

70-72

V_SSA

Note) Do not use this terminal for a main GND.

LCD driving voltages

•When the internal voltage booster is not used, external LCD

driving voltages (V₁to V₄and V_LCD) should be supplied onto

these terminals. The external voltages should be maintained

with the following relationship.

148-150,

151-153,

155-157,

158-160,

162-164

V_LCD

V₁

V₂

V₃

V₄

Power/O

V_SS<V₄<V₃<V₂<_V1<V_LCD

• When the internal voltage booster is used, the LCD driving

voltages (V₁to V₄and V_LCD) are enabled by the “Power control”

instruction. The capacitors between these terminals and Vss

terminal are required

190-192,

194-196

198-200,

202-204

206-208,

210-212

214-216,

218-220

222-224,

226-228

230-232,

234-236

174-176

170-172

C₁+

C₁-

C₂+

C₂-

C₃+

C₃-

C₄+

C₄-

C₅+

C₅-

C₆+

C₆-

V_BA

V_REF

O

Capacitor connection terminal for the voltage booster

Capacitor connection terminal or the voltage booster

Capacitor connection terminal for the voltage booster

O

I

Reference-voltage generator output

Voltage regulator input

Voltage booster input

•This terminal is normally connected to the V_DDlevel.

180-182

V_EE

Power

Voltage booster output for high voltage circuits (in external

242-244

165-167

39

V_OUT

V_REG

RES

Power/O

power supply)

Voltage regulator output

Reset

O

I

Active “0”

- 13 -

NJU6825

ꢀꢀ TERMINAL DESCRIPTION 2

No.

Symbol

I/O

Function

Parallel interface:

D₇to D₀: 8-bit bi-directional bus

•In the parallel interface mode (P/S=“1”), these terminals should

be connected to 8-bit bi-directional bus of MPU.

88

D₀/SCL

Serial interface:

SDA : serial data

SCL : serial clock

SMODE : 3-/4-line serial interface mode select

SPOL : RS polarity select (in the 3-line serial interface mode)

90

94

96

D₁/SDA

D₃/SMODE

D₄/SPOL

I/O

•In the 3-/4-line serial interface mode (P/S=“0”), the D0 terminal

is assigned to the SCL and the D₁terminal to the SDA.

•In the 3-line serial interface mode, the D₄terminal is assigned

to the SPOL.

•The serial data on the SDA is fetched at the rising edge of the

SCL signal in the order of the D₇, D₆…D₀, and the fetched data

is converted into 8-bit parallel data at the falling edge of the 8th

SCL signal.

92, 98,

100,102

D₂, D₅,

D₆, D₇

•The SCL signal should be set to “0” after data transmissions or

during non-access.

8-bit bi-directional bus

104,106,108,

110,112,114,

116,118

D₈, D₉, D₁₀,

D₁₁, D₁₂, D₁₃,

D₁₄, D₁₅

•In the 16-bit data bus mode, these terminals are assigned to

the upper 8-bit data bus.

•In the serial interface mode or 8-bit data bus mode in the

parallel interface, these terminals should be fixed to “1” or “0”.

Chip select

I/O

I

43

CS

Active “0”

Resister select

•This signal distinguishes an instruction data and display data

for transferred data.

47

RS

I

RS

H

L

Distinct.

Instruction

Display data

80 series MPU interface (P/S=“1”, SEL68=“0”)

RD signal. Active “0”.

79

75

RD (E)

68 series MPU interface (P/S=“1”, SEL68=“1”)

Enable signal. Active “1”.

80 series MPU interface (P/S=“1”, SEL68=“0”)

WR signal. Active “0”.

68 series MPU interface (P/S=“1”, SEL68=“1”)

R/W signal.

I

WR (R/W)

R/W

H

L

Status

Read

Write

- 14 -

NJU6825

ꢀꢀ TERMINAL DESCRIPTION 3

No.

Symbol

I/O

I

Function

MPU interface type select

SEL68

Status

H

L

67

SEL68

68 series

80 series

Parallel / serial interface mode select

Chip

Select

Data/Instructio

n

P/S

Data

Read/Write

Serial clock

H

L

CS

RS

D0 to D7

SDA (D1)

-

RD, WR

Write only

63

P/S

CL

I

SCL (D0)

•In the serial interface mode (P/S=“0”), the D15 to D5 terminals are in

the high impedance status therefore those terminals should be fixed to

“1” or “0”. The RD and WR terminals also should be “1” or “0”.

124

I/O

This terminal should be opened.

127

130

FLM

FR

I/O

This terminal should be opened.

Maker test terminal

This terminal should be fixed to “0”.

Maker test terminal

24

55

TEST₁

TEST₂

I

This terminal must be fixed to “1”.

- 15 -

NJU6825

ꢀꢀ TERMINAL DESCRIPTION 4

No.

Symbol

I/O

Function

Segment output

Mode

Normal

Reverse

Turn-off

Turn-on

0

1

0

•These terminals output LCD driving waveforms in accordance

with the combination of FR signal and display data.

SEGA₀to SEGA₁₂₇

,

331-714

SEGB₀to SEGB₁₂₇

SEGC₀to SEGC₁₂₇

,

O

In the B/W mode

FR signal

Display data

Normal display mode

V₂

V_LCD

V₂

V ₃

V_SS

V₃

Reverse display

V_LCD

V_SS

mode

Common output

•These terminals output LCD driving waveforms in accordance

311-330,

260-308,

246-257,

715-734,

737-785,

2-13

with the combination of the FR signal and scanning data.

Data

H

L

FR

H

L

Output level

COM₀to COM₁₆₁

O

V_SS

V₁

V_LCD

V₄

H

L

OSC

•When the internal oscillator clock is used, OSC₁terminal must be

fixed to “1” or “0”. OSC₂terminal should be opened. When the

oscillation frequency from the internal oscillator is adjusted by an

external resistor between OSC₁terminal and OSC₂

137,

140

OSC₁

OSC₂

I

O

•When an external oscillator is used, external clocks should be

input onto the OSC₁terminal or an external resistor should be

connected between the OSC₁and OSC₂terminals.

133

CLK

I/O

This terminal should be opened.

(Terminal No.14,15,20-23,25-29,33-38,40-42,44-46,48,49,53,54,56,57,61,62,64-66,68,69,73,74,76-78,80-82,

86,87,89,91,93,95,97,99,101,103,105,107,109,111,113,115,117,119,123,125,126,128,129,131,132,134-136,

138,139,141,142,146,147,154,161,168,169,173,177-179,183,184,188,189,193,197,201,205,209,213,217,221,

225,229,233,237-241,245,258,259,309,310,735,736, and 786 are dummy.)

- 16 -

NJU6825

ꢀꢀ Functional Description

(1) MPU Interface

(1-1) Parallel / serial interface mode select

The P/S terminal is used to select parallel or serial interface mode as shown in the following table. In the

serial interface mode, it is impossible to read out display data from the DDRAM and status from the

internal resistor.

Table1

WR

-

P/S

H

P/S mode

Parallel I/F

Serial I/F

CS

RS

RD

-

SEL68

-

SDA

SCL

Data

D₇-D₀(D₁₅-D₀)

-

L

Note 1) “ -” mark: Fix to “1” or “0”.

(1-2) MPU interface type select

In the parallel interface mode, the SEL68 terminal is used to select 68- or 80-series MPU interface type

as shown in the following table.

Table2

WR

R/W

WR

SEL68

MPU type

CS

RS

RD

E

Data

D₇-D₀(D₁₅-D₀)

H

L

68 series MPU

80 series MPU

RD

(1-3) Data distinction

In the parallel interface mode, the combination of RS, RD, and WR (R/W) signals distinguishes an

instruction data or display data for the transferred data from or to MPU as shown in the following table.

Table3

68 series

80 series

Function

RS

RD

WR

H

R/W

H

Read out instruction data

Write instruction data

Read out display data

Write display data

H

L

H

L

H

L

H

L

(1-4) 3- / 4-line serial interface mode select

In the serial interface mode, the SMODE is used to select 3- or 4-line serial interface mode as shown in

the following table.

Table4

SMODE

Serial interface mode

H

L

3-line

4-line

- 17 -

NJU6825

(1-5) 4-line serial interface mode

In the 4-line serial interface mode, during the chip select is active (CS=“0”), the SDA and SCL are

enabled. During the chip select is not active (CS=“1”), the SDA and SCL are disabled and the internal shift

register and counter are being initialized. The 8-bit serial data on the SDA is fetched at the rising edge of

the SCL signal (serial clock) in order of the D₇, D₆…D₀, and the fetched data is converted into the 8-bit

parallel data at the rising edge of the 8th SCL signal.

In the 4-line serial interface mode, the transferred data on the SDA is distinguished as display data or

instruction data in accordance with the condition of the RS signal.

Table5

RS

H

Data distinction

Instruction data

Display data

L

Since the serial interface operation is sensitive to external noises, the SCL should be set to “0” after data

transmissions or during non-access. To prevent for the continuous mal-function caused by the external

noises, the chip-selected status should be released (CS=“1”) after each of the 8-bit data transmissions.

The following figure illustrates the interface timing for the 4-line serial interface operation.

CS

RS

VALID

D₀

SDA

D₇

1

D₆

2

D₅

3

D₄

4

D₃

5

D₂

D₁

SCL

6

7

8

Fig1 4-line serial interface timing

(1-6) 3-line serial interface mode

In the 3-line serial interface mode, during the chip select is active (CS=“0”), the SDA and SCL are

enabled. During the chip select is not active (CS=“1”), the SDA and SCL are disabled and the internal shift

register and counter are being initialized. The 9-bit serial data on the SDA is fetched at the rising edge of

the SCL signal in order of the RS, D₇, D₆…D₀, and the fetched data is converted into the 9-bit parallel data

at the rising edge of the 9th SCL signal.

In the 3-line serial interface mode, the data on the SDA is distinguished as display data or instruction

data in accordance with the condition of the RS bit of SDA data and the status of the SPOL, as follows.

Table6

SPOL=L

Data distinction

SPOL=H

Data distinction

RS

L

RS

L

Display data

Instruction data

Display data

H

Instruction data

H

- 18 -

NJU6825

Since the serial interface operation is sensitive to external noises, the SCL should be set to “0” after data

transmissions or during non-access. To prevent for the continuous mal-function caused by the external

noises, the chip-selected status should be released (CS=“1”) after each of the 9-bit data transmissions.

The following figure illustrates the interface timing for the 3-line serial interface operation.

CS

SDA

SCL

RS

1

D₇

2

D₆

D₅

4

D₄

5

D₃

D₂

D₁

D₀

3

6

7

8

9

Fig2 3-line serial interface timing

- 19 -

NJU6825

(2) Access to the DDRAM

During the CS signal is ”0”, the transferred data is written into the DDRAM or instruction register in

accordance with the condition of the RS signal.

In condition that the RS signal is “1”, the transferred data is distinguished as display data. After the “column

address” and “row address” instructions are executed, the display data is written into the DDRAM by the

“display data write” instruction. The data is written at the rising edge of the WR signal in the 80 series MPU

mode or falling edge of the E signal in the 68 series MPU mode.

Table6

RS

L

Data

Display RAM Data

H

Internal Command Register

In the sequence of the “display data read” operation, the transferred data from MPU is temporarily held in the

internal bus-holder and then transferred to the internal data-bus. When the “display data read” operation is

executed just after the “column address” and “row address” instructions or “display data write” instruction,

unexpected data on the bus-holder is read out at the 1st execution and then the correct designated DDRAM

address data is read out from the 2nd execution. For this reason, a dummy read cycle must be executed to

avoid the unexpected 1st data read.

Display data write operation

n

n+1

n+2

n+3

n+4

D₀to D₁₅

WR

n

n+1

n+2

n+3

n+4

Bus Holder

WR

Display data read operation

WR

D₀to D₇(D₀to D₁₅)

n

n+1

Data Read

n+1 Address n+2 Address

n+2

Address Set

n

Dummy

Read

Data Read

n Address

Data Read

RD

Fig3

- 20 -

NJU6825

(3) Access to the instruction register

Each of the instruction resisters is assigned to the address in between 0_Hand F_Hin order that it is possible to

read out the content of the instruction registers by the combination instructions of the “Instruction resister

address” and ”Instruction resister read”.

WR

M

m

N

n

D₀to D₇

Instruction resister Instruction resister Instruction resister Instruction resister

address set

contents read

address set

contents read

RD

Fig4

(4) 8-/16-bit data bus length for display data (in the parallel interface mode)

The 8- or 16-bit data bus length for display data is determined by the “WLS” in the “Data bus length”

instruction.

In the 16-bit data bus mode, not only the display data but also the instruction data is required to be

transferred by 16-bit data (D₁₅to D₀). However, in case of the access to the instruction register, the only lower

8-bit data (D₇to D₀) of the 16-bit data is valid. In case of the access to the DDRAM, all of the 16-bit data (D₁₅to

D₀) is valid.

Table8

WLS

L

Data bus length mode

8-bit

H

16-bit

(5) Initial display line register

The initial display line resister specifies the line address, corresponding to the initial COM line, by the “Initial

display line” instruction. The initial COM line signifies the common driver, starting scanning the display data in

the DDRAM, and specified by the “Initial COM line” instruction.

The line address, established in the initial display line resister, is preset into the line counter whenever the

FLM signal becomes “1”. At the rising edge of the CL signal, the line counter is counted-up and addressed 384-

bit display data is latched into the data latch circuit. At the falling edge of the CL signal, the latched data output

to the segment drivers.

- 21 -

NJU6825

(6) DDRAM mapping

The DDRAM is capable of 1,536-bit (12-bit x 128-segment) for the column address and 162-bit for the row

address.

In the gradation mode, each pixel for RGB corresponds to the successive 3-segment drivers with 16-

gradation per segment, so that the LSI can drive a 4096-color display (16-gradation x 16-gradation x 16-

gradation) with up to 128x162 pixels.

ꢁ In the 8-bit data bus length mode

column-address

0_H

7bit

1_H

5bit

FE_H

7bit

FF_H

5bit

0 _H

row-address

A1_H

7bit

5bit

7bit

5bit

column-address

0_H

4bit

1_H

8bit

FE_H

4bit

FF_H

8bit

ABS=’1’

0 _H

row-address

A1_H

4bit

8bit

4bit

8bit

0_H

8bit

1_H

8bit

BE_H

8bit

BF_H

8bit

HSW=’1’

0 _H

row-address

A1_H

8bit

0_H

8bit

1_H

8bit

7E_H

8bit

7F_H

8bit

C256=’1’

0 _H

row-address

A1_H

8bit

- 22 -

NJU6825

ꢁ In the 16-bit data bus length mode

column-address

0_H

7F_H

0 _H

12bit

row-address

A1_H

12bit

Fig6

In the B&W mode, only MSB data from each 4-bit display data group in the DDRAM is used. Therefore, 384 x

162 pixels B&W display or 128 x 162 pixels 8 kinds display is also available.

The column address range varies depending on the data bus length. The range between 00_Hand FF_His used

in the 8-bit data bus length and the range between 00_Hand 3F_His in the 16-bit data bus length.

The DDRAM is accessing 8-bit or 16-bit unit addressed by column and row address. In the 16-bit data bus

length mode, over 40_Haddress setting is prohibited.

The increment for the column address and row address can be set in the auto-increment mode by

programming “AXI” and “AYI” registers in the “Increment control” instruction. In this mode, the contents of the

column address and row address counters automatically increment whenever the DDRAM is accessed.

The column address and row address counters are independent of the line counter. They are used to

designate the column address and row address for the display data transferred from MPU. On the other hand,

the line counter is used to generate the line address and output the display data to the segment drivers, being

synchronized with the display control timing of the FLM and CL signals.

- 23 -

NJU6825

REF

SWAP

A3

WLS

ABS

HSW

REF

256

WLS

ABS

HSW

REF

256

A2

A1

A0

B3

A3

B2

A2

A1

A0

B3

B2

B1

B0

C3

C2

C1

C0

A3

A2

A1

A0

B3

B2

B1

B0

C3

C2

C1

C0

A2

A1

A0

B3

B2

B1

B0

C3

C2

C1

C0

A3

A2

A1

A0

B3

B2

B1

B0

C3

C2

C1

C0

B1

B0

C3

C2

C1

C0

A3

A2

A1

A0

B3

B2

B1

B0

C3

C2

C1

C0

A3

A2

A1

A0

B3

B2

B1

B0

C3

C2

C1

C0

A3

A2

A1

A0

B3

B2

B1

B0

C3

C2

C1

C0

A3

A2

A1

A0

B3

B2

B1

B0

C3

C2

C1

C0

- 24 -

NJU6825

(7) Window addressing mode

In addition to the full DDRAM addressing, it is possible to access only to the part of DDRAM by the window

addressing mode. In the window addressing mode, the address space of the DDRAM designated by the start

and end point is defined. The start point is determined by the “column address” and “row address” instructions,

and the end point is determined by the “Window end column address “and ”Window end row address”

instructions. Designating of the DDRAM address is changed by each data writing mode as 16-bit length or 8-bit

by “WLS” instruction and “HSW”, and Display mode of 256-color by “C256”. The setting for the window

addressing is listed in the following.

1. “Increment control” instruction (WIN=1, AXI=1, AYI=1)

2. Set “column address” and “row address” instructions for the start point

3. Set “Window end column address” and “Window end row address” instructions for the end point

4. Enable to access to the DDRAM by the window addressing mode

In addition, the read-modify-write operation is available by setting “AIM” register to ”L” in the “Increment

control” instruction in the window addressing mode (WIN=1, AXI=1, AYI=1).

Also in the window addressing mode, correct start and end point setting is required to abide to access invalid

addressing space. The following relationship for the start and end point must be maintained.

AX (column address of start point) < EX (column address of end point) < Maximum of column address

AY (row address of start point) < EY (row address of end point) < Maximum of row address

column address

(X, Y)

Start point

End point

Window display area

(X, Y)

Whole DDRAM area

Fig7

(8) Reverse display ON/OFF

The “Reverse display ON/OFF” function is used to reverse the display data without changing the display data

in the DDRAM.

Table9

REV

Display

Normal

DDRAM data → Display data

0

1

0

1

0

1

0

1

Reverse

(9) Segment direction

The “Segment direction” function is used to reverse the assignment for the segment drivers and column

address, so that it is possible to reduce the restrictions for the placement of the LSI in the LCD modules.

- 25 -

NJU6825

(10) The relationship among the DDRAM column address, display data and segment drivers

Color mode, 16-bit data bus mode

HSW ABS REF SWAP

X address / bit / segment assign

*

0

1

0

1

X=00_H

X=7F_H

ꢂꢃ

X=7F_H

X=00_H

ꢂꢃ

HSW ABS REF SWAP

X address / bit / segment assign

*

0

1

0

X=00_H

X=7F_H

ꢂꢃ

X=7F_H

X=00_H

ꢂꢃ

HSW ABS REF SWAP

X address / bit / segment assign

*

1

0

1

0

1

X=00_H

X=7F_H

ꢂꢃ

X=7F_H

X=00_H

ꢂꢃ

HSW ABS REF SWAP

X address / bit / segment assign

*

1

0

1

0

X=00_H

X=7F_H

ꢂꢃ

X=7F_H

X=00_H

ꢂꢃ

- 26 -

NJU6825

Color mode, 8-bit data bus mode

HSW ABS REF SWAP

X address / bit / segment assign

0

1

0

1

X=00_H

X=FE_H

X=01_H

X=FF_H

ꢂꢃ

X=FE_H

X=00_H

X=FF_H

X=01_H

ꢂꢃ

HSW ABS REF SWAP

X address / bit / segment assign

0

1

0

X=00_H

X=FE_H

X=01_H

X=FF_H

ꢂꢃ

X=FE_H

X=00_H

X=FF_H

X=01_H

ꢂꢃ

HSW ABS REF SWAP

X address / bit / segment assign

0

1

0

1

0

1

X=00_H

X=FE_H

X=01_H

X=FF_H

ꢂꢃ

X=FE_H

X=00_H

X=FF_H

X=01_H

ꢂꢃ

HSW ABS REF SWAP

X address / bit / segment assign

0

1

0

1

0

X=00_H

X=FE_H

X=01_H

X=FF_H

ꢂꢃ

X=FE_H

X=00_H

X=FF_H

X=01_H

ꢂꢃ

- 27 -

NJU6825

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

SEGA

Palette A

0

SEGC

0

SEGC

0

SEGA

0

Palette A

Palette B

Palette C

Palette A

Palette B

Palette C

Palette A

Palette B

Palette C

Palette A

Palette B

Palette C

Palette A

Palette B

Palette C

Palette A

Palette B

Palette C

SEGB

Palette B

0

SEGB

0

SEGB

0

SEGB

0

SEGC

Palette C

0

SEGA

0

SEGA

0

SEGC

0

SEGA

Palette A

1

SEGC

1

SEGC

1

SEGA

1

SEGB

Palette B

1

SEGB

1

SEGB

1

SEGB

1

SEGC

Palette C

1

SEGA

1

SEGA

1

SEGC

1

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

SEGA

Palette A

126

SEGC

126

SEGC

126

SEGA

126

Palette A

Palette B

Palette C

Palette A

Palette B

Palette C

Palette A

Palette B

Palette C

Palette A

Palette B

Palette C

Palette A

Palette B

Palette C

Palette A

Palette B

Palette C

SEGB

Palette B

126

SEGB

126

SEGB

126

SEGB

126

SEGC

Palette C

126

SEGA

126

SEGA

126

SEGC

126

SEGA

Palette A

127

SEGC

127

SEGC

127

SEGA

127

SEGB

Palette B

127

SEGB

127

SEGB

127

SEGB

127

SEGC

Palette C

127

SEGA

127

SEGA

127

SEGC

127

- 28 -

NJU6825

Color mode, 8-bit data bus mode, C256 mode (C256=1)

HSW ABS REF SWAP X address / bit / segment assign

*

0

1

0

1

X=00_H

X=7F_H

ꢂꢃ

X=7F_H

X=00_H

ꢂꢃ

HSW ABS

SWA

REF

X address / bit / segment assign

P

1

0

*

0

1

X=00_H

X=7F_H

ꢂꢃ

X=7F_H

X=00_H

ꢂꢃ

- 29 -

NJU6825

B&W mode, 16-bit data bus mode

HSW ABS REF SWAP

X address / bit / segment assign

*

0

1

0

1

X=00_H

X=7F_H

ꢂꢃ

X=7F_H

X=00_H

ꢂꢃ

HSW ABS REF SWAP

X address / bit / segment assign

*

0

1

0

X=00_H

X=7F_H

ꢂꢃ

X=7F_H

X=00_H

ꢂꢃ

HSW ABS REF SWAP

X address / bit / segment assign

*

1

0

1

0

1

X=00_H

X=7F_H

ꢂꢃ

X=7F_H

X=00_H

ꢂꢃ

HSW ABS REF SWAP

X address / bit / segment assign

*

1

0

1

0

X=00_H

X=7F_H

ꢂꢃ

X=7F_H

X=00_H

ꢂꢃ

- 30 -

NJU6825

B&W mode, 8-bit data bus mode

HSW ABS REF SWAP

X address / bit / segment assign

0

1

0

1

X=00_H

X=FE_H

X=01_H

X=FF_H

ꢂꢃ

X=FE_H

X=00_H

X=FF_H

X=01_H

ꢂꢃ

HSW ABS REF SWAP

X address / bit / segment assign

0

1

0

X=00_H

X=FE_H

X=01_H

X=FF_H

ꢂꢃ

X=FE_H

X=00_H

X=FF_H

X=01_H

ꢂꢃ

HSW ABS REF SWAP

X address / bit / segment assign

0

1

0

1

0

1

X=00_H

X=FE_H

X=01_H

X=FF_H

ꢂꢃ

X=FE_H

X=00_H

X=FF_H

X=01_H

ꢂꢃ

HSW ABS REF SWAP

X address / bit / segment assign

0

1

0

1

0

X=00_H

X=FE_H

X=01_H

X=FF_H

ꢂꢃ

X=FE_H

X=00_H

X=FF_H

X=01_H

ꢂꢃ

- 31 -

NJU6825

SEGA 0

SEGB 0

SEGC 0

SEGA 1

SEGB 1

SEGC 1

SEGC 0

SEGB 0

SEGA 0

SEGC 1

SEGB 1

SEGA 1

SEGC 0

SEGB 0

SEGA 0

SEGC 1

SEGB 1

SEGA 1

SEGA 0

SEGB 0

SEGC 0

SEGA 1

SEGB 1

SEGC 1

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

SEGA 126

SEGB 126

SEGC 126

SEGA 127

SEGB 127

SEGC 127

SEGC 126

SEGB 126

SEGA 126

SEGC 127

SEGB 127

SEGA 127

SEGC 126

SEGB 126

SEGA 126

SEGC 127

SEGB 127

SEGA 127

SEGA 126

SEGB 126

SEGC 126

SEGA 127

SEGB 127

SEGC 127

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

- 32 -

NJU6825

Write and read data bit assignment (in the 16-bit data bus mode)

ABS=0

Write data

D₁₅

D₁₄

D₁₃

D₁₂

D₁₁

D₁₀

D₉

D₈

D₇

D₆

1

D₅

1

D₄

D₃

D₂

D₁

D₀

1

Read data

D₁₅

D₁₄

D₁₃

D₁₂

1

D₁₀

D₉

D₈

ABS=1

Write data

D₁₅

D₁₄

D₁₃

D₁₂

D₁₁

D₁₀

D₉

D₈

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

Read data

1

Examples for write and read display data (In 8 bit bus mode)

ABS=0, HSW=0, C256=0 (Address; 00, 02……FC,FE_H)

Write data

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

Read data

D₇

D₆

D₅

D₄

1

D₂

D₁

ABS=0, HSW=0, C256=0 (Address; 01,03……FD,FF_H)

Write data

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

1

Read data

D₇

1

D₄

D₃

D₂

ABS=1, HSW=0, C256=0 (Address; 00, 02……FC,FE_H)

Write data

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

Read data

1

D₃

D₂

D₁

ABS=1, HSW=0, C256=0 (Address; 01,03……FD,FF_H)

Write data

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

Read data

D₇

D₆

D₅

D₄

D₃

D₂

ABS=0, HSW=1, C256=0 (Address; 00, 01……BE,BF_H)

Write data

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

Read data

D₇

D₆

D₅

D₄

D₃

D₂

D₁

ABS=0, HSW=0, C256=1 (Address; 00, 01…… 7E ,7F_H)

Write data

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

Read data

D₇

D₆

D₅

D₄

D₃

D₂

D₁

- 33 -

NJU6825

(11) Gradation palette

In the gradation mode, variable or fixed gradation mode is selected by programming the “PWM” register in

the “Gradation control” instruction.

PWM=0:

PWM=1:

Variable gradation mode

(Select 16 gradation levels out of a palette consisting of 32-gradation levels)

Fixed gradation mode

(Fixed 8-gradation levels)

In the gradation mode, each of the gradation palettes Aj, Bj and Cj can select 16-gradation levels out of a

palette consisting of 32-gradation levels by setting 5-bit palette value into the “PA” registers in the “Gradation

palette j” instructions (j=0 to Fh).

The gradation palettes Aj correspond to the SEGAi, the Bj to SEGBj and the Cj to SEGCi (j=0 to 15, i=0 to

127).

- 34 -

NJU6825

The correspondence between display data and gradation palettes

Table 10 (Palette Aj, Palette Bj, Palette Cj (j=0 to 15))

(MSB) Display data (LSB)

Gradation palette

Palette 0

Palette 1

Palette 2

Palette 3

Palette 4

Palette 5

Palette 6

Palette 7

Palette 8

Palette 9

Palette10

Palette11

Palette12

Palette13

Palette14

Palette15

Default palette value

0 0 0 0 0

0 0 0 1 1

0 0 1 0 1

0 0 1 1 1

0 1 0 0 1

0 1 0 1 1

0 1 1 0 1

0 1 1 1 1

1 0 0 0 1

1 0 0 1 1

1 0 1 0 1

1 0 1 1 1

1 1 0 0 1

1 1 0 1 1

1 1 1 0 1

1 1 1 1 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Gradation palette table (PWM=”0”, MON=”0”, Variable gradation mode)

Table 11 (Palette Aj, Palette Bj, Palette Cj (j=0 to 15))

Palette

value

Gradation

level

Palette value

Gradation level

Gradation palette

Palette 0(default)

Gradation palette

0 0 0 0 0

0 0 0 0 1

0 0 0 1 0

0 0 0 1 1

0 0 1 0 0

0 0 1 0 1

0 0 1 1 0

0 0 1 1 1

0 1 0 0 0

0 1 0 0 1

0 1 0 1 0

0 1 0 1 1

0 1 1 0 0

0 1 1 0 1

0 1 1 1 0

0 1 1 1 1

0

1 0 0 0 0

1 0 0 0 1

1 0 0 1 0

1 0 0 1 1

1 0 1 0 0

1 0 1 0 1

1 0 1 1 0

1 0 1 1 1

1 1 0 0 0

1 1 0 0 1

1 1 0 1 0

1 1 0 1 1

1 1 1 0 0

1 1 1 0 1

1 1 1 1 0

1 1 1 1 1

16/31

17/31

18/31

19/31

20/31

21/31

22/31

23/31

24/31

25/31

26/31

27/31

28/31

29/31

30/31

31/31

1/31

2/31

3/31

4/31

5/31

6/31

7/31

8/31

9/31

10/31

11/31

12/31

13/31

14/31

15/31

Palette 0(default)8

Palette 9(default)

Palette 10(default)

Palette 11(default)

Palette 12(default)

Palette 13(default)

Palette 14(default)

Palette 15(default)

Palette 1(default)

Palette 2(default)

Palette 3(default)

Palette 4(default)

Palette 5(default)

Palette 6(default)

Palette 7(default)

- 35 -

NJU6825

Gradation palette table (PWM=”1”, MON=”0”, Fixed gradation mode)

Table 12 8-gradation segment drivers

Gradation

level

(MSB) Display data (LSB)

Gradation level

0/7

(MSB) Display data (LSB)

0/7

0

*

0

*

0

1

0

1

0

1

0

1

0

1

0

1

*

1/7

2/7

3/7

4/7

5/7

6/7

7/7

0

1

0

1

0

1

*

3/7

5/7

7/7

The correspondence between display data and gradation level (MON=”1”, B&W mode)

Table 13

Gradation

level

(MSB) Display data (LSB)

0

1

*

0

1

*:Don’t care

- 36 -

NJU6825

(12) Gradation control and display data

(12-1)Gradation mode

In the graduation mode, each pixel for RGB corresponds to the successive 3 segment drivers that

consist of 3 segment drivers for 16-graduation, so that NJU6825 can drive a 4096-color display (16-

gradation x 16-gradation x 16-gradation = 4-bit x 4-bit x 4-bit) with up to 128x162 pixels. The 16-gradation

segment drivers can generate 16-gradation levels controlled by using 4-bit of display data in the DDRAM.

In addition, the LSI can transfer 16-bit display data for 1-pixel RGB by one-time access or 8-bit by two-

time access. The display data assignments for the gradation palettes and segment drivers vary in

accordance with the setting for the “SWAP” bit and “REF” bit in the "Display control (2)" instruction.

(REF, SWAP)=(0, 0) or (1, 1)

SEGAi

SEGBi

SEGCi

Gradation palette

j=0 to 15

Paltte Aj

Palette Bj

Palette Cj

Gradation control circuit

Display data in DDRAM

1

0

LSB

MSB LSB

MSB

Display data from MPU

0

D₄

D₀

D₄

*

0

1

D₇

D₄

D₀

*

1

D₂

D₁

D₅

*

1

D₇

D₆

D₅

D₁

D₅

D₂

D₇

D₃

D₄

D₁

D₆

D₂

D₃

D₀

D₅

D₁

D₂

D₄

D₃

D₇

D₁

D₃

D₂

D₆

D₀

D₁

D₀)

D₄)

* )

Column address:2n_H:2n+1_H

ABS=1

HSW=1

C256=1

(D₃D₂

(D₇D₆

Note) DDRAM column address

:2n_H,2n_H+1_H

:FE_H-2n_H, FF_H-(2n_H+1_H)

In HSW=1; 00_Hto BF_H,In C256=1; 00_Hto 7F_H

(REF=”0”)

(REF=”1”)

- 37 -

NJU6825

(REF, SWAP)=(0, 1) or (1, 0)

SEGAi

SEGBi

SEGCi

(i=0 to 127)

Gradation palette

j=0 to 15

Palette Aj

Palette Bj

Palette Cj

Gradation control circuit

Display data in DDRAM

1

0

1

0

1

0

1

0

LSB

MSB LSB

MSB

Display data from MPU

0

1

Column address:2n_H:2n+1_H

D₇

(D₃D₂

(D₇D₆

D₆

D₅

D₁

D₅

D₄

D₀

D₄

D₂

D₇

D₃

D₁

D₆

D₂

D₀

D₅

D₁

D₇

D₄

D₀

D₄

D₃

D₇

D₃

D₂

D₆

D₂

D₁

D₅

D₁

D₀)

D₄)

ABS=1

HSW=1

C256=1

(D₇D₆

D₅

*

D₄

D₃

D₂

*

D₁

D₀

*

* )

Note) DDRAM column address

: 2n_H,2n_H+1_H

: FE_H-2n_H, FF_H-(2n_H+1_H)

In HSW=1; 00_Hto BF_H,In C256=; 00_Hto 7F_H

(REF=”0”)

(REF=”1”)

In the 16-bit data bus mode, the display data assignments for the gradation palettes and segment

drivers vary in accordance with the setting for the “SWAP” and “REF” bit in the "Display control (2)"

instruction as well as the assignment in the 8-bit data bus mode.

(REF, SWAP)=(0, 0) or (1, 1)

SEGAi

SEGBi

SEGCi

(i=0 to 127)

Gradation palette

j=0 to 15

Palette Aj

Palette Bj

Palette Cj

Gradation control circuit

Display data in DDRAM

0

1

MSB

LSB MSB

LSB

Display data from MPU

0

1

D₁₅D₁₄D₁₃D₁₂D₁₀D₉

D₈

D₇

D₄

D₃

D₂

D₁

Column address; n_H

(D₁₁D₁₀D₉D₈D₇D₆

D₅

D₄

D₃

D₂

D₁

D₀)

ABS=1

Note) DDRAM column address

:n_H

(REF=”0”)

:7F_H- n_H(REF=”1”)

- 38 -

NJU6825

(REF, SWAP)=(0, 1) or (1, 0)

SEGAi

SEGBi

SEGCi

i=0 to 127

Gradation palette

j=0 to 15

Palette Aj

Palette Bj

Palette Cj

Gradation control circuit

Display data in DDRAM

1

0

1

0

1

0

1

0

1

0

LSB

MSB LSB

MSB

Display data from MPU

0

1

D₁₅D₁₄D₁₃D₁₂D₁₀D₉

D₈

D₅

D₇

D₄

D₃

D₂

D₁

Column address ; n_H

(D₁₁D₁₀D₉

D₈

D₇

D₆

D₀)

ABS=1

Note) DDRAM column address

:n_H

(REF=”0”)

:7F_H-n_H(REF=”1”)

- 39 -

NJU6825

(12-2)B&W mode (MON=”1”)

In the B&W mode, only 3 of MSB of each display data are used for the display by the 16-bit data bus

mode and 8-bit.

(REF, SWAP)=(0, 0) or (1, 1)

SEGAi

SEGBi

SEGCi

(i=0 to 127)

Gradation palette

j=0 to 15

Palette Aj

Palette Bj

Palette Cj

Gradation control circuit

Display data in DDRAM

0

1

MSB

LSB MSB

LSB

Display data in DDRAM

0

1

D₁₅D₁₄D₁₃D₁₂D₁₀D₉

(D₁₁D₁₀D₉D₈D₇D₆

: n_H

D₈

D₅

D₇

D₄

D₃

D₂

D₁

D₀)

Column address; n_H

ABS=1

Note) DDRAM column address

(REF=”0”)

(REF=”1”)

: 7F_H-n_H

(REF, SWAP)=(0, 1) or (1, 0)

SEGAi

SEGBi

SEGCi

(i=0 to 127)

Gradation palette

j=0 to 15

Palette Aj

Palette Bj

Palette Cj

Gradation control circuit

Display data in DDRAM

1

0

1

0

1

0

1

0

1

0

LSB

MSB LSB

MSB

Display data in DDRAM

0

1

D₁₅D₁₄D₁₃D₁₂D₁₀D₉

(D₁₁D₁₀D₉D₈D₇D₆

D₈

D₅

D₇

D₄

D₃

D₂

D₁

Column address; n_H

D₀)

ABS=1

Note ) DDRAM column address

: n_H

: 7F_H-n_H

(REF=”0”)

(REF=”1”)

- 40 -

NJU6825

(13) Display timing generator

The display-timing generator creates the timing pulses such as the CL, FLM, FR and CLK by dividing the

oscillation frequency oscillate an external or internal resister mode. The each of timing pulses is outputted

through the each output terminals by “SON” = 1.

(14) LCD line clock (CL)

The LCD line clock (CL) is used as the count-up signal for the line counter and the latch signal for the data

latch circuit. At the rising edge of the CL signal, the line counter is counted-up and the 384-bit display data,

corresponding to the counted-up line address, is latched into the data latch circuit. And at the falling edge of the

CL signal, the latched data output onto the segment drivers. The read out operation from DDRAM to the latch

is completely independent from the MPU accessing. Therefore, MPU can access to the LSI regardless the

internal operation.

(15) LCD alternate signal (FR) and LCD synchronous signal (FLM)

Both of the FR and FLM signals are created from the CL signal. The FR signal is used to alternate inverse

driving for the LCD panel. It can be programmed so that the FR signal is toggle on every frame in the default

setting or once every N frames in the N-line inversion mode. The FLM signal is used to indicate the start line of

a new display frame. It presets an initial display line address into the line counter when the FLM signal

becomes ”1”.

(16) Data latch circuit

The data latch circuit is used temporarily store the display data that will output to the segment drivers. The

display data in this circuit is updated in synchronization of the CL signal.

The “All pixels ON/OFF”, “Display ON/OFF” and “Reverse display ON/OFF” instructions change the display

data in this circuit but do not change the display data in the DDRAM.

- 41 -

NJU6825

LCD Driving waveforms (Reverse display OFF, 1/163 duty, B&W mode)

COM₀

1

2

3

4

5

1

2

3

4

5

1

163

COM₁

CL

FLM

FR

V_LCD

V₁

V₂

V₃

COM₀

V₄

V_SS

V_LCD

V₁

V₂

V₃

V₄

V_SS

COM₁

SEG₀

V_LCD

V₁

V₂

V₃

V₄

V_SS

V_LCD

V₁

V₂

SEG₁

V₃

V₄

V_SS

Fig 8

- 42 -

NJU6825

(17) Common and segment drivers

The LSI includes 384-segment drivers and 162-common drivers for a graphic display. The common drivers

generate the LCD driving waveforms composed of the V_LCD, V₁, V₄and V_SSin accordance with the FR signal

and scanning data. The segment drivers generate the waveforms composed of the V_LCD, V₂, V₃and V_SSin

accordance with the FR signal and display data.

(18) Oscillator

The oscillator generates the internal clock for the display timing and voltage booster. The C and R for the

oscillator are on chipped, therefore, there is no C, R required as an external components. Use an external R

instead of internal R is also available, in this time connect the resister between OSC₁and OSC₂terminals.

However, when the internal oscillator is not used, an external clock, which duty should be 50%, inputs onto the

OSC₁terminal.

In addition, the value of the feed back resister for the oscillator can be varied by programming the “Rf”

register in the “Frequency control” instruction so that it is possible to optimize the frame frequency for a LCD

panel.

[Setting of MON and PWL in the external oscillation mode]

MON and PWL in the external oscillation mode. (CKS=1)

ꢄIn case of the external oscillation mode

Symbol

MON PWL

Display mode

FR1

FR2

FR3

0

1

0

1

*

Variable gradation mode

Fixed gradation mode

B&W mode

*: Don’t care

ꢅIn case of the external clock input mode

In case of the external clock input operation, on clock frequency as same as the frequency of external

resistor oscillation mode should be input display on a display mode. And also MON and PWL require

making same conditions. Because the frame frequency and the internal voltage booster circuit operation

frequency are determined by the external clock frequency and conditions of MON and PWL.

(19) Power supply circuits

The internal power supply circuits are composed of the voltage booster, electrical variable resister (EVR),

voltage regulator, reference voltage generator and voltage followers.

The status of the power supply circuits is arranged by programming the “DCON” and “AMPON” registers in

the “Power control” instruction. For this arrangement, the part of the internal power supply circuits can be used

in combination with an external power supply as described in the following table.

Table 14

Voltage followers

DCON

AMPON

Voltage booster

Voltage regulator

EVR

External voltage

Note

0

1

0

1

Disable

Enable

Disable

Enable

1, 3

2, 3

−

V

_OUT, V_LCD, V₁, V₂, V₃, V₄

V_OUT

−

Note1) The internal power circuits are not used. The C₁+, C₁-, C₂+, C₂-, C₃+, C₃-, C₄+, C₄-, C₅+, C₅-, C₆+, C₆-,

V_OUT, V_REF, V_REGand V_EEterminals should be open.

Note2) The internal power circuits are used, excluding the voltage booster. The external V_OUTvoltage is required

and the C₁+, C₁-, C₂+, C₂-, C₃+, C₃-, C₄+, C₄-, C₅+, C₅-, C₆+, C₆- and V_EEterminals should be open. The

reference voltage is required into V_REFterminal.

Note3) The relation among the voltages should be maintained.

V_OUT≥ V_LCD≥ V₁≥ V₂≥ V₃≥ V₄≥ V_SS

- 43 -

NJU6825

(20) Voltage booster

The voltage booster generates maximum 7x voltage of the V_EElevel. It is programmed so that the boost level

can be selected out of 1x, 2x, 3x, 4x, 5x, 6x and 7x by the “Boost level select” instruction. The boosted voltage

V_OUTmust not exceed beyond 18.0V, otherwise the voltage stress may cause a permanent damage to the LSI.

Boosted voltages

V_OUT=17.5V

V_OUT=9V

V_EE=2.5V

V_SS=0V

V_EE=3V

V_SS=0V

7-time boost

5-time boost

3-time boost

Capacitor connections for the voltage Booster

7-time boost

6-time boost

C₁+

C₁-

C₂+

C₂-

C₃+

C₃-

C₄+

C₄-

C₅+

C₅-

C₆+

C₆-

C₁+

C₁-

C₂+

C₂-

C₃+

C₃-

C₄+

C₄-

C₅+

C₅-

C₆+

C₆-

C₁+

C₁-

C₂+

C₂-

C₃+

C₃-

C₄+

C₄-

C₅+

C₅-

C₆+

C₆-

+

V_OUT

+

4-time boost

3-time boost

2-time boost

C₁+

C₁-

C₂+

C₂-

C₃+

C₃-

C₁+

C₁-

C₂+

C₂-

C₃+

C₃-

C₁+

C₁-

C₂+

C₂-

C₃+

C₃-

+

C₄+

C₄-

C₄+

C₄-

C₄+

C₄-

C₅+

C₅-

C₅+

C₅-

C₅+

C₅-

C₆+

C₆-

C₆+

C₆-

C₆+

C₆-

V_OUT

+

Fig 9

- 44 -

NJU6825

(21) Reference voltage generator

The reference voltage generator is used to produce the reference voltage (V_BA) that is output from the V_BA

terminal and input to the V_REFterminal.

V_BA= V_EEx 0.9

(22) Voltage regulator

The voltage regulator, composed of the gain control circuit and operational amplifier, is used to gain the

reference voltage (V_REF) and create the regulated voltage (V_REG). The V_REGis used for the input voltage for the

EVR by programming the “VU” register in the “Boost level” instruction.

V_REG= V_REFx N

(N: register value for the boost level)

(23) Electrical variable resister (EVR)

The EVR, variable with 128-step, is used to fine-tune the LCD driving voltage (V_LCD) by programming the “DV”

register in the “EVR control” instruction, so that it is possible to optimize the contrast level for a LCD panel.

V_LCD= 0.5 x V_REG+ M (V_REG- 0.5 x V_REG) / 127 (M: register value for the EVR)

(24) Voltage followers

The voltage followers are used to stabilize the LCD driving voltages (V₁to V₄and V_LCD) produced by the

internal bleeder resisters.

In case that the voltage followers are used, the capacitor CA₂for the V_LCD, V₁, V₂, V₃and V₄terminals are

required in order to stabilize the LCD driving voltages and the capacitor CA₃for the V_REGterminal to stabilize

the reference voltage. It can be programmed to select the LCD bias ratio out of 1/5, 1/6, 1/7, 1/8, 1/9, 1/10, 1/11

and 1/12 by the “LCD bias ratio” instruction.

In case that the external power supply is used, the internal power supply circuits is required to being disabled

by setting “0” into the “DCON” and “AMPON” registers in the “Power control” instruction and the external LCD

driving voltages should be supplied onto the V₁to V₄, V_LCDand V_OUTterminals.

- 45 -

NJU6825

Capacitor connections for the voltage booster

All of the internal power supply circuits

(7-time boost)

None of the internal power supply circuits

V_DD

V_EE

V_BA

V_REF

V_REG

CA₃

V_REG

CA₃

V_SS

C₁-

C₁+

C₂-

C₂+

C₃-

C₃+

CA₁

C₁+

C₂-

CA₁

C₂+

C₃-

CA₁

C₃+

C₄-

NJU6825

CA₁

NJU6825

C₄+

C₅-

CA₁

C₅+

C₆-

CA₁

C₆+

V_OUT

CA₁

V_SS

V_LCD

CA₂

V_LCD

V₁

V_LCD

V₁

External

Power

circuit

CA₂

V₂

V₃

V₄

V₂

CA₂

V₃

CA₂

V₄

V₃

V₄

V_SS

CA₂

Fig 10

Fig11

Reference values

CA₁

CA₂

CA₃

1.0 to 4.7µF

1.0 to 2.2µF

0.1µF

Note) B grade capacitors are required.

- 46 -

NJU6825

The internal power supply circuits

Excluding the reference voltage generator(1)

(7-time boost)

The internal power supply circuit

Excluding the reference voltage generator(2)

(7-time boost, temperature compensation)

V_DD

V_EE

V_BA

V_REF

V_EE

V_BA

V_REF

V_REG

CA₃

V_SS

CA₃

V_SS

C₁-

CA₁

C₁+

CA₁

C₁+

C₂-

CA₁

C₂-

CA₁

C₂+

C₃-

CA₁

C₃-

CA₁

C₃+

C₄-

CA₁

NJU6825

C₄+

C₅-

CA₁

C₅-

CA₁

C₅+

C₆-

CA₁

C₆-

CA₁

C₆+

V_OUT

CA₁

V_SS

V_LCD

CA₂

V_LCD

CA₂

V₁

CA₂

V₂

CA₂

V₃

CA₂

V₄

CA₂

V_SS

CA₂

V_SS

Fig 12

Fig 13

Reference value

CA₁

CA₂

CA₃

1.0 to 4.7µF

1.0 to 2.2µF

0.1µF

Note) B grade capacitors are required.

- 47 -

NJU6825

The internal power supply circuits

Excluding the voltage booster

V_DD

V_EE

V_BA

CA₃

V_REF

V_REG

CA₃

V_SS

C₁-

C₁+

C₂-

C₂+

C₃-

C₃+

C₄-

NJU6825

C₄+

C₅-

C₅+

C₆-

External

power

circuit

C₆+

V_OUT

V_LCD

V₁

CA₂

V₂

CA₂

V₃

V₄

CA₂

V_SS

Fig 14

Reference value

CA₁

CA₂

CA₃

1.0 to 4.7µF

1.0 to 2.2µF

0.1µF

Note) B grade capacitors are required.

- 48 -

NJU6825

(25) Partial display function

The partial display function is used to specify the partial display area on a LCD panel in the condition of lower

duty cycle ratio, lower LCD bias ratio, lower boost level and lower LCD driving voltage, so that it is possible to

display a time and calendar in the extremely low power consumption. It can be programmed to select a duty

cycle ratio (1/16, 1/24, 1/32, 1/40, 1/48, 1/56, 1/64, 1/72, 1/80, 1/96, 1/112, 1/128, 1/133, 1/144, 1/160, 1/163),

LCD bias ratio, boost level and EVR value by the instructions so that it is possible to optimize the LSI condition

in accordance with the display status.

Partial display image

NJRC

LCD DRIVER

Low Power and

Low Voltage

LCD DRIVER

Partial display

Normal display

Partial display sequence

Optional status

Display OFF (ON/OFF=”0”)

Internal Power supply OFF (DCON=”0”, AMPON=”0”)

WAIT

Setting for LCD driving voltage-related functions

Internal Power supply ON (DCON=”1”, AMPON=”1”)

- Boost level

- EVR value

- LCD bias ratio

WAIT

- Duty cycle ratio

- Initial display line

- Initial COM line

- Other instructions

Setting for display-related functions

Display ON (ON/OFF =”1”)

Partial display Status

- 49 -

NJU6825

(26) Discharge circuit

The discharge circuit is used to discharge the electric charge in the capacitors connected to the V₁to V₄and

V_LCDterminals. It is activated by setting “0” into the “DIS” register in the “Discharge” instruction or by setting

“RES” terminal to ”0” level. The “Discharge ON/OFF” instruction is usually required just after the internal power

supply is turned off by setting “0” into the “DCON” and “AMPON” registers, or just after the external power

supply is turned off. During the discharge operation, it is required that no supply the power neither from an

internal or external power supply to the LSI.

(27) Reset circuit

The reset circuit initializes the LSI into the following default status. It is activated by setting the RES terminal

to “0” level. The RES terminal is usually required to connect to the MPU’s reset terminal in order that the LSI

can be initialized at the same timing of the MPU reset.

ꢀꢀ Default status

1. DDRAM display data

2. column address

:Undefined

:(00)_H

3. row address

:(00)_H

4. Initial display line

5. Display ON/OFF

6. Reverse display ON/OFF

7. Duty cycle ratio

:(0)_H(1st line)

:OFF

:OFF (normal)

:1/163 duty

8. N-line Inversion ON/OFF

9. COM scan direction

10. Increment mode

:OFF

:COM₀→ COM₁₆₁

:OFF

11. Reverse SEG direction

12. SWAP mode

13. EVR value

14. Internal power supply

15. Display mode

16. LCD bias ratio

:OFF (normal)

:(0, 0, 0, 0, 0, 0, 0)

:OFF

:Gradation display mode

:1/9 bias

17. Gradation Palette 0

18. Gradation Palette 1

19. Gradation Palette 2

20. Gradation Palette 3

21. Gradation Palette 4

22. Gradation Palette 5

23. Gradation Palette 6

24. Gradation Palette 7

25. Gradation Palette 8

26. Gradation Palette 9

27. Gradation Palette 10

28. Gradation Palette 11

29. Gradation Palette 12

30. Gradation Palette 13

31. Gradation Palette 14

32. Gradation Palette 15

33. Gradation mode control

34. Data bus length

:(0, 0, 0, 0, 0)

:(0, 0, 0, 1, 1)

:(0, 0, 1, 0, 1)

:(0, 0, 1, 1, 1)

:(0, 1, 0, 0, 1)

:(0, 1, 0, 1, 1)

:(0, 1, 1, 0, 1)

:(0, 1, 1, 1, 1)

:(1, 0, 0, 0, 1)

:(1, 0, 0, 1, 1)

:(1, 0, 1, 0, 1)

:(1, 0, 1, 1, 1)

:(1, 1, 0, 0, 1)

:(1, 1, 0, 1, 1)

:(1, 1, 1, 0, 1)

:(1, 1, 1, 1, 1)

:Variable gradation mode

:8-bit data bus length

:OFF

35. Discharge circuit

- 50 -

NJU6825

(28) Power supply ON/OFF sequences

The following paragraphs describes the power supply ON/OFF sequences to prevent high current flowing into

the LSI, otherwise the current may cause a permanent damage to the LSI.

(28-1)Using an external power supply

ꢁPower supply ON sequence

The logic voltage (V_DD) is turned on first, and then the LCD driving voltages (V₁to V₄and V_LCD) can

be turned on. When supply the V_OUTfrom outside, turn on the logic voltage (V_DD), then reset, after

then supply the V_OUTis required.

ꢁPower supply OFF sequence

The reset operation, cut off the V₁to V₄and V_LCDfrom the LSI by the RES terminal or the “Power

control” instruction first, and then the V_DDcan be turned off. It is recommended that a series-resister

between 50 ohms and 100 ohms is inserted in the V_LCDline (or V_OUTline in case of using only an

external V_OUTvoltage) in order to protect the LSI from an over current.

(28-2)Using the internal power supply circuits

ꢁPower supply ON sequence

The V_DDis turned on and the reset operation is required first, and then the V₁to V₄and V_LCDcan be

turned on by setting “1” into the “DCON” and “AMPON” registers in the “Power control” instruction.

ꢁPower supply OFF sequence

The reset operation is required first in order to cut off the V1 to V4 and V_LCDfrom the LSI, and then

the input voltage for the voltage booster (V_EE) and the V_DDcan be turned off.

In case that the V_EEand V_DDare supplied from deferent voltage sources, the V_EEis required to be

turned off first, and then the V_DDcan be turned off.

- 51 -

NJU6825

(29) Referential instruction sequences

(29-1)Initialization in using the internal power supply circuits

V_DD, V_EEpower ON

Wait for power-ON stabilization

RESET Input

WAIT

Setting for LCD driving voltage-related functions

End of initialization

- EVR value

- LCD bias ratio

- Power control (DCON=”1”, AMPON=”1”)

(29-2)Display data writing

End of Initialization

Setting for display-related functions

- Initial display line

- Increment mode

- column address

- row address

Display data write

Display ON (ON/OFF =”1”)

- 52 -

NJU6825

(29-3)Power OFF

Optional status

- All COM/SEG output V_SSlevel.

Power save or reset operation

Discharge ON

WAIT

V_EE, V_DDpower OFF

- 53 -

NJU6825

(30) Instruction table

Instruction Table (1)

Code (80 series MPU I/F)

Code

Functions

Instructions

CS RS RD WR RE₂RE₁RE₀D₇D₆D₅D₄D₃

D₂

D₁

D₀

Display data write

0

1

0

1

0

1

0

0/1 0/1 0/1

Write Data

Read Data

Write display data to DDRAM

Read display data from DDRAM

DDRAM column address

DDRAM row address

Display data read

column address

AX3

AX7

AY3

AY7

LA3

LA7

N3

AX2

AX6

AY2

AY6

LA2

LA6

N2

AX1

AX5

AY1

AY5

LA1

LA5

N1

AX0

AX4

AY0

AY4

LA0

LA4

N0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

(Lower) [0_H]

column address

(Upper) [1_H]

row address

(Lower) [2_H]

row address

(Upper) [3_H]

DDRAM row address

Initial display line

(Lower) [4_H]

Sets row address corresponding to

initial COM line (scan-starting line)

Initial display line

(Upper) [5_H]

Sets row address corresponding to

initial COM line (scan-starting line)

N-line inversion

(Lower) [6_H]

Sets the number of N-line inversion

N-line inversion

(Upper) [7_H]

N7

N6

N5

N4

Sets the number of N-line inversion

SHIFT: Common direction

Display control (1)

Display control (2)

ALL

ON

ON/ MON: Gradation or B/W display mode

SHIFT MON

0

1

0

1

0

1

OFF

ALLON: All pixels ON/OFF

ON/OFF: Display ON/OFF

REV: Reverse display ON/OFF

NLIN: N-line inversion ON/OFF,

SWAP: SWAP mode ON/OFF

REF: Segment direction

[8_H]

[9_H]

REV NLIN SWAP REF

WIN: Window end column and row

addresses

Increment control

Power control

WIN AIM

AYI

AXI

AIM: Read-modify-write ON/OFF

AYI: row increment mode

AXI: column increment mode

AMPON: Voltage followers ON/OFF

HALT: Power save ON/OFF

DCON: Voltage booster ON/OFF

ACL: Reset

0

1

0

1

0

1

0

1

[A_H]

[B_H]

AMP

HALT

ON

DC

ON

ACL

Duty cycle ratio

Boost level

DS3 DS2 DS1 DS0

0

1

0

1

0

1

0

1

0

1

Sets LCD duty cycle ratio

Sets boost level

[C_H]

[D_H]

[E_H]

[F_H]

VU2 VU1 VU0

*

LCD bias ratio

RE register

B2

B1

B0

Sets LCD bias ratio

RE flag set

TST₀RE₂RE₁RE₀

0/1 0/1 0/1

Note 1)

Note 2) [ ]

Note 3)

*

: Don’t care.

: Instruction register address

The dual instructions including upper and lower bytes is enabled after either upper or lower

bytes are set into the register. The only “EVR control” instruction is enabled after both of the

upper and lower bytes are set.

- 54 -

NJU6825

Instruction Table (2)

Code (80 series MPU I/F)

Code

Instructions

Functions

CS RS RD WR RE₂RE₁RE₀D₇D₆D₅D₄D₃D₂D₁D₀

Gradation palette A0/A8

(Lower) [0_H]

Sets palette values to gradation

palette A0(PS=0)/A8(PS=1)

PA03/ PA02/ PA01/ PA00/

PA83 PA82 PA81 PA80

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Gradation palette A0/A8

(Upper) [1_H]

Sets palette values to gradation

palette A0(PS=0)/A8(PS=1)

PA04/

PA84

*

Gradation palette A1/A9

(Lower) [2_H]

Sets palette values to gradation

palette A1(PS=0)/A9(PS=1)

PA13/ PA12/ PA11/ PA10/

PA93 PA92 PA91 PA90

Gradation palette A1/A9

(Upper) [3_H]

Sets palette values to gradation

palette A1(PS=0)/A9(PS=1)

PA14/

PA94

*

Gradation palette A2/A10

(Lower) [4_H]

Sets palette values to gradation

palette A2(PS=0)/A10(PS=1)

PA23/ PA22/ PA21/ PA20/

PA103 PA102 PA101 PA100

Gradation palette A2/A10

(Upper) [5_H]

Sets palette values to gradation

palette A2(PS=0)/A10(PS=1)

PA24/

PA104

*

Gradation palette A3/A11

(Lower) [6_H]

Sets palette values to gradation

palette A3(PS=0)/A11(PS=1)

PA33/ PA32/ PA31/ PA30/

PA113 PA112 PA111 PA110

Gradation palette A3/A11

(Upper) [7_H]

Sets palette values to gradation

palette A3(PS=0)/A11(PS=1)

PA34/

PA114

*

Gradation palette A4/A12

(Lower) [8_H]

Sets palette values to gradation

palette A4(PS=0)/A12(PS=1)

PA43/ PA42/ PA41/ PA40/

PA123 PA122 PA121 PA120

Gradation palette A4/A12

(Upper) [9_H]

Sets palette values to gradation

palette A4(PS=0)/A12(PS=1)

PA44/

PA124

*

Gradation palette A5/A13

(Lower) [A_H]

Sets palette values to gradation

palette A5(PS=0)/A13(PS=1)

PA53/ PA52/ PA51/ PA50/

PA133 PA132 PA131 PA130

Gradation palette A5/A13

(Upper) [B_H]

Sets palette values to gradation

palette A5(PS=0)/A13(PS=1)

PA54/

PA134

*

Gradation palette A6/A14

(Lower) [C_H]

Sets palette values to gradation

palette A6(PS=0)/A14(PS=1)

PA63/ PA62/ PA61/ PA60/

PA143 PA142 PA141 PA140

Gradation palette A6/A14

(Upper) [D_H]

Sets palette values to gradation

palette A6(PS=0)/A14(PS=1)

PA64/

PA144

*

RE register

[F_H]

TST₀RE₂RE₁RE₀

0/1 0/1 0/1

RE flag set

Note 1)

Note 2) [ ]

Note 3)

*

: Don’t care.

: Instruction register address

The dual instructions including upper and lower bytes is enabled after either upper or lower

bytes are set into the register. The only “EVR control” instruction is enabled after both of the

upper and lower bytes are set.

- 55 -

NJU6825

Instruction Table (3)

Instructions

Code (80 series MPU I/F)

Code

Functions

CS RS RD WR RE₂RE₁RE₀D₇D₆D₅D₄D₃D₂D₁D₀

Gradation palette A7/A15

(Lower) [0_H]

Sets palette values to gradation

palette A7(PS=0)/A15(PS=1)

PA73/ PA72/ PA71/ PA70/

PA153 PA152 PA151 PA150

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Gradation palette A7/A15

(Upper) [1_H]

Sets palette values to gradation

palette A7(PS=0)/A15(PS=1)

PA74/

PA154

*

Gradation palette B0/B8

(Lower) [2_H]

Sets palette values to gradation

palette B0(PS=0)/B8(PS=1)

PB03/ PB02/ PB01/ PB00/

PB83 PB82 PB81 PB80

Gradation palette B0/B8

(Upper) [3_H]

Sets palette values to gradation

palette B0(PS=0)/B8(PS=1)

PB04/

PG84

*

Gradation palette B1/B9

(Lower) [4_H]

Sets palette values to gradation

palette B1(PS=0)/B9(PS=1)

PB13/ PB12/ PB11/ PB10/

PB93 PB92 PB91 PB90

Gradation palette B1/B9

(Upper) [5_H]

Sets palette values to gradation

palette B1(PS=0)/B9(PS=1)

PB14/

PB94

*

Gradation palette B2/B10

(Lower) [6_H]

Sets palette values to gradation

palette B2(PS=0)/B10(PS=1)

PB23/ PB22/ PB21/ PB20/

PB103 PB102 PB101 PB100

Gradation palette B2/B10

(Upper) [7_H]

Sets palette values to gradation

palette B2(PS=0)/B10(PS=1)

PB24/

PB104

*

Gradation palette B3/B11

(Lower) [8_H]

Sets palette values to gradation

palette B3(PS=0)/B11(PS=1)

PB33/ PB32/ PB31/ PB30/

PB113 PB112 PB111 PB110

Gradation palette B3/B11

(Upper) [9_H]

Sets palette values to gradation

palette B3(PS=0)/B11(PS=1)

PB34/

PB114

*

Gradation palette B4/B12

(Lower) [A_H]

Sets palette values to gradation

palette B4(PS=0)/B12(PS=1)

PB43/ PB42/ PB41/ PB40/

PB123 PB122 PB121 PB120

Gradation palette B4/B12

(Upper) [B_H]

Sets palette values to gradation

palette B4(PS=0)/B12(PS=1)

PB44/

PB124

*

Gradation palette B5/B13

(Lower) [C_H]

Sets palette values to gradation

palette B5(PS=0)/B13(PS=1)

PB53/ PB52/ PB51/ PB50/

PB133 PB132 PB131 PB130

Gradation palette B5/B13

(Upper) [D_H]

Sets palette values to gradation

palette B5(PS=0)/B13(PS=1)

PB54/

PB134

*

RE register

[F_H]

TST₀RE₂RE₁RE₀

0/1 0/1 0/1

RE flag set

Note 1)

Note 2) [ ]

Note 3)

*

: Don’t care.

: Instruction register address

The dual instructions including upper and lower bytes is enabled after either upper or lower

bytes are set into the register. The only “EVR control” instruction is enabled after both of the

upper and lower bytes are set.

- 56 -

NJU6825

Instruction Table (4)

Code (80 series MPU I/F)

Code

Instructions

Functions

CS RS RD WR RE₂RE₁RE₀D₇

D₆

0

D₅

0

D₄

D₃D₂

D₁D₀

Gradation palette B6/B14

(Lower) [0_H]

Sets palette values to gradation

palette B6(PS=0)/B14(PS=1)

PB63/ PB62/ PB61/ PB60/

PB143 PB142 PB141 PB140

0

1

0

1

0

1

0

Gradation palette B6/B14

(Upper) [1_H]

Sets palette values to gradation

palette B6(PS=0)/B14(PS=1)

PB64/

PB144

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

*

Gradation palette B7/B15

(Lower) [2_H]

Sets palette values to gradation

palette B7(PS=0)/B15(PS=1)

PB73/ PB72/ PB71/ PB70/

PB153 PB152 PB151 PB150

Gradation palette B7/B15

(Upper) [3_H]

Sets palette values to gradation

palette B7(PS=0)/B15(PS=1)

PB74/

PB154

*

Gradation palette C0/C8

(Lower) [4_H]

Sets palette values to gradation

palette C0(PS=0)/C8(PS=1)

PC03/ PC02/ PC01/ PC00/

PC83 PC82 PC81 PC80

Gradation palette C0/C8

(Upper) [5_H]

Sets palette values to gradation

palette C0(PS=0)/C8(PS=1)

PC04/

PC84

*

Gradation palette C1/C9

(Lower) [6_H]

Sets palette values to gradation

palette C1(PS=0)/C9(PS=1)

PC13/ PC12/ PC11/ PC10/

PC93 PC92 PC91 PC90

Gradation palette C1/C9

(Upper) [7_H]

Sets palette values to gradation

palette C1(PS=0)/C9(PS=1)

PC14/

PC94

*

Gradation palette C2/C10

(Lower) [8_H]

Sets palette values to gradation

palette C2(PS=0)/C10(PS=1)

PC23/ PC22/ PC21/ PC20/

PC103 PC102 PC101 PC100

Gradation palette C2/C10

(Upper) [9_H]

Sets palette values to gradation

palette C2(PS=0)/C10(PS=1)

PC24/

PC104

*

Gradation palette C3/C11

(Lower) [A_H]

Sets palette values to gradation

palette C3(PS=0)/C11(PS=1)

PC33P PC32/ PC31/ PC30/

C113 PC112 PC111 PC110

Gradation palette C3/C11

(Upper) [B_H]

Sets palette values to gradation

palette C3(PS=0)/C11(PS=1)

PC34/

PC114

*

Gradation palette C4/C12

(Lower) [C_H]

Sets palette values to gradation

palette C4(PS=0)/C12(PS=1)

PC43/ PC42/ PC41/ PC40/

PC123 PC122 PC121 PC120

Gradation palette C4/C12

(Upper) [D_H]

Sets palette values to gradation

palette C4(PS=0)/C12(PS=1)

PC44/

PC124

*

RE register

[F_H]

TST₀RE₂RE₁RE₀

0/1 0/1 0/1

RE flag set

Note 1)

Note 2) [ ]

Note 3)

*

: Don’t care.

: Instruction register address

The dual instructions including upper and lower bytes is enabled after either upper or lower

bytes are set into the register. The only “EVR control” instruction is enabled after both of the

upper and lower bytes are set.

- 57 -

NJU6825

Instruction Table (5)

Instructions

Code (80 series MPU I/F)

Code

Functions

CS RS RD WR RE₂RE₁RE₀D₇D₆D₅D₄D₃D₂D₁D₀

Gradation palette C5/C13

(Lower) [0_H]

Sets palette values to gradation

palette C5(PS=0)/C13(PS=1)

PC53/ PC52/ PC51/ PC50/

PC133 PC132 PC131 PC130

0

1

0

1

0

1

*

0

1

0

1

*

0

1

0

1

0

1

0

1

0

*

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

*

Gradation palette C5/C13

(Upper) [1_H]

Sets palette values to gradation

palette C5(PS=0)/C13(PS=1)

PC54/

PC134

*

Gradation palette C6/C14

(Lower) [2_H]

Sets palette values to gradation

palette C6(PS=0)/C14(PS=1)

PC63/P PC62/ PC61/ PC60/

C143 PC142 PC141 PC140

Gradation palette C6/C14

(Upper) [3_H]

Sets palette values to gradation

palette C6(PS=0)/C14(PS=1)

PC64/

PC154

*

Gradation palette C7/C15

(Lower) [4_H]

Sets palette values to gradation

palette C7(PS=0)/C15(PS=1)

PC73/ PC72/ PC71/ PC70/

PC153 PC152 PC151 PC150

Gradation palette C7/C15

(Upper) [5_H]

Sets palette values to gradation

palette C7(PS=0)/C15(PS=1)

PC74/

PC154

*

Initial COM line

[6_H]

SC3 SC2 SC1 SC0

Sets scan-starting common driver

CL, FLM, FR, CLK signal

Display control Signal

[7_H]

SON

*

PWM : Variable 16 Gradation Mode

Stability 8 Gradation Mode

C256 : 256 Color Mode

Gradation mode control

[8_H]

PWM C256 FDC1 FDC2

HSW ABS CKS WLS

DV3 DV2 DV1 DV0

FDC : Boost Clock

HSW : Fast Writing at 8bits RAM Access

ABS : 12bits RAM Data Select

CSK : OSC Select

Data bus length

[9_H]

WLS : Data Length at Data Access

EVR control

Sets EVR level

(Lower bit)

(Lower) [A_H]

EVR control

Sets EVR level

(Upper bit)

DV6 DV5 DV4

RF2 RF1 RF0

*

(Upper) [B_H]

Frequency control

[D_H]

Controls oscillation frequency

Discharge ON/OFF

[E_H]

Discharge the electric charge in

capacitors on V₁to V₄and V_LCD

DIS

*

RE register

[F_H]

TST₀RE₂RE₁RE₀

Reading register address

Read Data

0/1 0/1 0/1

RE flag

Instruction register address

[C_H]

1

0

Sets instruction register address

Read out instruction register data

Instruction register read

0/1 0/1 0/1

Note 1)

Note 2) [ ]

Note 3)

*

: Don’t care.

: Instruction register address

The dual instructions including upper and lower bytes is enabled after either upper or lower

bytes are set into the register. The only “EVR control” instruction is enabled after both of the

upper and lower bytes are set.

Note 4)

CKS=0: Internal oscillation mode (default)

CKS=1: External oscillation mode

- 58 -

NJU6825

Instruction Table (6)

Code (80 series MPU I/F)

Code

Instructions

Functions

CS RS RD WR RE₂RE₁RE₀D₇D₆D₅D₄D₃D₂D₁D₀

Window end

column address

(Lower) [0_H]

Window end

column address

(Upper) [1_H]

EX3 EX2 EX1 EX0

EX7 EX6 EX5 EX4

EY3 EY2 EY1 EY0

EY7 EY6 EY5 EY4

LS3 LS2 LS1 LS0

LS7 LS6 LS5 LS4

LE3 LE2 LE1 LE0

LE7 LE6 LE5 LE4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Sets column address for end point

Sets row address for end point

Sets address for reverse line

Window end row address

(Lower) [2_H]

Window end row address

(Upper) [3_H]

Initial reverse line

(Lower) [4_H]

Initial reverse line

(Upper) [5_H]

Last reverse line

(Lower) [6_H]

Last reverse line

(Upper) [7_H]

Reverse line display

ON/OFF

BT : Blink type setting

LREV : Reverse line display ON/OFF

BT LREV

*

[8_H]

Gradation palette

setting control

[9_H]

Upper 8 gradation setting

Lower 8 gradation setting

PS

*

PWM control

[A_H]

PWM PWM PWM PWM

Sets PWM mode

RE flag

S

A

B

C

RE register

[F_H]

TST₀RE₂RE₁RE₀

0/1 0/1 0/1

Note 1)

Note 2) [ ]

Note 3)

*

: Don’t care.

: Instruction register address

The dual instructions including upper and lower bytes is enabled after either upper or lower

bytes are set into the register. The only “EVR control” instruction is enabled after both of the

upper and lower bytes are set.

- 59 -

NJU6825

(31) Instruction descriptions

This chapter provides detail description of the instructions, registers, their settings and programming

examples. The non-existent instruction codes in the instruction tables (1), (2)…(6) are required not to be

programmed.

(31-1)Display data write

The “Display data write” instruction is used to write 8-bit display data into the DDRAM.

CS

0

RS

0

RD WR RE₂RE₁RE₀

0/1 0/1 0/1

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

1

0

Display data

(31-2)Display data read

The “Display data read” instruction is used to read out 8-bit display data from the DDRAM, where the

column address and row address are required to be specified beforehand by the “column address” and

“row address” instructions. The dummy read is required just after the “column address” and “row address”

instructions.

CS

0

RS

0

RD WR RE₂RE₁RE₀

0/1 0/1 0/1

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

0

1

Display data

(31-3)Column address

The “column address” instruction is used to specify the column address for the display data read and

write operations. It includes dual instructions for lower 4-bit and upper 4-bit data. The instruction for the

lower 4-bit data is required to be executed first.

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

0

D₅

0

D₄

0

D₃

D₂

D₁

D₀

1

0

AX₃AX₂AX₁AX₀

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

0

D₅

0

D₄

1

D₃

D₂

D₁

D₀

1

0

AX₇AX₆AX₅AX₄

(31-4)Row address

The “row address” instruction is used to specify the row address for the display data read and write

operations. It includes dual instructions for lower 4-bit and upper 4-bit data. The instruction for the lower 4-

bit data is required to be executed first.

The row address can be specified in between 00_Hand A1_H. The setting for the non-existence row

address between A2_Hand FF_His prohibited.

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

0

D₅

1

D₄

0

D₃

D₂

D₁

D₀

1

0

AY₃AY₂

AY₁AY₀

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

0

D₅

1

D₄

1

D₃

D₂

D₁

D₀

1

0

AY₇AY₆

AY₅AY₄

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NJU6825

(31-5)Initial display line

The “Initial display line” instruction is used to specify the line address corresponding to the initial COM

line. The initial COM line indicates the common driver that starts scanning the display data, which is

specified by the “Initial COM line” instruction.

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

1

D₅

0

D₄

0

D₃

D₂

D₁

D₀

1

0

LA₃

LA₂

LA₁LA₀

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

1

D₅

0

D₄

1

D₃

D₂

D₁

D₀

1

0

LA₇

LA₆

LA₅LA₄

LA₇

LA₆

0

LA₅

0

LA₄

LA₃

0

LA₂

LA₁

LA₀

0

Line address

0

1

0

1

:

1

0

1

0

1

161

(31-6)N-line inversion

The “N-line inversion” instruction is used to control the alternate rates of the liquid crystal direction. It is

programmed to select the N value between 2 and 161, so that the FR signal toggles once every N frames

by setting “1” into the “NLIN” register in the “Display control (2)” instruction. In case that the N-line

inversion is disabled by setting “0” into “NLIN” register, the FR signal toggles by the frame.

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

1

D₅

1

D₄

0

D₃

D₂

D₁

D₀

1

0

N3

N2

N1

N0

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

1

D₅

1

D₄

1

D₃

D₂

D₁

D₀

1

0

N7

N6

N5

N4

N7

N6

0

N5

0

N4

0

N3

0

N2

N1

0

N0

N value

Inhibited

2

0

1

0

:

1

0

1

0

161

- 61 -

NJU6825

ꢁN-line Inversion Timing (1/163 duty cycle ratio)

N-line inversion OFF

1st line

3rd line

162nd line

1st line

2nd line

163rd line

CL

FLM

FR

N-line inversion ON

N-line control

1st line

3rd line

Nst line

2nd line

1st line

CL

FR

(31-7)Display control (1)

The “Display control (1)” instruction is used to control the display conditions for the “Display ON/OFF”,

“All pixels ON/OFF”, Display mode” and “Common direction” registers.

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

1

D₆

0

D₅

0

D₄

0

D₃

D₂

D₁

D₀

SHIFT

MON

ALLON ON/OFF

1

0

ꢁON/OFF register

ON/OFF=0 : Display OFF (All COM/SEG output Vss level.)

ON/OFF=1 : Display ON

ꢁAll ON register

The “All pixels ON/OFF” register is used to turn on all pixels without changing the display data in the

DDRAM. The setting for the “All pixels ON/OFF” register has a priority over the “Reverse display

ON/OFF” register.

ALLON=0

ALLON=1

: Normal

: All pixels turn on.

ꢁMON register

MON=1

MON=0

: Gradation mode

: B&W mode

ꢁSHIFT register

SHIFT=0

SHIFT=1

: COM₀→ COM₁₆₁

: COM₁₆₁→ COM₀

- 62 -

NJU6825

(31-8)Display control (2)

The “Display control (2)” instruction is used to control the display conditions for the “Segment direction”,

“SWAP mode ON/OFF”, “N-line inversion ON/OFF” and “Reverse display ON/OFF”.

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

1

D₆

0

D₅

0

D₄

1

D₃

D₂

D₁

D₀

REV

NLIN

SWAP

REF

1

0

ꢁREF register

The “REF” register is used to reverse the assignment for the segment drivers and column address,

so that it is possible to reduce the restrictions for the placement of the LSI in the LCD modules. For

more information, see (10) “The relationship among the DDRAM column address, display data and

segment drivers”.

ꢁSWAP register

The “SWAP” register is used to reverse the arrangement for the display data in the DDRAM.

SWAP=0

SWAP=1

: SWAP mode OFF

: SWAP mode ON

(Normal)

SWAP=”0”

SWAP=”1”

Write data

D₇D₆D₅D₄D₃D₂D₁D₀

d7 d6 d5 d4 d3 d2 d1 d0

D₇D₆D₅D₄D₃D₂D₁D₀

RAM data

d0 d1 d2 d3 d4 d5 d6 d7

D₇D₆D₅D₄D₃D₂D₁D₀

Read data

ꢁNLIN register

The “NLIN” is used to enable or disable the N-line inversion.

NLIN=0

NLIN=1

: N-line inversion OFF

: N-line inversion ON

(The FR signal toggles by the flame.)

(The FR signal toggles once every N frames.)

ꢁREV register

The “REV” register is used to enable or disable the reverse display mode that reverses the polarity

of the display data without changing the display data in the DDRAM.

REV=0

REV=1

: Reverse display mode OFF

: Reverse display mode ON

REV

Display

Normal

DDRAM data → Display data

0

1

0

1

0

1

0

1

Reverse

- 63 -

NJU6825

(31-9)Increment control

The “Increment control” instruction is used to control the conditions for the increment mode. In the auto-

increment mode, the DDRAM address is automatically incremented (+1) whenever the DDRAM is

accessed by the “Display data write” and “Display data read” instructions, so that it is possible to

continuously access to the DDRAM without executing the “column address” and “row address” instructions

after each “Display data write” or “Display data read” instruction. The settings for the “AIM”, “AXI” and “AYI”

registers are listed in the following tables.

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

1

D₆

0

D₅

1

D₄

0

D₃

D₂

D₁

D₀

1

0

WIN AIM AYI AXI

ꢁAIM, AYI and AXI registers

AIM

Increment mode

Note

Auto-increment for both of the display data read and write operations

Auto-increment for the display write operation (Read modify write)

0

1

2

Note 1) It is valid during continuing to write or read serial address area.

Note 2) It is valid at writing modified data that read, write, and read every address.

AYI

0

AXI

0

1

Increment mode

Note

No auto-increment

1

2

3

Auto-increment for the column address

Auto-increment for the row address

Auto-increment for the column address and row

address

1

0

1

4

Note 1) The auto-increment is disabled independent of the “AIM” register.

Note 2) The auto-increment is enabled for the column address in accordance with the “AIM” register.

MAX_H

MAX_Hin the 8-bit data bus mode

00_H

: FF_H

MAX_Hin the 16-bit data bus mode : 7F_H

Note 3) The auto-increment is enabled for the row address in accordance with the “AIM” register.

A1_H

00_H

Note 4)The auto-increment is enabled for the column address and row address. The auto-increment for

the row address is interlocked with the auto-increment for the column address, so that the row

address will be incremented when the column address is reached to the MAX_H.

Max_H

00_H

A1_H

00_H

column address

row address

MAX_Hin the 8-bit data bus mode

: FF_H

MAX_Hin the 16-bit data bus mode : 7F_H

- 64 -

NJU6825

ꢁWIN register

The “WIN” register is used to access to the DDRAM for the window display area that defines the

designated area determined by the portions of the start point and end point. The start point is

determined by the “column address” and “row address” instructions, and the end point by the

“Window end column address “and ”Window end row address” instructions. The setting sequence for

the window display area is listed as follows. For more detail, see (7) “Window display area”.

1. “Increment control” instruction (WIN=1, AXI=1, AYI=1)

2. “column address” and “row address” instructions for the start point

3. “Window end column address” and “Window end row address” instructions for the end point

4. Enable to access to the window display area in the DDRAM

START

Address

END

Address

END

Address

START

Address

column address

row address

- 65 -

NJU6825

(31-10)Power control

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

1

D₆

0

D₅

1

D₄

1

D₃

D₂

D₁

D₀

AMPON HALT DCON

ACL

1

0

ꢁACL register

The “ACL” register is used to initialize the internal power supply circuits. It is available only in the

master mode.

ACL=0

ACL=1

: Initialization OFF (Normal)

: Initialization ON

When the data in the “ACL register” is read out by the “Instruction register read” instruction, the

read-out data is “1” during the initialization and “0” after the initialization. This initialization is

performed using the internal reset signal produced by 2 clocks on the OSC₁. For this reason, the wait

time for 2 clocks on the OSC₁is required until the next instruction after the initialization by

programming “ACL” register.

ꢁDCON register

The “DCON” register is used to enable or disable the voltage booster.

DCON=0

DCON=1

: Voltage booster OFF

: Voltage booster ON

ꢁHALT register

The “HALT” register is used to enable or disable the power save mode. It is possible to reduce the

operating current down to the stand-by level in the power save mode. The internal status in the power

save mode is listed below.

HALT=0

HALT=1

: Power save OFF (Normal)

: Power save ON

Internal status in the power save mode

• The oscillation circuits and internal power supply circuits are halted.

• All segment and common drivers output V_SSlevel.

• The display data in the DDRAM is maintained.

• The operational modes before the power save mode are maintained.

• The V₁to V₄and V_LCDare in the high impedance.

• The clock input into the OSC₁is inhibited.

In the power save ON sequence, it is required that the “Display OFF” instruction is executed before

the “Power save ON” instruction, so that all common and segment drivers output V_SSlevel. And in the

power save OFF sequence, it is required that the “Power save OFF” instruction is executed first and

then the “Display ON” instruction is executed. If the “Power save OFF” instruction is executed in the

display ON status, unexpected pixels may be instantly turned on.

ꢁAMPON register

The “AMPON” register is used to enable or disable the voltage followers, voltage regulator and EVR.

AMPON=0 : The voltage followers, voltage regulator and EVR OFF

AMPON=1 : The voltage followers, voltage regulator and EVR ON

- 66 -

NJU6825

(31-11)Duty cycle ratio

The “Duty cycle ratio” instruction is used to select the LCD duty cycle ratio for the partial display function.

The partial display function specifies the partial display area on a LCD panel in the condition of lower duty

cycle ratio, lower LCD bias ratio, lower boost level and lower LCD driving voltage, so that it is possible to

display a time and calendar in the extremely low power consumption.

It can be also programmed to select not only the duty cycle ratio but also the LCD bias ratio, boost level

and EVR value by the instructions so that it is possible to optimize the LSI conditions in accordance with

the display.

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

1

D₆

1

D₅

0

D₄

0

D₃

D₂

D₁

D₀

1

0

DS₃DS₂DS₁DS₀

DS₃

0

DS₂

0

1

DS₁

DS₀

0

1

0

1

0

1

0

1

Duty cycle ratio

0

1

0

1

0

1

0

1

Row way 162 dots display, 1/163 Duty

Row way 160 dots display, 1/160 Duty

Row way 144 dots display, 1/144 Duty

Row way 133 dots display, 1/133 Duty

Row way 128 dots display, 1/128 Duty

Row way 112 dots display, 1/112 Duty

Row way 96 dots display, 1/96 Duty

Row way 80 dots display, 1/80 Duty

Row way 72 dots display, 1/72 Duty

Row way 64 dots display, 1/64 Duty

Row way 56 dots display, 1/56 Duty

Row way 48 dots display, 1/48 Duty

Row way 40 dots display, 1/40 Duty

Row way 32 dots display, 1/32 Duty

Row way 24 dots display, 1/24 Duty

Row way 16 dots display, 1/16 Duty

1

0

1

0

1

0

1

0

1

0

1

(31-12)Boost level

The “Boost level” is used to select the multiple for the voltage booster for the partial display function.

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

1

D₆

1

D₅

0

D₄

1

D₃

*

D₂

D₁

D₀

1

0

VU₂VU₁VU₀

VU₂VU₁

VU₀

0

1

0

1

0

1

0

1

Boost level

1-time (No boost)

2-time

0

1

0

1

0

1

3-time

4-time

5-time

6-time

7-time

Inhibited

- 67 -

NJU6825

(31-13)LCD bias ratio

The “LCD bias ratio” is used to select the LCD bias ratio for the partial display function.

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

1

D₆

1

D₅

1

D₄

0

D₃

*

D₂

B₂

D₁

B₁

D₀

B₀

1

0

B₂

0

1

B₁

0

1

0

1

B₀

0

1

0

1

0

1

0

1

LCD bias ratio

1/9

1/8

1/7

1/6

1/5

1/10

1/11

1/12

(31-14)RE flag

The “RE flag” registers are used to determine the contents for the RE registers (RE₂, RE₁and RE₀) in

order that it is possible to access to the instruction registers.

The data in the “TST₀” register must be “0”, which is used only for maker tests.

CS

0

RS

1

RD WR RE₂RE₁RE₀

0/1 0/1 0/1

D₇

1

D₆

1

D₅

1

D₄

1

D₃

D₂

D₁

D₀

1

0

TST₀RE₂RE₁RE₀

- 68 -

NJU6825

(31-15)Gradation palette A, B and C

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

0

D₅

0

D₄

0

D₃

D₂

D₁

D₀

PA₀₃

PA₈₃

/

PA₀₂

PA₈₂

/

PA₀₁

PA₈₁

/

PA₀₀/

PA₈₀

1

0

1

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

0

D₅

0

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PA₀₄

PA₈₄

/

1

0

1

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

0

D₅

1

D₄

0

D₃

D₂

D₁

D₀

PA13/ PA₁₂

PA₉₃

/

PA₁₁/ PA₁₀/

PA₉₁

1

0

1

PA₉₂

PA₉₀

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

0

D₅

1

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PA₁₄

PA₉₄

/

1

0

1

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

1

D₅

0

D₄

0

D₃

D₂

D₁

D₀

PA₂₃

/

PA₂₂

/

PA₂₁

/

PA₂₀/

1

0

1

PA₁₀₃PA₁₀₂PA₁₀₁PA₁₀₀

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

1

D₅

0

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PA₂₄

PA₁₀₄

/

1

0

1

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

1

D₅

1

D₄

0

D₃

D₂

D₁

D₀

PA₃₃

/

PA₃₂

/

PA₃₁

/

PA₃₀/

1

0

1

PA₁₁₃PA₁₁₂PA₁₁₁PA₁₁₀

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

1

D₅

1

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PA₃₄

PA₁₁₄

/

1

0

1

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

1

D₆

0

D₅

0

D₄

0

D₃

D₂

D₁

D₀

PA₄₃

/

PA₄₂

/

PA₄₁

/

PA₄₀/

1

0

1

PA₁₂₃PA₁₂₂PA₁₂₁PA₁₂₀

- 69 -

NJU6825

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

1

D₆

0

D₅

0

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PA₄₄

PA₁₂₄

/

1

0

1

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

1

D₆

0

D₅

1

D₄

0

D₃

D₂

D₁

D₀

PA₅₃

/

PA₅₂

/

PA₅₁

/

PA₅₀/

1

0

1

PA₁₃₃PA₁₃₂PA₁₃₁PA₁₃₀

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

1

D₆

0

D₅

1

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PA₅₄

PA₁₃₄

/

1

0

1

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

1

D₆

1

D₅

0

D₄

0

D₃

D₂

D₁

D₀

PA₆₃

/

PA₆₂

/

PA₆₁

/

PA₆₀/

1

0

1

PA₁₄₃PA₁₄₂PA₁₄₁PA₁₄₀

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

1

D₆

1

D₅

0

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PA₆₄

PA₁₄₄

/

1

0

1

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

0

D₅

0

D₄

0

D₃

D₂

D₁

D₀

PA₇₃

/

PA₇₂

/

PA₇₁

/

PA₇₀/

1

0

1

0

PA₁₅₃PA₁₅₂PA₁₅₁PA₁₅₀

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

0

D₅

0

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PA₇₄

PA₁₅₄

/

1

0

1

0

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

0

D₅

1

D₄

0

D₃

D₂

D₁

D₀

PB₀₃

PB₈₃

/

PB₀₂

PB₈₂

/

PB₀₁

PB₈₁

/

PB₀₀/

PB₈₀

1

0

1

0

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

0

D₅

1

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PB₀₄

PB₈₄

/

1

0

1

0

- 70 -

NJU6825

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

1

D₅

0

D₄

0

D₃

D₂

D₁

D₀

PB₁₃

PB₉₃

/

PB₁₂

PB₉₂

/

PB₁₁/ PB₁₀/

PB₉₁

1

0

1

0

PB₉₀

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

1

D₅

0

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PB₁₄

PB₉₄

/

1

0

1

0

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

1

D₅

1

D₄

0

D₃

D₂

D₁

D₀

PB₂₃

/

PB₂₂

/

PB₂₁

/

PB₂₀/

1

0

1

0

PB₁₀₃PB₁₀₂PB₁₀₁PB₁₀₀

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

1

D₅

1

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PB₂₄

PB₁₀₄

/

1

0

1

0

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

1

D₆

0

D₅

0

D₄

0

D₃

D₂

D₁

D₀

PB₃₃

/

PB₃₂

/

PB₃₁

/

PB₃₀/

1

0

1

0

PB₁₁₃PB₁₁₂PB₁₁₁PB₁₁₀

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

1

D₆

0

D₅

0

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PB₃₄

PB₁₁₄

/

1

0

1

0

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

1

D₆

0

D₅

1

D₄

0

D₃

D₂

D₁

D₀

PB₄₃

/

PB₄₂

/

PB₄₁

/

PB₄₀/

1

0

1

0

PB₁₂₃PB₁₂₂PB₁₂₁PB₁₂₀

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

1

D₆

0

D₅

1

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PB₄₄

PB₁₂₄

/

1

0

1

0

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

1

D₆

1

D₅

0

D₄

0

D₃

D₂

D₁

D₀

PB53/ PB₅₂

PB₁₃₃PB₁₃₂PB₁₃₁PB₁₃₀

/

PB₅₁

/

PB₅₀/

1

0

1

0

- 71 -

NJU6825

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

1

D₆

1

D₅

0

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PB₅₄

PB₁₃₄

/

1

0

1

0

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

0

D₅

0

D₄

0

D₃

D₂

D₁

D₀

PB₆₃

/

PB₆₂

/

PB61/ PB₆₀/

1

0

1

PB₁₄₃PB₁₄₂PB₁₄₁PB₁₄₀

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

0

D₅

0

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PB₆₄

PB₁₄₄

/

1

0

1

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

0

D₅

1

D₄

0

D₃

D₂

D₁

D₀

PB₇₃

/

PB₇₂

/

PB₇₁

/

PB₇₀/

1

0

1

PB₁₅₃PB₁₅₂PB₁₅₁PB₁₅₀

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

0

D₅

1

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PB₇₄

PB₁₅₄

/

1

0

1

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

1

D₅

0

D₄

0

D₃

D₂

D₁

D₀

PC₀₃

PC₈₃

/

PC₀₂

PC₈₂

/

PC₀₁

PC₈₁

/

PC₀₀/

PC₈₀

1

0

1

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

1

D₅

0

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PC₀₄

PC₈₄

/

1

0

1

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

1

D₅

1

D₄

0

D₃

D₂

D₁

D₀

PC₁₃

PC₉₃

/

PC₁₂

PC₉₂

/

PC₁₁/ PC₁₀/

PC₉₁

1

0

1

PC₉₀

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

1

D₅

1

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PC₁₄

PC₉₄

/

1

0

1

- 72 -

NJU6825

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

1

D₆

0

D₅

0

D₄

0

D₃

D₂

D₁

D₀

PC₂₃

/

PC₂₂

/

PC₂₁

/

PC₂₀/

1

0

1

PC₁₀₃PC₁₀₂PC₁₀₁PC₁₀₀

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

1

D₆

0

D₅

0

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PC₂₄

PC₁₀₄

/

1

0

1

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

1

D₆

0

D₅

1

D₄

0

D₃

D₂

D₁

D₀

PC₃₃

/

PC₃₂

/

PC₃₁

/

PC₃₀/

1

0

1

PC₁₁₃PC₁₁₂PC₁₁₁PC₁₁₀

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

1

D₆

0

D₅

1

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PC₃₄

PC₁₁₄

/

1

0

1

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

1

D₆

1

D₅

0

D₄

0

D₃

D₂

D₁

D₀

PC₄₃

/

PC₄₂

/

PC₄₁

/

PC₄₀/

1

0

1

PC₁₂₃PC₁₂₂PC₁₂₁PC₁₂₀

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

1

D₆

1

D₅

0

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PC₄₄

PC₁₂₄

/

1

0

1

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

0

D₅

0

D₄

0

D₃

D₂

D₁

D₀

PC₅₃

/

PC₅₂

/

PC₅₁

/

PC₅₀/

1

0

1

0

PC₁₃₃PC₁₃₂PC₁₃₁PC₁₃₀

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

0

D₅

0

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PC₅₄

PC₁₃₄

/

1

0

1

0

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

0

D₅

1

D₄

0

D₃

D₂

D₁

D₀

PC₆₃

/

PC₆₂

/

PC₆₁

/

PC₆₀/

1

0

1

0

PC₁₄₃PC₁₄₂PB₁₄₁PB₁₄₀

- 73 -

NJU6825

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

0

D₅

1

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PC₆₄

PC₁₄₄

/

1

0

1

0

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

1

D₅

0

D₄

0

D₃

D₂

D₁

D₀

PC₇₃

/

PC₇₂

/

PC₇₁

/

PC₇₀/

1

0

1

0

PC₁₅₃PC₁₅₂PC₁₅₁PC₁₅₀

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

1

D₅

0

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PC₇₄

PC₁₅₄

/

1

0

1

0

Gradation Level Table

(PAj, PBj, PCj, j=0−15)

Gradation

Level

Gradation

Level

Palette Value

0 0 0 0 0

0 0 0 0 1

0 0 0 1 0

0 0 0 1 1

0 0 1 0 0

0 0 1 0 1

0 0 1 1 0

0 0 1 1 1

0 1 0 0 0

0 1 0 0 1

0 1 0 1 0

0 1 0 1 1

0 1 1 0 0

0 1 1 0 1

0 1 1 1 0

0 1 1 1 1

Note

Palette Value

Note

Gradation Palette 0

Initial Value

0/31

1/31

1

0 0

0 1

1 0

1 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

16/31

17/31

18/31

19/31

20/31

21/31

22/31

23/31

24/31

25/31

26/31

27/31

28/31

29/31

30/31

31/31

Gradation Palette 8

Initial Value

2/31

Gradation Palette 1

Initial Value

Gradation Palette 9

Initial Value

3/31

4/31

Gradation Palette2

Initial Value

Gradation Palette 10

Initial Value

5/31

6/31

Gradation Palette 3

Initial Value

Gradation Palette 11

Initial Value

7/31

8/31

Gradation Palette 4

Initial Value

Gradation Palette 12

Initial Value

9/31

10/31

11/31

12/31

13/31

14/31

15/31

Gradation Palette 5

Initial Value

Gradation Palette 13

Initial Value

Gradation Palette 6

Initial Value

Gradation Palette 14

Initial Value

Gradation Palette 7

Initial Value

Gradation Palette 15

Initial Value

- 74 -

NJU6825

(31-16)Initial COM line

The “Initial COM line” instruction is used to specify the common driver that starts scanning the display

data. The line address, corresponding to the initial COM line, is specified by the “Initial display line”

instruction.

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

1

D₅

1

D₄

0

D₃

D₂

D₁

D₀

1

0

1

0

SC₃SC₂SC₁SC₀

SC3

0

1

SC2 SC1 SC0

Initial COM line (SHIFT=0)

COM₀

Initial COM line (SHIFT=1)

COM₁₆₁

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

COM₁

COM₉

COM₁₄

COM₁₇

COM₂₅

COM₃₃

COM₄₁

COM₄₉

COM₅₇

COM₆₅

COM₇₃

COM₁₂₂

COM₁₃₀

COM₁₃₈

COM₁₄₆

COM₁₆₀

COM₁₅₂

COM₁₄₆

COM₁₄₄

COM₁₃₆

COM₁₂₈

COM₁₂₀

COM₁₁₂

COM₁₀₄

COM₉₆

COM₈₈

COM₃₉

COM₃₁

COM₂₃

COM₁₅

SHIFT=0: Positive direction

SHIFT=1: Negative direction

(for instance, COM₀→ COM₁₄₆

(for instance, COM₁₆₁→ COM₁₅)

)

(31-17)Display control signal

CL, FLM, FR, and CLK signal outputs control ON/OFF.

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

1

D₅

1

D₄

1

D₃

*

D₂

*

D₁

*

D₀

SON

1

0

1

0

SON=0:

SON=1:

CL, FLM, FR, and CLK outputs level “0”.

CL, FLM, FR, and CLK outputs are active.

- 75 -

NJU6825

(31-18)Gradation mode control

The “Gradation mode control” is selecting the gradation mode, selecting the 256-color mode, and setting

boost clock.

CS

RS

1

RD WR RE₂RE₁RE₀

D₇

1

D₆

0

D₅

0

D₄

0

D₃

D₂

D₁

D₀

PWM C256

0

1

0

1

0

FDC1 FDC2

ꢁPWM register

PWM=0:

Variable gradation mode

(16-gradation levels out of a palette consisting of 32-gradation levels)

Fixed gradation mode

PWM=1:

(Fixed 8-gradation levels)

ꢁC256 register

C256=0

Variable gradation mode

(16-gradation levels out of a palette consisting of 32-gradation levels.)

C256=1

256-color mode

(8-gradation levels out of a palette consisting of 32-gradation levels.)

(4-gradation levels out of a palette consisting of 32-gradation levels at the palette

B.)

ꢁFDC1 and FDC2 register

FDC1

FDC2

Boost Clock

0

1

0

1

0

1

×1

×2

×4

×1/2

- 76 -

NJU6825

(31-19)Data bus length

The “Data bus length” instruction is used to select the 8- or 16- bit data bus length and determine the

internal or external oscillation. In the 16-bit data bus mode, not only the display data but also the

instruction data is required to be transferred by 16-bit data (D₁₅to D₀). However, in case of the access to

the instruction register, the only lower 8-bit data (D₇to D₀) of the 16-bit data is valid. In case of the access

to the DDRAM, all of the 16-bit data (D₁₅to D₀) is valid.

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

1

D₆

0

D₅

0

D₄

1

D₃

D₂

D₁

D₀

1

0

1

0

HSW ABS CKS WLS

ꢁHSW register

HSW =0:

HSW=1:

High Speed Witting mode off.

High Speed Witting mode on at accessing the 8-bit RAM.

ꢁABS register

ABS=0:

ABS=1:

Normal Mode

ABS Mode

ꢁWLS register

WLS=0:

WLS =1:

8-bit data bus length

16-bit data bus length

ꢁCKS register

CKS =0:

Internal oscillation

(The OSC₁terminal must be fixd “1” or “0”.)

External oscillation

CKS =1:

(By the external clock into the OSC₁or external resister between the OSC₁and

OSC₂. OSC₂should be open when clock is inputted from OSC₁.)

- 77 -

NJU6825

(31-20)EVR control

The “EVR control” instruction is used to fine-tune the LCD driving voltage (V_LCD) so that it is possible to

optimize the contrast level for the display.

The “EVR control” instruction requires to be programmed by the upper 3-bit data first and then lower 4-

bit data, where programming the only upper 3-bit data has not enabled it, so that it is possible to prevent

unexpected high voltage for the V_LCD

.

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

1

D₆

0

D₅

1

D₄

0

D₃

D₂

D₁

D₀

1

0

1

0

DV₃DV₂DV₁DV₀

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

1

D₆

0

D₅

1

D₄

1

D₃

*

D₂

D₁

D₀

1

0

1

0

DV₆DV₅DV₄

DV₆DV₅DV₄DV₃DV₂DV₁DV₀

V_LCD

0

:

0

1

Low

:

1

High

The V_LCDis calculated by the following equation.

V_LCD[V] = 0.5 x V_REG+ M (V_REG– 0.5 x V_REG) / 127

V

_BA= V_EEx 0.9

V_BA

V_REF

V_REG

N

: Output voltage of the reference voltage generator

: Input voltage of the voltage regulator

: Output voltage of the voltage regulator

: Register value for the voltage booster

: Register value for the EVR

V_REG= V_REFx N

M

- 78 -

NJU6825

(31-21)Frequency control

The “Frequency control” instruction is used to control the frame frequency for a LCD panel.

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

1

D₆

1

D₅

0

D₄

1

D₃

*

D₂

D₁

D₀

1

0

Rf₂

Rf₁

Rf₀

ꢁRfx register (x=0, 1, 2)

The “Rfx” register is used to determine the feed back resister value for the internal oscillator in

order that it is possible to adjust the frame frequency.

Rf 2 Rf 1 Rf 0

Feedback resistor value

Reference value

0.8 x reference value

0.9 x reference value

1.1 x reference value

1.2 x reference value

Inhibited

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Inhibited

(31-22)Discharge ON/OFF

The “Discharge ON/OFF” instruction is used to enable or disable the discharge circuits, so that it is

possible to prevent unexpected pixels turned on just after the internal or external power supply is turned

off. During the discharge operation, do not supply the power neither from an internal or external power

supplies to the LSI.

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

1

D₆

1

D₅

1

D₄

0

D₃

*

D₂

*

D₁

*

D₀

1

0

1

0

DIS

DIS=0:

DIS=1:

Discharge OFF

Discharge ON

- 79 -

NJU6825

(31-23)Instruction register address

The “Instruction register address” is used to specify the instruction register address, so that it is possible

to read out the contents of the instruction registers in combination with the “Instruction register read”

instruction.

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

1

D₆

1

D₅

0

D₄

0

D₃

D₂

D₁

D₀

1

0

1

0

RA₃RA₂RA₁RA₀

(31-24)Instruction register read

The “Instruction register read” instruction is used to read out the contents of the instruction register in

combination with the “Instruction register address” instruction.

CS

0

RS

1

RD WR RE₂RE₁RE₀

0/1 0/1 0/1

D₇

*

D₆

*

D₅

*

D₄

*

D₃

D₂

D₁

D₀

0

1

Internal register data read

(31-25)Window end column address

The “Window end column address” is used to specify the column address for the window end point. The

lower 4-bit data is required to be programmed first and then the upper 4-bit data can be programmed.

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

0

D₅

0

D₄

0

D₃

D₂

D₁

D₀

1

0

1

0

1

EX₃EX₂EX₁EX₀

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

0

D₅

0

D₄

1

D₃

D₂

D₁

D₀

1

0

1

0

1

EX₇EX₆EX₅EX₄

(31-26)Window end row address set

The “Window end row address” is used to specify the row address for the window end point. The lower

4-bit data is required to be programmed first and then the upper 4-bit data can be programmed.

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

0

D₅

1

D₄

0

D₃

D₂

D₁

D₀

1

0

1

0

1

EY₃EY₂EY₁EY₀

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

0

D₅

1

D₄

1

D₃

D₂

D₁

D₀

1

0

1

0

1

EY₇EY₆EY₅EY₄

- 80 -

NJU6825

(31-27)Initial reverse line

The “Initial reverse line” instruction is used to specify the initial reverse line address for the reverse line

display. The lower 4-bit data is required to be programmed first and then the upper 4-bit data can be

programmed. It can be programmed in between 00_Hand A1_Hand the line address beyond A1_His inhibited.

The address relationship: LSi < LEi (i=7 to 0) must be maintained in the reverse line display.

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

1

D₅

0

D₄

0

D₃

D₂

D₁

D₀

1

0

1

0

1

LS₃LS₂LS₁LS₀

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

1

D₅

0

D₄

1

D₃

D₂

D₁

D₀

1

0

1

0

1

LS₇LS₆LS₅LS₄

(31-28)Last reverse line

The “Last reverse line” instruction is used to specify the last reverse line address for the reverse line

display. The lower 4-bit data is required to be programmed first and then the upper 4-bit data can be

programmed. It can be programmed in between 00_Hand A1_Hand the line address beyond A1_His inhibited.

The address relationship: LSi < LEi (i=7 to 0) must be maintained in the reverse line display.

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

1

D₅

1

D₄

0

D₃

D₂

D₁

D₀

1

0

1

0

1

LE₃LE₂LE₁LE₀

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

0

D₆

1

D₅

1

D₄

1

D₃

D₂

D₁

D₀

1

0

1

0

1

LE₇LE₆LE₅LE₄

(31-29)Reverse line display ON/OFF

The “Reverse line display ON/OFF” is used to enable or disable the reverse line display for the blink

operation and determine the reverse line display mode.

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

1

D₆

0

D₅

0

D₄

0

D₃

*

D₂

*

D₁

D₀

1

0

1

0

1

BT LREV

ꢁLREV register

The “LREV” register is used to enable or disable the reverse line display.

LREV =0:

LREV =1:

Reverse line display OFF (Normal)

Reverse line display ON

- 81 -

NJU6825

ꢁBT register

The “BT” register is used to determine the reverse line display mode in the reverse line display ON

(LREV=1) status.

BT =0:

BT =1:

Normal reverse line display

Blink once every 32 frames

Display examples in the LREV=”1” and BT=”1”

!" " " !

"! ! ! "

"! ! ! !

!" " " !

!! ! ! "

"! ! ! "

!" " " !

!! ! ! !

" ! ! ! "

! " " " !

! " " " "

" ! ! ! "

" " " " !

! " " " !

" ! ! ! "

" " " " "

Blink once every 32 frames

NJRC

LCD DRIVER

Low Power and

Low Voltage

Blink once every 32 frames

NJRC

←Initial reverse line address

←Last reverse line address

LCD DRIVER

Low Power and

Low Voltage

- 82 -

NJU6825

(31-30) Gradation Palette setting control

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

1

D₆

0

D₅

0

D₄

1

D₃

*

D₂

*

D₁

*

D₀

1

0

1

0

1

PS

PS=0: Lower 8 Gradation setting

PS=1: Upper 8 Gradation setting

(31-31)PWM control

The “PWM control” is used to determine the PWM type for the segment waveforms, where the type can

be specified for each of the SEGAi, SEGBi and SEGCi (i=0-127) drivers.

CS

0

RS

1

RD WR RE₂RE₁RE₀

D₇

1

D₆

0

D₅

1

D₄

0

D₃

D₂

D₁

D₀

PWMS PWMA PWMB PWMC

1

0

1

0

1

ꢁPWMS register

PWMS=0: Type 1

PWMS=1: Type 2

ꢁPWMA, B and C registers

The “PWMA, PWMB and PWMC” registers are used to select the type 1-O or type 1-E.

PWMZ=0 (Z=A, B and C): Type 1-O

PWMZ=1 (Z=A, B and C): Type 1-E

PWM type1 (PWMS=”0”)

Odd line

Even line

“H”

“L”

CL

V_LCD

V₂

→

←

Type-O

Type-E

SEG

V_LCD

V₂

→

←

PWM type2 (PWMS=”1”)

“H”

CL

“L”

V_LCD

V₂

SEG

→

- 83 -

NJU6825

(32) The relationship between Common driver and row address

The row address assignment for the common driver can be programmed by the “SHIF” register in the

“Display control (1), and “Duty cycle ratio”, “Initial display line” and “Initial COM line” instructions.

ꢁWhen initial display line is “0”

The relation between common drivers and row address of DDRAM (MY) is changing by the “Duty

cycle ratio” and “Initial COM line” instructions. If the shift bit is “0”, the order of common scanning is

normal and if it is “1”, the common scanning order is inversed. When LA₀to LA₇of initial display line

setting is “0”, the “MY” corresponding to the Initial COM line is also “0”. And “MY” is increasing.

ꢁWhen initial display line is not “0”

The relation between common drivers and row address of DDRAM (MY) is changing by the “Duty

cycle ratio” and “Initial COM line” instructions. If the shift bit is “0”, the order of common scanning is

normal and if it is “1”, the common scanning order is inversed. When LA₀to LA₇of initial display line

setting is not “0”, the “MY” corresponding to the Initial COM line is biased by the setting value. During

the display, “MY” is increasing up to “79”. When “MY” over than “161”, its back to “0”. And “MY” is

increasing from 0 continuously.

The following are Examples of setting the start-line 0 or 5 at 1/163, 1/80, or 1/16 duty.

- 84 -

NJU6825

(32-1)Initial display line “0”, 1/163 duty cycle (Common forward scan)

SHIFT=”0”(Common forward scan), DS₃, ₂, , ₀=”0000”, LA₇….LA₀=”00000000”(Initial display line 0)

1

SC₃

SC₂

SC₁

SC₀

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

89

1100

40

1101

32

1110

24

1111

16

COM₀

COM₁

0

161

0

153

148

145

137

129

121

113

105

97

COM₂

COM₃

COM₄

COM₅

COM₆

COM₇

COM₈

COM₉

161

0

COM₁₀

COM₁₁

COM₁₂

COM₁₃

COM₁₄

COM₁₅

COM₁₆

COM₁₇

:

161

0

161

0

COM₂₃

COM₂₄

COM₂₅

COM₂₆

COM₂₇

COM₂₈

COM₂₉

COM₃₀

COM₃₁

COM₃₂

COM₃₃

COM₃₄

COM₃₅

COM₃₆

COM₃₇

COM₃₈

COM₃₉

COM₄₀

COM₄₁

COM₄₂

COM₄₃

COM₄₄

COM₄₅

COM₄₆

COM₄₇

COM₄₈

COM₄₉

COM₅₀

COM₅₁

COM₅₂

COM₅₃

COM₅₄

COM₅₅

COM₅₆

COM₅₇

COM₅₈

COM₅₉

COM₆₀

COM₆₁

COM₆₂

COM₆₃

COM₆₄

COM₆₅

COM₆₆

COM₆₇

COM₆₈

COM₆₉

COM₇₀

COM₇₁

COM₇₂

COM₇₃

COM₇₄

COM₇₅

COM₇₆

COM₇₇

COM₇₈

:

161

0

161

0

161

0

161

0

161

0

161

0

161

0

COM₁₂₀

COM₁₂₁

COM₁₂₂

:

161

0

COM₁₂₈

COM₁₂₉

COM₁₃₀

:

161

0

COM₁₃₆

COM₁₃₇

COM₁₃₈

COM₁₃₉

COM₁₄₀

COM₁₄₁

COM₁₄₂

COM₁₄₃

COM₁₄₄

COM₁₄₅

COM₁₄₆

COM₁₄₇

COM₁₄₈

COM₁₄₉

COM₁₅₀

COM₁₅₁

COM₁₅₂

COM₁₅₃

COM₁₅₄

COM₁₅₅

COM₁₅₆

COM₁₅₇

COM₁₅₈

COM₁₅₉

COM₁₆₀

COM₁₆₁

161

0

161

0

161

160

161

152

161

147

161

144

161

136

161

128

161

120

161

112

161

104

161

96

88

39

31

23

15

(163^rdCOM period) *1

161

DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line

*1 : 163^rdCOM period is not selected.

- 85 -

NJU6825

(32-2)Initial display line “0”, 1/163 duty cycle (Common backward scan)

SHIFT=”1”(Common backward scan), DS₃, ₂, , ₀=”0000”, LA₇….LA₀=”00000000”(Initial display line 0)

1

SC₃

SC₂

SC₁

SC₀

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

88

1100

39

1101

31

1110

23

1111

15

COM₀

161

160

152

146

144

136

128

120

112

104

96

COM₁

COM₂

COM₃

COM₄

COM₅

COM₆

COM₇

COM₈

COM₉

COM₁₀

COM₁₁

COM₁₂

COM₁₃

COM₁₄

COM₁₅

COM₁₆

COM₁₇

COM₁₈

COM₁₉

COM₂₀

COM₂₁

COM₂₂

COM₂₃

COM₂₄

COM₂₅

:

0

161

0

161

COM₃₁

COM₃₂

:

0

161

COM₃₉

COM₄₀

:

0

161

COM₈₈

COM₈₉

COM₉₀

COM₉₁

COM₉₂

COM₉₃

COM₉₄

COM₉₅

COM₉₆

COM₉₇

COM₉₈

COM₉₉

COM₁₀₀

COM₁₀₁

COM₁₀₂

COM₁₀₃

COM₁₀₄

COM₁₀₅

COM₁₀₆

COM₁₀₇

COM₁₀₈

COM₁₀₉

COM₁₁₀

COM₁₁₁

COM₁₁₂

COM₁₁₃

COM₁₁₄

COM₁₁₅

COM₁₁₆

COM₁₁₇

COM₁₁₈

COM₁₁₉

COM₁₂₀

COM₁₂₁

COM₁₂₂

COM₁₂₃

COM₁₂₄

COM₁₂₅

COM₁₂₆

COM₁₂₇

COM₁₂₈

COM₁₂₉

COM₁₃₀

COM₁₃₁

COM₁₃₂

COM₁₃₃

COM₁₃₄

COM₁₃₅

COM₁₃₆

COM₁₃₇

COM₁₃₈

COM₁₃₉

COM₁₄₀

COM₁₄₁

COM₁₄₂

COM₁₄₃

COM₁₄₄

COM₁₄₅

COM₁₄₆

COM₁₄₇

COM₁₄₈

COM₁₄₉

COM₁₅₀

COM₁₅₁

COM₁₅₂

COM₁₅₃

COM₁₅₄

COM₁₅₅

COM₁₅₆

COM₁₅₇

COM₁₅₈

COM₁₅₉

COM₁₆₀

COM₁₆₁

0

161

0

161

0

161

0

161

0

161

0

161

0

161

0

161

0

161

0

161

0

161

0

153

161

147

161

145

161

137

161

129

161

121

161

113

161

105

161

97

89

40

32

24

16

(163^rdCOM period) *1

161

DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line

*1 : 163^rdCOM period is not selected.

- 86 -

NJU6825

(32-3)Initial display line “0”, 1/80 duty cycle (Common forward scan)

SHIFT=”0”(Common forward scan), DS₃, ₂, , ₀=”0111”, LA₇….LA₀=”00000000”(Initial display line 0)

1

SC₃

SC₂

SC₁

SC₀

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

40

1101

32

1110

24

1111

16

COM₀

COM₁

:

0

COM₉

COM₁₀

COM₁₁

COM₁₂

COM₁₃

COM₁₄

COM₁₅

COM₁₆

COM₁₇

COM₁₈

:

0

COM₂₅

COM₂₆

:

0

COM₃₃

:

0

COM₃₉

COM₄₀

COM₄₁

:

79

0

COM₄₇

COM₄₈

COM₄₉

COM₅₀

COM₅₁

COM₅₂

COM₅₃

COM₅₄

COM₅₅

COM₅₆

COM₅₇

COM₅₈

COM₅₉

COM₆₀

COM₆₁

COM₆₂

COM₆₃

COM₆₄

COM₆₅

COM₆₆

COM₆₇

COM₆₈

COM₆₉

COM₇₀

COM₇₁

COM₇₂

COM₇₃

COM₇₄

COM₇₅

COM₇₆

COM₇₇

COM₇₈

COM₇₉

COM₈₀

COM₈₁

:

79

0

79

0

79

0

79

COM₈₈

COM₈₉

COM₉₀

COM₉₁

COM₉₂

COM₉₃

COM₉₄

COM₉₅

COM₉₆

COM₉₇

:

79

COM₁₀₄

COM₁₀₅

:

79

COM₁₁₂

COM₁₁₃

:

79

COM₁₂₀

COM₁₂₁

COM₁₂₂

COM₁₂₃

COM₁₂₄

COM₁₂₅

COM₁₂₆

COM₁₂₇

COM₁₂₈

COM₁₂₉

COM₁₃₀

COM₁₃₁

COM₁₃₂

COM₁₃₃

COM₁₃₄

COM₁₃₅

COM₁₃₆

COM₁₃₇

COM₁₃₈

COM₁₃₉

COM₁₄₀

COM₁₄₁

COM₁₄₂

COM₁₄₃

COM₁₄₄

COM₁₄₅

COM₁₄₆

COM₁₄₇

COM₁₄₈

COM₁₄₉

COM₁₅₀

COM₁₅₁

COM₁₅₂

:

79

0

79

0

79

0

79

0

79

COM₁₆₀

COM₁₆₁

39

31

23

15

DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line

- 87 -

NJU6825

(32-4)Initial display line “0”, 1/80 duty cycle (Common backward scan)

SHIFT=”1”(Common backward scan), DS₃, ₂, , ₀=”0111”, LA₇….LA₀=”00000000”(Initial display line 0)

1

SC₃

SC₂

SC₁

SC₀

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

79

1100

39

1101

31

1110

23

1111

15

COM₀

:

COM₉

COM₁₀

COM₁₁

COM₁₂

COM₁₃

COM₁₄

COM₁₅

COM₁₆

COM₁₇

COM₁₈

COM₁₉

COM₂₀

COM₂₁

COM₂₂

COM₂₃

COM₂₄

COM₂₅

COM₂₆

COM₂₇

COM₂₈

COM₂₉

COM₃₀

COM₃₁

COM₃₂

COM₃₃

COM₃₄

COM₃₅

COM₃₆

COM₃₇

COM₃₈

COM₃₉

COM₄₀

COM₄₁

:

0

79

0

79

0

79

0

79

COM₄₉

:

79

COM₅₇

:

79

COM₆₅

COM₆₆

COM₆₇

COM₆₈

COM₆₉

COM₇₀

COM₇₁

COM₇₂

COM₇₃

:

79

COM₈₁

COM₈₂

COM₈₃

COM₈₄

COM₈₅

COM₈₆

COM₈₇

COM₈₈

:

79

0

COM₉₆

COM₉₇

COM₉₈

COM₉₉

COM₁₀₀

COM₁₀₁

COM₁₀₂

COM₁₀₃

COM₁₀₄

COM₁₀₅

COM₁₀₆

COM₁₀₇

COM₁₀₈

COM₁₀₉

COM₁₁₀

COM₁₁₁

COM₁₁₂

COM₁₁₃

COM₁₁₄

COM₁₁₅

COM₁₁₆

COM₁₁₇

COM₁₁₈

COM₁₁₉

COM₁₂₀

COM₁₂₁

COM₁₂₂

COM₁₂₃

COM₁₂₄

COM₁₂₅

COM₁₂₆

COM₁₂₇

COM₁₂₈

:

0

79

0

79

0

79

0

79

0

COM₁₃₆

:

0

COM₁₄₄

COM₁₄₅

COM₁₄₆

:

0

COM₁₅₂

:

0

COM₁₆₀

COM₁₆₁

0

40

32

24

16

DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line

- 88 -

NJU6825

(32-5)Initial display line “0”, 1/16 duty cycle (Common forward scan)

SHIFT=”0”(Common forward scan), DS₃, ₂, , ₀=”1111”, LA₇….LA₀=”00000000”(Initial display line 0)

1

SC₃

SC₂

SC₁

SC₀

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

COM₀

COM₁

COM₂

:

0

COM₉

COM₁₀

COM₁₁

COM₁₂

COM₁₃

COM₁₄

COM₁₅

COM₁₆

COM₁₇

COM₁₈

COM₁₉

COM₂₀

COM₂₁

COM₂₂

COM₂₃

COM₂₄

COM₂₅

COM₂₆

COM₂₇

COM₂₈

COM₂₉

COM₃₀

COM₃₁

COM₃₂

COM₃₃

COM₃₄

COM₃₅

COM₃₆

COM₃₇

COM₃₈

COM₃₉

COM₄₀

COM₄₁

COM₄₂

COM₄₃

COM₄₄

COM₄₅

COM₄₆

COM₄₇

COM₄₈

COM₄₉

COM₅₀

COM₅₁

COM₅₂

COM₅₃

COM₅₄

COM₅₅

COM₅₆

COM₅₇

COM₅₈

COM₅₉

COM₆₀

COM₆₁

COM₆₂

COM₆₃

COM₆₄

COM₆₅

COM₆₆

COM₆₇

COM₆₈

COM₆₉

COM₇₀

COM₇₁

COM₇₂

COM₇₃

COM₇₄

COM₇₅

COM₇₆

COM₇₇

COM₇₈

COM₇₉

COM₈₀

COM₈₁

:

0

15

0

15

0

15

0

15

0

15

0

15

0

15

0

15

0

15

COM₈₈

:

15

COM₁₂₁

COM₁₂₂

:

0

COM₁₃₀

COM₁₃₁

COM₁₃₂

COM₁₃₃

COM₁₃₄

COM₁₃₅

COM₁₃₆

COM₁₃₇

COM₁₃₈

:

0

15

0

COM₁₄₅

COM₁₄₆

:

15

0

COM₁₅₃

:

15

COM₁₆₀

COM₁₆₁

15

DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line

- 89 -

NJU6825

(32-6)Initial display line “0”, 1/16 duty cycle (Common backward scan)

SHIFT=”1”(Common backward scan), DS₃, ₂, , ₀=”1111”, LA₇….LA₀=”00000000”(Initial display line 0)

1

SC₃

SC₂

SC₁

SC₀

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

15

COM₀

COM₁

COM₂

COM₃

COM₄

COM₅

COM₆

COM₇

COM₈

15

COM₉

COM₁₀

COM₁₁

COM₁₂

COM₁₃

COM₁₄

COM₁₅

COM₁₆

COM₁₇

COM₁₈

COM₁₉

COM₂₀

COM₂₁

COM₂₂

COM₂₃

COM₂₄

COM₂₅

COM₂₆

COM₂₇

COM₂₈

COM₂₉

COM₃₀

COM₃₁

:

0

15

0

15

0

COM₃₉

:

0

COM₇₃

:

15

COM₈₁

COM₈₂

COM₈₃

COM₈₄

COM₈₅

COM₈₆

COM₈₇

COM₈₈

COM₈₉

COM₉₀

COM₉₁

COM₉₂

COM₉₃

COM₉₄

COM₉₅

COM₉₆

COM₉₇

:

15

0

15

0

15

COM₁₀₄

COM₁₀₅

COM₁₀₆

COM₁₀₇

COM₁₀₈

COM₁₀₉

COM₁₁₀

COM₁₁₁

COM₁₁₂

COM₁₁₃

:

0

15

0

15

COM₁₂₀

COM₁₂₁

COM₁₂₂

COM₁₂₃

COM₁₂₄

COM₁₂₅

COM₁₂₆

COM₁₂₇

COM₁₂₈

COM₁₂₉

COM₁₃₀

COM₁₃₁

COM₁₃₂

COM₁₃₃

COM₁₃₄

COM₁₃₅

COM₁₃₆

COM₁₃₇

:

0

15

0

15

0

15

COM₁₄₄

COM₁₄₅

COM₁₄₆

COM₁₄₇

COM₁₄₈

COM₁₄₉

COM₁₅₀

COM₁₅₁

COM₁₅₂

:

0

15

0

COM₁₆₀

COM₁₆₁

0

DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line

- 90 -

NJU6825

(32-7)Initial display line “5”, 1/163 duty cycle (Common forward scan)

SHIFT=”0”(Common forward scan), DS₃, ₂, , ₀=”0000”, LA₇….LA₀=”00000101”(Initial display line 5)

1

SC₃

SC₂

SC₁

SC₀

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

94

1100

45

1101

37

1110

29

1111

21

COM₀

COM₁

COM₂

COM₃

COM₄

COM₅

COM₆

COM₇

COM₈

COM₉

COM₁₀

COM₁₁

COM₁₂

COM₁₃

COM₁₄

COM₁₅

COM₁₆

COM₁₇

COM₁₈

COM₁₉

COM₂₀

COM₂₁

COM₂₂

COM₂₃

COM₂₄

COM₂₅

COM₂₆

COM₂₇

COM₂₈

:

5

4

5

158

153

150

142

134

126

118

110

102

161

0

161

0

5

161

0

5

161

0

5

161

0

COM₃₃

COM₃₄

COM₃₅

COM₃₆

:

5

161

0

COM₄₁

COM₄₂

COM₄₃

COM₄₄

:

5

161

0

COM₄₉

COM₅₀

COM₅₁

COM₅₂

COM₅₃

COM₅₄

COM₅₅

COM₅₆

COM₅₇

COM₅₈

COM₅₉

COM₆₀

:

5

161

0

5

1161

0

COM₆₅

COM₆₆

COM₆₇

COM₆₈

COM₆₉

COM₇₀

COM₇₁

COM₇₂

COM₇₃

:

5

161

0

5

COM₁₁₆

COM₁₁₇

:

161

0

COM₁₂₂

COM₁₂₃

COM₁₂₄

COM₁₂₅

COM₁₂₆

COM₁₂₇

COM₁₂₈

COM₁₂₉

COM₁₃₀

COM₁₃₁

COM₁₃₂

COM₁₃₃

COM₁₃₄

COM₁₃₅

COM₁₃₆

COM₁₃₇

COM₁₃₈

COM₁₃₉

COM₁₄₀

COM₁₄₁

COM₁₄₂

COM₁₄₃

COM₁₄₄

COM₁₄₅

COM₁₄₆

:

5

161

0

5

161

0

5

161

0

5

COM₁₅₆

COM₁₅₇

COM₁₅₈

COM₁₅₉

COM₁₆₀

COM₁₆₁

161

0

161

0

4

3

157

161

152

161

149

161

141

161

133

161

125

161

117

161

109

161

101

161

93

44

36

28

20

(163^rdCOM period) *1

161

DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line

*1 : 163^rdCOM period is not selected.

- 91 -

NJU6825

(32-8)Initial display line “5”, 1/163 duty cycle (Common backward scan)

SHIFT=”1”(Common backward scan), DS₃, ₂, , ₀=”0000”, LA₇….LA₀=”00000101”(Initial display line 5)

1

SC₃

SC₂

SC₁

SC₀

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

93

1100

44

1101

36

1110

28

1111

20

COM₀

4

3

157

151

149

141

133

125

117

109

101

COM₁

COM₂

COM₃

0

COM₄

0

161

COM₅

161

:

COM₁₅

COM₁₆

COM₁₇

COM₁₈

COM₁₉

COM₂₀

COM₂₁

COM₂₂

COM₂₃

COM₂₄

COM₂₅

COM₂₆

COM₂₇

COM₂₈

COM₂₉

COM₃₀

COM₃₁

COM₃₂

COM₃₃

COM₃₄

COM₃₅

COM₃₆

COM₃₇

COM₃₈

COM₃₉

COM₄₀

COM₄₁

COM₄₂

COM₄₃

COM₄₄

COM₄₅

:

5

0

161

5

0

161

5

0

161

5

0

161

COM₈₈

COM₈₉

COM₉₀

COM₉₁

COM₉₂

COM₉₃

COM₉₄

COM₉₅

COM₉₆

COM₉₇

COM₉₈

COM₉₉

COM₁₀₀

COM₁₀₁

COM₁₀₂

COM₁₀₃

COM₁₀₄

COM₁₀₅

COM₁₀₆

COM₁₀₇

COM₁₀₈

COM₁₀₉

COM₁₁₀

COM₁₁₁

COM₁₁₂

COM₁₁₃

COM₁₁₄

COM₁₁₅

COM₁₁₆

COM₁₁₇

COM₁₁₈

COM₁₁₉

COM₁₂₀

:

5

0

161

5

0

161

5

0

161

5

0

161

5

COM₁₂₅

COM₁₂₆

COM₁₂₇

COM₁₂₈

COM₁₂₉

COM₁₃₀

COM₁₃₁

COM₁₃₂

COM₁₃₃

COM₁₃₄

COM₁₃₅

COM₁₃₆

:

0

161

5

0

161

5

COM₁₄₁

COM₁₄₂

COM₁₄₃

COM₁₄₄

COM₁₄₅

COM₁₄₆

COM₁₄₇

COM₁₄₈

COM₁₄₉

COM₁₅₀

COM₁₅₁

COM₁₅₂

COM₁₅₃

COM₁₅₄

COM₁₅₅

COM₁₅₆

COM₁₅₇

COM₁₅₈

COM₁₅₉

COM₁₆₀

COM₁₆₁

0

161

5

0

161

0

161

5

0

161

5

4

5

158

161

152

161

150

161

142

161

134

161

126

161

118

161

110

161

102

161

94

45

37

29

21

(163^rdCOM period) *1

161

DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line

*1 : 163^rdCOM period is not selected.

- 92 -

NJU6825

(32-9)Initial display line “5”, 1/80 duty cycle (Common forward scan)

SHIFT=”0”(Common forward scan), DS₃, ₂, , ₀=”0111”, LA₇….LA₀=”00000101”(Initial display line 5)

1

SC₃

SC₂

SC₁

SC₀

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

45

1101

37

1110

29

1111

21

COM₀

COM₁

:

5

COM₉

COM₁₀

COM₁₁

COM₁₂

COM₁₃

COM₁₄

COM₁₅

COM₁₆

COM₁₇

COM₁₈

:

5

COM₂₅

COM₂₆

:

5

COM₃₃

:

5

COM₃₉

COM₄₀

COM₄₁

:

84

5

COM₄₇

COM₄₈

COM₄₉

COM₅₀

COM₅₁

COM₅₂

COM₅₃

COM₅₄

COM₅₅

COM₅₆

COM₅₇

COM₅₈

COM₅₉

COM₆₀

COM₆₁

COM₆₂

COM₆₃

COM₆₄

COM₆₅

COM₆₆

COM₆₇

COM₆₈

COM₆₉

COM₇₀

COM₇₁

COM₇₂

COM₇₃

COM₇₄

COM₇₅

COM₇₆

COM₇₇

COM₇₈

COM₇₉

COM₈₀

COM₈₁

:

84

5

84

5

84

5

84

COM₈₈

COM₈₉

COM₉₀

COM₉₁

COM₉₂

COM₉₃

COM₉₄

COM₉₅

COM₉₆

COM₉₇

:

84

COM₁₀₄

COM₁₀₅

:

84

COM₁₁₂

COM₁₁₃

:

84

COM₁₂₀

COM₁₂₁

COM₁₂₂

COM₁₂₃

COM₁₂₄

COM₁₂₅

COM₁₂₆

COM₁₂₇

COM₁₂₈

COM₁₂₉

COM₁₃₀

COM₁₃₁

COM₁₃₂

COM₁₃₃

COM₁₃₄

COM₁₃₅

COM₁₃₆

COM₁₃₇

COM₁₃₈

COM₁₃₉

COM₁₄₀

COM₁₄₁

COM₁₄₂

COM₁₄₃

COM₁₄₄

COM₁₄₅

COM₁₄₆

COM₁₄₇

COM₁₄₈

COM₁₄₉

COM₁₅₀

COM₁₅₁

COM₁₅₂

:

84

5

84

5

84

5

84

5

84

COM₁₆₀

COM₁₆₁

44

36

28

20

DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line

- 93 -

NJU6825

(32-10)Initial display line “5”, 1/80 duty cycle (Common backward scan)

SHIFT=”1”(Common backward scan), DS₃, ₂, , ₀=”0111”, LA₇….LA₀=”00000101”(Initial display line 5)

1

SC₃

SC₂

SC₁

SC₀

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

84

1100

44

1101

36

1110

28

1111

20

COM₀

:

COM₉

COM₁₀

COM₁₁

COM₁₂

COM₁₃

COM₁₄

COM₁₅

COM₁₆

COM₁₇

COM₁₈

COM₁₉

COM₂₀

COM₂₁

COM₂₂

COM₂₃

COM₂₄

COM₂₅

COM₂₆

COM₂₇

COM₂₈

COM₂₉

COM₃₀

COM₃₁

COM₃₂

COM₃₃

COM₃₄

COM₃₅

COM₃₆

COM₃₇

COM₃₈

COM₃₉

COM₄₀

COM₄₁

:

5

84

5

84

5

84

5

84

COM₄₉

:

84

COM₅₇

:

84

COM₆₅

COM₆₆

COM₆₇

COM₆₈

COM₆₉

COM₇₀

COM₇₁

COM₇₂

COM₇₃

:

84

COM₈₁

COM₈₂

COM₈₃

COM₈₄

COM₈₅

COM₈₆

COM₈₇

COM₈₈

:

84

5

COM₉₆

COM₉₇

COM₉₈

COM₉₉

COM₁₀₀

COM₁₀₁

COM₁₀₂

COM₁₀₃

COM₁₀₄

COM₁₀₅

COM₁₀₆

COM₁₀₇

COM₁₀₈

COM₁₀₉

COM₁₁₀

COM₁₁₁

COM₁₁₂

COM₁₁₃

COM₁₁₄

COM₁₁₅

COM₁₁₆

COM₁₁₇

COM₁₁₈

COM₁₁₉

COM₁₂₀

COM₁₂₁

COM₁₂₂

COM₁₂₃

COM₁₂₄

COM₁₂₅

COM₁₂₆

COM₁₂₇

COM₁₂₈

:

5

84

5

84

5

84

5

84

5

COM₁₃₆

:

5

COM₁₄₄

COM₁₄₅

COM₁₄₆

:

5

COM₁₅₂

:

5

COM₁₆₀

COM₁₆₁

5

45

37

29

21

DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line

- 94 -

NJU6825

(32-11)Initial display line “5”, 1/16 duty cycle (Common forward scan)

SHIFT=”0”(Common forward scan), DS₃, ₂, , ₀=”1111”, LA₇….LA₀=”00000101”(Initial display line 5)

1

SC₃

SC₂

SC₁

SC₀

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

COM₀

COM₁

COM₂

:

5

COM₉

COM₁₀

COM₁₁

COM₁₂

COM₁₃

COM₁₄

COM₁₅

COM₁₆

COM₁₇

COM₁₈

COM₁₉

COM₂₀

COM₂₁

COM₂₂

COM₂₃

COM₂₄

COM₂₅

COM₂₆

COM₂₇

COM₂₈

COM₂₉

COM₃₀

COM₃₁

COM₃₂

COM₃₃

COM₃₄

COM₃₅

COM₃₆

COM₃₇

COM₃₈

COM₃₉

COM₄₀

COM₄₁

COM₄₂

COM₄₃

COM₄₄

COM₄₅

COM₄₆

COM₄₇

COM₄₈

COM₄₉

COM₅₀

COM₅₁

COM₅₂

COM₅₃

COM₅₄

COM₅₅

COM₅₆

COM₅₇

COM₅₈

COM₅₉

COM₆₀

COM₆₁

COM₆₂

COM₆₃

COM₆₄

COM₆₅

COM₆₆

COM₆₇

COM₆₈

COM₆₉

COM₇₀

COM₇₁

COM₇₂

COM₇₃

COM₇₄

COM₇₅

COM₇₆

COM₇₇

COM₇₈

COM₇₉

COM₈₀

COM₈₁

:

5

20

5

20

5

20

5

20

5

20

5

20

5

20

5

20

5

20

COM₈₈

:

20

COM₁₂₁

COM₁₂₂

:

5

COM₁₃₀

COM₁₃₁

COM₁₃₂

COM₁₃₃

COM₁₃₄

COM₁₃₅

COM₁₃₆

COM₁₃₇

COM₁₃₈

:

5

20

5

COM₁₄₅

COM₁₄₆

:

20

5

COM₁₅₃

:

20

COM₁₆₀

COM₁₆₁

20

DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line

- 95 -

NJU6825

(32-12)Initial display line “5”, 1/16 duty cycle (Common backward scan)

SHIFT=”1”(Common backward scan), DS₃, ₂, , ₀=”1111”, LA₇….LA₀=”00000101”(Initial display line 5)

1

SC₃

SC₂

SC₁

SC₀

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

20

COM₀

COM₁

COM₂

COM₃

COM₄

COM₅

COM₆

COM₇

COM₈

20

COM₉

COM₁₀

COM₁₁

COM₁₂

COM₁₃

COM₁₄

COM₁₅

COM₁₆

COM₁₇

COM₁₈

COM₁₉

COM₂₀

COM₂₁

COM₂₂

COM₂₃

COM₂₄

COM₂₅

COM₂₆

COM₂₇

COM₂₈

COM₂₉

COM₃₀

COM₃₁

:

5

20

5

20

5

COM₃₉

:

5

COM₇₃

:

20

COM₈₁

COM₈₂

COM₈₃

COM₈₄

COM₈₅

COM₈₆

COM₈₇

COM₈₈

COM₈₉

COM₉₀

COM₉₁

COM₉₂

COM₉₃

COM₉₄

COM₉₅

COM₉₆

COM₉₇

:

20

5

20

5

20

COM₁₀₄

COM₁₀₅

COM₁₀₆

COM₁₀₇

COM₁₀₈

COM₁₀₉

COM₁₁₀

COM₁₁₁

COM₁₁₂

COM₁₁₃

:

5

20

5

20

COM₁₂₀

COM₁₂₁

COM₁₂₂

COM₁₂₃

COM₁₂₄

COM₁₂₅

COM₁₂₆

COM₁₂₇

COM₁₂₈

COM₁₂₉

COM₁₃₀

COM₁₃₁

COM₁₃₂

COM₁₃₃

COM₁₃₄

COM₁₃₅

COM₁₃₆

COM₁₃₇

:

5

20

5

20

5

20

COM₁₄₄

COM₁₄₅

COM₁₄₆

COM₁₄₇

COM₁₄₈

COM₁₄₉

COM₁₅₀

COM₁₅₁

COM₁₅₂

:

5

20

5

COM₁₆₀

COM₁₆₁

5

DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line

- 96 -

NJU6825

ꢀꢀ ABSOLUTE MAXIMUM RATINGS

PARAMETER

Supply Voltage (1)

Supply Voltage (2)

Supply Voltage (3)

Supply Voltage (4)

Supply Voltage (5)

Supply Voltage (6)

Input Voltage

SYMBOL

V_DD

V_EE

V_OUT

V_REG

V_LCD

V₁, V₂, V₃, V₄

V_I

CONDITION

TERMINAL

V_DD

RATING

-0.3 to +4.0

UNIT

V

°C

V_EE

V_OUT

V_REG

V_LCD

-0.3 to +20.0

-0.3 to V_LCD+ 0.3

-0.3 to V_DD+ 0.3

-45 to +125

V_SS=0V

Ta = +25°C

V₁, V₂, V₃, V₄

*1

Storage Temperature

T_stg

Note 1) D₀to D₁₅, CS, RS, RD, WR, OSC₁, RES, TEST_1,TEST₂, terminals.

ꢀ

RECOMMENDED OPERATING CONDITIONS

PARAMETER

SYMBOL

V_DD1

V_DD2

V_EE

V_LCD

V_OUT

V_REG

V_REF

TERMINAL

V_DD

MIN

1.7

2.4

5

TYP

MAX

3.3

UNIT

V

NOTE

*1

*2

*3

*4

Supply Voltage

V_EE

V_LCD

V_OUT

V_REG

V_REF

3.3

18.0

_OUT× 0.9

3.3

Operating Voltage

V

2.1

-30

*5

Operating

Temperature

T_opr

85

°C

Note1) Applies to the condition when the reference voltage generator is not used.

Note2) Applies to the condition when the reference voltage generator is used.

Note3) Applies to the condition when the voltage booster is used.

Note4) The following relationship among the supply voltages must be maintained.

V_SS<V₄<V₃<V₂<V₁<V_LCD<V_OUT

Note5) The relationship: V_REF<V_EEmust be maintained.

- 97 -

NJU6825

ꢀꢀ DC CHARACTERISTICS 1

V_SS= 0V, V_DD= +1.7 to +3.3V, Ta = -30 to +85°C

SYM

PARAMETER

BOL

CONDITION

MIN

TYP

MAX

UNIT NOTE

V_IH

V_IL

High level input voltage

Low level input voltage

High level output voltage

Low level output voltage

High level output voltage

Low level output voltage

Input leakage current

0.8 V_DD

0

V_DD- 0.4

V_DD

0.2V_DD

V

µA

*1

*2

*3

*4

*5

V_OH1

V_OL1

V_OH2

V_OL2

I_LI

I_OH= -0.4mA

I_OL= 0.4mA

I_OH= -0.1mA

I_OL= 0.1mA

V_I= V_SSor V_DD

0.4

V_DD- 0.4

0.4

10

2

-10

I_LO

Output leakage current

V_LCD= 10V

V_LCD= 6V

1

2

R_ON1

Driver ON-resistance

Stand-by current

*6

|∆V_ON| = 0.5V

kΩ

µA

4

I_STB

V_DD= 3V

15

*7

CS=V_DD, Ta=25°C

f_OSC1

f_OSC2

f_OSC3

f_r1

625

141

20.5

763

172

25

750

185

27.2

900

203

29.5

*8

*9

*10

V_DD= 3V

Ta = 25°C

Internal oscillation

Frequency

kHz

Rf=10kΩ

Rf=51kΩ

Rf=390kΩ

N-time booster (N=2 to 7)

RL = 500kΩ (V_OUT- V_SS

V_DD= 2.5V, 7-time booster

Whole ON pattern

V_DD= 2.5V, 7-time booster

Checker pattern

V_DD= 3V, 6-time booster

Whole ON pattern

V_DD= 3V, 6-time booster

Checker pattern

V_DD= 3V, 5-time booster

Whole ON pattern

V_DD= 3V, 5-time booster

Checker pattern

External oscillation

Frequency

f_r2

kHz

V

*11

*12

f_r3

Voltage converter

output voltage

(N x V_EE

x 0.95

)

V_OUT

I_DD1

I_DD2

I_DD3

I_DD4

I_DD5

I_DD6

I_DD7

I_DD8

V_BA

)

Supply current (1)

Supply current (2)

Supply current (3)

Supply current (4)

Supply current (5)

Supply current (6)

Supply current (7)

Supply current (8)

V_BAOperating voltage

870

1060

760

1300

1590

1140

1400

780

930

*13

µA

520

650

980

V_DD= 3V, 4-time booster

Whole ON pattern

V_DD= 3V, 4-time booster

Checker pattern

360

540

450

680

(0.9 V_EE

x 0.98

)

(0.9 V_EE

x 1.02

)

V_EE= 2.4 to 3.3V

0.9 V_EE

V

*14

*15

V_EE= 2.4 to 3.3V

(V_REFx N)

x 0.97

(V_REFx N)

x 1.03

V_REG

(V_REFx N)

V_REGOperating voltage

V_REF= 0.9 x V_EE

N-time booster (N=2 to 7)

V₂

-100

-30

0

+100

+30

V₃

Output Voltage

V_D12

V_D34

V_D24

mV

*16

- 98 -

NJU6825

ꢀꢀ CLOCK and FRAME FREQUENCY

Display duty cycle ratio (1/D)

1/80 to 1/56 1/48 to 1/32

PARAMETER SYMBOL

NOTE

Display mode

1/163 to 1/96

f_OSC/ (62xD)

1/24 to 1/16

16 Gradation mode

f_OSC/ (62xDx2) f_OSC/ (62xDx4) f_OSC/ (62xDx8)

f_OSC/ (14xDx2) f_OSC/ (14xDx4) f_OSC/ (14xDx8)

Internal

f_OSC

Simplified

8 gradation mode

f

_OSC/ (14xD)

_OSC/ (2xD)

f_CK/ (62xD)

_CK/ (14xD)

_CK/ (2xD)

clock

B&W mode

f

f_OSC/ (2xDx2)

f_CK/ (62xDx2)

f_CK/ (14xDx2)

f_CK/ (2xDx2)

f_OSC/ (2xDx4)

f_CK/ (62xDx4)

f_CK/ (14xDx4)

f_CK/ (2xDx4)

f_OSC/ (2xDx8)

f_CK/ (62xDx8)

f_CK/ (14xDx8)

f_CK/ (2xDx8)

FLM

16 Gradation mode

External

f_CK

Simplified

8 gradation mode

f

clock

B&W mode

f

- 99 -

NJU6825

APPLIED TERMINALS and CONDITIONS

Note 1) D₀-D₁₅, CS, RS, RD, WR, P/S, SEL68, RES

Note 2) D₀-D₁₅

Note 3) CL, FLM, FR, CLK

Note 4) CS, RS, SEL68, RD, WR, P/S, RES, OSC₁

Note 5) D₀-D₁₅in the high impedance

Note 6) SEGA₀-SEGA₁₂₇, SEGB₀-SEGB₁₂₇, SEGC₀-SEGC₁₂₇, COM₀-COM₁₆₁

Defines the resistance between each of the SEG and COM terminals and each of the power supply

terminals (V_LCD, V₁, V₂, V₃and V₄) in the 0.5V deference and 1/9 LCD bias ratio.

Note 7) V_DD

The oscillator is halted, CS=”1” (disabled), No-load onto the segment and common drivers

Note 8) OSC

Defines the internal oscillation frequency at (Rf₂, Rf₁, Rf₀)=(0,0,0) in the variable gradation mode.

Note 9) OSC

Defines the internal oscillation frequency at (Rf₂, Rf₁, Rf₀)=(0,0,0) in the fixed gradation mode.

Note 10) OSC

Defines the internal oscillation frequency at (Rf₂, Rf₁, Rf₀)=(0,0,0) in the Black & White mode.

Note 11) V_DD=3V, Ta=25°C

Note 12) V_OUT

Applies to the condition when the internal voltage booster (N=2-7), internal oscillator and internal

power circuits are used. V_EE=2.4V to 3.3V, EVR= (1,1,1,1,1,1,1)

1/5 to 1/12 LCD bias, 1/163 duty cycle, No-load on segment and common drivers

RL=500Kohm between V_OUTand V_SS, CA₁=CA₂=1.0uF, CA₃=0.1uF, DCON=”1”, AMPON=”1”

Note 13) V_DD

Applies to the condition when using the internal oscillator and internal power circuits without any

access from MPU. EVR= (1,1,1,1,1,1,1), All pixels turned-on or checkerboard display in gradation

mode.

No-load onto the segment and common drivers

V_DD=V_EE, V_REF=0.9V_EE, CA₁=CA₂=1.0uF, CA₃=0.1uF, DCON=”1”, AMPON=”1”, NLIN=”0”

1/163 Duty cycle, Ta=25°C

Note 14) V_BA

Applies to the condition that V_BA=V_REFand voltage booster N= 1.

When DCON=”0”, V_OUT=13.5V input.

Note 15) V_REG

V_EE=2.4V to 3.3V, V_REF=0.9V_EE, 1/5 to 1/12 LCD bias ratio, 1/163 duty cycle, EVR=(1,1,1,1,1,1,1)

Checkerboard display, No-load onto the segment and common drivers, voltage booster N=2 to 7

CA₁=CA₂=1.0uF, CA₃=0.1uF, DCON=”1”, AMPON=”1”, NLIN=”0”

Note 16) V_LCD, V₁, V₂, V₃, V₄

V_EE=3.0V, V_REF=0.9V_EE, V_OUT=15V, 1/5 to 1/12 LCD Bias, EVR= (1,1,1,1,1,1,1), Display OFF, No-

load onto the segment and common drivers, voltage booster N=5, CA₁=CA₂=1.0uF, CA₃=0.1uF,

DCON=”1”, AMPON=”1”

V_LCD

(1)

(2)

V_D12: (1)-(2)

V_D34: (3)-(4)

V_D24: (2)-(4)

V₁

V₂

V₃

V₄

V_SS

(3)

(4)

- 100 -

NJU6825

ꢀꢀ AC CHARACTERISTICS

ꢁ Write operation (80-type MPU)

t_AS8

t_AH8

CS

RS

WR

t_WRLW8

t_WRHW8

t_DS8

t_DH8

D₀to D₁₅

t_CYC8

(V_DD=2.5 to 3.3V, Ta=-30 to +85°C)

PARAMETER

SYMBOL CONDITION

MIN.

MAX.

UNIT

TERMINAL

Address hold time

Address setup time

t_AH8

t_AS8

0

ns

CS

RS

System cycle time

Enable ”L” level pulse width

Enable ”H” level pulse width

t_CYC8

t_WRLW8

t_WRHW8

90

35

ns

WR

Data setup time

Data hold time

t_DS8

t_DH8

30

5

ns

D₀to D₁₅

(V_DD=2.2 to 2.5V, Ta=-30 to +85°C)

PARAMETER

SYMBOL CONDITION

MIN.

MAX.

UNIT

TERMINAL

Address hold time

Address setup time

t_AH8

t_AS8

0

ns

CS

RS

System cycle time

Enable ”L” level pulse width

Enable ”H” level pulse width

t_CYC8

t_WRLW8

t_WRHW8

160

70

ns

WR

Data setup time

Data hold time

t_DS8

t_DH8

40

5

ns

D₀to D₁₅

(V_DD=1.7 to 2.2V, Ta=-30 to +85°C)

PARAMETER

SYMBOL CONDITION

MIN.

MAX.

UNIT

TERMINAL

Address hold time

Address setup time

t_AH8

t_AS8

0

ns

CS

RS

System cycle time

Enable ”L” level pulse width

Enable ”H” level pulse width

t_CYC8

t_WRLW8

t_WRHW8

180

80

ns

WR

Data setup time

Data hold time

t_DS8

t_DH8

70

10

ns

D₀to D₁₅

Note) Each timing is specified based on 20% and 80% of V_DD.

- 101

NJU6825

ꢁ

Read operation (80-type MPU)

t_AH8

t_AS8

CS

RS

t_WRLR8

RD

t_WRHR8

t_RDH8

D₀to D₁₅

t_RDD8

t_CYC8

(V_DD=2.5 to 3.3V, Ta=-30 to +85°C)

PARAMETER

SYMBOL CONDITION

MIN.

MAX.

UNIT

TERMINAL

Address hold time

Address setup time

t_AH8

t_AS8

0

ns

CS

RS

System cycle time

Enable ”L” level pulse width

Enable ”H” level pulse width

t_CYC8

t_WRLR8

t_WRHR8

180

80

ns

RD

Read Data setup time

Read Data hold time

T_RDD8

60

ns

CL=15pF

T_RDH8

D₀to D₁₅

0

(V_DD=2.2 to 2.5V, Ta=-30 to +85°C)

PARAMETER

SYMBOL CONDITION

MIN.

MAX.

UNIT

TERMINAL

Address hold time

Address setup time

t_AH8

t_AS8

0

ns

CS

RS

System cycle time

Enable ”L” level pulse width

Enable ”H” level pulse width

t_CYC8

t_WRLR8

t_WRHR8

180

80

ns

RD

Read Data setup time

Read Data hold time

T_RDD8

60

ns

CL=15pF

T_RDH8

D₀to D₁₅

0

(V_DD=1.7 to 2.2V, Ta=-30 to +85°C)

PARAMETER

SYMBOL CONDITION

MIN.

MAX.

UNIT

TERMINAL

Address hold time

Address setup time

t_AH8

t_AS8

0

ns

CS

RS

System cycle time

Enable ”L” level pulse width

Enable ”H” level pulse width

t_CYC8

t_WRLR8

t_WRHR8

250

120

ns

RD

Read Data setup time

Read Data hold time

t_RDD8

110

ns

CL=15pF

t_RDH8

D₀to D₁₅

0

Note) Each timing is specified based on 20% and 80% of V_DD.

- 102 -

NJU6825

ꢁ Write operation (68-type MPU)

t_AS6

t_AH6

CS

RS

R/W

(WR)

t_ELW6

t_EHW6

E

(RD)

t_DS6

t_DH6

D₀to D₁₅

t_CYC6

(V_DD=2.5 to 3.3V, Ta=-30 to +85°C)

PARAMETER

SYMBOL CONDITION

MIN.

MAX.

UNIT

TERMINAL

Address hold time

Address setup time

t_AH6

t_AS6

0

ns

CS

RS

System cycle time

Enable ”L” level pulse width

Enable ”H” level pulse width

t_CYC6

t_ELW6

t_EHW6

90

35

ns

E

Data setup time

Data hold time

t_DS6

t_DH6

40

5

ns

D₀to D₁₅

(V_DD=2.2 to 2.5V, Ta=-30 to +85°C)

PARAMETER

SYMBOL CONDITION

MIN.

MAX.

UNIT

TERMINAL

Address hold time

Address setup time

t_AH6

t_AS6

0

ns

CS

RS

System cycle time

Enable ”L” level pulse width

Enable ”H” level pulse width

t_CYC6

t_ELW6

t_EHW6

160

70

ns

E

Data setup time

Data hold time

t_DS6

t_DH6

50

5

ns

D₀to D₁₅

(V_DD=1.7 to 2.2V, Ta=-30 to +85°C)

PARAMETER

SYMBOL CONDITION

MIN.

MAX.

UNIT

TERMINAL

Address hold time

Address setup time

t_AH6

t_AS6

0

ns

CS

RS

System cycle time

Enable ”L” level pulse width

Enable ”H” level pulse width

t_CYC6

t_ELW6

t_EHW6

180

80

ns

E

Data setup time

Data hold time

t_DS6

t_DH6

70

10

ns

D₀to D₁₅

Note) Each timing is specified based on 20% and 80% of V_DD.

- 103

NJU6825

ꢁ Read operation (68-type MPU)

t_AS6

t_AH6

CS

RS

R/W

(WR)

t_ELR6

t_EHR6

E

(RD)

t_RDH6

D₀to D₁₅

t_RDD6

t_CYC6

(V_DD=2.5 to 3.3V, Ta=-30 to +85°C)

PARAMETER

SYMBOL

t_AH6

CONDITION

MIN.

MAX.

UNIT

TERMINAL

Address hold time

Address setup time

0

ns

CS

RS

t_AS6

System cycle time

Enable ”L” level pulse width

Enable ”H” level pulse width

t_CYC6

t_ELR6

t_EHR6

180

80

ns

E

Read Data setup time

Read Data hold time

t_RDD6

t_RDH6

ns

70

CL=15pF

D₀to D₁₅

0

(V_DD=2.2 to 2.5V, Ta=-30 to +85°C)

PARAMETER

SYMBOL

CONDITION

MIN.

MAX.

UNIT

TERMINAL

Address hold time

Address setup time

t_AH6

t_AS6

0

ns

CS

RS

System cycle time

Enable ”L” level pulse width

Enable ”H” level pulse width

t_CYC6

t_ELR6

t_EHR6

180

80

ns

E

Read Data setup time

Read Data hold time

t_RDD6

t_RDH6

ns

70

CL=15pF

D₀to D₁₅

0

(V_DD=1.7 to 2.2V, Ta=-30 to +85°C)

PARAMETER

SYMBOL

CONDITION

MIN.

MAX.

UNIT

TERMINAL

Address hold time

Address setup time

t_AH6

t_AS6

0

ns

CS

RS

System cycle time

Enable ”L” level pulse width

Enable ”H” level pulse width

t_CYC6

t_ELR6

t_EHR6

250

120

ns

E

Read Data setup time

Read Data hold time

t_RDD6

t_RDH6

ns

110

CL=15pF

D0 to D15

0

Note) Each timing is specified based on 20% and 80% of V_DD.

- 104 -

NJU6825

ꢁ Serial interface

t_CSH

t_CSS

CS

RS

t_ASS

t_AHS

t_SLW

t_SHW

SCL

t_CYCS

t_DSS

t_DHS

SDA

(V_DD=2.5 to 3.3V, Ta=-30 to +85°C)

UNIT

PARAMETER

Serial clock cycle

SCL ”H” level pulse width

SCL ”L” level pulse width

Address setup time

Address hold time

Data setup time

SYMBOL CONDITION

MIN.

MAX.

TERMINAL

t_CYCS

t_SHW

t_SLW

t_ASS

t_AHS

t_DSS

t_DHS

50

20

ns

SCL

RS

SDA

Data hold time

CS – SCL time

CS hold time

t_CSS

t_CSH

20

ns

CS

(V_DD=2.2 to 2.5V, Ta=-30 to +85°C)

UNIT

PARAMETER

SYMBOL CONDITION

MIN.

MAX.

TERMINAL

Serial clock cycle

t_CYCS

t_SHW

t_SLW

t_ASS

t_AHS

t_DSS

t_DHS

50

20

ns

SCL ”H” level pulse width

SCL ”L” level pulse width

Address setup time

Address hold time

Data setup time

SCL

RS

SDA

Data hold time

CS – SCL time

CS hold time

t_CSS

t_CSH

20

ns

CS

(V_DD=1.7 to 2.2V, Ta=-30 to +85°C)

UNIT

PARAMETER

SYMBOL CONDITION

MIN.

MAX.

TERMINAL

Serial clock cycle

t_CYCS

t_SHW

t_SLW

t_ASS

t_AHS

t_DSS

t_DHS

80

35

ns

SCL ”H” level pulse width

SCL ”L” level pulse width

Address setup time

Address hold time

Data setup time

SCL

RS

SDA

Data hold time

CS – SCL time

CS hold time

t_CSS

t_CSH

35

ns

CS

Note) Each timing is specified based on 20% and 80% of V_DD.

- 105

NJU6825

ꢁ Display control timing

CLK

t_DCL

CL

t_DFLM

FLM

t_FR

FR

Output timing

(V_DD=2.4 to 3.3V, Ta=-30 to +85°C)

PARAMETER

FLM delay time

FR delay time

SYMBOL CONDITION

t_DFLMCL=15pF

t_FR

MIN.

MAX.

500

UNIT

ns

TERMINAL

FLM

0

FR

CL

CL delay time

t_DCL

200

ns

Output timing

(V_DD=1.7 to 2.4V, Ta=-30 to +85°C)

PARAMETER

FLM delay time

FR delay time

SYMBOL CONDITION

t_DFLMCL=15pF

t_FR

MIN.

MAX.

1000

200

UNIT

ns

TERMINAL

FLM

0

FR

CL

CL delay time

t_DCL

ns

Note) Each timing is specified based on 20% and 80% of V_DD.

- 106 -

NJU6825

ꢁ Input clock timing

t_CKLW

t_CKHW

OSC₁

(V_DD=1.7 to 3.3V, Ta=-30 to +85°C)

UNIT

PARAMETER

SYMBOL CONDITION

MIN.

MAX.

0.800

3.54

24.4

TERMINAL

OSC₁

1

OSC₁

2

OSC₁

3

OSC₁“H” level pulse width (1)

OSC₁“L” level pulse width (1)

OSC₁“H” level pulse width (2)

OSC₁“L” level pulse width (2)

OSC₁“H” level pulse width (3)

OSC₁“L” level pulse width (3)

t_CKHW1

t_CKLW1

t_CKHW2

t_CKLW2

t_CKHW3

t_CKLW3

0.555

2.46

16.9

µs

24.4

Note) Each timing is specified based on 20% and 80% of V_DD.

Note 1) Applied in the variable gradation mode

Note 2) Applied in the fixed gradation mode

Note 3) Applied in the B&W mode

- 107

NJU6825

ꢁ Reset input timing

t_RW

RES

t_R

Internal circuit

status

During reset

End of reset

(V_DD=2.4 to 3.3V, Ta=-30 to +85°C)

UNIT

PARAMETER

Reset time

SYMBOL CONDITION

MIN.

10.0

MAX.

Terminal

t_R

1.0

µs

RES

RES “L” level pulse width

t_RW

(V_DD=1.7 to 2.4V, Ta=-30 to +85°C)

UNIT

PARAMETER

Reset time

SYMBOL CONDITION

MIN.

10.0

MAX.

Terminal

t_R

1.5

µs

RES

RES “L” level pulse width

t_RW

Note) Each timing is specified based on 20% and 80% of V_DD.

- 108 -

NJU6825

ꢁ Typical characteristic

PARAMETER

Basic delay time of gate

SYMBOL

MIN

TYP

10

MAX

UNIT

ns

Ta=+25°C, V_SS=0V, V_DD=3.0V

ꢁ Input output terminal type

(a) Input circuit

V_DD

Terminals:

CS, RS, RD, WR, SEL68,

P/S, RES

I

Input signal

V_SS(0V)

(b) Output circuit

Terminals:

FLM, CL, FR, CLK

V_DD

Output control signal

Output signal

O

V_SS(0V)

(c) Input/Output circuit

V_DD

Terminals:

D₀to D₁₅

I/O

Input signal

V_SS(0V)

Input control signal

V_DD

Output control signal

Output signal

V_SS(0V)

- 109

NJU6825

(d) Display output circuit

V_LCD

V₁/V₂

Output control

signal 1

Output control signal 2

Output control signal 4

O

Output control

signal 3

V_SS(0V)

V₃/V₄

V_SS(0V)

Terminals:

SEGA₀to SEGA₁₂₇

SEGB₀to SEGB₁₂₇

SEGC₀to SEGC₁₂₇

COM₀to COM₁₆₁

- 110 -

NJU6825

ꢀꢀ APPLICATION CIRCUIT EXAMPLES

(1) MPU Connections

80-type MPU interface

1.7V to 3.3V

V_CC

V_DD

A₀

RS

CS

A₁to A₇

Decoder

8

7

(80-type MPU)

IORQ

D₀to D₇

RD

WR

RES

GND

RES

V_SS

RESET

68-type MPU interface

1.7V to 3.3V

V_CC

V_DD

A₀

RS

CS

A₁to A₁₅

Decoder

8

15

(68-type MPU) VMA

D₀to D₇

E

D₀to D₇

RD(E)

R/W

WR(R/W)

RES

GND

RES

V_SS

RESET

Serial interface

1.7V to 3.3V

V_CC

V_DD

RS

A₀

A₁to A₇

Decoder

7

CS

(MPU)

PORT₁

PORT₂

SDA

SCL

RES

V_SS

GND

RESET

- 111

NJU6825

[CAUTION]

The specifications on this databook are only

given for information , without any guarantee

as regards either mistakes or omissions. The

application circuits in this databook are

described only to show representative usages

of the product and not intended for the

guarantee or permission of any right including

the industrial rights.

- 112 -


型号：	NJU6825CJ-Z
厂家：	NEW JAPAN RADIO
描述：	Liquid Crystal Driver, 546-Segment, CMOS, BUMP, DIE-786 驱动接口集成电路
文件：	总112页 (文件大小：1089K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NJU6825CJ-Z [NJRC]

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