SM5844AF [NPC]
Asynchronous Sample Rate Converter; 异步采样率转换器
| 型号： | SM5844AF |
| 厂家： | 
NIPPON PRECISION CIRCUITS INC |
| 描述： | Asynchronous Sample Rate Converter |
| 文件： | 总26页 (文件大小：279K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SM5844AF
NIPPON PRECISION CIRCUITS LTD.
Asynchronous Sample Rate Converter
OVERVIEW
APPLICATIONS
The SM5844AF is
a
digital audio signal,
■ Digital audio equipment, sample rate conversion
(audiovisual amplifiers, CD-R, DAT, MD and 8
mm VTRs)
■ Commercial recording/editing equipment, sample
rate conversion
asynchronous sample rate converter LSI. It reads 16
or 20-bit word length input data, and writes 16, 18,
or 20-bit word length output data. It also features a
built-in digital deemphasis filter and digital
attenuator.
■ Input data jitter elimination
The SM5844AF operates from a 5 V supply, and is
available in 44-pin QFPs.
PINOUT
FEATURES
Functions
■ Left/right-channel processing (stereo)
■ Input sample rate (fsi) ranges
• 24 to 48 kHz (256fsi mode)
• 27 to 55 kHz (384fsi mode)
■ Output sample rate (fso) range
• 20 to 100 kHz
DI
VSS
BCKI
RSTN
LRCI
TST2N
TST1N
STATE
ICLK
ICKSL
IFM1
IFM2
IISN
OW20N
■ Sample rate conversion ratio (fso/fsi)
• 0.5 to 2.0 times
■ Asynchronous input and output timing (clock
inputs)
■ System clock inputs (input and output clocks
independent)
• 256fsi or 384fsi input system clock
• 256fso or 384fso output system clock
■ Deemphasis filter
PACKAGE DIMENSIONS
Unit: mm
• IIR-type filter
44-pin QFP
• 44.1, 48 or 32 kHz
■ Digital attenuator
• 11-bit data for 1025 levels
• Smooth, incremental attenuation change
• +12 dB gain shift function
■ Direct mute function
+
12.80 0.30
-
10.00
■ Through mode operation
• Input to output direct
■ Output data clocks (LRCO, BCKO)
• External input (slave mode)
• Output system clock generated internally
(master mode)
■ CMOS-level input/outputs
■ 5 V (standard) single supply
■ 44-pin QFP
+
0.60 0.20
-
+
0.35 0.10
0.80
-
■ Molybdenum-gate CMOS process
NIPPON PRECISION CIRCUITS—1
SM5844AF
Filter Characteristics and Converter
Efficiency
Interfaces
■ Input data format
• 2s-complement, L/R alternating, serial
• Normal format (non IIS)
■ 20-bit internal data word length
■ Deemphasis filter characteristics (IIR filter)
• ±0.03 dB gain deviation from ideal filter
characteristics
Front/rear
packing
Data
Mo d e
Word length
s equence
■ Converter noise levels
• ≤ −110 dB internally-generated noise
• −98 dB (16-bit output), −110 dB (18-bit output)
and −122 dB (20-bit output) word rounding
noise
■ Anti-aliasing LPF characteristics (4 FIR filters)
with automatic output/input sample rate
conversion ratio selection
• Up converter LPF (1.0 to 2.0 times)
• Down converter LPF 1 (48.0 to 44.1 kHz or
0.92 times)
• Down converter LPF 2 (44.1 to 32.0 kHz or
0.73 times)
1
2
3
4
16 bits
Rear
MSB first
LSB first
20 bits
Front
Rear
■ Output data format
• 2s-complement, MSB first, L/R alternating,
serial
• Continuous bit clock
Front/rear
packing
Mo d e
Word length
IIS selection
• Down converter LPF 3 (48.0 to 32.0 kHz or
0.67 times)
1
2
3
4
5
6
7
16 bits
18 bits
20 bits
20 bits
16 bits
18 bits
20 bits
■ Output S/N ratio (theoretical values)
Rear
Normal (non
IIS)
S/N ratio
Output s ignal word
16-bit input word
length
20-bit input word
length
length
16 bits
18 bits
20 bits
94.8 dB
97.5 dB
97.7 dB
97 dB
106 dB
109 dB
Front
IIS
NIPPON PRECISION CIRCUITS—2
SM5844AF
BLOCK DIAGRAM
IFM1
IFM2
BCKI
DI
MCOM
MDT/FSI1
MCK/FSI2
Input data
interface
Deemphasis and
attenuator setup
MLEN/DEEM
Arithmetic
operations
ICLK
Input-stage
divider
Deemphasis
operation
ICKSL
LRCI
Input timing
controller
Attenuator
RSTN
Filter characteristic
select
Interpolation
filter operation
TST1N
TST2N
Output operation
timing controller
Output
operation
OW18N
OW20N
IISN
Dither
Output format
controller
Output data
interface
Output-stage
clock select
SLAVE
LRCI BCKI
DI
OCLK
Output-stage
divider
Through mode
switching
OCKSL
THRUN
DMUTE
Mute
generator
Direct mute
STATE
LRCO
BCKO
DOUT
NIPPON PRECISION CIRCUITS—3
SM5844AF
PIN DESCRIPTION
1
2
Nu mb e r
Na me
DI
I/O
Ip
Ip
Ip
I
Des cription
1, 2
3, 4
5
Data input
BCKI
Input bit clock
3
LRCI
Input word clock (fsi)
6
ICLK
Input system clock input
7
ICKSL
Ip
Input system clock (ICLK) select. 384fsi when HIGH, and 256fsi when LOW.
Input format select
IFM1
LOW
LOW
HIGH
HIGH
IFM2
LOW
HIGH
LOW
HIGH
Word length
Data s equence
Data pos ition
8, 9
IFM1
IFM2
Ip
Ip
16 bits
Rear packed
MSB first
20 bits
Front packed
Rear packed
10, 11
LSB first
12, 13
14, 15
VDD
–
5 V supply pin
Direct mute pin
DMUTE
Ip
Interface switch control pin. MDT, MCK and MLEN control when HIGH. FSI1, FSI2 and DEEM
control when LOW.
16
MCOM
Ip
Ip
When MCOM is LOW: Deemphasis frequency
set pins
When MCOM is HIGH: Microcontroller interface
data input (MDT)
17
MDT/FSI1
FSI1
FSI2
HIGH
LOW
HIGH
fsi
LOW
×
48.0 kHz
44.1 kHz
32.0 kHz
When MCOM is HIGH: Microcontroller interface
bit clock (MCK)
18
MCK/FSI2
Ip
Ip
HIGH
When MCOM is HIGH: Microcontroller data word latch clock (MLEN)
When MCOM is LOW: Deemphasis ON/OFF control (DEEM)
19, 20
MLEN/DEEM
Output format select
When IISN = HIGH (normal mode)
OW20N
LOW
OW18N
LOW
Word length
Data pos ition
Front packed
21, 22
OW18N
Ip
20 bits
LOW
HIGH
LOW
HIGH
HIGH
18 bits
16 bits
Rear packed
HIGH
When IISN = LOW (IIS mode)
OW20N
LOW
OW18N
LOW
Word length
Data pos ition
20 bits
23, 24
OW20N
Ip
LOW
HIGH
LOW
IIS mode
Front packed
HIGH
HIGH
18 bits
16 bits
HIGH
25, 26
27
IISN
Ip
O
Ip
Ip
IIS output mode select. Normal mode when HIGH, and IIS mode when LOW.
Internal operation status output (for operation check)
STATE
TST1N
TST2N
28
Output dither control. Dither ON when LOW, and OFF when HIGH.
Test pin. Test mode when LOW. Normal operating mode when HIGH.
29
NIPPON PRECISION CIRCUITS—4
SM5844AF
1
2
Nu mb e r
30, 31
Na me
RS TN
VS S
I/O
Des cription
Ip
Reset pin
32, 33
–
0 V ground pin
BCKO and LRCO mode set. Outputs (master mode) when LOW, and inputs (slave mode) when
HIGH.
34, 35
SLAVE
Ip
36, 37
38
THRUN
OCKS L
OCLK
Ip
Ip
I
DOUT through mode set. Normal mode when HIGH, and through mode when LOW.
Output system clock (OCLK) select. 384fso when HIGH, and 256fso when LOW.
Output system clock input
39
3
40
LRCO
I/O
I/O
O
Output word clock input/output (fso). Input/output mode set by the level on SLAVE.
Output bit clock input/output. Input/output mode set by the level on SLAVE.
Data output
41, 42
43, 44
BCKO
DOUT
1. Pins which have the same name are connected internally. Accordingly, circuit connections can be made to either pin or to both pins.
2. I = input, Ip = Input with pull-up resistor (HIGH-level pins can be left open), O = output, I/O = input/output
3. fsi is the input word clock (LRCI) frequency, and fso is the output word clock (LRCO) frequency.
SPECIFICATIONS
Absolute Maximum Ratings
V
= 0 V
SS
Parameter
Symbol
Rating
Unit
V
Supply voltage range
Input voltage range
V
−
0.3 to 7.0
DD
V
−0.3 to V
+
0.3
V
IN
DD
Storage temperature range
Power dissipation
T
−
40 to 125
550
°C
stg
P
m W
D
Soldering temperature
Soldering time
T
255
°C
sld
t
10
s
sld
Recommended Operating Conditions
V
= 0 V
SS
Parameter
Symbol
Rating
Unit
Supply voltage range
Operating temperature range
V
4.75 to 5.5
20 to 70
V
DD
T
−
°C
opr
NIPPON PRECISION CIRCUITS—5
SM5844AF
DC Electrical Characteristics
V
= 4.75 to 5.5 V, V = 0 V, T = −20 to 70 °C
DD
SS
a
Rating
Parameter
Symbol
Condition
Unit
min
typ
–
ma x
80
1
Current consumption
I
V
= 5.0 V
–
mA
V
DD
DD
2,3
HIGH-level input voltage
V
0.7V
–
–
IH
DD
2,3
2
LOW -level input voltage
V
–
–
0.3V
V
IL
DD
AC-coupled input voltage
V
0.3V
–
–
–
V
p-p
ACI
DD
4
HIGH-level output voltage
V
I
=
−
1.0 mA
= 1.0 mA
OL
V −
DD
0.5
–
V
OH
OH
4
LOW -level output voltage
V
I
–
–
0.4
20
V
OL
2
HIGH-level input current
I
V
V
V
= V
DD
–
–
–
10
10
–
µA
µA
µA
IH
IN
IN
IN
2,3
LOW -level input current
I
= 0 V
= V
20
IL
3
Input leakage current
I
1.0
1000
LH
DD
3
Pull-up resistance
R
250
500
kΩ
IH
1. ICKSL = LOW, OCKSL = LOW, f
= 13.0 MHz, f
= 13.0 MHz, no output load
ICLK
OCLK
2. Pins ICLK and OCLK.
3. Pins DI, BCKI, LRCI, ICKSL, IFM1, IFM2, DMUTE, MCOM, MDT/FSI1, MCK/FSI2, MLEN/DEEM, OW18N, OW20N, IISN, TST1N, TST2N, RSTN,
THRUN, OCKSL and SLAVE.
4. Pins DOUT, BCKO, LRCO and STATE.
AC Electrical Characteristics
V
= 4.75 to 5.5 V, V = 0 V, T = −20 to 70 °C
SS a
DD
ICLK input
Condition
Sys tem clock
Rating
Parameter
Symbol
Unit
ns
ICKSL
LOW
min
30
10
30
10
80
47
typ
–
ma x
–
256fsi
384fsi
256fsi
384fsi
256fsi
384fsi
LOW -level clock
pulsewidth
t
CWL
HIGH
LOW
–
–
–
–
HIGH-level clock
pulsewidth
t
ns
CWH
HIGH
LOW
–
–
–
162
106
Clock pulse cycle
t
ns
CY
HIGH
–
OCLK input
Condition
Rating
Parameter
Symbol
Unit
ns
OCKS L
LOW
Sys tem clock
256fso
min
15
10
15
10
39
26
typ
–
ma x
–
LOW -level clock
pulsewidth
t
CWL
HIGH
LOW
384fso
–
–
256fso
–
–
HIGH-level clock
pulsewidth
t
ns
CWH
HIGH
LOW
384fso
–
–
256fso
–
200
130
Clock pulse cycle
t
ns
CY
HIGH
384fso
–
ICLK and OCLK timing
>0.7V
0.5V
DD
DD
DD
ICLK
OCLK
<0.3V
t
t
CWL
CWH
t
CY
NIPPON PRECISION CIRCUITS—6
SM5844AF
BCKI, DI, LRCI inputs
Rating
Parameter
Symbol
Unit
min
50
typ
–
ma x
BCKI LOW-level pulsewidth
BCKI HIGH-level pulsewidth
BCKI pulse cycle
t
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
BCWL1
t
50
–
BCWH1
t
100
50
–
BCY1
DI setup time
t
–
DS
DI hold time
t
50
–
DH
Last BCKI rising edge to LRCI edge
LRCI edge to first BCKI rising edge
t
50
–
BL1
t
50
–
LB1
BCKI, DI, LRCI timing
t
BCY1
t
t
BCWL1
BCWH1
BCKI
0.5V
DD
t
t
DH
DS
0.5V
DD
DI
t
t
LB1
BL1
LRCI
0.5V
DD
BCKO, LRCO (Inputs when SLAVE = HIGH)
Rating
Parameter
Symbol
Unit
min
typ
–
ma x
BCKO LOW -level pulsewidth
BCKO HIGH-level pulsewidth
t
78
78
–
–
–
–
–
ns
ns
ns
ns
ns
BCWL2
t
–
BCWH2
1
BCKO pulse cycle
t
156
78
–
BCY2
Last BCKO rising edge to LRCO edge
LRCO edge to first BCKO rising edge
t
–
BL2
t
78
–
LB2
1. BCKO clock inputs exceeding 64fso cannot be detected, and will cause incorrect operation.
NIPPON PRECISION CIRCUITS—7
SM5844AF
BCKO, LRCO timing
t
BCY2
t
t
BCWL2
BCWH2
BCKO
LRCO
0.5V
DD
t
t
LB2
BL2
0.5V
DD
MDT, MCK, MLEN inputs
Rating
Parameter
Symbol
Unit
min
typ
–
ma x
1
MCK and MLEN rise time
t
–
100
100
–
ns
ns
ns
ns
ns
ns
ns
ns
r
1
MCK and MLEN fall time
t
–
–
f
MDT setup time
t
50
50
50
50
50
50
–
MDS
MDT hold time
t
–
–
MDH
MLEN setup time
t
–
–
MCS
MLEN hold time
t
–
–
MCH
MLEN LOW-level pulsewidth
MLEN HIGH-level pulsewidth
t
–
–
MEWL
t
–
–
ME WH
1. t and t are the input waveform transition times measured between 0.1V and 0.9V levels.
r
f
DD
DD
MDT, MCK, MLEN timing
MDT
0.5V
DD
t
t
t
MDS
MDH
0.5V
DD
MCK
t
MCS
MCH
MLEN
0.5V
DD
t
t
MEWH
MEWL
NIPPON PRECISION CIRCUITS—8
SM5844AF
DEEM, DMUTE inputs
Rating
Parameter
Symbol
Unit
min
–
typ
–
ma x
100
100
Rise time
Fall time
t
ns
ns
r
t
–
–
f
DOUT, BCKO, LRCO input/outputs
SLAVE = LOW (outputs), C = 15 pF
L
Rating
typ
Parameter
Symbol
Condition
Unit
min
–
ma x
LRCO pulse cycle
t
1/fso
–
–
–
–
–
–
–
–
–
ns
ns
ns
LOCY
LRCO LOW-level pulsewidth
LRCO HIGH-level pulsewidth
t
–
1/2fso
LOCL
t
–
1/2fso
LOCH
OCKSL = LOW
OCKSL = HIGH
OCKSL = LOW
OCKSL = HIGH
OCKSL = LOW
OCKSL = HIGH
–
1/64fso
1/48fso
1/128fso
1/96fso
1/128fso
1/96fso
BCKO pulse cycle
t
ns
ns
ns
BOCY
–
–
BCKO LOW -level pulsewidth
BCKO HIGH-level pulsewidth
t
BOWL
–
–
t
BOWH
–
From OCLK fall to BCKO
rise
t
10
10
15
15
0
–
–
–
–
–
–
70
70
80
80
20
20
ns
ns
ns
ns
ns
ns
s bH1
OCLK to BCKO delay time
(OCKSL = LOW)
From OCLK fall to BCKO
fall
t
sbL1
From OCLK fall to BCKO
rise
t
s bH2
OCLK to BCKO delay time
(OCKSL = HIGH)
From OCLK fall to BCKO
fall
t
sbL2
From BCKO fall to DOUT
rise
t
bdH1
BCKO to DOUT and LRCO delay
time
From BCKO fall to DOUT
fall
t
0
bdL1
SLAVE = HIGH (inputs), C = 15 pF
L
Rating
typ
Parameter
Symbol
Condition
Unit
min
ma x
From BCKO fall to DOUT
rise
t
10
–
–
100
ns
ns
bdH2
BCKO to DOUT delay time
From BCKO fall to DOUT
fall
t
10
100
bdL2
NIPPON PRECISION CIRCUITS—9
SM5844AF
DOUT, BCKO, LRCO timing
OCLK
BCKO
t
, t
sbL1 sbL2
t
, t
sbH1 sbH2
t
t
BOWL
BOWH
t
BOCY
BCKO
DOUT
LRCO
t
t
, t
bdH bdL
t
bdH
bdL
t
t
LOCL
LOCH
t
LROOY
NIPPON PRECISION CIRCUITS—10
SM5844AF
Filter Characteristics
Anti-aliasing filter frequency characteristic
0
48k
44.1k
20
48k
32k
40
60
44.1k
32k
Up conversion
80
100
120
140
0.250
0.300
0.350
0.400
0.450
Frequency (fs)
0.500
0.550
0.600
0.650
Deemphasis filter frequency characteristic
0
2
0
48.0 kHz
44.1 kHz
32 kHz
–20
4
–40
–60
6
48.0, 44.1 and 32 kHz
8
10
Phase
50
Attenuation
12
10
20
100
200
500
1k
2K
5k
10k
20k
Frequency (Hz)
NIPPON PRECISION CIRCUITS—11
SM5844AF
FUNCTIONAL DESCRIPTION
Input Data Interface (DI, LRCI, BCKI, IFM1, IFM2)
Data
s equence
Mo d e
IFM1
IFM2
Word length
Data pos ition
Common features
1
2
3
4
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
HIGH
16 bits
Rear packed
Non IIS
L/R alternating
Bit serial
MSB first
LSB first
20 bits
Front packed
Rear packed
Attenuator and Deemphasis Selection
The attenuator is set using the microcontroller
interface. When the attenuator is used, deemphasis
settings also need to be set using the microcontroller
interface. The microcontroller interface comprises
MDT, MCK and MLEN, and is used to receive all
input serial data.
Table 1. Attenuator and deemphasis function
selection
Function s et method
Microcontroller
interface flags
(MCOM = HIGH)
Function
External pins
(MCOM = LOW)
Deemphasis
ON/OFF
DEEM
FDEEM
Deemphasis
frequency (fsi)
select
FSI1, FSI2
FFSI1, FFSI2
Attenuator data set
Test mode select
N/A (no attenuation)
11 bits (a1 to a11)
FTST1, FTST2
Irreversible
(test mode 1)
When MCOM is HIGH, serial data received on
MDT, MCK and MLEN sets the attenuation data and
control flag data.
When MCOM is LOW, the logic levels on FSI1,
FSI2 and DEEM select the device function.
NIPPON PRECISION CIRCUITS—12
SM5844AF
Microcontroller Interface (MCOM, MDT, MCK, MLEN)
When MCOM is HIGH, MDT (data), MCK (clock)
and MLEN (latch enable clock) interface pins are
used.
latched into the mode register on the rising edge of
the latch enable clock MLEN.
The mode register addressed is determined by the 1st
bit of the 12 data bits before MLEN goes HIGH. If
this bit is LOW, then the data is read into the
attenuation data register as shown in figure 1. If this
bit is HIGH, then the data is read into the mode flag
register as shown in figure 2. The function of each bit
in the mode flag register is described in table 1.
Input data on MDT is synchronized to the MCK
clock. Data is read into the input stage shift register
on the rising edge of MCK. Accordingly, the input
data should change on the falling edge of MCK.
Input data enters an internal SIPO (serial-to-parallel
converter register), and then the parallel data is
B1
B2
a0
B3
a1
B4
a2
B8
a6
B9
a7
B10
a8
B11
a9
B12
a10
LSB
LOW
MDT
MCK
MSB
MLEN
MCK and MLEN can also follow the dotted lines.
Figure 1. Attenuation data format (B1 = LOW)
B1
B2 * * B5
Not used
B6
B7
B8
B9
B10
B11
B12
HIGH
FTST1
FTST2
FRATE
F12DB
FFSI1
FFSI2
FDEEM
MDT
MCK
MLEN
MCK and MLEN can also follow the dotted lines.
Figure 2. Mode flag data format (B1 = HIGH)
NIPPON PRECISION CIRCUITS—13
SM5844AF
Table 2. Mode flag description
Mode function s elect
Res et
mo d e
B1
Bit
Mode flag
Parameter
Not used
LOW/HIGH
Select
B2 to B5
TST2N = LOW
FTST2
LOW
FTST1
LOW
Mo d e
B6
B7
FTST1
FTST2
Test mode select 1
Test mode select 2
LOW
LOW
0
1
2
3
LOW
HIGH
LOW
HIGH
HIGH
HIGH
Input/output sample rate ratio check after every
output
LOW
B8
FRATE
Input/output rate
Attenuator
LOW
Input/output sample rate ratio check for high
accuracy after every 2048 outputs
HIGH
HIGH
LOW
Normal operation (no shift)
+12 dB gain shift
B9
F12DB
FFSI1
LOW
LOW
HIGH
Deemphasis filter fs
select 1
FFSI2
LOW
LOW
HIGH
HIGH
FFSI1
LOW
HIGH
LOW
HIGH
fsi
B10
44.1 kHz
48.0 kHz
32.0 kHz
Deemphasis filter fs
select 2
B11
B12
FFSI2
LOW
LOW
LOW
Deemphasis filter OFF
Deemphasis filter ON
Deemphasis control
ON/OFF
FDEEM
HIGH
Deemphasis (DEEM, FSI1, FSI2 pins or FDEEM, FFSI1, FFSI2 flags)
Table 4. Deemphasis fs select (FSI1, FSI2 pins or
FFSI1, FFSI2 flags)
The digital deemphasis filter is an IIR filter with var-
iable coefficients to faithfully reproduce the gain and
phase characteristics of standard analog deemphasis
filters.
MCOM = LOW (MCOM = HIGH)
fs
FSI1 (FFSI1)
FSI2 (FFSI2)
The filter coefficients are selected by FSI1 (or FFSI1
flag) and FSI2 (or FFSI2 flag) to correspond to the
sampling frequencies fs = 44.1, 48.0 and 32.0 kHz.
LOW
LOW
44.1 kHz
HIGH
LOW
Table 3. Deemphasis ON/OFF
LOW
HIGH
48.0 kHz
32.0 kHz
Whe n MCOM = LOW
DEEM = HIGH
Whe n MCOM = HIGH
FDEEM = HIGH
Deemphas is
ON
HIGH
HIGH
DEEM = LOW
FDEEM = LOW
OFF
NIPPON PRECISION CIRCUITS—14
SM5844AF
Attenuation (MDT, MCK, MLEN)
The digital attenuator coefficients are read in as
serial data on the microcontroller interface. Data on
MDT is read into the internal shift register on the
rising edge of MCK, and then 12 bits are latched
internally on the rising edge of MLEN.
When the leading bit is 0 (B1 = LOW), the following
11 bits are read into the attenuation register and used
as an unsigned integer in MSB first format. See
figure 3.
B1
B2
a0
B3
a1
B4
a2
B8
a6
B9
a7
B10
a8
B11
a9
B12
a10
LSB
LOW
MDT
MCK
MSB
MLEN
MCK and MLEN can also follow the dotted lines.
Figure 3. Attenuation data format (microcontroller interface)
Although the attenuation data comprises 11 bits,
only 1025 levels are valid as given by the following.
DATT
---------------
1024
Gain = 20 × log
[dB]
10
when F12DB = LOW
(10 – i)
DATT =
a × 2
∑
i
i = 0
DATT
256
---------------
= 20 × log
[dB]
The gain of the attenuator for values of DATT from
001H to 400H are given by the following equations.
Note that when the F12DB flag is HIGH, the gain is
shifted by +12.0412 dB.
when F12DB = HIGH
After a system reset initialization, DATT is set to
400H and the F12DB flag is LOW, corresponding to
0 dB gain. (The F12DB flag is described in table 2.)
Table 5. Attenuator settings
F12DB = LOW (default)
Attenuation data DATT
F12DB = HIGH
Gain (dB)
Linear expres s ion
Gain (dB)
Linear expres s ion
000H
−∞
0.0
1/1024
↓
−∞
0.0
1/256
↓
001H
−
−
−
60.206
−
48.165
↓
100H
↓
↓
0.0
↓
12.041
256/1024
↓
256/256
↓
↓
↓
3FFH
0.0085
0
1023/1024
1.0
12.032
12.041
1023/256
4.0
400H (to 7FFH)
NIPPON PRECISION CIRCUITS—15
SM5844AF
Attenuator operation
A change in the attenuation data DATT causes the
gain to change smoothly from its previous value
towards the new setting. The new attenuation data is
stored in the attenuation data register and the current
attenuation level is stored in a temporary register.
Consequently, if a new attenuation level is read in
before the previously set level is reached, the gain
changes smoothly from the current value towards the
latest setting as shown in figure 4.
The attenuation counter output changes, and hence
the gain changes, by 1 step every output sample. The
time taken to reduce the gain from 0 dB (or 12 dB) to
−∞ dB is (1024/fso), which corresponds to
approximately 23.2 ms when fso = 44.1 kHz.
Level 1
Level 5
0 dB
Level 3
Gain
Level 2
− ∞
∆t
Level 4
Time
Figure 4. Attenuator operation example
NIPPON PRECISION CIRCUITS—16
SM5844AF
Direct Mute (DMUTE)
Direct mute ON/OFF
Table 6. DMUTE operation
DMUTE
Function
Normal data is output from the next output word (mute
OFF)
LOW
HIGH
0 data is output from the next output word (mute ON)
Reset mute
Table 7. RSTN mute operation
RS TN
Function
LOW
0 data is output from the next output word (mute ON)
Normal data is output from the 3073rd output word
(mute OFF)
HIGH
Internal operating status (STATE)
Internally, all functions are performed using 20-bit
serial data, and the conversion rate and filter type are
automatically selected for output. Output data is in
20-bit front-packed format.
Table 8. Bit function
Output bit pos ition
Content
(Output data cycle/input data cycle)
Ex.
− 9
1st
18th
1st to 18th
19th
00.1111111111110111
01.1111111111110111
00.0111111111110111
1.0 times
2.0 times (1/2 conversion rate ratio)
0.5 times (2.0 conversion rate ratio)
DA1
Selected filter type
DA1
DA0
Filter
Mo d e
0
1
0
1
0
0
1
1
Up converter
1
2
3
4
44.1 to 48 kHz
32 to 44.1 kHz
32 to 48 kHz
20th
DA0
Note that when THRUN is LOW, LRCO and BCKO are not guaranteed to be synchronized to the STATE
output.
NIPPON PRECISION CIRCUITS—17
SM5844AF
System Clock
Input system clock (ICLK, ICKSL)
Output system clock (OCLK, OCKSL)
The input system clock can be set to run at either
256fsi or 384fsi, where fsi is the input frequency on
LRCI.
The output system clock can be set to run at either
256fso or 384fso, where fso is the input frequency on
LRCO. In through mode, OCLK and OCKSL have
no function and are not used.
Note that ICLK and LRCI should be divided from a
common clock source or PLL to maintain
synchronism.
Note that in slave mode, a suitable clock must be
input on OCLK. The clock on OCLK should ideally
have a protection circuit to prevent incorrect
operation for times when the clock on ICLK is
halted.
Table 9. ICLK system clock
ICKSL
HIGH
LOW
ICLK s ys tem clock rate
Table 10. OCLK system clock
384fsi
256fsi
S LAVE
OCKS L
HIGH
LOW
×
OCLK s ys tem clock rate
384fso
256fso
LOW
HIGH
Not used
Output data interface and output clock selection (LRCO, BCKO, DOUT, SLAVE)
Table 11. Output mode description
Function
THRUN
HIGH
LOW
S LAVE
Mo d e
Des cription
LRCO, BCKO s tate
Output word clock (LRCO) and output bit clock
(BCKO) are divided from OCLK.
LOW
Master mode
Outputs
Output word clock (LRCO) and output bit clock
(BCKO) are supplied externally.
1
HIGH
Slave mode
Inputs
Output word clock (LRCO), output bit clock
(BCKO) and output data (DOUT) are the
same as LRCI, BCKI and DI, respectively.
×
Through mode
Outputs
1. The number of BCKO input clock cycles should not exceed 64 per word. Correct operation is not guaranteed beyond these limits.
System Reset (RSTN)
Through Mode (THRUN)
At power-ON, all device functions must be reset. The
device is reset by applying a LOW-level pulse on
RSTN. At system reset, the internal arithmetic
operation, output timing counter and internal flag
register operation are synchronized on the next LRCI
rising edge. Note that all flags are set to their defaults
(all LOW).
Table 12. THRUN operation
THRUN
Mo d e
Des cription
Direct connections are made: LRCI
to LRCO, BCKI to BCKO, and DI to
DOUT.
LOW
Through mode
Normal mode
HIGH
Sample rate converter operation
A power-ON reset signal can be applied from an
external microcontroller. For systems where ICLK
and LRCI are stable at power ON, initialization can
be performed by connecting a 0.001 µF capacitor
between RSTN and VSS. Otherwise, a capacitor
value should be chosen such that RSTN does not go
HIGH until after LRCI and ICLK have stabilized.
NIPPON PRECISION CIRCUITS—18
SM5844AF
Internal Arithmetic Timing Auto-reset
Output Timing Calculation
The clock on LRCI should pass through 1 cycle for
every 384 (ICKSL = HIGH) or 256 (ICKSL = LOW)
ICLK clock cycles to maintain correct internal
arithmetic sequence. If the number of ICLK cycles is
different, increases or decreases, or any jitter is
present, device operation could be affected.
The output timing is calculated to maintain the
desired ratio between the output data cycle and the
input data cycle.
Filter Characteristic Selection
Conversion rates from 0.5 to 2.0 times are supported
using the following 4 filter types.
There is a fixed-value tolerance within which the
internal sequence and LRCI clock timing are not
adversely affected.
The ratio between the output sample rate and input
sample rate is measured automatically and the most
suitable filter type for this ratio is selected
automatically.
Table 13. Clock tolerance
ICKSL
Allowa ble clock variation
Table 15. fs ratio and filter selection
HIGH (384fs mode)
LOW (256fs mode)
+8/
+4/
−
6 cycles
3 cycles
−
Mo d e
Filter
fs ratio (fso/fsi)
1.0 to 2.0
0.91875
Selects range
≥ 0.97
1
2
3
4
Up converter
Whenever the allowable tolerance is exceeded, the
internal sequence is automatically reset so that the
internal sequence matches the LRCI clock. When
this occurs, there is a possibility that click noise will
be generated.
48.0 to 44.1 kHz
44.1 to 32.0 kHz
48.0 to 32.0 kHz
0.865 to 0.97
0.711 to 0.865
≤ 0.711
0.72562
0.66667
When the selected fs conversion ratio and the actual
sample rate conversion ratio do not coincide, the
following phenomenon are generated.
Output Format Control (OW18N,
OW20N, IISN)
The output is in MSB-first, 2s-complement, L/R
alternating, bit serial format with a continuous bit
clock.
Table 16. fs ratio mismatch
Condition
Affect
Actual sample rate conversion
ratio is lower than the selected
filter conversion ratio
Table 14. Output format selection
The audio band high-pass
develops aliasing noise.
Inputs
Output format
IIS Front/rear
Mo d e
Word
length s election
IISN OW20N OW18N
Actual sample rate conversion
ratio is higher than the selected
filter conversion ratio
packing
The audio band high-pass is cut
off.
1
2
3
4
5
6
7
HIGH
HIGH
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
×
16 bits
18 bits
Non IIS
20 bits
Rear
Note: An output noise may be generated if the fs conversion ratio
changes at a rate greater than 0.057%/sec.
HIGH
LOW
20 bits
16 bits
Front
18 bits
20 bits
IIS
NIPPON PRECISION CIRCUITS—19
SM5844AF
TIMING DIAGRAMS
Input Timing Examples (DI, BCKI, LRCI)
Audio data input timing (rear-packed 16-bit word, IFM1 = LOW, IFM2 = LOW)
1/fs
Left-channel data
Right-channel data
MSB
1
LSB
MSB
1
LSB
DI
BCKI
LRCI
2
14 15 16
2
14 15 16
Audio data input timing (rear-packed 20-bit word, IFM1 = LOW, IFM2 = HIGH)
1/fs
Left-channel data
Right-channel data
MSB
1
LSB
MSB
1
LSB
DI
BCKI
LRCI
2
18 19 20
2
18 19 20
Audio data input timing (front-packed 20-bit word, IFM1 = HIGH, IFM2 = LOW)
1/fs
Left-channel data
Right-channel data
MSB
1
LSB
MSB
1
LSB
DI
BCKI
LRCI
2
3
19 20
2
3
19 20
1
All data bits after the LSB (20th bit) are ignored. Accordingly, more than 20 BCKI cycles are required.
NIPPON PRECISION CIRCUITS—20
SM5844AF
Audio data input timing (rear-packed 20-bit word, LSB first, IFM1 = HIGH, IFM2 = HIGH)
1/fs
Left-channel data
Right-channel data
LSB
1
MSB
LSB
1
MSB
DI
BCKI
LRCI
2
18 19 20
2
18 19 20
Output Timing Examples (DOUT, BCKO, LRCO)
Audio data output timing (rear-packed 16-bit word)
1/fso
1/fso
1/fso
Left-channel data
Right-channel data
Right-channel data
Right-channel data
MSB
1
LSB
16
MSB
1
LSB
16
DOUT
BCKO
LRCO
2
15
2
2
2
15
17
19
Audio data output timing (rear-packed 18-bit word)
Left-channel data
MSB
1
LSB
18
MSB
1
LSB
18
DOUT
BCKO
LRCO
2
17
Audio data output timing (rear-packed 20-bit word)
Left-channel data
MSB
1
LSB
20
MSB
1
LSB
20
DOUT
BCKO
LRCO
2
19
NIPPON PRECISION CIRCUITS—21
SM5844AF
Audio data output timing (front-packed 20-bit word, OW18N = LOW, OW20N = LOW)
1/fso
Left-channel data
Right-channel data
MSB
1
LSB
20
MSB
1
LSB
20
DOUT
BCKO
LRCO
2
19
2
19
Audio data output timing (IIS mode, front-packed 16/18/20-bit word selected by OW18N and
OW20N)
1/fso
Left-channel data
Right-channel data
MSB
1
LSB
20
MSB
1
LSB
20
DOUT
BCKO
LRCO
2
16
17
18
19
2
16
17
18
19
Data is output in 20-bit units.
State Data Output Timing
State data output timing (IISN = HIGH)
1/fso
State data
MSB
LSB
20
STATE
BCKO
LRCO
1
2
19
State data output timing (IISN = LOW)
1/fso
State data
MSB
LSB
20
STATE
BCKO
LRCO
1
2
19
NIPPON PRECISION CIRCUITS—22
SM5844AF
Delay Time
t
is the time when the serial input data has been
been read out completely (on the rising edge of
LRCO). The delay between input and output is given
INPUT
read in completely (on the rising edge of LRCI).
t
is the time when the serial output data has
by t
− t
= (49 ± 2)/fsi.
OUTPUT
OUTPUT
INPUT
1/fs
LRCI
Serial data input
49 ±2
t
input
LRCO
Serial data output
1/fso
t
output
t
INPUT
t
– t
INPUT
OUTPUT
t
OUTPUT
NIPPON PRECISION CIRCUITS—23
SM5844AF
TYPICAL APPLICATIONS
Input Interface Circuits
Digital audio interface receiver (PD0052)
384fs
VCOOUT
ICLK
ICKSL
LRCI
BCKI
DI
LRCK
BCK
DIR
PD0052
DATA
SM5844AF
MODE
EMP
MCOM
MLEN/DEEM
MDT/FSI1
1FM1
1FM2
MCK/FSI2
32k
44.1k
48k
Digital audio interface transceiver(YM3613)
OCKSL
384fs 16.9344 MHz
OCLK
LRCO
øA
WCI
BCI
DIN
BCKO
DOUT
IISN
DIT
YM3613
SM5844AF
OW18N
OW20N
THRUN
SLAVE
SEL
NIPPON PRECISION CIRCUITS—24
SM5844AF
APPLICATION NOTE
Delay in the slave mode
When tbdH2, tbdL2 is maximum 100ns, ideal timing
may not be attained for the following devise,
depending on the OCLK cycle (example 1).
In the slave mode , the delay (tbdH2, tbdL2)of
DUOT from BCKO is MIN= 10ns, MAX= 100ns
which is ratter wide width.
Please use considering the timing in the following
examples in the slave mode.
As specified in AC Electrical Characteristics, and
BCKO is prohibited from inputting longer than
64fso.
(example 1) OCLK= 39ns(fs= 99.84kHz), OCKSL= L(256fs), BCKO(64fso)= 156ns, OW20N= L, OW18N= H
LRCO
BCKO
(LSB)
L1
DOUT
L2
100ns
156ns
100ns
(example 2) OCLK= 59ns(fs= 44.1kHz), OCKSL= H(384fs), BCKO(64fso)= 354ns, OW20N= L, OW18N= H
LRCO
BCKO
(LSB)
DOUT
L2
L1
100ns
354ns
100ns
NIPPON PRECISION CIRCUITS—25
SM5844AF
NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to
improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for
the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits
are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision
Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification.
The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or
malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter,
including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or
indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies.
NIPPON PRECISION CIRCUITS INC.
4-3, Fukuzumi 2 chome
Koto-ku, Tokyo 135-8430, Japan
Telephone: 03-3642-6661
Facsimile: 03-3642-6698
NIPPON PRECISION CIRCUITS LTD.
NC9308DE 2000.09
NIPPON PRECISION CIRCUITS—26
相关型号：
©2020 ICPDF网 联系我们和版权申明