SM5876 [NPC]
3rd-order, 2-channel D/A Converter; 3阶， 2路D / A转换器
| 型号： | SM5876 |
| 厂家： | 
NIPPON PRECISION CIRCUITS INC |
| 描述： | 3rd-order, 2-channel D/A Converter |
| 文件： | 总17页 (文件大小：155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SM5876AM
3rd-order Σ∆, 2-channel D/A Converter
NIPPON PRECISION CIRCUITS INC.
OVERVIEW
PINOUT
The SM5876AM is a 3rd-order Σ∆, 2-channel D/A
converter LSI for CD-ROM digital audio reproduc-
tion equipment. It incorporates an 8-times oversam-
pling digital filter, deemphasis filter, attenuator, and
soft mute circuits built-in., using NPC’s Molybde-
num-gate CMOS technology.
1
24
MLEN
CKSL
CKO
MCK
MDT
RSTN
MUTEO
XVSS
XTO
DVSS
BCKI
DI
The SM5876AM operates from a 2.7 to 5.5 V supply,
and is available in 24-pin SSOPs.
DVDD
LRCI
TSTN
LO
XTI
XVDD
RO
FEATURES
AVDDR
RON
AVDDL
LON
■ System clock
12
13
AVSS
• 768fs (33.8688MHz)
• 384fs (16.9344MHz)
■ Crystal oscillator circuit built-in
■ Infinity-zero detector circuit built-in
■ MSB first, rear-packed serial data input format
(≤ 64fs bit clock)
■ 8-times oversampling digital filter
• 32 dB stopband attenuation
• ±0.05 dB passband ripple
PACKAGE DIMENSIONS
Unit: mm
24-pin SSOP
• −0.34 dB passband correction for 70 kHz LPF
■ 3-line microcontroller interface for output mode
and attenuator control settings
■ 16 output modes
■ Deemphasis filter operation
• 36 dB stopband attenuation
• −0.09 to +0.23 dB deviation
• −0.34 dB passband correction for 70 kHz LPF
■ Attenuator
• 8-bit attenuator (linear 256 steps)
• Independent left/right-channel set function
• Soft mute function (approx. 1024/fs mute time)
■ Σ∆ 2-channel D/A converter
• 3rd-order noise shaper
10.05 0.20
10.20 0.30
0.7
0.8
0.36 0.10
0
10
0.50 0.20
• 32fs oversampling
■ 44.1 kHz sampling frequency
■ 2.7 to 5.5 V operating supply voltage range (4.5 to
5.5 V operating supply voltage range with 768fs
system clock)
■ 24-pin SSOP
■ Molybdenum-gate CMOS process
NIPPON PRECISION CIRCUITS—1
SM5876AM
BLOCK DIAGRAM
LRCI
BCKI
DI
Input interface
MUTEO
MLEN
MCK
L
R
Filter & attenuation
operation block
Microcontroller
interface
MDT
CKO
XVSS
XTO
XTI
L
R
RSTN
CKSL
DVSS
DVDD
TSTN
Timing
control
L
R
PWM data
generation block
Noise shaper
operation block
XVDD
AVDDL
AVDDR
LO
LON
AVSS
RON
RO
PIN DESCRIPTION
Number
Name
MLEN
CKSL
CKO
I/O
Ip
Description
1
2
Microcontroller control latch clock input
Ip
768fs/384fs clock select. 768fs when HIGH, and 384fs when LOW.
3
O
Oscillator clock buffer output
4
DVSS
BCKI
DI
Digital ground pin
5
Ip
Ip
Data bit clock input pin
6
Serial data input pin
7
DVDD
LRCI
TSTN
LO
Digital supply pin
8
Ip
Ip
O
Sample data rate (fs) clock input pin. Left channel when HIGH, and right channel when LOW.
9
Test input pin
10
11
12
13
14
Left-channel analog output (+)
Left-channel analog supply pin
Left-channel analog output (−)
Analog ground pin
AVDDL
LON
O
O
AVSS
RON
Right-channel analog output (−)
NIPPON PRECISION CIRCUITS—2
SM5876AM
Number
15
Name
AVDDR
RO
I/O
Description
Right-channel analog supply pin
Right-channel analog output (+)
Crystal oscillator supply pin
16
O
17
XVDD
XTI
18
I
Crystal oscillator or external clock input pin
Crystal oscillator output pin
19
XTO
O
20
XVSS
MUTEO
RSTN
MDT
Crystal oscillator ground pin
21
O
Ip
Ip
Ip
Infinity-zero detector output (analog mute control)
Reset pin. Reset when LOW.
22
23
Microcontroller control data input pin
Microcontroller control clock input pin
24
MCK
I: INPUT O: OUTPUT Ip: Input with pull-up Registor
SPECIFICATIONS
Absolute Maximum Ratings
DV = AV = XV = 0 V, AV = AV
= AV
DDR
SS
SS
SS
DD
DDL
Parameter
Symbol
Rating
Unit
V
Supply voltage range
DV , AV , XV
−0.3 to 7.0
DD
DD
DD
1
Input voltage range
V
DV − 0.3 to DV + 0.3
V
IN1
SS
DD
XTI input voltage range
V
XV − 0.3 to XV + 0.3
V
IN
SS
DD
Storage temperature range
Power dissipation
T
−40 to 125
°C
mW
°C
s
stg
P
250
255
10
D
Soldering temperature
Soldering time
T
sld
t
sld
1.Pins MLEN, CKSL, BCKI, DI, LRCI, TSTN, MCK, MDT.
Also applicable during supply switching.
Recommended Operating Conditions
5 V operation: DV = AV = XV = 0 V, AV = AV
= AV
DDR
SS
SS
SS
DD
DDL
Parameter
Symbol
DV , AV , XV
DD
Rating
Unit
Supply voltage range
4.5 to 5.5
V
DD
DD
DV − XV
,
DD
DD
DV − AV
,
DD
DD
XV − AV
,
,
,
DD
DD
Supply voltage variation
±0.1
V
DV − XV
SS
SS
DV − AV
SS
SS
XV − AV
SS
SS
Operating temperature range
T
−40 to 85
°C
opr
NIPPON PRECISION CIRCUITS—3
SM5876AM
= AV , CKSL = LOW (384fs)
DDR
3 V operation: DV = AV = XV = 0 V, AV = AV
SS
SS
SS
DD
DDL
Parameter
Symbol
DV , AV , XV
DD
Rating
Unit
Supply voltage range
2.7 to 4.5
V
DD
DD
DV − XV
,
DD
DD
DV − AV
,
DD
DD
XV − AV
,
,
,
DD
DD
Supply voltage variation
±0.1
V
DV − XV
SS
SS
DV − AV
SS
SS
XV − AV
SS
SS
Operating temperature range
T
−20 to 70
°C
opr
DC Electrical Characteristics
5 V operation: DV = AV = XV = 0 V, DV = AV = XV = 4.5 to 5.5 V, AV = AV
= AV
,
DDR
SS
SS
SS
DD
DD
DD
DD
DDL
T = −40 to 85 °C
a
Rating
Parameter
Symbol
Condition
Unit
min
–
typ
15
6
max
25
10
2
1
DVDD digital supply current
I
mA
mA
mA
V
DDD
1
XVDD system clock supply current
I
–
DDX
1
AVDD analog supply current
I
Total current
Clock input
Clock input
–
1
DDA
XTI HIGH-level input voltage
XTI LOW-level input voltage
XTI AC-coupled input voltage
V
0.7XV
–
–
IH1
DD
V
–
–
0.3XV
V
IL1
DD
V
0.3XV
–
–
–
V
p-p
INAC
DD
2
HIGH-level input voltage
V
2.4
–
–
V
V
IH2
2
LOW-level input voltage
V
–
0.5
–
IL2
3
HIGH-level output voltage
V
I
= −1 mA
= 1 mA
OL
AV − 0.4
–
V
OHA
OH
DD
3
LOW-level output voltage
V
I
–
–
0.4
–
V
OLA
CKO HIGH-level output voltage
CKO LOW-level output voltage
XTI HIGH-level input current
XTI LOW-level input current
V
I
= −1 mA
= 1 mA
OL
DV − 0.4
–
V
OHC
OH
DD
V
I
–
–
–
–
–
–
0.4
25
25
25
1.0
V
OLC
I
V
= XV
DD
12
12
12
–
µA
µA
µA
µA
IH1
IN
I
V
= 0 V
= 0 V
IL1
IN
2
LOW-level input current
I
V
IN
IL2
2
Input leakage current
I
V = DV
IN DD
LH
1. DV = AV = XV = 5 V, CKSL = HIGH (768fs), XTI clock input frequency f = 33.8688 MHz, no output load, NPC-standard input data pattern.
DD
DD
DD
XTI
2.Pins MLEN, CKSL, BCKI, DI, LRCI, TSTN, MCK, MDT.
3.Pins LO, LON, RO, RON,MUTEO.
3 V operation: DV = AV = XV = 0 V, DV = AV = XV = 2.7 to 4.5 V, AV = AV
= AV
,
DDR
SS
SS
SS
DD
DD
DD
DD
DDL
T = −20 to 70 °C
a
Rating
typ
6
Parameter
Symbol
Condition
Unit
min
–
max
1
DVDD digital supply current
I
9
3
1
–
mA
mA
mA
V
DDD
1
XVDD system clock supply current
I
–
1.5
0.5
–
DDX
1
AVDD analog supply current
I
Total current
Clock input
–
DDA
XTI HIGH-level input voltage
V
0.7XV
DD
IH1
NIPPON PRECISION CIRCUITS—4
SM5876AM
Rating
Parameter
Symbol
Condition
Unit
min
typ
–
max
0.3XV
XTI LOW-level input voltage
XTI AC-coupled input voltage
V
Clock input
–
V
IL1
DD
V
0.3XV
–
–
–
V
p-p
INAC
DD
2
HIGH-level input voltage
V
2.4
–
–
V
V
IH2
2
LOW-level input voltage
V
–
0.5
–
IL2
3
HIGH-level output voltage
V
I
= −0.5 mA
= 0.5 mA
= −0.5 mA
= 0.5 mA
AV − 0.4
–
V
OHA
OH
DD
3
LOW-level output voltage
V
I
–
–
0.4
–
V
OLA
OL
CKO HIGH-level output voltage
CKO LOW-level output voltage
XTI HIGH-level input current
XTI LOW-level input current
V
I
DV − 0.4
–
V
OHC
OH
DD
V
I
–
–
–
–
–
–
0.4
15
15
15
1.0
V
OLC
OL
I
V
= XV
DD
4
µA
µA
µA
µA
IH1
IN
I
V
= 0 V
= 0 V
4
IL1
IN
2
LOW-level input current
I
V
4
IL2
IN
2
Input leakage current
I
V
= DV
DD
–
LH
IN
1. DV = AV = XV = 3 V, CKSL = LOW (384fs), XTI clock input frequency f = 16.9344 MHz, no output load, NPC-standard input data pattern.
DD
DD
DD
XTI
2.Pins MLEN, CKSL, BCKI, DI, LRCI, TSTN, MCK, MDT.
3.Pins LO, LON, RO, RON,MUTEO.
AC Electrical Characteristics
5 V operation: DV = AV = XV = 0 V, DV = AV = XV = 4.5 to 5.5 V, AV = AV
= AV
= AV
,
,
SS
SS
SS
DD
DD
DD
DD
DDL
DDL
DDR
DDR
T = −40 to 85 °C
a
3 V operation: DV = AV = XV = 0 V, DV = AV = XV = 2.7 to 4.5 V, AV = AV
SS
SS
SS
DD
DD
DD
DD
T = −20 to 70 °C, CKSL = LOW (384fs system clock)
a
System clock (XTI)
Crystal Oscillator
Rating
typ
Parameter
Symbol
Condition
Unit
min
8.0
4.0
max
35.6
17.8
768fs
384fs
33.8688
16.9344
MHz
MHz
Oscillator frequency
f
OSC
External clock input
Parameter
Rating
typ
Symbol
Condition
Unit
min
13.0
26.0
13.0
26.0
28.0
56.0
max
62.5
125
62.5
125
125
250
768fs
384fs
768fs
384fs
768fs
384fs
14.75
29.5
ns
ns
ns
ns
ns
ns
HIGH-level clock pulsewidth
LOW-level clock pulsewidth
Clock pulse cycle
t
CWH
14.75
29.5
t
CWL
29.5
t
XI
59.0
NIPPON PRECISION CIRCUITS—5
SM5876AM
XTI input clock
V
IH1
0.5VDD
V
IL1
tCWH
tCWL
tXI
Serial input (BCKI, DI, LRCI)
Rating
Parameter
Symbol
Unit
min
50
typ
–
max
–
BCKI HIGH-level pulsewidth
BCKI LOW-level pulsewidth
BCKI pulse cycle
t
ns
ns
ns
ns
ns
ns
ns
BCWH
t
50
–
–
BCWL
t
1/(64fs)
50
–
–
BCY
DI setup time
t
–
–
DS
DI hold time
t
50
–
–
DH
Last BCKI rising edge to LRCI edge
LRCI edge to first BCKI rising edge
t
50
–
–
BL
t
50
–
–
LB
Serial input timing
tBCY
tBCWH
tBCWL
BCKI
DI
1.5V
1.5V
1.5V
tDS
tDH
tBL
tLB
LRCI
NIPPON PRECISION CIRCUITS—6
SM5876AM
Control input (MCK, MDT, MLEN)
Rating
Parameter
Symbol
Unit
min
typ
–
max
–
MCK HIGH-level pulsewidth
MCK LOW-level pulsewidth
MCK pulse cycle
MDT setup time
t
140
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MCWH
t
140
–
–
MCWL
t
280
–
–
MCY
t
100
–
–
MDS
MDT hold time
t
100
1/(192fs) + 20
1/(192fs) + 20
1/(192fs) + 20
–
–
–
MDH
MLEN setup time
MLEN hold time
MLEN level pulsewidth
Rise time
t
–
–
MLS
t
–
–
MLH
T
–
–
MLH
t
–
50
50
r
Fall time
t
–
–
f
Control input timing
MCK
1.5V
1.5V
1.5V
1.5V
t
MCWH
t
MCWL
tMCY
MDT
t
MDH
t
MDS
tMLS
tMLH
MLEN
t
MLY
tf
tr
MCK
MDT
MLEN
2.4V
2.4V
0.5V
0.5V
Reset Input (RSTN)
Rating
typ
Parameter
RSTN LOW-level pulsewidth after supply rising edge
Symbol
Unit
min
max
t
50
–
–
ns
RSTN
NIPPON PRECISION CIRCUITS—7
SM5876AM
Theoretical Filter Characteristics
Deemphasis OFF overall characteristics
Frequency band
Attenuation (dB)
Parameter
Passband ripple
f
@ fs = 44.1 kHz
0 to 20.0 kHz
24.1 to 328.7 kHz
20.0 kHz
min
−0.05
32
typ
–
max
+0.05
–
0 to 0.4535fs
0.5465fs to 7.4535fs
0.4535fs
Stopband attenuation
–
Built-in analog LPF compensation
–
−0.34
–
Overall frequency characteristic (deemphasis OFF)
0
10
20
30
40
50
60
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
Frequency (fs)
Passband characteristic (deemphasis OFF)
0.0
0.2
0.4
0.6
0.8
0.000
0.125
0.250
0.375
0.4535
0.500
Frequency (fs)
NIPPON PRECISION CIRCUITS—8
SM5876AM
Deemphasis ON overall characteristics
Frequency band
@ fs = 44.1 kHz
Attenuation (dB)
typ
Parameter
f
min
max
Deviation from ideal deemphasis filter
characteristics
0 to 0.4535fs
0 to 20.0 kHz
−0.09
–
+0.23
Stopband attenuation
0.5465fs to 7.4535fs
0.4535fs
24.1 to 328.7 kHz
20.0 kHz
36
–
–
–
–
Built-in analog LPF compensation
−0.34
Overall frequency characteristic (deemphasis ON)
0
10
20
30
40
50
60
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
Frequency (fs)
Passband characteristic (deemphasis ON)
0
2
4
6
8
10
12
0.000
0.125
0.250
0.375
0.4535 0.500
Frequency (fs)
NIPPON PRECISION CIRCUITS—9
SM5876AM
AC Analog Characteristics
5 V operation: DV = AV = XV = 0 V, DV = AV = XV = 5 V, AV = AV
= AV
,
SS
SS
SS
DD
DD
DD
DD
DDL
DDR
CKSL = 0 V, deemphasis OFF, crystal oscillator frequency f
= 16.9344 MHz, T = 25 °C
OSC
a
Rating
Parameter
Symbol
Condition
1 kHz, 0 dB
Unit
min
–
typ
0.005
1.53
2.0
max
0.01
–
Total harmonic distortion
THD + N
%
1
LSI output level
V
1 kHz, 0 dB
–
V
rms
out1
Evaluation board output level
Dynamic range
V
1 kHz, 0 dB
1.8
88
88
84
2.2
–
V
rms
out2
D.R
S/N
1 kHz, −60 dB
1 kHz, 0/−∞ dB
1 kHz, −∞/0 dB
92
dB
dB
dB
2
Signal-to-noise ratio
92
–
Channel separation
Ch. Sep
86
–
1.The LSI output level = 0.3058AV Vrms.
DD
2. Signal-to-noise is measured following a device reset, with DATA = 0 (DI = LOW). Under these conditions, the signal-to-noise ratio includes noise-shaper
noise.
3 V operation: DV = AV = XV = 0 V, DV = AV = XV = 3 V, AV = AV
= AV
,
SS
SS
SS
DD
DD
DD
DD
DDL
DDR
CKSL = 0 V, deemphasis OFF, crystal oscillator frequency f
= 16.9344 MHz, T = 25 °C
OSC
a
Rating
Parameter
Symbol
Condition
1 kHz, 0 dB
Unit
min
–
typ
0.007
0.92
1.2
max
–
Total harmonic distortion
THD + N
%
1
LSI output level
V
1 kHz, 0 dB
–
–
V
rms
out1
Evaluation board output level
Dynamic range
V
1 kHz, 0 dB
–
–
V
rms
out2
D.R
S/N
1 kHz, −60 dB
1 kHz, 0/−∞ dB
1 kHz, −∞/0 dB
–
90
–
dB
dB
dB
2
Signal-to-noise ratio
–
90
–
Channel separation
Ch. Sep
–
82
–
1.The LSI output level = 0.3058AV Vrms.
DD
2. Signal-to-noise is measured following a device reset, with DATA = 0 (DI = LOW). Under these conditions, the signal-to-noise ratio includes noise-shaper
noise.
NIPPON PRECISION CIRCUITS—10
SM5876AM
AC Measurement Circuit and Conditions
Measurement circuit block diagram
CKO
(768fs/384fs)
Left Channel
BCK
Evaluation
Board
L/R Channel
Selector
Distortion
Analyzer
Signal
Generator
LRCK(fs)
DATA
Right Channel
fs= 44.1kHz
DATA= 16bit
RMS Measurement
Shibasoku AD725C
10kΩ Input Impedance
NF Corporation 3346A
Measurement conditions
3346A left/right-channel selector
switch
AD725C distortion analyzer with
built-in filter
1
Parameter
Symbol
Total harmonic distortion
Output level
THD + N
THRU
20 kHz lowpass filter ON
400 Hz highpass filter OFF
V
out
Dynamic range
DR
D-RANGE
20 kHz lowpass filter ON
400 Hz highpass filter OFF
JIS A filter ON
Signal-to-noise ratio
Channel separation
S/N
THRU
THRU
20 kHz lowpass filter ON
400 Hz highpass filter OFF
Ch. Sep
1.Pins LO and RO should have an output load of 10 kΩ (min).
NIPPON PRECISION CIRCUITS—11
SM5876AM
Measurement circuit
A V S S
R O N
L O N
A V D D L
L O
A V D D R
T S T N
R O
L R C I
D V D D
D I
X V D D
X T I
X T O
X V S S
M U T E O
B C K I
D V S S
C K O
R S T N
M D T
C K S L
M L E N
M C K
NIPPON PRECISION CIRCUITS—12
SM5876AM
FUNCTIONAL DESCRIPTION
System Clock/Speed Switching (XTI, XTO, CKO, CKSL)
Note that the input clock accuracy and signal-to-
The system clock on XTI can be set to run at one of
two speeds, 384fs (normal speed) or 768fs (double-
speed), where fs is the input frequency on LRCI. The
speed for CD playback is set by the input level on
CKSL, as shown in table 1.
noise ratio greatly influence the AC analog character-
istics. Accordingly, care should be taken to ensure
that the clock is free from jitter.
The system clock can be controlled by a crystal
oscillator comprising a crystal connected between
XTI and XTO and the built-in CMOS inverter. Alter-
natively, an external system clock can be input on
XTI. As the internal CMOS inverter has a feedback
resistor, the external clock can be AC coupled to
XTI. The system clock is output on CKO.
Table 1. System clock select
CKSL
Parameter
Symbol
HIGH
LOW
XTI input clock
frequency
f
XI
768fs
384fs
(= 1/t )
XI
33.8688 MHz
at fs = 44.1
kHz
16.9344 MHz
at fs = 44.1
kHz
CD playback XTI
frequency
f
XI
CKO output clock
frequency
f
768fs
384fs
CO
Internal system
clock period
T
2t
t
XI
SYS
XI
System Reset (RSTN)
The device should be reset in the following cases.
The device is reset by applying a LOW-level pulse on
RSTN. At system reset, the internal arithmetic opera-
tion and output timing counter are synchronized on
the next LRCI rising edge, as shown in figure 1.
■ At power ON
■ When LRCI and/or the system clock XTI stop, or
other abnormalities occur.
■ When switching the XTI clock 768fs
384fs.
Low
RSTN
1
2
3
9
10
LRCI
Internal
Reset
LO(LON)
RO(RON)
Output Muted
Figure 1. System reset timing
Output mute
At power-ON reset (when RSTN goes LOW), the
outputs LO (LON) and RO (RON) enter the output
mute state. Mute is released on the 9th LRCI rising
edge after RSTN goes HIGH. During this cycle, the
timing reset can cause output noise to be generated.
NIPPON PRECISION CIRCUITS—13
SM5876AM
Infinity-Zero Detector (analog mute control) Output (MUTEO)
Also from immediately after a reset input on RSTN
until the initialization cycle finishes and the first data
cycle occurs.
The SM5876AM outputs an infinity-zero detection
output signal under the following circumstances.
1. When an infinity-zero occurs on both the left and
right channels.
2. When an infinity-zero occurs in the input data for
the channel set by the output mode setting.
3. When the output mode setting is muting for both
the left and right channels.
In cases 1 and 2, from when an infinity-zero is
14
detected a period of 2 × (1/fs) ≈ 0.37 seconds takes
place before MUTEO goes HIGH.
In cases 3 and 4, from when the attenuation counter
14
value is 0 a period of 2 × (1/fs) ≈ 0.37 seconds
4. When the attenuation counter for both the left and
right channels is 0 (−∞).
takes place before MUTEO goes HIGH.
214/fs
1
2
3
8
9
LRCI
DI
Signal
No Signal
Signal
RSTN
MUTEO
Initialize
Figure 2. MUTEO output timing
Audio Data Input (DI, BCKI, LRCI)
The digital audio data is input on DI in MSB-first,
2s-complement, 16-bit serial format.
MDT, can control the left and right channels either
independently or together (independent when the
MDT attenuation control flag is LOW, and together
when HIGH).
Serial data bits are read into the SIPO register (serial-
to-parallel converter register) on the rising edge of
the bit clock BCKI.
The left-channel counter contents DATTL and the
right-channel counter contents DATTR control the
left-channel gain and right-channel gain, respec-
tively, using the following equations.
The arithmetic operation and output timing are inde-
pendent of the input timing. Accordingly, after a
reset, as long as the clock frequency ratio between
LRCI and the system clock XTI is maintained, phase
differences between LRCI, BCKI and the system
clock XTI do not affect the functional operation.
Also, any jitter present on the data input clock does
not appear as output pulse jitter.
DATTL
-------------------
255
Left-channel gain = 20 × log
Right-channel gain = 20 × log
[dB]
DATTR
-------------------
255
[dB]
The bit clock frequency on BCKI should be between
32fs and 64fs.
After system reset initialization, independent
left/right-channel attenuation mode with the maxi-
mum gain of 0 dB is the default.
Operating Modes (MLEN, MDT, MCK)
The microcontroller data is used to control the fol-
lowing parameters.
Deemphasis filter (MDT DEM flag)
Digital attenuator
The built-in digital deemphasis filter is designed to
operate at 44.1 kHz. Deemphasis is ON when the
DEM flag is HIGH, and OFF when the DEM flag is
LOW. After reset, deemphasis OFF is the default.
Digital attenuation is controlled by attenuation data
input on MDT.
The attenuation operation is determined by a mathe-
matical operation of the internal 8-bit up/down
counter’s output data on the signal data. The 8-bit
up/down counter, when attenuation data is input on
NIPPON PRECISION CIRCUITS—14
SM5876AM
Output mode setting (MDT 4-bit data)
The left-channel and right-channel outputs can be set
to any one of 16 different modes, as shown in table 2.
Table 2. Output mode control
PL0
0
PL1
0
PL2
0
PL3
0
Left-channel output
Right-channel output
Notes
Mute
Mute
Mute
0
0
0
1
Mute
R
L
0
0
1
0
Mute
0
0
1
1
Mute
(L + R)/2
Mute
R
0
1
0
0
R
0
1
0
1
R
0
1
1
0
R
L
Reverse
Stereo
0
1
1
1
R
L
(L+R)/2
Mute
R
1
0
0
0
1
0
0
1
L
1
0
1
0
L
L
1
0
1
1
L
(L+R)/2
Mute
R
1
1
0
0
(L+R)/2
(L+R)/2
(L+R)/2
(L+R)/2
1
1
0
1
1
1
1
0
L
1
1
1
1
(L + R)/2
“Stereo” is the default after system reset.
“Mute” refers to soft muting.
Soft mute (output mode setting)
Upon system reset initialization, mute is released,
which corresponds to the maximum gain of 0 dB.
The channel output muting set by the output mode
control 4-bit data is soft mute mode.
The attenuation counter output decrements by 1 step
at a time, reducing the gain. The signal is completely
muted after a time of (1024/fs), which corresponds to
approximately 23.2 ms when fs = 44.1 kHz.
MUTE
0 dB
Gain
Conversely, when soft mute is released using the out-
put mode control, the attenuation counter output
increments by 1 step at a time, increasing the gain.
The time taken to return to 0 dB from full muting is
also (1024/fs).
– ∞
1024/fs
1024/fs
Figure 3. Soft mute operation example
Attenuator control (ATC flag)
When an attenuation value is set, the output gain
decreases from the value set by the attenuation data
until the gain is −∞. Similarly for mute release, the
output gain increases from the current value until the
gain is 0 dB.
The attenuator control (ATC) flag is input on MDT.
When the ATC flag is HIGH, the left-channel and
right-channel attenuator data is common. In this
mode, the left-channel data is used for both channels.
Soft mute operation is shown in figure 3.
NIPPON PRECISION CIRCUITS—15
SM5876AM
TIMING DIAGRAMS
Input Timing
(DI, BCKI, LRCI)
1/fs
Left
16 bit
Right
16 bit
Channel
Channel
MSB
LSB
MSB
LSB
DI
BCKI
(64fs MAX)
LRCI
(MDT, MCK, MLEN)
L channel
Attenuation Data
R channel
Attenuation Data
Output
Mode Control
MCK
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PL0 PL1 PL2 PL3 DEM ATC
MDATA
MLEN
LSB
MSB LSB
MSB
Data is recognized on the rising edge of MLEN.
NIPPON PRECISION CIRCUITS—16
SM5876AM
TYPICAL APPLICATIONS
Input Interface Circuit
X'tal
XTI
XTO
CKO
44.1kHz
LRCI
DI
SM5876
2.1168MHz
BCKI
Note that the output analog characteristics and other specifications are not guaranteed for a particular format or
application circuit.
Output Analog Processing Circuit
(Left channel only is shown.)
LON
SM5876
−
+
LOUT
LO
NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to
improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for
the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits
are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision
Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification.
The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or
malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter,
including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or
indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies.
NIPPON PRECISION CIRCUITS INC.
4-3, 2-chome Fukuzumi
Koutou-ku, Tokyo 135-8430, Japan
Telephone: 03-3642-6661
Facsimile: 03-3642-6698
NIPPON PRECISION CIRCUITS INC.
NC9504BE 1996.06
NIPPON PRECISION CIRCUITS—17
相关型号：
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