SM8702AM [NPC]
Clock Generator IC; 时钟发生器IC
| 型号： | SM8702AM |
| 厂家： | 
NIPPON PRECISION CIRCUITS INC |
| 描述： | Clock Generator IC |
| 文件： | 总16页 (文件大小：156K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SM8702AM
Clock Generator IC
NIPPON PRECISION CIRCUITS INC.
OVERVIEW
The SM8702AM is a clock generator IC that can generate clock signals up to and exceeding 100MHz for per-
sonal computer (PC) motherboards. It uses a single 14.318MHz crystal oscillator element and 2 built-in PLLs
to simultaneously and independently generate 2 CPU clocks, 6 PCI bus clocks, 2 reference clocks with the
same frequency as the crystal element, 48MHz USB interface clock, and 24MHz Super I/O chip clock outputs.
It also has 14 outputs that can function as SDRAM clocks by buffering an external input SDRAM clock.
FEATURES
PINOUT
■ Intel Pentium II, Pentium III, and AMD x86-
compatibles supported
■ 2.5/3.3V CPU clock outputs and IOAPIC clock
output
48-pin SSOP (300 mil)
(Top view)
■ 14 × SDRAM clock outputs (3 DIMMs)
■ 2 × CPU clock outputs
1
48
VDD1
VDDL1
IOAPIC
REF1/FS2
VSS
REF0
(60), 66, 75, 83, 95, 100, 103, 112, (124), 133MHz
CPU/SDRAM clock frequencies. Values in paren-
theses are available as mask options.
■ 6 × PCI bus clock outputs (one free-running out-
put)
33MHz or 1/2, 1/3, 1/4 of the CPU clock fre-
quency
■ 2 × reference clock outputs and 1 × IOAPIC clock
output
VSS
XT
XTN
CPUCLK0
CPUCLK1
VDDL2
SDRAM13
SDRAM12
VSS
VDD2
PCICLK_F/MODE
PCICLK0
VSS
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDD2
SDRAM0
SDRAM1
VDD3
SDRAM2
SDRAM3
VSS
14.318MHz REF/IOAPIC clock frequency
■ 1 × 48MHz USB interface clock output
■ 1 × 24MHz clock output for Super I/O chip
BUFFERIN
VSS
SDRAM11/CPU_STOP#
SDRAM10/PCI_STOP#
VDD3
SDRAM4
SDRAM5
VDD3
2
■ I C serial data bus for frequency/mode output con-
trol
SDRAM9
SDRAM8
VSS
SDRAM6
SDRAM7
VDD4
■ CPU-stop and PCI-stop functions
■ Spread Spectrum Clock Generator (SSCG) out-
puts
48MHz/FS0
24MHz/FS1
SDATA
24
25
SCLK
Center spread/Down spread, ± 0.5% or ± 1.5%
■ 3.3V (VDD) and 2.5/3.3V (VDDL) supply volt-
ages
■ 48-pin SSOP package (pin compatible with
ICS9148-26)
ORDERING INFORMATION
De vice
Packag e
48-pin SSOP
APPLICATIONS
SM8702AM
■ PC motherboards using Intel Pentium , Pen-
tium II/III, AMD-K6 devices, and x86 architec-
ture CPUs
Intel and Pentium are registered trademarks of Intel co..
AMD and AMD-K6 are registered trademarks of Advanced Micro Devices, Inc..
2
I C Bus is a registered trademark of Philips Electronics N. V..
NIPPON PRECISION CIRCUITS—1
SM8702AM
PACKAGE DIMENSIONS
(Unit: mm)
15.85 0.1
0.635
0
8
0.05
0.25 0.03
0.80 0.1
M
0.12
NIPPON PRECISION CIRCUITS—2
SM8702AM
BLOCK DIAGRAM
(1st PLL)
Unlock Detector
PCICLK_F
XT
XTN
5
2
PCICLK
[0:4]
Phase
Detector
Charge
Pump
DIV/3
to DIV/6
R-Countor
VCO
Current
Source
N-Countor
CPUCLK
[0:1]
DIV/2
SS_CONTROLLER
14
SDRAM
[0:13]
(MS)
BUFFERIN
Buff. Amp.
(2nd PLL)
Unlock Detector
48MHz
(USB)
Phase
Detector
Charge
Pump
R-Countor
VCO
DIV/3
1/2
Current
Source
24MHz
(Super I/O)
N-Countor
2
REF[0:1]
IOAPIC
3
FS[0:2]
MODE
I/O
Latch
ROM
SDATA
SCLK
2
Control Logic
I C
CPU_STOP#
PCI_STOP#
PIN DESCRIPTION
Nu mb e r
Na me
VDD1
REF0
VS S
I/O
–
Function
Notes
1
2
3
4
5
3.3V supply
XT, XTN oscillator, REF[0:1] buffer, stop logic, 3.3V line
I/O
–
14.318MHz reference clock output
Ground
Crystal oscillator, REF[0:1], 3.3Vline
XT
I
Crystal oscillator input
Crystal oscillator output
XTN
O
PCI clock output buffers, pre-buffer, stop logic, and
internal circuit logic supply
6
VDD2
–
3.3V supply
PCICLK_F
O
PCI bus free-running clock output
CP U_S TOP# (pin 17) and PCI_STOP# (pin 18) mode
select pin.
MODE = HIGH: Desktop mode
MODE = LOW: Mobile mode
7
MODE
I
Mode settings (latch input)
8
9
PCICLK0
VS S
O
–
PCI bus clock output
Ground (3.3V supply)
PCI bus clock output
PCI clock output buffers, pre-buffer, stop logic
10
PCICLK1
O
NIPPON PRECISION CIRCUITS—3
SM8702AM
Nu mb e r
Na me
PCICLK2
PCICLK3
PCICLK4
VDD2
I/O
O
Function
PCI bus clock output
Notes
11
12
13
14
O
PCI bus clock output
PCI bus clock output
3.3V supply
O
–
PCI clock output buffers, pre-buffer, stop logic
Input on BUFFERIN is buffered and then output on
SDRAM[0:13]
15
16
BUFFERIN
I
SDRAM clock input
VS S
–
Ground (3.3V supply)
SDRAM clock output
SDRAM clock output buffers, pre-buffer, stop logic
S DRAM11
17
18
I/O
I/O
In mobile mode (MODE = LOW), CPUCLK[0:1] tied LOW
whe n CPU_STOP# = LOW.
CP U_S TOP #
S DRAM10
CPU clock outputs stop control
SDRAM clock output
In mobile mode (MODE = LOW), PCICLK[0:4] tied LOW
when PCI_STOP# = LOW.
PCI_STOP #
PCI clock outputs stop control
19
20
21
VDD3
–
O
O
3.3V supply
SDRAM clock output buffers, pre-buffer, stop logic
S DRAM9
S DRAM8
SDRAM clock output
SDRAM clock output
2
PLL and internal logic ground, I C interface,
24MHz/48MHz output ground
22
VS S
–
Ground (3.3V supply)
2
23
24
S DATA
SCLK
24MHz
FS1
I/O
I
I C serial data input
2
I C clock input
24MHz clock output
25
I/O
Frequency select 1 (latch input)
48MHz USB clock output
Frequency select 0 (latch input)
48MHz
FS0
26
27
I/O
–
2
I C interface, 24MHz/48MHz output supply, PLL and
VDD4
3.3V supply
internal logic supply
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
S DRAM7
S DRAM6
VDD3
O
O
–
SDRAM clock output
SDRAM clock output
3.3V supply
SDRAM clock output buffers, pre-buffer, stop logic
SDRAM clock output buffers, pre-buffer, stop logic
SDRAM clock output buffers, pre-buffer, stop logic
SDRAM clock output buffers, pre-buffer, stop logic
CPU clock output buffers, pre-buffer, stop logic
CPU clock output buffers, pre-buffer, stop logic
S DRAM5
S DRAM4
VS S
O
O
–
SDRAM clock output
SDRAM clock output
Ground (3.3V supply)
SDRAM clock output
SDRAM clock output
3.3V supply
S DRAM3
S DRAM2
VDD3
O
O
–
S DRAM1
S DRAM0
VS S
O
O
–
SDRAM clock output
SDRAM clock output
Ground (3.3V supply)
SDRAM clock output
SDRAM clock output
2.5/3.3V supply
S DRAM12
S DRAM13
VDDL2
O
O
–
CP UCLK1
CP UCLK0
VS S
O
O
–
CPU clock output
CPU clock output
Ground (2.5/3.3V supply)
14.318MHz reference clock output
Frequency select 2 (latch input)
14.318MHz IOAPIC clock output
2.5/3.3V supply
REF1
46
I/O
FS2
47
48
IOAPIC
VDDL1
O
–
IOAPIC output buffer, pre-buffer, stop logic
NIPPON PRECISION CIRCUITS—4
SM8702AM
SPECIFICATIONS
Absolute Maximum Ratings
VDD:VDD1, VDD2, VDD3, VDD4
VDDL:VDDL1, VDDL2 unless otherwise noted.
Parameter
Symbol
Rating
Unit
V
DD
, V
−0.3 to 6.0
V
(V
, V
, V
)
DD1
DD2
DD3
DD4
Supply voltage range
V
DDL
−
0.3 to 6.0
0
V
(V
, V
)
DDL1
DDL2
V
V
V
V
S S
Input voltage range
V
−
−
0.3 to V
0.3 to V
+ 0.3
+ 0.3
IN
DD
DD
Output voltage range
Storage temperature range
Power dissipation
V
OUT
T
−55 to 125
°C
stg
P
0.8
W
D
Recommended Operating Conditions
V
= 0V
SS
Rating
typ
Parameter
Symbol
Condition
Unit
min
ma x
V
Excludes internal core, CPU
clock and IOAPIC output
stages
DD
, V
(V
V
,
)
3.135
3.300
2.500
3.465
V
V
DD1
DD2
, V
DD3
DD4
Supply voltages
V
Internal core, CPU clock
and IOAPIC output stages
DDL
2.375
2.625
(V
, V
)
DDL1
DDL2
Operating temperature range
Maximum load capacitance
Reference frequency
T
0
–
70
20
30
20
–
°C
opr
C
CP UCLK
10
20
10
–
–
pF
pF
L1
L2
L3
C
C
PCICLK, SDRAM
REF, 24/48MHz, IOAPIC
–
–
pF
f
14.318
MHz
REF
NIPPON PRECISION CIRCUITS—5
SM8702AM
DC Electrical Characteristics
T = 0 to 70°C, V = 3.3V ± 5%, V
= 2.5V ± 5%, V = 0V unless otherwise noted.
a
DD
DDL
SS
Rating
Parameter
Symbol
Condition
Unit
V
min
typ
–
ma x
HIGH-level input voltage
LOW -level input voltage
V
All pins excl. XT, XTN
2.0
V
DD
IH
All pins excl. XT, XTN, SDATA, SCLK
V
V
−
–
0.8
0.7
10
S S
V
V
IL
2
S DATA, SCLK: I C interface
–
S S
10
HIGH-level input current
LOW -level input current
I
V
V
= V
DD
–
µA
µA
IH
IH
IL
I
= 0V
–
–
10
IL
All clock outputs:
1mA, V = 3.135V
PCICLK, SDRAM, REF,
24/48MHz pins.
Also, CPUCLK[0:1] and
IOAPIC outputs, when
VDDL[1:2] = 3.3V.
HIGH-level output voltage
LOW -level output voltage
V
2.4
–
–
–
0.4
–
V
V
OH(3.3V)
I
= −
OH
DD
All clock outputs:
= 1mA, V = 3.135V
V
–
OL(3.3V)
I
OL
DD
CPUCLK[0:1], IOAPIC:
1mA, V = 2.375V
HIGH-level output voltage
LOW -level output voltage
V
2.0
–
–
V
V
OH(2.5V)
CPUCLK[0:1] and
IOAPIC outputs, when
VDDL[1:2] = 2.5V.
I
= −
OH
DDL
CPUCLK[0:1], IOAPIC:
= 1mA, V = 2.375V
V
–
0.4
OL(2.5V)
I
OL
DDL
CPUCLK[0:1]: V
= 1.7V
8.5
23.0
42.6
42.6
42.6
OH
PCICLK_F, PCICLK[0:4]:
= 2.0V
18.7
18.7
18.7
–
–
–
V
OH
HIGH-level output current
I
SDRAM[0:13]: V
= 2.0V
f = 66.5MHz
OUT
mA
OH
OH
REF[0:1], 24/48MHz:
= 2.0V
V
OH
IOAPIC: V
= 1.7V
8.5
–
–
23.0
25.3
OH
CPUCLK[0:1]: V = 0.7V
OL
11.0
PCICLK_F, PCICLK[0:4]:
18.7
18.7
18.7
11.0
–
–
–
40.3
40.3
40.3
V
= 0.8V
OL
LOW -level output current
I
SDRAM[0:13]: V = 0.8V
OL
mA
OL
f
= 66.5MHz
OUT
REF[0:1], 24/48MHz:
V
= 0.8V
OL
IOAPIC: V = 0.7V
OL
–
–
–
–
–
25.3
10
Output leakage current
Current consumption
I
Outputs high impedance
−10
µA
OZ
I
C
C
C
= 0pF, V = 3.465V
–
–
–
180
30
DD
L
L
L
DD
I
= 0pF, V
= 0pF, V
= 3.465V
= 2.625V
f = 66.5MHz
OUT
mA
DDL1
DDL
DDL
I
20
DDL2
NIPPON PRECISION CIRCUITS—6
SM8702AM
AC Electrical Characteristics
CPU clock characteristics 1
T = 0 to 70°C, V = 3.3V ± 5%, V
= 2.5V ± 5%, V = 0V, f
= 14.318MHz, C = 20pF unless other-
a
DD
DDL
SS
X’tal
L
wise noted.
Rating
Parameter
Symbol
Condition
Unit
min
–
typ
–
ma x
2.0
1
Output clock rise time
t
V
= 0.4V
→
→
V
= 2.0V transition time
V = 0.4V transition time
OL
ns
ns
%
r
OL
OH
1
Output clock fall time
t
V
= 2.0V
–
–
2.0
f
OH
Duty cycle
Dt
V
V
= 1.25V
45
–
50
–
55
T
T
1
Output clock jitter
t
= 1.25V, rising edge
= 1.25V, rising edge
Cycle-to-cycle jitter
250
ps
jc
Between CPUCLK0 and
CP UCLK1
1
Output clock skew
t
V
–
–
250
ps
s kw
T
Supply ON (V = 3.3V)
DD
until clock reaches
specified frequency
1
Clock frequency stabilize time
t
Cold start
–
–
–
3
ms
stb
2
Output impedance
Z
V
= 0.5V
DDL
10
90
Ω
O
O
1. Design maximum values, not 100% guaranteed.
2. Design estimate values, not 100% guaranteed.
CPU clock characteristics 2
T = 0 to 70°C, V = V
= 3.3V ± 5%, V = 0V, f
= 14.318MHz, C = 20pF unless otherwise noted.
a
DD
DDL
SS
X’tal
L
Rating
Parameter
Symbol
Condition
Unit
min
–
typ
–
ma x
2.5
1
Output clock rise time
t
V
= 0.4V
= 2.4V
→
→
V
= 2.4V transition time
V = 0.4V transition time
OL
ns
ns
%
r
OL
OH
1
Output clock fall time
t
V
V
V
–
–
2.5
f
OH
Duty cycle
Dt
= 1.5V
45
–
50
–
55
T
T
1
Output clock jitter
t
= 1.5V, rising edge
= 1.5V, rising edge
Cycle-to-cycle jitter
250
ps
jc
Between CPUCLK0 and
CP UCLK1
1
Output clock skew
t
V
–
–
250
ps
s kw
T
Supply ON (V = 3.3V)
DD
until clock reaches
specified frequency
1
Clock frequency stabilize time
t
Cold start
–
–
–
3
ms
stb
2
Output impedance
Z
V
= 0.5V
DDL
10
60
Ω
O
O
1. Design maximum values, not 100% guaranteed.
2. Design estimate values, not 100% guaranteed.
NIPPON PRECISION CIRCUITS—7
SM8702AM
PCI clock characteristics
T = 0 to 70°C, V = 3.3V ± 5%, V = 0V, f
= 14.318MHz, C = 30pF unless otherwise noted.
a
DD
SS
X’tal
L
Rating
Parameter
Symbol
Condition
Unit
min
–
typ
–
ma x
2.0
1
Output clock rise time
t
V
= 0.8V
→
→
V
= 2.4V transition time
V = 0.8V transition time
OL
ns
ns
%
r
OL
OH
1
Output clock fall time
t
V
= 2.4V
= 1.5V
–
–
2.0
f
OH
Duty cycle
Dt
V
V
45
–
50
–
55
T
T
1
Output clock jitter
t
= 1.5V, rising edge
Cycle-to-cycle jitter
250
ps
jc
Between PCI clocks:
PCICLK_F and
PCICLK[0:4]
1
Output clock skew
t
V
= 1.5V, rising edge
–
–
250
4.0
ps
ns
s kw
T
V
V
= 1.25/1.5V,
= 1.5V, rising
Between CPU and PCI
clocks: CPUCLK[0:1] and
PCICLK_F/PCICLK[0:4]
T-CPUCLK
2
CPU/PCI clock skew
t
1.0
2.2
hpsk
T-PCICLK
edges
Supply ON (V = 3.3V)
DD
until clock reaches
specified frequency
1
Clock frequency stabilize time
t
Cold start
–
–
–
3
ms
stb
3
Output impedance
Z
V
= 0.5V
10
60
Ω
O
O
DD
1. Design maximum values, not 100% guaranteed.
2. CPUCLK and PCICLK rising edges, V
= 1.25V (V
= 2.5V)/1.5V (V
= 3.3V), V
= 1.5V skew measurement.
T-CPUCLK
DDL
DDL
T-PCICLK
3. Design estimate values, not 100% guaranteed.
SDRAM clock characteristics
T = 0 to 70°C, V = V
= 3.3V ± 5%, V = 0V, f
= 14.318MHz, C = 30pF unless otherwise noted.
a
DD
DDL
SS
X’tal
L
Rating
Parameter
Symbol
Condition
Unit
min
–
typ
–
ma x
2.0
1
Output clock rise time
t
V
= 0.8V
= 2.4V
→
→
V
= 2.4V transition time
V = 0.8V transition time
OL
ns
ns
r
OL
OH
1
Output clock fall time
t
V
V
–
–
2.0
f
OH
= 1.5V, BUFFERIN
T
3.3V BUFFERIN input
clock signal logic level
1
Duty cycle
Dt
input clock signal rise
and fall time rate ≥ 1V/ns
40
–
50
60
%
V
= 1.5V, rising edge,
T
BUFFERIN input clock
signal rise and fall time
rate ≥ 1V/ns
Between SDRAM clocks:
SDRAM[0:13]
1
Output clock skew
t
200
600
ps
s kw
V
V
= 1.5V,
= 1.5V, rising
T-BUFFERIN
T-S DRAM
Input to output propagation
delay
Between BUFFERIN and
SDRAM[0:13]
t
edges, BUFFERIN input
clock signal rise and fall
time rate ≥ 1V/ns
–
5.5
–
7.0
60
ns
2,3
pd
3
Output impedance
Z
V
= 0.5V
DD
10
Ω
O
O
1. Design maximum values, not 100% guaranteed.
2. BUFFERIN and SDRAM rising edges, V
= 1.5V (logic level = 3.3V), V
= 1.5V delay measurement.
T-BUFFERIN
T-S DRAM
3. Design estimate values, not 100% guaranteed.
NIPPON PRECISION CIRCUITS—8
SM8702AM
24MHz/48MHz, REF[0:1] clock characteristics
T = 0 to 70°C, V = 3.3V ± 5%, V = 0V, f
= 14.318MHz, C = 20pF unless otherwise noted.
a
DD
SS
X’tal
L
Rating
Parameter
Symbol
Condition
Unit
min
–
typ
–
ma x
2.0
1
Output clock rise time
t
V
= 0.8V
→
→
V
= 2.4V transition time
V = 0.8V transition time
OL
ns
ns
%
r
OL
OH
1
Output clock fall time
t
V
= 2.4V
= 1.5V
–
–
2.0
f
OH
1
Duty cycle
Dt
V
V
40
–
50
250
60
T
T
1
Output clock jitter
t
= 1.5V, rising edge
Absolute jitter
800
ps
jc
Supply ON (V = 3.3V)
DD
until clock reaches
specified frequency
1
Clock frequency stabilize time
t
Cold start
–
–
–
3
ms
stb
2
Output impedance
Z
V
= 0.5V
DD
10
60
Ω
O
O
1. Design maximum values, not 100% guaranteed.
2. Design estimate values, not 100% guaranteed.
IOAPIC clock characteristics
T = 0 to 70°C, V = 3.3V ± 5%, V = 0V, f
= 14.318MHz, C = 20pF unless otherwise noted.
a
DD
SS
X’tal
L
Rating
Parameter
Symbol
Condition
Unit
min
typ
ma x
V
= 0.8V
= 3.3V
→
V
= 2.4V transition time,
OL
OH
–
–
2.0
V
DDL1
1
Output clock rise time
t
ns
r
V
= 0.4V
= 2.5V
→
V
= 2.0V transition time,
= 0.8V transition time,
= 0.4V transition time,
OL
OH
–
–
–
–
–
–
2.0
2.0
2.0
V
DDL1
V
= 2.4V → V
OL
= 3.3V
OH
V
DDL1
1
Output clock fall time
t
ns
f
V
= 2.0V
= 2.5V
→
V
OH
OL
V
DDL1
1
Duty cycle
Dt
V
V
= 1.5V, V
= 3.3V
40
–
50
60
%
T
T
DDL1
1
Output clock jitter
t
= 1.5V, rising edge
Absolute jitter
250
800
ps
jc
Supply ON (V = 3.3V)
DD
until clock reaches
specified frequency
1
Clock frequency stabilize time
t
Cold start
–
–
–
3
ms
stb
2
Output impedance
Z
V
= 0.5V
DD
10
90
Ω
O
O
1. Design maximum values, not 100% guaranteed.
2. Design estimate values, not 100% guaranteed.
NIPPON PRECISION CIRCUITS—9
SM8702AM
2
I C serial interface electrical characteristics
T = 0 to 70°C, V = 3.3V ± 5%, V = 0V, f
= 14.318MHz, C = 30pF unless otherwise noted.
a
DD
SS
X’tal
L
Rating
Parameter
Symbol
Condition
Unit
min
0
typ
–
ma x
100
–
2
Serial clock frequency
Serial clock start state hold time
Serial clock LOW -level pulsewidth
Serial clock HIGH-level pulsewidth
Successive start state setup time
Data hold time
f
I C standard mode
kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
pF
S CLK
t
4.0
4.7
4.0
4.7
0
–
HD;STA
t
–
–
LOW
t
–
–
HIGH
t
–
–
SU;STA
2
t
I C device data
–
3.45
–
HD;DAT
Data input setup time
t
250
–
–
SU;DAT
Pulse rise time
t
–
1000
300
–
r
Pulse fall time
t
–
–
f
Stop state setup time
t
4.0
4.7
–
–
SU;STO
Serial data bus buffer time
Bus line load capacitance
t
–
–
BUF
C
–
400
b
tBUF
SDATA
tr
tf
tr
t
tHD;STA
SU;DtAT
f
tLOW
SCLK
tHD;STA
tSU;STO
tHD;DAT
tSU;STA
tHIGH
2
I C serial data timing
NIPPON PRECISION CIRCUITS—10
SM8702AM
FUNCTIONAL DESCRIPTION
Mode Setting Overview
There are 2 methods that can be used to set the frequency and clock output start/stop operating modes.
■ Using external inputs (pins 7, 17, 18, 25, 26, 46) or,
2
■ Using data read in from an I C serial interface.
The default state is where the operating state is set by external pin control. Thus, the output frequency can be
2
set by FS[0:2] (pins 25, 26, 46). Note that the SSCG function is OFF in this case. If the I C serial data byte 0
2
bit 3 is set to 1, then the output frequency is determined by data using the I C interface. Then, the Spread Spec-
2
2
trum function (SSCG) can be selected using I C data. However, if mode settings using I C data and external
2
pin control conflict or overlap, the mode settings dictated by I C data have precedence over external pin con-
trol.
During normal operation, pins 17 and 18 can function as SDRAM clock outputs (desktop mode) or they can
function as CPUCLK output stop control and PCICLK output stop control (mobile mode), depending on the
state of MODE (pin 7) when power is first applied.
2
In addition to output frequency settings, other operating mode settings which can be controlled by I C serial
data include SSCG operation and mode, and output pin grouping enable/disable switching.
Hardware Frequency Selection
When power is applied, the frequency setting is controlled by FS[0:2] when byte 0 bit 3 is set to 0. Note that if
byte 0 bit 3 is set to 1, the frequency is selected by bits 4 to 6 in the same manner as inputs FS0 to FS2.
Inputs
FS1
Output frequency
CPUCLK
PCICLK
[MHz]
FS2
FS0
[MHz]
100.2
133
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
HIGH
HIGH
LOW
LOW
HIGH
HIGH
LOW
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
33.4
33.2
37.3
34.3
33.2
41.6
37.4
31.6
112.1
103
66.5
83.3
74.9
94.7
Mode and Power Management Inputs
The SM8702AM supports 2 operating modes, desktop mode and mobile mode, selected by MODE (pin 7).
If MODE is HIGH when power is first applied, desktop mode is selected. In this mode, pins 17 and 18 function
as SDRAM clock outputs, SDRAM11 and SDRAM10, respectively.
If MODE is LOW when power is first applied, mobile mode is selected. In this mode, pins 17 and 18 function
as the CPU clock (CPUCLK[0:1]) and PCI clock (PCICLK[0:4]) output stop control signal inputs,
CPU_STOP# and PCI_STOP#, respectively. This function is used mainly to reduce power consumption.
MODE
Pin 17
Pin 18
Mo d e
Desktop mode
HIGH
S DRAM11
S DRAM10
Pins 17 and 18 are outputs.
Mobile mode
Pins 17 and 18 are inputs.
LOW
CPU_STOP# PCI_STOP #
NIPPON PRECISION CIRCUITS—11
SM8702AM
Operating Mode Summary
The state of the various external inputs and outputs in the operating modes is indicated in the following table.
PCICLK_F,
CPUCLK[0:1] PCICLK[0:4] 24MHz/48MHz,
SDRAM[0:13]
VCO
(internal
signal)
SDRAM11/
CP U_S TOP #
SDRAM10/
PCI_STOP #
Crystal
oscillator
1
MODE
Notes
MODE = HIGH
(desktop
Desktop mode.
Enabled Enabled Pins 17 and 18
function as outputs.
Enabled
(SDRAM output)
Enabled
(SDRAM output)
Enabled
Enabled
Enabled
mode)
HIGH
HIGH
Enabled
Enabled
Disabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled Enabled
Mobile mode.
(CPU_STOP#input) (PCI_STOP# input)
Pins 17 and 18
function as inputs.
HIGH
LOW
Enabled Enabled
(CPU_STOP#input) (PCI_STOP# input)
MODE = LOW
(mobile mode)
Pin 17 =
LOW
HIGH
CP U_S TOP #
Pin 18 =
PCI_STOP #
Enabled Enabled
(CPU_STOP#input) (PCI_STOP# input)
LOW
LOW
Enabled Enabled
(CPU_STOP#input) (PCI_STOP# input)
1. Enabled = output functions active. Disabled = LOW-level output.
CPU Clock Stop Function
In mobile mode, selected using MODE (pin 7), the CPUCLK[0:1] clock outputs can be stopped by external pin
control. The asynchronous stop signal input on CPU_STOP# is sampled internally on the rising edge of the
PCI free-running output clock (PCICLK_F).
When CPU_STOP# goes LOW, the CPU clock outputs (CPUCLK) stop after a delay of 2 to 4 clock cycles.
When CPU_STOP# goes HIGH, the CPU clock outputs start after a delay of 2 to 4 clock cycles. The actual
start and stop delay varies with the output frequency up to a maximum of 4 CPU clock cycles.
CPUCLK
(internal)
PCICLK
(internal)
PCICLK_F
(free-running)
CPU_STOP#
PCI_STOP#
(All "H")
CPUCLK
(external)
NIPPON PRECISION CIRCUITS—12
SM8702AM
PCI Clock Stop Function
In mobile mode, selected using MODE (pin 7), the PCICLK[0:4] clock outputs can be stopped by external pin
control, in the same way as the CPU clock stop function.
When PCI_STOP# goes LOW, the PCI clock outputs (PCICLK) stop, and when PCI_STOP# goes HIGH, the
PCI clock outputs start. In either case, the PCI_STOP# signal is sampled internally on the rising edge of PCI-
CLK, and the output state transition occurs with 1 PCI clock cycle delay.
CPUCLK
(internal)
PCICLK
(internal)
PCICLK_F
(free-running)
CPU_STOP#
(All "H")
PCI_STOP#
PCICLK
(external)
NIPPON PRECISION CIRCUITS—13
SM8702AM
2
I C Bus Serial Data Format
2
The format of the I C serial data on SDATA (pin 23) which is input in sync with the serial data clock on SCLK
(pin 24) is shown below.
2
The SM8702AM I C address is given below.
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0 R/W#
1
−
R/W# = 0 or 1
2
In the start sequence, the I C bus serial data is fed into the clock generator in the following direction.
2
1. I C address with R/W# = 0
2. ACK acknowledge bit
3. Two successive 8-bit dummy command code data words (including ACK acknowledge bit)
4. 8-bit dummy command code (Byte 0 to Byte 5)
2
The direction of I C Data for Clock Generator
1bit 8bit 1bit 8bit 1bit 8bit 1bit 8bit 1bit 8bit 1bit
8bit 1bit
2
S
I C Addr.
A
Dummy
A
Dummy
A
A
C
K
A
C
K
A
C
K
A
C
K
T
O
P
+R/W#
C Command C Command C Byte 0
K
Byte 1
Byte 2
Byte 5
Code
K
Code
Bit 6
K
D2h
Bit 7
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
2
The data transfer speed is 100k bps (I C standard mode), with input logic level of 3.3V. When power is first
applied, all internal registers are restored to their default state as below.
■ Byte0 : default = 0 (bit 0 to bit 3 and bit 7)
: default = 1 (bit 4 to bit 6)
■ Byte 1 to Byte 5 : default = 1 (all bits)
NIPPON PRECISION CIRCUITS—14
SM8702AM
2
I C Bus Data Bytes
Byte 0: function and frequency select
Power-ON
default
Bit
Function
Notes
0: Spread spectrum ± 1.5% modulation
1: Spread spectrum ± 0.5% modulation
The spread spectrum accuracy of modulation is not
guaranteed.
7
0
Frequency select bits
CPUCLK
PCICLK
[MHz]
Bit 6
Bit 5
Bit 4
[MHz]
100.2
133
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
33.4
33.2
37.3
34.3
33.2
41.6
37.4
31.6
The power-ON default for bits 4 to 6 is 1.
112.1
103
2
6:4
1
When bit 3 is set to 1 (I C select), bits 4 to 6 select
the frequency in the same write cycle timing.
66.5
83.3
74.9
94.7
0: Hardware frequency select using FS[0:2]
1: I C bus serial data frequency select
3
2
1
0
0
0
0
0
FS[0:2] are latch inputs
2
0: Spread spectrum center spread select
1: Spread spectrum down spread select
0: Normal operating mode (SSCG disabled)
1: Spread spectrum operating mode (SSCG enabled)
0: Normal output mode (running)
1: Three-state output mode
All outputs are high impedance when bit 0 is set to 1.
Byte 1: CPU register
Byte 2: PCI register
Pin
numbe r
Power-ON
default
Pin
numbe r
Power-ON
default
Bit
Notes
48MHz USB
Bit
Notes
1
1
7
6
5
4
3
2
1
0
26
25
–
1
1
1
1
1
1
1
1
7
6
5
4
3
2
1
0
–
7
1
1
1
1
1
1
1
1
(Reserved)
24MHz (Super I/O)
(Reserved)
PCICLK_F enable
(Reserved)
–
–
(Reserved)
14
12
11
10
8
PCICLK4 enable
PCICLK3 enable
PCICLK2 enable
PCICLK1 enable
PCICLK0 enable
–
(Reserved)
–
(Reserved)
43
44
CPUCLK1 enable
CPUCLK0 enable
1. 1 = enabled, 0 = disabled
1. 1 = enabled, 0 = disabled
NIPPON PRECISION CIRCUITS—15
SM8702AM
Byte 3: SDRAM register
Byte 5: REF/IOAPIC register
Pin
numbe r
Power-ON
default
Pin
numbe r
Power-ON
default
Bit
Notes
Bit
Notes
1
1
7
6
5
4
–
–
–
–
1
1
1
1
(Reserved)
(Reserved)
(Reserved)
(Reserved)
7
6
5
4
3
2
1
0
–
–
1
1
1
1
1
1
1
1
(Reserved)
(Reserved)
(Reserved)
–
47
–
IOAPIC enable
(Reserved)
SDRAM[10:11] enable in
desktop mode only (MODE =
HIGH)
3
17, 18
1
–
(Reserved)
46
2
REF1 enable
REF0 enable
20, 21, 40,
41
2
1
0
1
1
1
SDRAM[8,9,12,13] enable
SDRAM[4:7] enable
28, 29, 31,
32
1. 1 = enabled, 0 = disabled
34, 35, 37,
38
SDRAM[0:3] enable
1. 1 = enabled, 0 = disabled
Byte 4: Reserved register
Pin
numbe r
Power-ON
default
Bit
Notes
1
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
–
1
1
1
1
1
1
1
1
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
1. 1 = enabled, 0 = disabled
NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to
improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for
the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits
are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision
Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification.
The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or
malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter,
including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or
indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies.
NIPPON PRECISION CIRCUITS INC.
4-3, Fukuzumi 2-chome
Koto-ku, Tokyo 135-8430, Japan
NIPPON PRECISION CIRCUITS INC.
Telephone: 03-3642-6661
Facsimile: 03-3642-6698
NP9907AE 1999.07
NIPPON PRECISION CIRCUITS—16
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