CLC417 [NSC]
Dual Low-Power, Programmable Gain Buffer; 双路低功耗,可编程增益缓冲器![CLC417](http://pdffile.icpdf.com/pdf1/p00076/img/icpdf/CLC417_399315_icpdf.jpg)
型号: | CLC417 |
厂家: | ![]() |
描述: | Dual Low-Power, Programmable Gain Buffer |
文件: | 总8页 (文件大小:150K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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September 1998
N
CLC417
Dual Low-Power, Programmable Gain Buffer
Features
General Description
■
0.01%, 0.03° D , Dφ
The CLC417 is a dual, low-cost, high-speed (120MHz) buffer which
features user-programmable gains of +2, +1, and -1V/V. The
CLC417’s high 60mA output current, coupled with its ultra-low
39mW per channel power consumption makes it the ideal choice for
demanding applications that are sensitive to both power and cost.
G
■
High output current: 60mA
■
High input impedance: 6MΩ
+
■
Gains of 1, +2 with no external
components
■
■
■
■
■
Low power
Very low input bias currents: 100nA
Excellent gain accuracy: 0.1%
High speed: 120MHz -3dB BW
Low-cost
Utilizing National’s proven architectures, this dual current feedback
amplifier surpasses the performance of alternate solutions with a
closed-loop design that produces new standards for buffers in gain
accuracy, input impedance, and input bias currents. The CLC417’s
internal feedback network provides an excellent gain accuracy of
0.1%. High source impedance applications will benefit from the
CLC417’s 6MΩ input impedance along with its exceptionally low
100nA input bias current.
Applications
■
Desktop video systems
■
Video distribution
■
Flash A/D driver
■
High-speed line driver
■
High-source impedance applications
Professional video processing
High resolution monitors
With exceptional gain flatness and low differential gain and phase
errors, the CLC417 is very useful for professional video processing
and distribution. A 120MHz -3dB bandwidth coupled with a 400V/µs
slew rate also make the CLC417 a perfect choice in cost-sensitive
applications such as video monitors, fax machines, copiers, and
CATV systems. Back-terminated video applications will be
enhanced by a gain of +2 configuration which requires no external
gain components reducing costs and board space.
■
■
Frequency Response (AV = +2V/V)
Typical Application
Differential Input/Differential Output Amplifier
Pinout
DIP & SOIC
-5V
Vin2
0.1µF
6.8µF
OUT1
-IN1
+VCC
OUT2
-IN2
250Ω
250Ω
250Ω
250Ω
-
CLC417
Vout
2
+
+IN1
-VCC
250Ω
250Ω
-
Vin1
250Ω
250Ω
+
+IN2
Vout
1
6.8µF
0.1µF
+5V
Vout1 – Vout2 = (Vin1 – Vin2) x 2
© 1998 National Semiconductor Corporation
Printed in the U.S.A.
http://www.national.com
(A = +2, Vcc = + 5V, RL = 100Ω unless specified)
CLC417 Electrical Characteristics
V
PARAMETERS
Ambient Temperature
CONDITIONS
CLC417AJ
TYP
+25˚C
MIN/MAX RATINGS
0 to 70˚C -40 to 85˚C
UNITS
NOTES
+25˚C
FREQUENCY DOMAIN RESPONSE
-3dB bandwidth
V
V
out < 1.0Vpp
out < 5.0Vpp
120
52
50
85
40
15
65
36
60
35
MHz
MHz
MHz
1
±
0.1dB bandwidth
Vout < 1.0Vpp
gain flatness
peaking
V
out < 1.0Vpp
DC to 200MHz
<30MHz
<20MHz
4.43MHz, R =150Ω
4.43MHz, R =150Ω
0
0.05
0.3
0.01
0.03
0.5
0.5
0.6
0.04
0.08
0.6
0.65
0.7
0.04
0.11
0.8
0.7
0.7
0.04
0.12
dB
dB
deg
%
rolloff
linear phase deviation
differential gain
differential phase
L
L
deg
TIME DOMAIN RESPONSE
rise and fall time
settling time to 0.05%
overshoot
2V step
2V step
2V step
2V step
1V step
4.3
22
3
400
700
6.5
30
12
7.2
38
12
7.4
41
12
ns
ns
%
V/µs
V/µs
slew rate
Av = +2
Av = -1
300
260
250
DISTORTION AND NOISE RESPONSE
2nd harmonic distortion
3rd harmonic distortion
2nd harmonic distortion
3rd harmonic distortion
equivalent input noise
voltage
2Vpp, 1MHz
-80
-80
-66
-57
dBc
dBc
dBc
dBc
2Vpp, 1MHz
2Vpp, 10MHz
2Vpp, 10MHz
-55
-50
-50
-47
-47
-46
>1MHz
>1MHz
5
12
3
6.3
15
3.8
66
6.6
16
4.0
66
6.7
17
4.2
66
nV/√Hz
pA/√Hz
pA/√Hz
dB
inverting current
non-inverting current
crosstalk, input referred
>1MHz
2Vpp, 10MHz
72
STATIC DC PERFORMANCE
input offset voltage
average drift
input bias current
average drift
input bias current
1
30
100
3
5
900
5
7
50
1600
8
8
50
2800
11
mV
µV/˚C
nA
nA/˚C
µA
A
A
A
non-inverting
inverting
1
6
8
average drift
output offset voltage
amplifier gain error
17
2.5
0.1%
40
17.6
1.5%
45
19.6
1.5%
nA/˚C
mV
V/V
13.3
A,2
A
±
±1.5%
±
±
internal resistors (Rf, Rg)
power supply rejection ratio
common-mode rejection ratio
supply current per channel
250Ω
52
50
±
20%
47
45
4.5
DC
DC
RL= ∞
47
45
4.6
45
43
4.9
dB
dB
mA
3.9
A
MISCELLANEOUS PERFORMANCE
input resistance
input capacitance
non-inverting
non-inverting
6
1
±2.2
+4.0,-3.4
+3.5,-2.9
60
3
2
2.4
2
±1.7
+3.8,-3.2
+2.9,-2.7
38
1
2
±1.5
+3.7,-2.8
+2.4,-1.7
20
MΩ
pF
V
V
V
common mode input range
output voltage range
output voltage range
output current
±1.8
+3.9,-3.3
+3.1,-2.8
44
RL= ∞
RL= 100Ω
mA
Ω
output resistance, closed loop
0.06
0.2
0.25
0.4
+
Recommended gain range 1, +2 V/V
Transistor count = 110
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
Absolute Maximum Ratings
supply voltage
out is short circuit protected to ground
Notes
1) At temps < 0°C, spec is guaranteed for RL = 500Ω.
2) Source impedance 1kΩ.
±7V
I
A) J-level: spec is 100% tested at +25°C.
common-mode input voltage
maximum junction temperature
storage temperature range
lead temperature (soldering 10 sec)
ESD rating (human body model)
±
Vcc
+175°C
65 C to +150°C
˚
+300°C
2000V
Ordering Information
Package Thermal Resistance
Model
Temperature Range
Description
8-pin PDIP
8-pin SOIC
Package
Plastic (AJP)
Surface Mount (AJE)
θJC
θJA
CLC417AJP
CLC417AJE
-40 C to +85 C
°
°
80°C/W
95°C/W
95°C/W
115°C/W
-40 C to +85 C
°
°
http://www.national.com
2
(Vcc = ±5V, Av = +2, R = 100Ω; unless specified)
CLC417 Typical Performance Characteristics
L
Frequency Response
Frequency Response vs. CL
Frequency Response vs. RL
Av = 1
Vout = 1Vpp
Av = +2
Vout = 1Vpp
RL = 100 RL = 1k
Av = -1
Rs = 80.6Ω
CL = 10pf
Av = 2
RL = 50
Rs = 30.1Ω
CL = 100pf
RL = 1k
Av = 1
0
0
Rs = 7.7Ω
CL = 1000pf
-90
-90
Av = -1
RL = 50
Av = 2
-180
-270
-360
-450
-180
-270
-360
-450
RL = 100
1
10
100
1
10
100
1
10
100
Frequency (MHz)
Frequency (MHz)
Frequency (MHz)
Frequency Response vs. Vout (Av = +1)
Frequency Response vs. Vout (Av = -1)
Frequency Response vs. Vout (Av = +2)
Vo = 0.2Vpp
Vo = 2Vpp
Vo = 2Vpp
Vo = 0.2Vpp
Vo = 4Vpp
Vo = 2Vpp
Vo = 4Vpp
Vo = 0.2Vpp
Vo = 4Vpp
1
10
100
1
10
100
1
10
100
Frequency (MHz)
Frequency (MHz)
Frequency (MHz)
Equivalent Input Noise
Recommended Rs vs. Capacitive Load
Maximum Output Voltage vs. RL
100
10
1
100
4
2
100
80
60
40
20
0
Inverting Current = 12pA/√Hz
10
1
0
Voltage = 5nV/√Hz
Non-Inverting Current = 3pA/√Hz
-2
-4
100
1k
10k
100k
1M
10M
10
100
1000
0
100
200
300
400
500
600
CL (pF)
Frequency (Hz)
Load (Ω)
2nd & 3rd Harmonic Distoration
2nd Harmonic Distortion vs. Pout
3rd Harmonic Distortion vs. Pout
-40
-50
-40
-50
-60
-70
-80
-90
-55
-60
-65
-70
-75
-80
-85
-90
Po
50Ω
Po
50Ω
3rd, RL = 100Ω
10MHz
50Ω
Vo = 2Vpp
50Ω
10MHz
5MHz
348Ω
348Ω
348Ω
348Ω
-60
5MHz
-70
2nd, RL = 100Ω
2nd, RL = 1kΩ
-80
1MHz
1MHz
-90
500kHz
3rd, RL = 1kΩ
500kHz
-100
1
10
-10
-5
0
5
10
-10
-5
0
5
10
Frequency (MHz)
Output Power (dBm)
Output Power (dBm)
Large Signal Pulse Response
Small Signal Pulse Response
Differential Gain & Phase
2
1
0.08
0.06
0.04
0.02
0
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
0.40
0.35
0.30
0.25
0.20
0.15
0.01
0.05
0
Av = +1
Av = +2
Phase Negative Sync
0
Gain Negative
Sync
-0.02
-0.04
-0.06
-0.08
Phase
Positive
Sync
-1
-2
Av = -1
Gain Positive Sync
Time (5ns/div)
1
2
3
4
Time (5ns/div)
Number of 150Ω Loads
3
http://www.national.com
(Vcc = ±5V, Av = +2, R = 100Ω; unless specified)
CLC417 Typical Performance Characteristics
L
Typical DC Errors vs. Temperature
Power Derating Curves
PSRR and CMRR
6
5
4
3
2
1
60
50
40
30
20
10
1.0
0.8
1
PSRR
CMRR
IBN
0
AJP
AJE
0.6
0.4
-1
-2
-3
IBI
0.2
0
VIO
-50
0
50
100
0
20
40
60
80 100 120 140 160 180
10k
100k
1M
10M
100M
Temperature (°C)
Ambient Temperature (°C)
Frequency (Hz)
CLC417 OPERATION
Description
Non-Inverting Unity Gain Considerations
The CLC417 is a dual current feedback buffer with the
following features:
Gains of +1V/V are obtained by removing all resistive
and capacitive connections between the inverting
pins and ground on the CLC417 amplifiers. Too much
capacitive coupling between the inverting pin and ground
may cause stability problems. Minimize this capacitive
coupling by removing the ground plane near the
input and output pins. The response labeled open in
Figure 1 is the result of the inverting pin left open and all
capacitive coupling removed. A flatter response can be
■
Gains of +1, -1, and 2 are achievable without
external resistors
■
Differential gain and phase errors of 0.01%
and 0.03° into a 150Ω load
■
Low, 3.9mA, supply current per amplifier
The convenient 8-pin package and internal resistors
make common applications, like that seen on the front
page, easily feasible in a limited amount of space. The
professional video quality differential gain and phase
errors and low power capabilities of the CLC417 make
this product a good choice for video applications.
obtained by inserting
a
resistor between the
inverting and non-inverting pins as shown in Figure 2.
The two remaining plots in Figure 1 illustrate a 300Ω
resistor and a short connected between pins 2 and 3 of
the CLC417.
If gains other than +1, -1, or +2V/V are required, then the
CLC416 can be used. The CLC416 is a dual current
feedback amplifier with near identical performance, and
allows for external feedback and gain resistors.
Open
R = 300Ω
Short
Closed Loop Gain Selection
Gains of +1, +2, and -1V/V can be achieved by both of
the CLC417’s amplifiers. Implement the gain selection
by connecting the inverting (-IN) and non-inverting (+IN)
pins as described in the table below.
1
10
100
Input Connections
+IN
Gain
Frequency (MHz)
A
v
-IN
Figure 1: Frequency Response vs.
Unity Gain Configuration
-1V/V
+1V/V
+2V/V
ground
input signal
input signal
input signal
NC (open)
ground
Rout
SMA
Output1
250Ω
50Ω
The gain accuracy of the CLC417 is excellent and
stable over temperature. The internal feedback and gain
250Ω
-
+
R
setting resistors, R and R , are diffused silicon resistors.
f
g
SMA
Input1
250Ω
250Ω
R and R have a process variation of ±20% and a
-
f
g
temperature coefficient of ~ 2000ppm/°C. Although the
absolute values of R and R change with processing and
+
Rin
50Ω
f
g
NOTE: The same technique can also
be applied to Channel B. Bypass
capacitors not shown.
temperature, their ratio (R /R ) remains constant. If an
f
g
external resistor is used in series with R , gain accuracy
g
over temperature will be impacted by temperature coeffi-
cient differences between internal and external resistors.
Figure 2: Optional Unity Gain Configuration
http://www.national.com
4
Channel Matching
1. Determine the quiescent power
Channel matching and crosstalk efficiency are largely
dependent on board layout. The layout of National’s dual
amplifier evaluation boards are optimized to produce
maximum channel matching and isolation. Typical
channel matching for the CLC417 is shown in Figure 3.
•
P = (V - V ) I
Q
CC
EE
CC
2. Determine the RMS power at the output stage
= (V - V ) (I ), where V and I
load
P
O
CC
load
load
load
are the RMS voltage and current across the
external load.
3. Determine the total RMS power
P = P + P
T
Q
O
Av = +2
RL = 100Ω
Channel B
Vo = 2Vpp
Add the total RMS powers for both channels to determine
the power dissipated by the dual.
Channel A
Channel B
0
The maximum power that the package can dissipate at a
given temperature is illustrated in the Power Derating
curves in the Typical Performance section. The power
derating curve for any package can be derived by utiliz-
ing the following equation:
-90
Channel A
-180
-270
-360
-450
(175° − Tamb)
P =
1
10
100
Frequency (MHz)
θ
JA
where: T
= Ambient temperature (°C)
= Thermal resistance, from junction to
ambient, for a given package (°C/W)
amb
Figure 3: Channel Matching
θ
JA
The CLC417’s channel-to-channel isolation is better than
70dB for input frequencies of 4MHz. Input referred
crosstalk vs. frequency is illustrated in Figure 4.
Layout Considerations
A proper printed circuit layout is essential for achieving
high frequency performance. National provides
evaluation boards for the CLC417 (CLC730038 - DIP,
CLC730036 - SOIC) and suggests their use as a guide
for high frequency layout and as an aid for device testing
and characterization.
-20
-40
-60
-80
Supply bypassing is required for best performance. The
bypass capacitors provide a low impedance return
current path at the supply pins. They also provide high
frequency filtering on the power supply traces. Other
layout factors play a major role in high frequency
performance. The following are recommended as a basis
for high frequency layout:
-100
-120
1
10
100
Frequency (MHz)
1. Include 6.8µF tantalum and 0.1µF ceramic
Figure 4: Input Referred Crosstalk vs. Frequency
capacitors on both supplies.
Driving Cables and Capacitive Loads
2. Place the 6.8µF capacitors within 0.75 inches
When driving cables, double termination is used to
prevent reflections. For capacitive load applications, a
small series resistor at the output of the CLC417 will
of the power pins.
3. Place the 0.1µF capacitors less than 0.1
inches from the power pins.
improve stability.
The R vs. Capacitive Load
s
4. Remove the ground plane near the input
and output pins to reduce parasitic
capacitance.
plot, in the Typical Performance section, gives the
recommended series resistance value for optimum
flatness at various capacitive loads.
5. Minimize all trace lengths to reduce series
inductances.
Power Dissipation
The power dissipation of an amplifier can be described in
two conditions:
Additional information is included in the evaluation board
literature.
■
Quiescent Power Dissipation -
Special Evaluation Board Considerations
To optimize off-isolation of the CLC417, cut the R trace
on both the 730038 and 730036 evaluation boards. This
cut minimizes capacitive feedthrough between the input
P (No Load Condition)
Total Power Dissipation -
Q
f
■
P (with Load Condition)
T
The following steps can be taken to determine the power
consumption for each CLC417 amplifier:
and output. Figure
recommended to improve off-isolation.
5
indicates the alterations
5
http://www.national.com
730036 Top
Applications Circuits
+Vcc
OUT2
GND
Video Cable Driver
The CLC417 was designed to produce exceptional video
performance at all three closed-loop gains. A typical
cable driving configuration is shown in Figure 6. In this
example, the amplifier is configured with a gain of 2.
+
C3
ROUT2
C4
+
RG2
IN2
RF2
-Vcc
C1
OUT1
+5V
C2
ROUT1
0.1µF
6.8µF
RIN2
NOTE:
The same
technique can
also be applied
to Channel A.
250Ω
Rout
50Ω
250Ω
-
Video
RIN1
RF1
Output
+
RG1
Coax
J1
Comlinear
(970) 226-0500
50Ω
250Ω
50Ω
250Ω
-
0Ω
-5V
6.8µF
+
SMA
Input
IN1
0.1µF
Rin
50Ω
Cut traces here
Figure 6: Typical Cable Driver
Single to Differential Line Driver
730038 Bottom
The topology in Figure 7 accomplishes a single-ended to
differential conversion with no external components.
With this configuration, the value of Vin is limited to the
common mode input range of the CLC417.
+5V
0.1µF
6.8µF
Vout1
730038
REV B
250Ω
Vout2
250Ω
-
+
250Ω
250Ω
-
-5V
+
6.8µF
0.1µF
Vin
AV1 = 1V/V
AV2 = -1V/V
Vout1 = Vin
Vout2 = -Vin
Cut traces here
Figure 7: Single to Differential Line Driver
Figure 5: Optional Evaluation Board Alterations
SPICE Models
SPICE models provide a means to evaluate amplifier
designs. Free SPICE models are available for National’s
monolithic amplifiers that:
■
Support Berkeley SPICE 2G and its many
derivatives
■
Reproduce typical DC, AC, Transient, and
Noise performance
■
Support room temperature simulations
The readme file that accompanies the diskette lists
released models, and provides a list of modeled parame-
ters. The application note OA-18, Simulation SPICE
Models for National’s Op Amps, contains schematics and
a reproduction of the readme file.
http://www.national.com
6
This page intentionally left blank.
7
http://www.national.com
Customer Design Applications Support
National Semiconductor is committed to design excellence. For sales, literature and technical support, call the
National Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018.
Life Support Policy
National’s products are not authorized for use as critical components in life support devices or systems without the express written approval
of the president of National Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or
sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to
cause the failure of the life support device or system, or to affect its safety or effectiveness.
National Semiconductor
Corporation
National Semiconductor
Europe
National Semiconductor
Hong Kong Ltd.
National Semiconductor
Japan Ltd.
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
Fax: 1(800) 737-7018
Fax: (+49) 0-180-530 85 86
E-mail: europe.support.nsc.com
Deutsch Tel: (+49) 0-180-530 85 85
English Tel: (+49) 0-180-532 78 32
Francais Tel: (+49) 0-180-532 93 58
Italiano Tel: (+49) 0-180-534 16 80
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Tel: (852) 2737-1600
Fax: (852) 2736-9960
Tel: 81-043-299-2309
Fax: 81-043-299-2408
N
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said
circuitry and specifications.
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8
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