CLC5665IM [NSC]
Low Distortion Amplifier with Disable; 低失真放大器具有禁用
| 型号： | CLC5665IM |
| 厂家： | 
National Semiconductor |
| 描述： | Low Distortion Amplifier with Disable |
| 文件： | 总8页 (文件大小：123K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 1999
N
CLC5665
Low Distortion Amplifier with Disable
General Description
The CLC5665 is a low-cost, wideband amplifier that provides very
Features
■
0.1dB gain flatness to 20MHz (A = +2)
v
■
■
■
■
■
■
■
■
■
90MHz bandwidth (A = +1)
Large signal BW 25MHz
1800V/µs slew rate
0.05%/0.05° differential gain/phase
±5V, ±15V or single supplies
200ns disable to high-impedance output
Wide gain range
low 2nd and 3rd harmonic distortion at 1MHz (-89/-92dBc). The
v
great slew rate of 1800V/µs, bandwidth of 90MHz (A = +1) and
v
fast disable make it an excellent choice for many high speed
multiplexing applications. Like all current feedback op amps, the
CLC5665 allows the frequency response to be optimized
(or adjusted) by the selection of the feedback resistor. For
demanding video applications, the 0.1dB bandwidth to 20MHz
and differential gain/phase of 0.05%/0.05° make the CLC5665
the preferred component for broadcast quality NTSC and PAL
video systems.
-89/-92dBc HD2/HD3 (R = 500Ω)
L
Low cost
Applications
■
xDSL driver
■
Twisted pair driver
Cable driver
Video distribution
CCD clock driver
The large voltage swing (28V ), continuous output current
pp
■
(85mA) and slew rate (1800V/µs) provide high-fidelity signal
conditioning for applications such as CCDs, transmission lines
and low impedance circuits.
■
■
■
Multimedia systems
■
DAC output buffers
xDSL, video distribution, multimedia and general purpose
applications will benefit from the CLC5665’s wide bandwidth and
disable feature. Power is reduced and the output becomes a high
impedance when disabled. The wide gain range of the CLC5665
makes this general purpose op amp an improved solution for
circuits such as active filters, single-to-differential-ended drivers,
DAC transimpedance amplifiers and MOSFET drivers.
■
Imaging systems
Non-Inverting Frequency Response
Av = 1
Rf = 698
Gain
Av = 10
Rf = 100
Av = 2
Rf = 604
Phase
0
Av = 1
-45
-90
-135
-180
Av = 50
Av = 2
Av = 50
Rf = 500
Av = 10
1
10
100
Frequency (MHz)
DIS
Typical Application
Differential Line Driver for xDSL
Pinout
+
DIP & SOIC
+
CLC5665
-
Ro
NC
Vinv
1
2
3
4
8
7
6
5
DIS
Rf1
1:n
604Ω
-
+Vcc
Vout
NC
Rg
1.2kΩ
RL
Vin (Vpp
)
Vo = 2Vin
nVo
Rf2
+
Vnon-inv
-Vcc
604Ω
Ro
-
Note: Supply and Bypassing not shown.
CLC5665
-
+
DIS
© 1999 National Semiconductor Corporation
Printed in the U.S.A.
http://www.national.com
(VCC = ±15V, Av = +2V/V; Rf = 604Ω, RL = 100Ω; unless specified)
CLC5665 Electrical Characteristics
PARAMETERS
CONDITIONS
V
cc
TYP
MIN/MAX RATINGS
+25°C 0 to 70°C -40 to 85°C
UNITS NOTES
Ambient Temperature
CLC5665
+25°C
FREQUENCY DOMAIN RESPONSE
small-signal bandwidth (Av = +1) Vout < 1.0Vpp
±15
±15
±5
±15
±5
90
70
50
20
15
25
MHz
MHz
MHz
MHz
MHz
MHz
small-signal bandwidth
V
V
V
V
V
V
out < 1.0Vpp
out < 1.0Vpp
out < 1.0Vpp
out < 1.0Vpp
out = 10Vpp
out < 1.0Vpp
0.1dB bandwidth
large-signal bandwidth
gain flatness
peaking
rolloff
DC to 10MHz
DC to 20MHz
0.03
0.1
dB
dB
linear phase deviation
differential gain
DC to 20MHz
0.7
deg
%
%
deg
deg
4.43MHz, RL = 150Ω
4.43MHz, RL = 150Ω
4.43MHz, RL = 150Ω
4.43MHz, RL = 150Ω
±15
±5
±15
±5
0.05
0.05
0.05
0.1
differential phase
TIME DOMAIN RESPONSE
rise and fall time
2V step
10V step
2V step
2V step
20V step
5
10
35
5
1800
ns
ns
ns
%
V/µs
settling time to 0.05%
overshoot
slew rate
DISTORTION AND NOISE RESPONSE
2nd harmonic distortion
3rd harmonic distortion
input voltage noise
1Vpp,1MHz, RL = 500Ω
1Vpp,1MHz, RL = 500Ω
>1MHz
-89
-92
3.0
3.2
15
dBc
dBc
nV/√Hz
pA/√Hz
pA/√Hz
non-inverting input current noise >1MHz
inverting input current noise
>1MHz
DC PERFORMANCE
input offset voltage
average drift
input bias current
average drift
input bias current
average drift
power-supply rejection ratio
common-mode rejection ratio
supply current
±15
1.0
25
3
10
3
10
60
60
7.5
–
20
–
20
–
55
55
12
2.5
9.0
20
20
10.0
20
mV
µV/°C
µA
nA/°C
µA
nA/°C
dB
dB
A
A
A
non-inverting
inverting
±15, ±5
±15, ±5
20
DC
DC
RL = ∞
RL = ∞
50
50
14
2.5
50
50
15
2.5
±15, ±5 11, 8.5
±15, ±5
mA
mA
A
A
disabled
1.5
SWITCHING PERFORMANCE
turn on time
turn off time
off isolation
high input voltage
400
200
59
11.8
1.8
500
800
56
12.5
2.5
550
800
56
12.7
2.7
550
800
56
ns
ns
dB
V
(Note 2)
10MHz
VIH
±15
±5
V
low input voltage
VIL
±15
±5
10.8
0.8
10.5
0.6
10.0
0.1
V
V
MISCELLANEOUS PERFORMANCE
non-inverting input resistance
8.0
0.5
±12.5
±2.5
±14
±4.0
±85
3.0
1.0
±12.3
±2.3
±13.7
±3.9
±60
2.5
1.0
±12.1
±2.2
±13.7
±3.8
±50
1.7
1.0
±11.8
±1.9
±13.6
±3.7
±45
MΩ
pF
V
V
V
V
mA
non-inverting input capacitance
input voltage range
output voltage range
output current
common mode
±15
±5
±15
±5
common mode
RL = ∞
RL = ∞
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
Absolute Maximum Ratings
Notes
supply voltage
short circuit current
common-mode input voltage
maximum junction temperature
storage temperature range
lead temperature (soldering 10 sec)
±
16V
(see note 1)
VCC
A) J-level: spec is 100% tested at +25°C.
1) Output is short circuit protected to ground, however
maximum reliability is obtained if output current does not
exceed 125mA.
±
+150°C
-65°C to +150°C
+300°C
2) To >50dB attenuation @ 10MHz.
http://www.national.com
2
(VCC = ±15V, Av = +2V/V; Rf = 604Ω, RL = 100Ω; unless specified)
CLC5665 Typical Performance
Inverting Frequency Response
Frequency Response vs. Load
Non-Inverting Frequency Response
Gain
Av = -1
Rf = 500
Av = 1
Rf = 698
RL = 1k
Gain
Gain
RL = 50
Av = -10
Rf = 500
Av = 10
Rf = 100
RL = 100
RL = 1k
Av = 2
Phase
Av = -2
Rf = 500
Rf = 604
Phase
Phase
0
0
0
Av = 1
-45
-90
-135
-180
-45
-90
-135
-180
-45
-90
-135
-180
RL = 50
RL = 100
Av = -50
Av = 50
Av = -10
Av = -2
Av = 2
Av = -50
Rf = 2.5k
Av = 50
Rf = 500
Av = 10
Av = -1
1
10
100
1
10
100
1
10
100
Frequency (MHz)
Frequency (MHz)
Frequency (MHz)
Open-Loop Transimpedance Gain (Zs)
Flatness Gain and Linear Phase
Equivalent Input Noise
130
120
100
10
1
Gain
0
Gain
110
100
90
20
40
60
80
Inverting Current 14.8pA/√Hz
Phase
80
Phase
70
60
50
100
120
140
Non-Inverting Current 3.2pA/√Hz
Voltage 3.0nV/√Hz
40
30
160
0.0001 0.001
0.01
0.1
1
10
100
0
4
8
12
16
20
0.1k
1k
10k
100k
1M
10M
100M
Frequency (MHz)
Frequency (MHz)
Frequency (MHz)
Differential Gain and Phase (3.58MHz)
PSRR, CMRR and Closed Loop Ro
Signal Pulse Response
1
0.08
0.06
0.30
0.24
0.18
70
60
30
20
Large Signal
Small Signal
Gain Negative Sync
CMRR
PSRR
50
40
30
20
10
0
10
Phase
Positive Sync
0
-10
-20
-30
-40
0.04
0.02
0.12
0.06
Phase Negative Sync
20 log Ro
Gain Positive Sync
0
0.03
1
2
3
4
0.01
0.10
1
10
100
Time (20ns/div)
Number of 150Ω Loads
Frequency (MHz)
Short Term Settling Time
IBI, IBN. VOS vs. Temperature
2-Tone, 3rd Order Intermodulation Intercept
0.2
7.0
6.0
60
50
40
5.0
4.5
2V output step
0.15
5.0
4.0
3.0
2.0
4.0
3.5
3.0
2.5
0.1
0.05
0
Short Term
IBN
IBI
1.0
0
2.0
1.5
1.0
30
20
-0.05
VOS
50Ω
Pout
-0.1
-0.15
-0.2
50Ω
750Ω
-1.0
750Ω
-2.0
-3.0
0.5
0
10
Time (10ns/div)
-60
-20
20
60
100
140
106
107
Temperature (°C)
Frequency (MHz)
-1dBm Compression to Load
Harmonic Distortion vs. Frequency
Harmonic Distortion vs. Frequency
26
24
22
20
18
16
0
-10
-20
-30
-40
-50
0
-10
-20
-30
-40
-50
RL = 100Ω
Vout = 2Vpp
RL = 500Ω
Vout = 2Vpp
2nd
VCC = ±5V
2nd
VCC = ±5V
2nd
VCC = ±15V
2nd
VCC = ±15V
3rd
VCC = ±15V
14
12
-60
-70
-60
-70
Load
3rd
VCC = ±15V
50Ω
Vin
50Ω
10
8
-80
-90
-80
-90
698Ω
698Ω
3rd
VCC = ±5V
3rd
VCC = ±5V
6
-100
-100
0
5
10 15 20 25 30 35 40 45 50
1
10
100
1
10
100
Frequency (MHz)
Frequency (MHz)
Frequency (MHz)
3
http://www.national.com
V
±15V
>12.7V
<10.0V
±5V
>2.7V
<0.8V
CC
CLC5665 Design Considerations
Enable
Disable
The CLC5665 is a general purpose current-feedback
amplifier for use in a variety of small- and large-signal
applications. Use the feedback resistor to fine tune the
gain flatness and -3dB bandwidth for any gain setting.
National provides information for the performance at a
gain of +2 for small and large signal bandwidths. The
plots show feedback resistor values for selected gains.
The amplifier is enabled with pin 8 left open due to the
2kΩ pull-up resistor, shown in Figure 2.
+Vcc
2kΩ
Gain
To CLC5665
Bias network
Use the following equations to set the CLC5665’s non-
inverting or inverting gain:
R
f
Non−Inverting Gain = 1 +
8kΩ
R
g
-Vcc
-R
Pin 8 DISABLE
f
Inverting Gain =
R
g
Figure 2: Pin 8 Equivalent Disable Circuit
Choose the resistor values for non-inverting or inverting
gain by the following steps.
Open-collector or CMOS interfaces are recommended to
drive pin 8. The turn-on and off time depends on the
speed of the digital interface.
Vin
+
Rs
Vo
CLC5665
Rin
The equivalent output impedance when disabled is
-
shown in Figure 3. With R connected to ground, the sum
g
of R and R dominates and reduces the disabled output
f
g
Rf
impedance. To raise the output impedance in the dis-
abled state, connect the CLC5665 as a unity-gain
Rg
voltage follower by removing R . Current-feedback
g
op-amps need the recommended R in a unity-gain
Figure 1: Component Identification
f
follower circuit. For high density circuit layouts consider
using the dual CLC431 (with disable) or the dual CLC432
(without disable).
1) Select the recommended feedback resistor R .
f
2) Choose the value of R to set gain.
g
3) Select R to set the circuit output impedance.
s
Equivalent Impedance
in Disable
4) Select R for input impedance and input bias.
in
Vin
+
High Gains
300kΩ
Current feedback closed-loop bandwidth is independent
of gain-bandwidth-product for small gain changes. For
Vout
8pF
larger gain changes the optimum feedback register R is
-
f
derived by the following:
•
R = 724Ω – 60Ω (A )
f
v
Rf
Rg
As gain is increased, the feedback resistor allows band-
width to be held constant over a wide gain range. For a
more complete explanation refer to application note OA-25:
Stability Analysis of Current-Feedback Amplifiers.
1M
100k
10k
1k
Resistors have varying parasitics that affect circuit
performance in high-speed design. For best results, use
leaded metal-film resistors or surface mount resistors. A
SPICE model for the CLC5665 is available to simulate
overall circuit performance.
100
10
Enable/Disable Function
The CLC5665 amplifier features an enable/disable
function that changes the output and inverting input from
low to high impedance. The pin 8 enable/disable logic
levels are as follows:
1
1
10
100
Frequency (MHz)
Figure 3: Equivalent Disabled Output Impedance
http://www.national.com
4
2nd and 3rd Harmonic Distortion
+
Vin
AC
To meet low distortion requirements, recognize the effect
of the feedback resistor. Increasing the feedback
resistor will decrease the loop gain and increase
distortion. Decreasing the load impedance increases 3rd
harmonic distortion more than 2nd.
Vout
C
Rin
CLC5665
-
Vin
DC
Rf
R2
Rg
Differential Gain and Differential Phase
The CLC5665 has low DG and DP errors for video
applications. Add an external pulldown resistor to the
CLC5665’s output to improve DG and DP as seen in
Figure 5: Level Shifting Circuit
Multiplexing
Figure 4. A 604Ω R will improve DG and DP to 0.01%
p
Multiple signal switching is easily handled with the dis-
able function of the CLC5665. Board trace capacitance
at the output pin will affect the frequency response and
switching transients. To lessen the effects of output
and 0.02°.
Add Rp to
improve
DG and DP
Vin
capacitance place a resistor (R ) within the feedback
o
+
loop to isolate the outputs as shown in Figure 6.To match
the mux output impedance to a transmission line, add a
Vout
Rin
CLC5665
Rs
-
resistor (R ) in series with the output.
s
Rp
Rf
Rg
Rf
Rg
-
Ro
-Vcc
CLC5665
Vin1
+
Figure 4: Improved DG and DP Video Amplifier
Vout
Rs
DIS1
DIS2
Vin2
Rin
Printed Circuit Layout
+
Ro
RL
To get the best amplifier performance careful placement
of the amplifier, components and printed circuit traces
must be observed. Place the 0.1µF ceramic decoupling
capacitors less than 0.1” (3mm) from the power supply
pins. Place the 6.8µF tantalum capacitors less than
0.75” (20mm) from the power supply pins. Shorten traces
between the inverting pin and components to less
than 0.25” (6mm). Clear ground plane 0.1” (3mm) away
from pads and traces that connect to the inverting, non-
inverting and output pins. Do not place ground or power
plane beneath the op-amp package. National provides
literature and evaluation boards CLC730013 DIP or
CLC730027 SOIC illustrating the recommended op-amp
layout.
CLC5665
-
Rin
Rf
Rg
Figure 6: Output Connection for
Multiplexing Circuits
Differential Line Driver With Load
Impedance Conversion
The circuit shown in Figure 7, operates as a differential
line driver. The transformer converts the load impedance
to a value that best matches the CLC5665’s output
capabilities. The single-ended input signal is converted
to a differential signal by the CLC5665. The line’s
characteristic impedance is matched at both the input
and the output.The schematic shows Unshielded Twisted
Pair for the transmission line; other types of lines can also
be driven.
Applications Circuits
Level Shifting
The circuit shown in Figure 5 implements level shifting by
AC coupling the input signal and summing a DC voltage.
The resistor R and the capacitor C set the high-pass
in
break frequency. The amplifier closed-loop bandwidth is
fixed by the selection of R . The DC and AC gains for
Rg2
Rf2
f
circuit of Figure 5 are different. The AC gain is set by the
Vd/2
Vin
Rt1
+
ratio of R and R . And the DC gain is set by the parallel
f
g
Rm/2
Req
Io
CLC5665
-
1:n
-Vd/2
+
Vo
-
combination of R and R .
Zo
g
2
-
CLC5665
RL
Rf1
+
UTP
Rt2
Rm/2
Rg1
R
R
f
f
V
= V
1+
− V
inDC
out
inac
R
R
R
g
2
2
Figure 7: Differential Line Driver with
Load Impedance Conversion
5
http://www.national.com
Set up the CLC5665 as a difference amplifier. V is
determined by:
d
VinA
Rt1
VinB
Rt1
+
+
Z0
Rm1
Rm1
CLC5665
CLC5665
-
-
V
R
R
R
R
d
f1
f2
Rf1
Rf2
Rf1
Rf2
= 2 1+
= 2
Rg2
Rg2
V
in
g1
g2
-
-
Make the best use of the CLC5665’s output drive
capability as follows:
VoB
VoA
CLC5665
CLC5665
Rt2
Rt2
+
+
2 V
max
R
+R
=
eq
m
I
Figure 8: Full Duplex Cable Driver
is used to match the transmission line. R and R
g2
max
where R is the transformed value of the load imped-
R
eq
m1
f2
ance, V
is the Output Voltage Range, and I
is the
set the DC gain of the CLC5665, which is used in a
max
max
maximum Output Current.
difference mode. R provides good CMRR and DC
t2
offset. The transmitting CLC5665’s are shown in a unity
gain configuration because they consume the least
power of any gain, for a given load. For proper operation
we need R = R .
Match the line’s characteristic impedance:
R = Z
L
o
f2
g2
R
= R
eq
m
The receiver output voltages are:
R
L
n =
V
Z
(jω)
o(5665)
R
R
inB(A)
eq
f2
V
≈ V
A +
1−
+
outA(B)
inA(B)
2
R
R
m1
g2
Select the transformer so that it loads the line with a
where A is the attenuation of the cable, Z
(jω) is
value very near Z over frequency range. The output
o(5665)
o
the output impedance of the CLC5665, and |Z
(jω)|
impedance of the CLC5665 also affects the match. With
an ideal transformer we obtain:
o(5665)
<< R
.
m1
We selected the component values as follows:
2
n
Z
jω
o 5665
(
)
(
)
ReturnLoss = −20 log
,dB
10
■
R = 1.2kΩ, the recommended value for
f1
Z
o
CLC5665 at unity gain
■
R
= Z = 50Ω, the characteristic impedance
o
m1
where Z
(jω) is the output impedance of the
o(5665)
of the transmission line
CLC5665 and |Z
(jω)| << R .
m
■
o(5665)
R = R = 750Ω ≥ R , the recommended
f2 g2 m1
value for the CLC5665 at A = 2
v
The load voltage and current will fall in the ranges:
≤ n V
R
m1
■ R = (R ||R ) –
= 25Ω
t2
f2
g2
V
2
o
max
These values give excellent isolation from the other input:
I
max
I
≤
o
n
V
oA(B)
≈ −38dB, f = 5.0MHz
The CLC5665’s high output drive current and low
distortion make it a good choice for this application.
V
inB(A)
The CLC5665 provides large output current drive, while
consuming little supply current, at the nominal bias point.
It also produces low distortion with large signal swings
and heavy loads. These features make the CLC5665 an
excellent choice for driving transmission lines.
Full Duplex Cable Driver
The circuit shown in Figure 8 below, operates as a full
duplex cable driver which allows simultaneous transmis-
sion and reception of signals on one transmission line.
The circuit on either side of the transmission line uses are
CLC5665 as a cable driver, and the second CLC5665 as
a receiver. V is an attenuated version of V , while V
oA
inA
oB
is an attenuated version of V
.
inB
http://www.national.com
6
CCD Clock Driver
Reliability Information
Transistor Count
38
Vin
+
Rs
Vo
CL
CLC5665
RT
Package Thermal Resistance
Package
-
θJC
θJA
Voffset
Plastic (IN)
Surface Mount (IM)
65°C/W
50°C/W
130°C/W
145°C/W
R
Rf
Rg
Ordering Information
14
10
6
Model
Temperature Range
Description
CLC5665IN
CLC5665IM
CLC5665IMX
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
8-pin PDIP
8-pin SOIC
8-pin SOIC tape and reel
2
-2
-6
-10
-14
0
50
100
150
200
Frequency (ns)
Figure 9: CCD Clock Driver
7
http://www.national.com
Customer Design Applications Support
National Semiconductor is committed to design excellence. For sales, literature and technical support, call the
National Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018.
Life Support Policy
National’s products are not authorized for use as critical components in life support devices or systems without the express written approval of
the president of National Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or
sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to
cause the failure of the life support device or system, or to affect its safety or effectiveness.
National Semiconductor
Corporation
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
Fax: 1(800) 737-7018
National Semiconductor
Europe
National Semiconductor
Hong Kong Ltd.
2501 Miramar Tower
1-23 Kimberley Road
Tsimshatsui, Kowloon
Hong Kong
National Semiconductor
Japan Ltd.
Tel: 81-043-299-2309
Fax: (+49) 0-180-530 85 86
E-mail: europe.support.nsc.com
Deutsch Tel: (+49) 0-180-530 85 85
English Tel: (+49) 0-180-532 78 32
Francais Tel: (+49) 0-180-532 93 58
Italiano Tel: (+49) 0-180-534 16 80
Fax: 81-043-299-2408
N
Tel: (852) 2737-1600
Fax: (852) 2736-9960
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said
circuitry and specifications.
http://www.national.com
8
相关型号：
©2020 ICPDF网 联系我们和版权申明