DAC0830MDC [NSC]
IC PARALLEL, 8 BITS INPUT LOADING, 1 us SETTLING TIME, 8-BIT DAC, UUC, DIE, Digital to Analog Converter;
| 型号： | DAC0830MDC |
| 厂家： | 
National Semiconductor |
| 描述： | IC PARALLEL, 8 BITS INPUT LOADING, 1 us SETTLING TIME, 8-BIT DAC, UUC, DIE, Digital to Analog Converter 转换器 数模转换器 模数转换器 光电二极管 |
| 文件： | 总28页 (文件大小：554K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 2002
DAC0830/DAC0832
8-Bit µP Compatible, Double-Buffered D to A Converters
General Description
Features
n Double-buffered, single-buffered or flow-through digital
data inputs
The DAC0830 is an advanced CMOS/Si-Cr 8-bit multiplying
DAC designed to interface directly with the 8080, 8048,
8085, Z80®, and other popular microprocessors. A deposited
silicon-chromium R-2R resistor ladder network divides the
reference current and provides the circuit with excellent
temperature tracking characteristics (0.05% of Full Scale
Range maximum linearity error over temperature). The cir-
cuit uses CMOS current switches and control logic to
achieve low power consumption and low output leakage
current errors. Special circuitry provides TTL logic input volt-
age level compatibility.
n Easy interchange and pin-compatible with 12-bit
DAC1230 series
n Direct interface to all popular microprocessors
n Linearity specified with zero and full scale adjust
only—NOT BEST STRAIGHT LINE FIT.
±
n Works with 10V reference-full 4-quadrant multiplication
n Can be used in the voltage switching mode
n Logic inputs which meet TTL voltage level specs (1.4V
logic threshold)
n Operates “STAND ALONE” (without µP) if desired
n Available in 20-pin small-outline or molded chip carrier
package
Double buffering allows these DACs to output a voltage
corresponding to one digital word while holding the next
digital word. This permits the simultaneous updating of any
number of DACs.
The DAC0830 series are the 8-bit members of a family of
Key Specifications
n Current settling time: 1 µs
™
microprocessor-compatible DACs (MICRO-DAC ).
n Resolution: 8 bits
n Linearity: 8, 9, or 10 bits (guaranteed over temp.)
n Gain Tempco: 0.0002% FS/˚C
n Low power dissipation: 20 mW
n Single power supply: 5 to 15 VDC
Typical Application
00560801
™
™
BI-FET and MICRO-DAC are trademarks of National Semiconductor Corporation.
Z80® is a registered trademark of Zilog Corporation.
© 2002 National Semiconductor Corporation
DS005608
www.national.com
Connection Diagrams (Top Views)
Dual-In-Line and
Small-Outline Packages
00560821
Molded Chip Carrier Package
00560822
www.national.com
2
Absolute Maximum Ratings (Notes 1,
2)
Dual-In-Line Package (plastic)
Dual-In-Line Package (ceramic)
Surface Mount Package
Vapor Phase (60 sec.)
260˚C
300˚C
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
215˚C
220˚C
Infrared (15 sec.)
Supply Voltage (VCC
)
17 VDC
Voltage at Any Digital Input
Voltage at VREF Input
VCC to GND
Operating Conditions
Temperature Range
±
25V
T
MIN≤TA≤TMAX
0˚C to +70˚C
0˚C to +70˚C
0˚C to +70˚C
Storage Temperature Range
Package Dissipation
−65˚C to +150˚C
Part numbers with “LCN” suffix
Part numbers with “LCWM” suffix
Part numbers with “LCV” suffix
Part numbers with “LCJ” suffix
Part numbers with “LJ” suffix
Voltage at Any Digital Input
at TA=25˚C (Note 3)
500 mW
DC Voltage Applied to
−40˚C to +85˚C
−55˚C to +125˚C
VCC to GND
IOUT1 or IOUT2 (Note 4)
−100 mV to VCC
800V
ESD Susceptability (Note 4)
Lead Temperature (Soldering, 10 sec.)
Electrical Characteristics
VREF=10.000 VDC unless otherwise noted. Boldface limits apply over temperature, TMIN≤TA≤TMAX. For all other limits
TA=25˚C.
±
VCC = 5 VDC 5%
VCC = 4.75 VDC
VCC = 15.75 VDC
VCC = 12 VDC
±
5%
See
Limit
Units
±
to 15 VDC 5%
Parameter
Conditions
Note
Tested
Typ
Design
Limit
Limit
(Note 12)
(Note 5)
(Note 6)
CONVERTER CHARACTERISTICS
Resolution
8
8
8
bits
Linearity Error Max
Zero and full scale adjusted
4, 8
−10V≤VREF≤+10V
DAC0830LJ & LCJ
DAC0832LJ & LCJ
DAC0830LCN, LCWM &
LCV
0.05
0.2
0.05
0.2
% FSR
% FSR
% FSR
0.05
0.05
DAC0831LCN
DAC0832LCN, LCWM &
LCV
0.1
0.2
0.1
0.2
% FSR
% FSR
Differential Nonlinearity
Max
Zero and full scale adjusted
4, 8
−10V≤VREF≤+10V
DAC0830LJ & LCJ
DAC0832LJ & LCJ
DAC0830LCN, LCWM &
LCV
0.1
0.4
0.1
0.1
0.4
0.1
% FSR
% FSR
% FSR
DAC0831LCN
DAC0832LCN, LCWM &
LCV
0.2
0.4
0.2
0.4
% FSR
% FSR
Monotonicity
−10V≤VREF
≤+10V
LJ & LCJ
LCN, LCWM &
LCV
4
7
8
8
8
bits
bits
8
±
±
±
1
Gain Error Max
Using Internal Rfb
0.2
1
% FS
%
−10V≤VREF≤+10V
Gain Error Tempco Max Using internal Rfb
0.0002
0.0006
3
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Electrical Characteristics (Continued)
VREF=10.000 VDC unless otherwise noted. Boldface limits apply over temperature, TMIN≤TA≤TMAX. For all other limits
TA=25˚C.
±
VCC = 5 VDC 5%
VCC = 4.75 VDC
VCC = 15.75 VDC
VCC = 12 VDC
±
5%
See
Limit
Units
±
to 15 VDC 5%
Parameter
Conditions
Note
Tested
Typ
Design
Limit
Limit
(Note 12)
(Note 5)
(Note 6)
CONVERTER CHARACTERISTICS
FS/˚C
Power Supply Rejection All digital inputs latched high
VCC=14.5V to 15.5V
11.5V to 12.5V
4.5V to 5.5V
0.0002
0.0006
0.013
15
0.0025
%
FSR/V
0.015
20
Reference
Input
Max
Min
20
10
kΩ
kΩ
15
10
Output Feedthrough
Error
VREF=20 Vp-p, f=100 kHz
3
mVp-p
nA
All data inputs latched low
All data inputs LJ & LCJ
latched low LCN, LCWM &
LCV
Output
IOUT1
10
100
100
100
Leakage
Current Max
50
IOUT2
All data inputs LJ & LCJ
100
100
100
nA
latched high
LCN, LCWM &
LCV
50
Output
IOUT1
IOUT2
IOUT1
IOUT2
All data inputs
latched low
All data inputs
latched
45
115
130
30
pF
pF
Capacitance
high
DIGITAL AND DC CHARACTERISTICS
Digital Input
Voltages
Max
Logic Low
LJ: 4.75V
0.6
0.8
0.7
0.8
0.95
2.0
1.9
LJ: 15.75V
LCJ: 4.75V
LCJ: 15.75V
LCN, LCWM, LCV
LJ & LCJ
VDC
0.8
2.0
2.0
Min
Logic High
VDC
LCN, LCWM, LCV
<
Digital Input
Currents
Max
Digital inputs 0.8V
LJ & LCJ
LCN, LCWM, LCV
−50
−200
−200
−200
µA
µA
−160
>
Digital inputs 2.0V
LJ & LCJ
0.1
1.2
+10
+8
+10
+10
3.5
µA
LCN, LCWM, LCV
LJ & LCJ
Supply Current Max
Drain
3.5
1.7
mA
LCN, LCWM, LCV
2.0
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4
Electrical Characteristics
VREF=10.000 VDC unless otherwise noted. Boldface limits apply over temperature, TMIN≤TA≤TMAX. For all other limits
TA=25˚C.
VCC=12
VCC=5
±
VCC=15.75 VDC
VDC 5% to 15
V
CC=4.75 VDC
Tested
±
VDC 5%
±
VDC 5%
See
Limit
Units
Symbol
Parameter
Conditions
Note
Tested
Typ
Design
Limit
Design Limit
Typ
Limit
Limit
(Note 12)
(Note 5)
(Note 6)
(Note 12)
(Note 5) (Note 6)
AC CHARACTERISTICS
ts
Current Setting
VIL=0V,
1.0
1.0
µs
VIH=5V
Time
tW
Write and XFER
VIL=0V,
VIH=5V
11
100
100
250
375
600
Pulse Width Min
9
9
320
320
320
900
900
900
tDS
tDH
tCS
tCH
Data Setup Time VIL=0V,
250
375
600
VIH=5V
Min
320
900
Data Hold Time
VIL=0V,
VIH=5V
30
50
9
9
9
ns
Min
30
50
Control Setup
Time
VIL=0V,
VIH=5V
110
0
250
600
0
900
Min
320
320
10
1100
1100
Control Hold Time VIL=0V,
0
0
VIH=5V
Min
0
0
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
, θ , and the ambient temperature, T . The maximum
A
JMAX JA
allowable power dissipation at any temperature is P = (T
− T )/θ or the number given in the Absolute Maximum Ratings, whichever is lower. For this device,
A JA
D
JMAX
T
JMAX
= 125˚C (plastic) or 150˚C (ceramic), and the typical junction-to-ambient thermal resistance of the J package when board mounted is 80˚C/W. For the N
package, this number increases to 100˚C/W and for the V package this number is 120˚C/W.
Note 4: For current switching applications, both I and I must go to ground or the “Virtual Ground” of an operational amplifier. The linearity error is degraded
OUT1
OUT2
by approximately V
÷ V
. For example, if V
= 10V then a 1 mV offset, V , on I
or I
will introduce an additional 0.01% linearity error.
OUT2
OS
REF
REF
OS
OUT1
Note 5: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 6: Guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels.
±
±
1 V
Note 7: Guaranteed at V
=
10 V
and V
=
.
REF
DC
REF
DC
Note 8: The unit “FSR” stands for “Full Scale Range.” “Linearity Error” and “Power Supply Rejection” specs are based on this unit to eliminate dependence on a
particular V value and to indicate the true performance of the part. The “Linearity Error” specification of the DAC0830 is “0.05% of FSR (MAX)”. This guarantees
REF
that after performing a zero and full scale adjustment (see Sections 2.5 and 2.6), the plot of the 256 analog voltage outputs will each be within 0.05%xV
straight line which passes through zero and full scale.
of a
REF
Note 9: Boldface tested limits apply to the LJ and LCJ suffix parts only.
−9
3
Note 10: A 100nA leakage current with R =20k and V
=10V corresponds to a zero error of (100x10 x20x10 )x100/10 which is 0.02% of FS.
REF
fb
Note 11: The entire write pulse must occur within the valid data interval for the specified t , t , t , and t to apply.
W
DS DH
S
Note 12: Typicals are at 25˚C and represent most likely parametric norm.
Note 13: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
5
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Switching Waveform
00560802
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6
Definition of Package Pinouts
Control Signals
resistor for the external op amp which is used to
provide an output voltage for the DAC. This on-chip
resistor should always be used (not an external
resistor) since it matches the resistors which are
used in the on-chip R-2R ladder and tracks these
resistors over temperature.
(All control signals level actuated)
CS:
Chip Select (active low). The CS in combination
with ILE will enable WR1.
ILE:
Input Latch Enable (active high). The ILE in com-
bination with CS enables WR1.
WR1: Write 1. The active low WR1 is used to load the
digital input data bits (DI) into the input latch. The
data in the input latch is latched when WR1 is high.
To update the input latch–CS and WR1 must be low
while ILE is high.
VREF
:
Reference Voltage Input. This input connects an
external precision voltage source to the internal
R-2R ladder. VREF can be selected over the range
of +10 to −10V. This is also the analog voltage input
for a 4-quadrant multiplying DAC application.
WR2: Write 2 (active low). This signal, in combination with
XFER, causes the 8-bit data which is available in the
input latch to transfer to the DAC register.
VCC
:
Digital Supply Voltage. This is the power supply
pin for the part. VCC can be from +5 to +15VDC
Operation is optimum for +15VDC
.
XFER: Transfer control signal (active low). The XFER will
GND:
The pin 10 voltage must be at the same ground
potential as IOUT1 and IOUT2 for current switching
applications. Any difference of potential (VOS pin
10) will result in a linearity change of
enable WR2.
Other Pin Functions
DI0-DI7: Digital Inputs. DI0 is the least significant bit (LSB)
and DI7 is the most significant bit (MSB).
IOUT1
:
:
DAC Current Output 1. IOUT1 is a maximum for a
digital code of all 1’s in the DAC register, and is
zero for all 0’s in DAC register.
IOUT2
DAC Current Output 2. IOUT2 is a constant minus
For example, if VREF = 10V and pin 10 is 9mV offset from
IOUT1 and IOUT2 the linearity change will be 0.03%.
I
OUT1 , or IOUT1 + IOUT2 = constant (I full scale for a
fixed reference voltage).
±
Pin 3 can be offset 100mV with no linearity change, but the
Rfb
:
Feedback Resistor. The feedback resistor is pro-
vided on the IC chip for use as the shunt feedback
logic input threshold will shift.
Linearity Error
00560824
00560823
b) Best straight line
00560825
c) Shifting fs adj. to pass
best straight line test
a) End point test afterzero and fs
adj.
Definition of Terms
Resolution: Resolution is directly related to the number of
switches or bits within the DAC. For example, the DAC0830
has 28 or 256 steps and therefore has 8-bit resolution.
after a single full scale adjust. (One adjustment vs. multiple
iterations of the adjustment.) The “end point test’’ uses a
standard zero and F.S. adjustment procedure and is a much
more stringent test for DAC linearity.
Linearity Error: Linearity Error is the maximum deviation
from a straight line passing through the endpoints of the
DAC transfer characteristic. It is measured after adjusting for
zero and full-scale. Linearity error is a parameter intrinsic to
the device and cannot be externally adjusted.
Power Supply Sensitivity: Power supply sensitivity is a
measure of the effect of power supply changes on the DAC
full-scale output.
Settling Time: Settling time is the time required from a code
1
±
National’s linearity “end point test” (a) and the “best straight
line” test (b,c) used by other suppliers are illustrated above.
The “end point test’’ greatly simplifies the adjustment proce-
dure by eliminating the need for multiple iterations of check-
ing the linearity and then adjusting full scale until the linearity
is met. The “end point test’’ guarantees that linearity is met
transition until the DAC output reaches within
⁄2LSB of the
final output value. Full-scale settling time requires a zero to
full-scale or full-scale to zero output change.
Full Scale Error: Full scale error is a measure of the output
error between an ideal DAC and the actual device output.
7
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Monotonic: If the output of a DAC increases for increasing
digital input code, then the DAC is monotonic. An 8-bit DAC
which is monotonic to 8 bits simply means that increasing
digital input codes will produce an increasing analog output.
Definition of Terms (Continued)
Ideally, for the DAC0830 series, full scale is VREF −1LSB.
For VREF = 10V and unipolar operation, VFULL-SCALE
=
10,0000V–39mV 9.961V. Full-scale error is adjustable to
zero.
Differential Nonlinearity: The difference between any two
consecutive codes in the transfer curve from the theoretical
1 LSB to differential nonlinearity.
00560804
FIGURE 1. DAC0830 Functional Diagram
Typical Performance
Characteristics
Digital Input Threshold
vs. Temperature
Digital Input Threshold
Gain and Linearity Error
Variation vs. Temperature
vs. VCC
00560826
00560827
00560828
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8
Typical Performance Characteristics (Continued)
Gain and Linearity Error
Write Pulse Width
Variation vs. Supply Voltage
Data Hold Time
00560829
00560830
00560831
DAC0830 Series Application Hints
These DAC’s are the industry’s first microprocessor compat-
ible, double-buffered 8-bit multiplying D to A converters.
Double-buffering allows the utmost application flexibility from
a digital control point of view. This 20-pin device is also pin
for pin compatible (with one exception) with the DAC1230, a
12-bit MICRO-DAC. In the event that a system’s analog
output resolution and accuracy must be upgraded, substitut-
ing the DAC1230 can be easily accomplished. By tying
address bit A0 to the ILE pin, a two-byte µP write instruction
(double precision) which automatically increments the ad-
dress for the second byte write (starting with A0=“1”) can be
used. This allows either an 8-bit or the 12-bit part to be used
with no hardware or software changes. For the simplest 8-bit
application, this pin should be tied to VCC (also see other
uses in section 1.1).
The timing requirements and logic level convention of the
register control signals have been designed to minimize or
eliminate external interfacing logic when applied to most
popular microprocessors and development systems. It is
easy to think of these converters as 8-bit “write-only”
memory locations that provide an analog output quantity. All
inputs to these DAC’s meet TTL voltage level specs and can
also be driven directly with high voltage CMOS logic in
non-microprocessor based systems. To prevent damage to
the chip from static discharge, all unused digital inputs
should be tied to VCC or ground. If any of the digital inputs
are inadvertantly left floating, the DAC interprets the pin as a
logic “1”.
1.1 Double-Buffered Operation
Updating the analog output of these DAC’s in
a
Analog signal control versatility is provided by a precision
R-2R ladder network which allows full 4-quadrant multiplica-
tion of a wide range bipolar reference voltage by an applied
digital word.
double-buffered manner is basically a two step or double
write operation. In a microprocessor system two unique
system addresses must be decoded, one for the input latch
controlled by the CS pin and a second for the DAC latch
which is controlled by the XFER line. If more than one DAC
is being driven, Figure 2, the CS line of each DAC would
typically be decoded individually, but all of the converters
could share a common XFER address to allow simultaneous
updating of any number of DAC’s. The timing for this opera-
tion is shown, Figure 3.
1.0 DIGITAL CONSIDERATIONS
A most unique characteristic of these DAC’s is that the 8-bit
digital input byte is double-buffered. This means that the
data must transfer through two independently controlled 8-bit
latching registers before being applied to the R-2R ladder
network to change the analog output. The addition of a
second register allows two useful control features. First, any
DAC in a system can simultaneously hold the current DAC
data in one register (DAC register) and the next data word in
the second register (input register) to allow fast updating of
the DAC output on demand. Second, and probably more
important, double-buffering allows any number of DAC’s in a
system to be updated to their new analog output levels
simultaneously via a common strobe signal.
It is important to note that the analog outputs that will change
after a simultaneous transfer are those from the DAC’s
whose input register had been modified prior to the XFER
command.
9
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DAC0830 Series Application Hints (Continued)
00560835
*
TIE TO LOGIC 1 IF NOT NEEDED (SEE SEC. 1.1).
FIGURE 2. Controlling Mutiple DACs
00560836
FIGURE 3.
The ILE pin is an active high chip select which can be
decoded from the address bus as a qualifier for the normal
CS signal generated during a write operation. This can be
used to provide a higher degree of decoding unique control
signals for a particular DAC, and thereby create a more
efficient addressing scheme.
written to the DAC. This can be particularly useful in multi-
processing systems to allow a processor other than the one
controlling the DAC’s to take over control of the data bus and
control lines. If this second system were to use the same
addresses as those decoded for DAC control (but for a
different purpose) the ILE function would prevent the DAC’s
from being erroneously altered.
Another useful application of the ILE pin of each DAC in a
multiple DAC system is to tie these inputs together and use
this as a control line that can effectively “freeze” the outputs
of all the DAC’s at their present value. Pulling this line low
latches the input register and prevents new data from being
In a “Stand-Alone” system the control signals are generated
by discrete logic. In this case double-buffering can be con-
trolled by simply taking CS and XFER to a logic “0”, ILE to a
logic “1” and pulling WR1 low to load data to the input latch.
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10
DAC0830 Series Application Hints
(Continued)
Pulling WR2 low will then update the analog output. A logic
“1” on either of these lines will prevent the changing of the
analog output.
00560807
ILE=LOGIC “1”; WR2 and XFER GROUNDED
FIGURE 4.
1.2 Single-Buffered Operation
or erroneous data can be latched. This hold time is defined
as the length of time data must be held valid on the digital
inputs after a qualified (via CS) WR strobe makes a low to
high transition to latch the applied data.
In a microprocessor controlled system where maximum data
throughput to the DAC is of primary concern, or when only
one DAC of several needs to be updated at a time, a
single-buffered configuration can be used. One of the two
internal registers allows the data to flow through and the
other register will serve as the data latch.
If the controlling device or system does not inherently meet
these timing specs the DAC can be treated as a slow
memory or peripheral and utilize a technique to extend the
write strobe. A simple extension of the write time, by adding
a wait state, can simultaneously hold the write strobe active
and data valid on the bus to satisfy the minimum WR pulse-
width. If this does not provide a sufficient data hold time at
the end of the write cycle, a negative edge triggered
one-shot can be included between the system write strobe
and the WR pin of the DAC. This is illustrated in Figure 5 for
an exemplary system which provides a 250ns WR strobe
time with a data hold time of less than 10ns.
Digital signal feedthrough (see Section 1.5) is minimized if
the input register is used as the data latch. Timing for this
mode is shown in Figure 4.
Single-buffering in a “stand-alone” system is achieved by
strobing WR1 low to update the DAC with CS, WR2 and
XFER grounded and ILE tied high.
1.3 Flow-Through Operation
Though primarily designed to provide microprocessor inter-
face compatibility, the MICRO-DAC’s can easily be config-
ured to allow the analog output to continuously reflect the
state of an applied digital input. This is most useful in appli-
cations where the DAC is used in a continuous feedback
control loop and is driven by a binary up-down counter, or in
function generation circuits where a ROM is continuously
providing DAC data.
The proper data set-up time prior to the latching edge (LO to
HI transition) of the WR strobe, is insured if the WR pulse-
width is within spec and the data is valid on the bus for the
duration of the DAC WR strobe.
1.5 Digital Signal Feedthrough
When data is latched in the internal registers, but the digital
inputs are changing state, a narrow spike of current may flow
out of the current output terminals. This spike is caused by
the rapid switching of internal logic gates that are responding
to the input changes.
Simply grounding CS, WR1, WR2, and XFER and tying ILE
high allows both internal registers to follow the applied digital
inputs (flow-through) and directly affect the DAC analog
output.
There are several recommendations to minimize this effect.
When latching data in the DAC, always use the input register
as the latch. Second, reducing the VCC supply for the DAC
from +15V to +5V offers a factor of 5 improvement in the
magnitude of the feedthrough, but at the expense of internal
logic switching speed. Finally, increasing CC (Figure 8) to a
value consistent with the actual circuit bandwidth require-
ments can provide a substantial damping effect on any
output spikes.
1.4 Control Signal Timing
When interfacing these MICRO-DAC to any microprocessor,
there are two important time relationships that must be con-
sidered to insure proper operation. The first is the minimum
WR strobe pulse width which is specified as 900 ns for all
valid operating conditions of supply voltage and ambient
temperature, but typically a pulse width of only 180ns is
adequate if VCC=15VDC. A second consideration is that the
guaranteed minimum data hold time of 50ns should be met
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DAC0830 Series Application Hints (Continued)
00560808
FIGURE 5. Accommodating a High Speed System
2.0 ANALOG CONSIDERATIONS
The digital input code to the DAC simply controls the position
of the SPDT current switches and steers the available ladder
current to either IOUT1 or IOUT2 as determined by the logic
input level (“1” or “0”) respectively, as shown in Figure 6. The
MOS switches operate in the current mode with a small
voltage drop across them and can therefore switch currents
of either polarity. This is the basis for the 4-quadrant multi-
plying feature of this DAC.
The fundamental purpose of any D to A converter is to
provide an accurate analog output quantity which is repre-
sentative of the applied digital word. In the case of the
DAC0830, the output, IOUT1, is a current directly proportional
to the product of the applied reference voltage and the digital
input word. For application versatility, a second output,
IOUT2, is provided as a current directly proportional to the
complement of the digital input. Basically:
2.2 Basic Unipolar Output Voltage
To maintain linearity of output current with changes in the
applied digital code, it is important that the voltages at both
of the current output pins be as near ground potential (0VDC
)
as possible. With VREF=+10V every millivolt appearing at
either IOUT1 or IOUT2 will cause a 0.01% linearity error. In
most applications this output current is converted to a volt-
age by using an op amp as shown in Figure 7.
where the digital input is the decimal (base 10) equivalent of
the applied 8-bit binary word (0 to 255), VREF is the voltage
at pin 8 and 15 kΩ is the nominal value of the internal
resistance, R, of the R-2R ladder network (discussed in
Section 2.1).
The inverting input of the op amp is a “virtual ground” created
by the feedback from its output through the internal 15 kΩ
resistor, Rfb. All of the output current (determined by the
digital input and the reference voltage) will flow through Rfb
to the output of the amplifier. Two-quadrant operation can be
obtained by reversing the polarity of VREF thus causing IOUT1
to flow into the DAC and be sourced from the output of the
amplifier. The output voltage, in either case, is always equal
to IOUT1xRfb and is the opposite polarity of the reference
voltage.
Several factors external to the DAC itself must be consid-
ered to maintain analog accuracy and are covered in subse-
quent sections.
2.1 The Current Switching R-2R Ladder
The analog circuitry, Figure 6, consists of a silicon-chromium
(SiCr or Si-chrome) thin film R-2R ladder which is deposited
on the surface oxide of the monolithic chip. As a result, there
are no parasitic diode problems with the ladder (as there
may be with diffused resistors) so the reference voltage,
The reference can be either a stable DC voltage source or
an AC signal anywhere in the range from −10V to +10V. The
DAC can be thought of as a digitally controlled attenuator:
the output voltage is always less than or equal to the applied
reference voltage. The VREF terminal of the device presents
a nominal impedance of 15 kΩ to ground to external circuitry.
VREF, can range −10V to +10V even if VCC for the device is
5VDC
.
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12
DAC0830 Series Application Hints
(Continued)
Always use the internal Rfb resistor to create an output
voltage since this resistor matches (and tracks with tempera-
ture) the value of the resistors used to generate the output
current (IOUT1).
00560837
FIGURE 6.
00560838
FIGURE 7.
2.3 Op Amp Considerations
2.4 Bipolar Output Voltage with a Fixed Reference
The op amp used in Figure 7 should have offset voltage
nulling capability (See Section 2.5).
The addition of a second op amp to the previous circuitry can
be used to generate a bipolar output voltage from a fixed
reference voltage. This, in effect, gives sign significance to
the MSB of the digital input word and allows two-quadrant
multiplication of the reference voltage. The polarity of the
reference can also be reversed to realize full 4-quadrant
The selected op amp should have as low a value of input
bias current as possible. The product of the bias current
times the feedback resistance creates an output voltage
error which can be significant in low reference voltage appli-
±
±
±
multiplication: VREFx Digital Code= VOUT. This circuit is
shown in Figure 9.
™
cations. BI-FET op amps are highly recommended for use
with these DACs because of their very low input current.
This configuration features several improvements over exist-
ing circuits for bipolar outputs with other multiplying DACs.
Only the offset voltage of amplifier 1 has to be nulled to
preserve linearity of the DAC. The offset voltage error of the
second op amp (although a constant output voltage error)
has no effect on linearity. It should be nulled only if absolute
output accuracy is required. Finally, the values of the resis-
tors around the second amplifier do not have to match the
internal DAC resistors, they need only to match and tem-
perature track each other. A thin film 4-resistor network
available from Beckman Instruments, Inc. (part no.
694-3-R10K-D) is ideally suited for this application. These
resistors are matched to 0.1% and exhibit only 5 ppm/˚C
resistance tracking temperature coefficient. Two of the four
available 10 kΩ resistors can be paralleled to form R in
Figure 9 and the other two can be used independently as the
resistances labeled 2R.
Transient response and settling time of the op amp are
important in fast data throughput applications. The largest
stability problem is the feedback pole created by the feed-
back resistance, Rfb, and the output capacitance of the DAC.
This appears from the op amp output to the (−) input and
includes the stray capacitance at this node. Addition of a
lead capacitance, CC in Figure 8, greatly reduces overshoot
and ringing at the output for a step change in DAC output
current.
Finally, the output voltage swing of the amplifier must be
greater than VREF to allow reaching the full scale output
voltage. Depending on the loading on the output of the
±
amplifier and the available op amp supply voltages (only 12
volts in many development systems), a reference voltage
less than 10 volts may be necessary to obtain the full analog
output voltage range.
13
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This is accomplished for the typical DAC — op amp con-
nection (Figure 7) by shorting out Rfb, the amplifier feedback
resistor, and adjusting the VOS nulling potentiometer of the
op amp until the output reads zero volts. This is done, of
course, with an applied digital code of all zeros if IOUT1 is
driving the op amp (all one’s for IOUT2). The short around Rfb
is then removed and the converter is zero adjusted.
DAC0830 Series Application Hints
(Continued)
2.5 Zero Adjustment
For accurate conversions, the input offset voltage of the
output amplifier must always be nulled. Amplifier offset errors
create an overall degradation of DAC linearity.
The fundamental purpose of zeroing is to make the voltage
appearing at the DAC outputs as near 0VDC as possible.
00560839
ts
(O to Full Scale)
4 µs
OP Amp
LF356
CC
22 pF
22 pF
10 pF
LF351
LF357
5 µs
*
2 µs
*2.4 kΩ RESISTOR ADDED FROM−INPUT TO GROUND TO
INSURE STABILITY
FIGURE 8.
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14
DAC0830 Series Application Hints (Continued)
00560840
Input Code
IDEAL VOUT
MSB
LSB
+VREF
−VREF
1
1
1
0
0
0
1
1
0
1
0
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
*THESE RESISTORS ARE AVAILABLE FROM BECKMAN INSTRUMENTS, INC. AS THEIR PART NO. 694-3-R10K-D
FIGURE 9.
2.6 Full-Scale Adjustment
In the case where the matching of Rfb to the R value of the
error temperature coefficent would be degraded a maximum
of 0.0025%/˚C for an adjustment pot setting of less than 3%
of Rfb.
±
R-2R ladder (typically 0.2%) is insufficient for full-scale
accuracy in a particular application, the VREF voltage can be
adjusted or an external resistor and potentiometer can be
added as shown in Figure 10 to provide a full-scale adjust-
ment.
2.7 Using the DAC0830 in a Voltage Switching
Configuration
The R-2R ladder can also be operated as a voltage switch-
ing network. In this mode the ladder is used in an inverted
manner from the standard current switching configuration.
The reference voltage is connected to one of the current
output terminals (IOUT1 for true binary digital control, IOUT2 is
for complementary binary) and the output voltage is taken
from the normal VREF pin. The converter output is now a
voltage in the range from 0V to 255/256 VREF as a function
of the applied digital code as shown in Figure 11.
The temperature coefficients of the resistors used for this
adjustment are of an important concern. To prevent degra-
dation of the gain error temperature coefficient by the exter-
nal resistors, their temperature coefficients ideally would
have to match that of the internal DAC resistors, which is a
highly impractical constraint. For the values shown in Figure
10, if the resistor and the potentiometer each had a tempera-
±
ture coefficient of 100 ppm/˚C maximum, the overall gain
15
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DAC0830 Series Application Hints (Continued)
00560811
FIGURE 10. Adding Full-Scale Adjustment
00560812
FIGURE 11. Voltage Mode Switching
This configuration offers several useful application advan-
tages. Since the output is a voltage, an external op amp is
not necessarily required but the output impedance of the
DAC is fairly high (equal to the specified reference input
resistance of 10 kΩ to 20 kΩ) so an op amp may be used for
buffering purposes. Some of the advantages of this mode
are illustrated in Figures 12, 13, 14, 15.
There are two important things to keep in mind when using
this DAC in the voltage switching mode. The applied refer-
ence voltage must be positive since there are internal para-
sitic diodes from ground to the IOUT1 and IOUT2 terminals
which would turn on if the applied reference went negative.
There is also a dependence of conversion linearity and gain
error on the voltage difference between VCC and the voltage
applied to the normal current output terminals. This is a
result of the voltage drive requirements of the ladder
switches. To ensure that all 8 switches turn on sufficiently (so
as not to add significant resistance to any leg of the ladder
and thereby introduce additional linearity and gain errors) it
is recommended that the applied reference voltage be kept
less than +5VDC and VCC be at least 9V more positive than
00560841
•
•
Voltage switching mode eliminates output signal inver-
sion and therefore a need for a negative power supply.
VREF. These restrictions ensure less than 0.1% linearity and
Zero code output voltage is limited by the low level output
saturation voltage of the op amp. The 2 kΩ pull-down
resistor helps to reduce this voltage.
gain error change. Figures 16, 17, 18 characterize the ef-
fects of bringing VREF and VCC closer together as well as
typical temperature performance of this voltage switching
configuration.
•
VOS of the op amp has no effect on DAC linearity.
FIGURE 12. Single Supply DAC
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16
DAC0830 Series Application Hints (Continued)
00560842
FIGURE 13. Obtaining a Bipolar Output from a Fixed Reference with a Single Op Amp
00560860
FIGURE 14. Bipolar Output with Increased Output Voltage Swing
17
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DAC0830 Series Application Hints (Continued)
00560814
FIGURE 15. Single Supply DAC with Level Shift and Span- Adjustable Output
Gain and Linearity Error
Gain and Linearity Error
Variation vs. Supply Voltage
Variation vs. Reference Voltage
00560832
Note: For these curves, V
is the voltage applied to pin 11 (I
) with
OUT1
REF
00560833
pin 12 (I
) grounded.
OUT2
FIGURE 17.
FIGURE 16.
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18
During power-up supply voltage sequencing, the −15V (or
−12V) supply of the op amp may appear first. This will cause
the output of the op amp to bias near the negative supply
potential. No harm is done to the DAC, however, as the
on-chip 15 kΩ feedback resistor sufficiently limits the current
flow from IOUT1 when this lead is internally clamped to one
diode drop below ground.
DAC0830 Series Application Hints
(Continued)
Gain and Linearity Error
Variation vs. Temperature
Careful circuit construction with minimization of lead lengths
around the analog circuitry, is a primary concern. Good high
frequency supply decoupling will aid in preventing inadvert-
ant noise from appearing on the analog output.
Overall noise reduction and reference stability is of particular
concern when using the higher accuracy versions, the
DAC0830 and DAC0831, or their advantages are wasted.
3.0 GENERAL APPLICATION IDEAS
The connections for the control pins of the digital input
registers are purposely omitted. Any of the control formats
discussed in Section 1 of the accompanying text will work
with any of the circuits shown. The method used depends on
the overall system provisions and requirements.
00560834
The digital input code is referred to as D and represents the
decimal equivalent value of the 8-bit binary input, for ex-
ample:
FIGURE 18.
Binary Input
D
2.8 Miscellaneous Application Hints
Pin 13
MSB
Pin 7
LSB
Decimal
These converters are CMOS products and reasonable care
should be exercised in handling them to prevent catastrophic
failures due to static discharge.
Equivalent
1
1
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
1
0
0
1
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
255
128
16
2
Conversion accuracy is only as good as the applied refer-
ence voltage so providing a stable source over time and
temperature changes is an important factor to consider.
0
0
1
0
A “good” ground is most desirable. A single point ground
distribution technique for analog signals and supply returns
keeps other devices in a system from affecting the output of
the DACs.
0
19
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Applications
DAC Controlled Amplifier (Volume Control)
00560843
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20
Applications (Continued)
Capacitance Multiplier
00560844
21
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Applications (Continued)
Variable fO, Variable QO, Constant BW Bandpass Filter
00560817
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22
Applications (Continued)
DAC Controlled Function Generator
00560818
23
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Applications (Continued)
Two Terminal Floating 4 to 20 mA Current Loop Controller
00560819
•
DAC0830 linearly controls the current flow from the input terminal to the output terminal to be 4 mA (for D=0) to 19.94 mA (for
D=255).
•
•
•
Circuit operates with a terminal voltage differential of 16V to 55V.
P2 adjusts the magnitude of the output current and P1 adjusts the zero to full scale range of output current.
Digital inputs can be supplied from a processor using opto isolators on each input or the DAC latches can flow-through
(connect control lines to pins 3 and 10 of the DAC) and the input data can be set by SPST toggle switches to ground (pins 3
and 10).
DAC Controlled Exponential Time Response
00560820
•
Output responds exponentially to input changes and automatically stops when VOUT=VIN
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24
Applications (Continued)
•
•
Output time constant is directly proportional to the DAC input code and capacitor C
Input voltage must be positive (See section 2.7)
Ordering Information
Temperature Range
0˚C to +70˚
−40˚C to +85˚C −55˚C to +125˚C
0.05%
FSR
DAC0830LCN
DAC0830LCWM
DAC0830LCV
DAC0830LCJ
DAC0830LJ
Non
Linearity
0.1% FSR
0.2% FSR
DAC0831LCN
DAC0832LCN
N20A—Molded
DIP
DAC0832LCWM
DAC0832LCV
DAC0832LCJ
DAC0832LJ
Package Outline
M20B Small Outline
V20A Chip Carrier
J20A—Ceramic DIP
25
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Physical Dimensions inches (millimeters) unless otherwise noted
Ceramic Dual-In-Line Package (J)
Order Number DAC0830LCJ,
DAC0830LJ, DAC0832LJ or DAC0832LCJ
NS Package Number J20A
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26
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Molded Small Outline Package (M)
Order Number DAC0830LCWM
or DAC0832LCWM
NS Package Number M20B
Molded Dual-In-Line Package (N)
Order Number DAC0830LCN,
or DAC0832LCN
NS Package Number N20A
27
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Molded Chip Carrier (V)
Order Number DAC0830LCV
or DAC0832LCV
NS Package Number V20A
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1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
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Corporation
Americas
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Response Group
Tel: 65-2544466
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
相关型号：
DAC0832LCD
IC PARALLEL, 8 BITS INPUT LOADING, 1 us SETTLING TIME, 8-BIT DAC, CDIP20, D20A, Digital to Analog Converter
NSC
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