DM74163N [NSC]
Synchronous 4-Bit Counters; 同步4位计数器
| 型号： | DM74163N |
| 厂家： | 
National Semiconductor |
| 描述： | Synchronous 4-Bit Counters |
| 文件： | 总10页 (文件大小：179K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 1992
DM54161/DM74161/DM74163
Synchronous 4-Bit Counters
General Description
These synchronous, presettable counters feature an inter-
nal carry look-ahead for application in high-speed counting
designs. The 161 and 163 are 4-bit binary counters. The
carry output is decoded by means of a NOR gate, thus pre-
venting spikes during the normal counting mode of opera-
tion. Synchronous operation is provided by having all flip-
flops clocked simultaneously so that the outputs change co-
incident with each other when so instructed by the count-
enable inputs and internal gating. This mode of operation
eliminates the output counting spikes which are normally
associated with asynchronous (ripple clock) counters. A
buffered clock input triggers the four flip-flops on the rising
(positive-going) edge of the clock input waveform.
external NAND gate. The gate output is connected to the
clear input to synchronously clear the counter to all low out-
puts. Low-to-high transitions at the clear input of the 163 are
also permissible, regardless of the logic levels on the clock,
enable, or load inputs.
The carry look-ahead circuitry provides for cascading coun-
ters for n-bit synchronous applications without additional
gating. Instrumental in accomplishing this function are two
count-enable inputs and a ripple carry output. Both count-
enable inputs (P and T) must be high to count, and input T is
fed forward to enable the ripple carry output. The ripple car-
ry output thus enabled will produce a high-level output pulse
with a duration approximately equal to the high-level portion
These counters are fully programmable; that is, the outputs
may be preset to either level. As presetting is synchronous,
setting up a low level at the load input disables the counter
and causes the outputs to agree with the setup data after
the next clock pulse, regardless of the levels of the enable
input. The clear function for the 161 is asynchronous; and a
low level at the clear input sets all four of the flip-flop out-
puts low, regardless of the levels of clock, load, or enable
inputs. The clear function for the 163 is synchronous; and a
low level at the clear input sets all four of the flip-flop out-
puts low after the next clock pulse, regardless of the levels
of the enable inputs. This synchronous clear allows the
count length to be modified easily, as decoding the maxi-
mum count desired can be accomplished with one
of the Q output. This high-level overflow ripple carry pulse
A
can be used to enable successive cascaded stages. High-
to-low-level transitions at the enable P or T inputs of the 161
through 163 may occur, regardless of the logic level on the
clock.
Features
Y
Synchronously programmable
Y
Internal look-ahead for fast counting
Y
Carry output for n-bit cascading
Y
Synchronous counting
Y
Load control line
Y
Diode-clamped inputs
Connection Diagram
Dual-In-Line Package
TL/F/6551–1
Order Number DM54161J, DM54161W,
DM74161N or DM74163N
See NS Package Number J16A, N16E or W16A
C
1995 National Semiconductor Corporation
TL/F/6551
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Note: The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.
Supply Voltage
Input Voltage
7V
5.5V
Operating Free Air Temperature Range
DM54
DM74
b
b
a
55 C to 125 C
§
0 C to 70 C
§
a
§
§
a
65 C to 150 C
Storage Temperature Range
§
§
Recommended Operating Conditions
DM54161
DM74161 and 163
Symbol
Parameter
Units
Min
4.5
2
Nom
Max
Min
Nom
Max
V
V
V
Supply Voltage
5
5.5
4.75
2
5
5.25
V
V
CC
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
Low Level Output Current
Clock Frequency (Note 6)
IH
0.8
0.8
V
IL
b
0.8
16
b
I
I
0.8
mA
mA
MHz
OH
OL
16
f
0
25
0
25
CLK
W
t
Pulse Width
(Note 6)
Clock
25
20
20
34
25
20
0
25
20
20
34
25
20
0
ns
Clear
t
SU
Setup Time
(Note 6)
Data
Enable P
Load
ns
ns
Clear (Note 5)
t
H
Hold Time (Note 6)
b
T
A
Free Air Operating Temperature
55
125
0
70
C
§
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol
Parameter
Conditions
Min
Max
Units
(Note 1)
e
e
e b
e
b
1.5
V
V
Input Clamp Voltage
V
Min, I
Min, I
12 mA
V
V
I
CC
I
High Level Output
Voltage
V
V
Max
Min
OH
CC
OH
2.4
3.4
0.2
e
e
Max, V
IL
IH
e
e
V
OL
Low Level Output
Voltage
V
V
Min, I
Max
CC
OL
0.4
V
e
e
Min, V
Max
IH
IL
@
Input Current Max
e
e
I
I
I
V
Max, V
5.5V
I
CC
1
mA
Input Voltage
e
High Level Input
Current
V
V
Max
Enable T
Clock
80
80
40
IH
CC
e
2.4V
mA
I
Others
Enable T
Clock
e
b
I
IL
Low Level Input
Current
V
V
Max
3.2
3.2
1.6
CC
e
b
b
0.4V
mA
I
Others
2
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted) (Continued)
Typ
Symbol
Parameter
Conditions
Min
Max
Units
(Note 1)
e
CC
b
b
b
b
I
I
I
Short Circuit
V
Max
DM54
DM74
DM54
DM74
DM54
DM74
20
20
57
57
OS
mA
Output Current
(Note 2)
e
V
CC
Supply Current
Max
85
CCH
CCL
mA
mA
with Outputs High
(Note 3)
59
63
94
91
e
(Note 4)
Supply Current
V
CC
Max
with Outputs Low
101
e
e
25 C.
Note 1: All typicals are at V
5V, T
§
Note 2: Not more than one output should be shorted at a time.
CC
A
Note 3: I
Note 4: I
is measured with the LOAD high, then again with the LOAD low, with all inputs high and all outputs open.
is measured with the CLOCK high, then again with the CLOCK input low, with all inputs low and all outputs open.
CCH
CCL
Note 5: Applies to 163 which has synchronous clear inputs.
e
e
5V.
Note 6: T
25 C and V
§
A
CC
e
e
25 C (See Section 1 for Test Waveforms and Output Load)
Switching Characteristics at V
5V and T
§
CC
A
e
e
L
R
400X, C
15 pF
Max
From (Input)
To (Output)
L
Symbol
Parameter
Units
Min
f
t
t
t
t
t
t
t
t
t
Maximum Clock
Frequency
MAX
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PHL
25
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Propagation Delay Time
Low to High Level Output
Clock to
35
35
20
23
25
29
16
16
38
Ripple Carry
Propagation Delay Time
High to Low Level Output
Clock to
Ripple Carry
Propagation Delay Time
Low to High Level Output
Clock
(Load High) to Q
Propagation Delay Time
High to Low Level Output
Clock
(Load High) to Q
Propagation Delay Time
Low to High Level Output
Clock
(Load Low) to Q
Propagation Delay Time
High to Low Level Output
Clock
(Load Low) to Q
Propagation Delay Time
Low to High Level Output
Enable T to
Ripple Carry
Propagation Delay Time
High to Low Level Output
Enable T to
Ripple Carry
Propagation Delay Time
High to Low Level Output
Clear (Note 7)
to Q
Note 7: Propagation delay for clearing is measured from the clear input for the 161 or from the clock input transition for the 163.
3
Logic Diagrams
161
TL/F/6551–3
4
Logic Diagrams (Continued)
163
TL/F/6551–8
5
Logic Diagrams (Continued)
161, 163 Synchronous Binary Counters
Typical Clear, Preset, Count and Inhibit Sequences
TL/F/6551–5
(1) Clear outputs to zero
(2) Reset to binary twelve
(3) Count to thirteen, fourteen, fifteen, zero, one and two
(4) Inhibit
6
Parameter Measurement Information
Switching Time Waveforms
TL/F/6551–6
s
s
50%, Z
&
Note A: The input pulses are supplied by generators having the following characteristics: PRR
s
10 ns. Vary PRR to measure f
1 MHz, duty cycle
50X. For 161 and 163,
OUT
s
t
r
10 ns, t
.
MAX
f
Note B: Outputs Q and carry are tested at t
D
for 161, 163 where t is the bit time when all outputs are low.
a
16 n
n
e
Note C: For 161 and 163, V
REF
1.5V.
7
Parameter Measurement Information (Continued)
Switching Time Waveforms
TL/F/6551–7
s
s
50%, Z
&
Note A: The input pulses are supplied by generators having the following characteristics: PRR
1 MHz, duty cycle
50X. For 161 and 163,
OUT
s
s
10 ns. Vary PRR to measure f
t
r
10 ns, t
.
f
MAX
Note B: Enable P and enable T setup times are measured at t
.
0
a
n
e
Note C: For 161 and 163, V
REF
1.5V.
8
Physical Dimensions inches (millimeters)
16-Lead Ceramic Dual-In-Line Package (J)
Order Number DM54161J or DM54163AJ
NS Package Number J16A
16-Lead Molded Dual-In-Line Package (N)
Order Number DM74161N or DM74163N
NS Package Number N16E
9
Physical Dimensions inches (millimeters) (Continued)
16-Lead Ceramic Flat Package (W)
Order Number DM54161W or DM54163AW
NS Package Number W16A
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systems which, (a) are intended for surgical implant
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failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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