DP8224N [NSC]
Clock Generator and Driver; 时钟发生器和驱动程序
| 型号： | DP8224N |
| 厂家： | 
National Semiconductor |
| 描述： | Clock Generator and Driver |
| 文件： | 总8页 (文件大小：145K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 1986
DP8224 Clock Generator and Driver
General Description
Features
Y
Crystal-controlled oscillator for stable system operation
Single chip clock generator and driver for 8080A micro-
processor
The DP8224 is a clock generator/driver contained in a stan-
dard, 16-pin dual-in-line package. The chip, which is fabri-
cated using Schottky Bipolar technology, generates clocks
and timing for the 8080A microcomputer family.
Y
Y
Provides status strobe for DP8228 or DP8238 system
controllers
Included in the DP8224 is an oscillator circuit that is con-
trolled by an external crystal, which is selected by the de-
signer to meet a variety of system speed requirements. Also
included in the chip are circuits that provide: a status strobe
for the DP8228 or DP8238 system controllers, power-on re-
set for the 8080A microprocessor, and synchronization of
the READY input to the 8080A.
Y
Y
Y
Provides power-on reset for 8080A microprocessor
Synchronizes READY input to 8080A microprocessor
Provides oscillator output for synchronization of exter-
nal circuits
Y
Reduces system component count
8080A Microcomputer Family Block Diagram
TL/F/8752–1
C
1995 National Semiconductor Corporation
TL/F/8752
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Note 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Operating Conditions
Min
Supply Voltage
Max
Units
V
CC
V
DD
4.75
11.4
5.25
12.6
V
V
Supply Voltage
a
Temperature (T )
A
0
70
C
§
V
V
7V
15V
CC
DD
b
a
1V to 5.5V
Input Voltage
b
a
65 C to 150 C
Storage Temperature Range
§
§
Maximum Power Dissipation* at 25 C
Cavity Package
Molded Package
§
1509 mW
1476 mW
Lead Temperature (Soldering, 4 seconds)
260 C
§
* Derate cavity package 10.1 mW/ C above 25 C; derate molded package
§
§
11.8 mW/ C above 25 C.
§
§
Electrical Characteristics (Note 3)
Symbol
Parameter
Input Current Loading
Input Leakage Current
Input Forward Clamp Voltage
Input ‘‘Low’’ Voltage
Conditions
Min
Typ
Max
Units
mA
mA
V
e
b
I
V
V
0.45V
5.25V
0.25
F
F
e
I
10
R
R
e b
e
b
1.0
V
V
V
I
C
5 mA
5V
C
V
CC
0.8
V
IL
IH
Input ‘‘High’’ Voltage
RESIN Input
2.6
2.0
V
All Other Inputs
V
b
e
5V
V
V
V
IL
RESIN Input Hysteresis
V
CC
0.25
V
IH
Output ‘‘Low’’ Voltage
(w1, w2), Ready, Reset STSTB
Osc., w2 (TTL)
OL
e
I
I
I
2.5 mA
10 mA
15 mA
0.45
0.45
0.45
V
V
V
OL
OL
OL
e
e
Osc., w2 (TTL)
V
OH
Output ‘‘High’’ Voltage
w1, w2
e b
e b
e b
I
I
I
100 mA
100 mA
1 mA
9.4
3.6
2.4
V
V
V
OH
OH
OH
Ready, Reset
Osc., w2 (TTL), STSTB
e
V
O
e
5V
I
Output Short-Circuit Current
(All Low Voltage Outputs Only),
(Note 1)
0V, V
CC
SC
b
b
60
10
mA
I
I
Power Supply Current
Power Supply Current
115
12
mA
mA
CC
DD
b
Note 1: Caution w1 and w2 output drivers do not have short circuit protection.
Note 2: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
a
Note 3: Unless otherwise specified min/max limits apply across the 0 C to 70 C range for the DP8224. All typical values are for T
e
e
5V, and
CC
25 C, V
§
§
§
A
e
V
DD
12V.
Crystal Requirements*
a
0.005% at 0 C to 70 C
Tolerance
Equivalent Resistance
Power Dissipation (Min)
75X to 20X
§
§
Fundamental
Resonance
4 mW
Load Capacitance
20 pF to 30 pF
*It is good design practice to ground the case of the crystal
**With tank circuit, use 3rd overtone mode
2
Switching Characteristics (Note 3)
Symbol
Parameter
w1 Pulse Width
Conditions
Min
Typ
Max
Units
2t
CY
t
w1
b
b
20
35
ns
9
5t
CY
t
w2 Pulse Width
w2
ns
ns
ns
9
t
t
w1 to w2 Delay
w2 to w1 Delay
0
D1
e
C
20 pF to 50 pF
L
2t
CY
D2
b
14
9
2t
2t
CY
t
D3
w1 to w2 Delay
CY
a
20
ns
9
9
t
t
t
w1 and w2 Rise Time
w1 and w2 Fall Time
w2 to w2 (TTL) Delay
20
ns
ns
r
20
15
f
e
L
w2 TTL, C
30 pF,
Dw2
b
5
ns
ns
ns
ns
ns
ns
e
e
600X
R1
300X, R2
6t
CY
6t
CY
t
t
t
t
t
t
f
w2 to STSTB Delay
DSS
PW
b
30
9
9
t
STSTB Pulse Width
CY
e
b
STSTB, C
15 pF
15
L
9
e
e
4 kX
R1
2 kX, R2
4t
RDYIN Set-Up Time to Status Strobe
RDYIN Hold Time After STSTB
READY or RESET to w2 Delay
CLK Period
CY
DRS
DRH
DR
b
50
9
4t
CY
9
e
4t
Ready and Reset, C
e
10 pF,
CY
L
b
25
e
R1
2 kX, R2
4 kX
9
t
CY
CLK
MAX
ns
MHz
pF
9
Maximum Oscillating Frequency
Input Capacitance
27
e
e
e
C
V
V
5V, V
DD
12V,
IN
CC
8
e
2.5V, f
1 MHz
BIAS
Test Circuit
TL/F/8752–2
3
Waveforms
TL/F/8752–3
e
e
8.0V. All other signals measured at 1.5V.
Voltage Measurement Points: w1, w2 Logic ‘‘0’’
1.0V, Logic ‘‘1’’
e
Switching Characteristics (For t
488.28 ns)
Conditions
CY
Symbol
Parameter
w1 Pulse Width
Min
89
Typ
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
f
w1
w2 Pulse Width
236
0
w2
Delay w1 to w2
D1
Delay w2 to w1
95
D2
Delay w1 to w2 Leading Edges
Output Rise Time
109
129
20
D3
r
e
w1 and w2 Loaded to C
20 to 50 pF
L
Output Fall Time
20
f
Ready and Reset Loaded to 2 mA/10 pF
All Measurements Referenced to 1.5V
unless Specified Otherwise
w2 to STSTB Delay
296
326
15
DSS
Dw2
PW
DRS
DRH
DR
MAX
b
w2 to w2 (TTL) Delay
Status Strobe Pulse Width
RDYIN Set-Up Time to STSTB
RDYIN Hold Time after STSTB
READY or RESET to w2 Delay
Oscillator Frequency
5
40
b
167
217
192
18.432
MHz
4
Functional Pin Definitions
The following describes the function of all of the DP8224
input/output pins. Some of these descriptions reference in-
ternal circuits.
For manual system reset, a momentary contact switch that
provides a low (ground) when closed is also connected to
the RESIN input.
Ready In (RDYIN): An asynchronous READY signal that is
re-clocked by a D-type flip-flop of the DP8224 to provide the
synchronous READY output discussed below.
INPUT SIGNALS
Crystal Connections (XTAL 1 and XTAL 2): Two inputs
that connect an external crystal to the oscillator circuit of
the DP8224. Normally, a fundamental mode crystal is used
to determine the basic operating frequency of the oscillator.
However, overtone mode crystals may also be used. The
crystal frequency is 9 times the desired microprocessor
a
a
5 Volts: V
CC
supply.
supply.
12 Volts: V
DD
Ground: 0 volt reference.
OUTPUT SIGNALS
c
speed (that is, crystal frequency equals 1/t
CY
9). When
Oscillator (OSC): A buffered oscillator signal that can be
used for external timing purposes.
the crystal frequency is above 10 MHz, a selected capacitor
(3 to 10 pF) may have to be connected in series with the
crystal to produce the exact desired frequency. Figure A.
w
and w Clocks: Two non-TTL compatible clock phases
2
1
that provide nonoverlapping timing references for internal
storage elements and logic circuits of the 8080A microproc-
essor. The two clock phases are produced by an internal
clock generator that consists of a divide-by-nine counter
and the associated decode gating logic. Figure B.
Tank: Allows the use of overtone mode crystals with the
oscillator circuit. When an overtone mode crystal is used,
the tank input connects to a parallel LC network that is ac
coupled to ground. The formula for determining the reso-
nant frequency of this LC network is as follows:
w
(TTL) Clock: A TTL w clock phase that can be used for
2
external timing purposes.
1
2
e
F
2q LC
0
Status Strobe (STSTB): Activated (low) at the start of each
new machine cycle. The STSTB signal is generated by gat-
Synchronizing (SYNC) Signal: When high, indicates the
beginning of a new machine cycle. The 8080A microproces-
sor outputs a status word (which describes the current ma-
chine cycle) onto its data bus during the first state (SYNC
interval) of each machine cycle.
ing a high-level SYNC input with the w timing signal from
1A
the internal clock generator of the DP8224. The STSTB sig-
nal is used to clock status information into the status latch
of the DP8228 system controller and bus driver.
Reset In (RESIN): Provides an automatic system reset and
start-up upon application of power as follows. The RESIN
input, which is obtained from the junction of an external RC
Reset: When the RESET signal is activated, the content of
the program counter of the 8080A is cleared. After
RESET, the program will start at location 0 in memory.
network that is connected between V and ground, is rout-
CC
Ready: The READY signal indicates to the 8080A that valid
memory or input data is available. This signal is used to
synchronize the 8080A with slower memory or input/output
devices.
ed to an internal Schmitt Trigger circuit. This circuit converts
the slow transition of the power supply rise into a sharp,
clean edge when its input reaches a predetermined value.
When this occurs, an internal D-type flip-flop is synchro-
nously reset, thereby providing the RESET output signal dis-
cussed below.
Logic and Connection Diagrams
Dual-In-Line Package
TL/F/8752–5
Top View
Order Number DP8224J or DP8224N
See NS Package Number
J16A or N16A
TL/F/8752–4
5
Applications Information
TL/F/8752–7
e
EXAMPLE: (8080 t
500 ns)
CY
e
OSC
18 MHz/55 ns
e
c
c
w
w
w
110 ns (2
55 ns)
55 ns)
1
2
2
e
275 ns (5
e
c
55 ns)
–w
110 ns (2
1
FIGURE B. DP8224 Clock Generator Waveforms
TL/F/8752–6
FIGURE A. DP8224 Connection Diagram
6
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number DP8224J
NS Package Number J16A
7
Physical Dimensions inches (millimeters) (Continued)
Molded Dual-In-Line Package (N)
Order Number DP8224N
NS Package Number N16A
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