DP83255_技术文档

February 1991

DP83251/55 PLAYER^TMDevice

(FDDI Physical Layer Controller)

General Description

Features

Y

Low power CMOS-BIPOLAR process

The DP83251/DP83255 PLAYER device implements one

Physical Layer (PHY) entity as defined by the Fiber Distribut-

ed Data Interface (FDDI) ANSI X3T9.5 Standard. The PLAY-

ER device contains NRZ/NRZI and 4B/5B encoders and

decoders, serializer/deserializer, framing logic, elasticity

buffer, line state detector/generator, link error detector, re-

peat filter, smoother, and configuration switch.

Single 5V supply

Full duplex operation

Separate management interface (Control Bus)

Parity on PHY-MAC Interface and Control Bus Interface

On-chip configuration switch

Internal and external loopback

DP83251 for single attach stations

DP83255 for dual attach stations

TL/F/10386–1

FIGURE 1-1. FDDI Chip Set Block Diagram

TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.

BSI^TM, BMAC^TM, PLAYER^TM, CDD^TMand CRD^TMare trademarks of National Semiconductor Corporation.

C

1995 National Semiconductor Corporation

TL/F/10386

RRD-B30M105/Printed in U. S. A.

Table of Contents

1.0 FDDI CHIP SET OVERVIEW

2.0 ARCHITECTURE DESCRIPTION

2.1 Overview

7.0 ELECTRICAL CHARACTERISTICS

7.1 Absolute Maximum Ratings

7.2 Recommended Operating Conditions

7.3 DC Electrical Charcteristics

7.4 AC Electrical Charcteristics

7.5 Test Circuits

2.2 Interfaces

3.0 FUNCTIONAL DESCRIPTION

3.1 Receiver Block

3.2 Transmitter Block

3.3 Configuration Switch

4.0 MODES OF OPERATION

4.1 Run Mode

8.0 DETAILED DESCRIPTIONS

8.1 Framing Hold Rules

8.2 Noise Events

8.3 Link Errors

4.2 Stop Mode

8.4 Repeat Filter

4.3 Loopback Mode

4.4 Cascade Mode

8.5 Smoother

8.6 National Byte-wide Code for PHY-MAC Interface

5.0 REGISTERS

6.0 PIN DESCRIPTIONS

6.1 DP83251

6.2 DP83255

2

1.0 FDDI Chip Set Overview

National Semiconductor’s FDDI chip set consists of five

components as shown in Figure 1-1. For more information

on the other devices of the chip set, consult the appropriate

datasheets and application notes.

DP83231 CRD^TMDevice

Clock Recovery Device

The Clock Recovery Device extracts a 125 MHz clock from

DP83261 BMAC^TMDevice

Media Access Controller

The BMAC device implements the Timed Token Media Ac-

cess Control protocol defined by the ANSI FDDI X3T9.5

MAC Standard.

the incoming bit stream.

Features

PHY Layer loopback test

Features

#

All of the standard defined ring service options

#

Crystal controlled

#

Full duplex operation with through parity

Supports all FDDI Ring Scheduling Classes (Synchro-

nous, Asynchronous, etc.)

#

Clock locks in less than 85 ms

#

DP83241 CDD^TMDevice

Clock Distribution Device

From a 12.5 MHz reference, the Clock Distribution Device

synthesizes the 125 MHz, 25 MHz, and 12.5 MHz clocks

required by the BSI, BMAC and PLAYER devices.

Supports Individual, Group, Short, Long, and External

Addressing

#

Generates Beacon, Claim, and Void frames internally

#

Extensive ring and station statistic gathering

Extensions for MAC level bridging

Separate management port that is used to configure and

control their operation

#

DP83251/55 PLAYER^TMDevice

Physical Layer Controller

Multi-frame streaming interface

#

The PLAYER device implements the Physical Layer (PHY)

protocol as defined by the ANSI FDDI PHY X3T9.5 Stan-

dard.

DP83265 BSI^TMDevice

System Interface

The BSI device implements the interface between the

Features

4B/5B encoders and decoders

BMAC device and a host system.

#

Framing logic

#

Features

32-bit wide Address/Data path with byte parity

Elasticity Buffer, Repeat Filter and Smoother

#

Line state detector/generator

Programmable transfer burst sizes of 4 or 8 32-bit words

#

Link error detector

Interfaces to low cost DRAMs or directly to system bus

#

Configuration switch

Provides 2 Output and 3 Input Channels

#

Full duplex operation

Supports Header/Info splitting

#

Separate management port that is used to configure and

control their operation

Efficient data structures

#

Programmable Big or Little Endian alignment

#

In addition, the DP83255 contains an additional

PHY Data.request and PHY Data.indicate port required

for concentrators and dual attach stations.

Full duplex data path allows transmission to self

#

Ð

Confirmation status batching services

#

Receive frame filtering services

#

Operates from 12.5 MHz to 25 MHz synchronously with

the host system

#

3

2.0 Architecture Description

2.1 OVERVIEW

Generates Idle, Master, Halt, Quiet or other user defined

symbol pairs upon request.

#

The PLAYER device is comprised of four blocks: Receiver,

Transmitter, Configuration Switch and Control Bus Interface

as shown in Figure 2-1.

Converts the data stream from NRZ to NRZI format

ready for transmission, if necessary.

Provides smoothing function when necessary.

Receiver

During normal operation, the Transmitter Block presents se-

rial data to the fiber optic transmitter. While in the External

Loopback mode, the Transmitter Block presents serial data

to the Clock Recovery Device.

During normal operation, the Receiver Block accepts serial

data as inputs at the rate of 125 Mbps from the Clock Re-

covery Device (DP83231). During the Internal Loopback

mode of operation, the Receiver Block accepts data from

the Transmitter Block as inputs.

Control Bus Interface

The Control Bus Interface allows a user to:

The Receiver Block performs the following operations:

Program the Configuration Switch.

#

Converts the incoming data stream from NRZI to NRZ, if

necessary

#

Enable/disable functions within the Transmitter and Re-

ceiver Blocks (i.e., NRZ/NRZI Encoder, Smoother, PHY

Request Data Parity, Line State Generation, Symbol Pair

Injection, NRZ/NRZI Decoder, Cascade Mode, etc.).

Decodes the data from 5B to 4B coding

#

Converts the serial bit stream into 10-bit bytes

Compensates for the differences between the upstream

and local clocks

The Control Bus Interface also performs the following func-

tions:

Decodes Line States

#

Monitors Line States received

#

Detects link errors

#

Finally, the Receiver Block presents data symbol pairs

(bytes) to the Configuration Switch Block

Monitors link errors detected by the Receiver Block

Monitors other error conditions

2.2 INTERFACES

Configuration Switch

The PLAYER device connects to external components via 5

functional interfaces: Serial Interface, PHY Port Interface,

Control Bus Interface, Clock Interface, and the Miscellane-

ous Interface.

An FDDI station may be in one of three configurations: Iso-

late, Wrap or Thru. The Configuration Switch supports these

configurations by switching the transmitted and received

data paths between the PLAYER and BMAC devices.

The configuration switching is performed internally, there-

fore no external logic is required for this function.

Serial Interface

The Serial Interface connects the PLAYER device to a fiber

optic transmitter (FOTX) and the Clock Recovery Device

(DP83231).

Transmitter

The Transmiter Block accepts 10-bit bytes from the Config-

uration Switch.

The Transmitter Block performs the following operations:

Encodes the data from 4B to 5B coding.

#

Filters out code violations from the data stream.

#

TL/F/10386–2

FIGURE 2-1. PLAYER Device Block Diagram

4

2.0 Architecture Description

(Continued)

3.0 Functional Description

The PLAYER Device is comprised of four blocks: Receiver,

Transmitter, Configuration Switch and Control Bus Inter-

face.

PHY Port Interface

The PHY Port Interface connects the PLAYER device to

one or more BMAC devices and/or PLAYER devices. Each

PHY Port Interface consists of two byte-wide-interfaces,

one for PHY Request data input to the PLAYER device and

one for the PHY Indicate data output of the PLAYER device.

Each byte-wide interface consists of a parity bit (odd parity),

a control bit, and two 4-bit symbols.

3.1 RECEIVER BLOCK

During normal operation, the Receiver Block accepts serial

data as inputs at the rate of 125 Mbps from the Clock Re-

covery Device (DP83231). During the Internal Loopback

mode of operation, the Receiver Block accepts data from

the Transmitter Block as input.

The DP8355 PLAYER device has two PHY Port Interfaces

and the DP83251 has only one PHY Port Interface.

The Receiver Block performs the following operations:

Converts the incoming data stream from NRZI to NRZ, if

necessary

#

Control Bus Interface

Decodes the data from 5B to 4B coding

#

The Control Bus Interface connects the PLAYER device to

a wide variety of microprocessors and microcontrollers. The

Control Bus is an asynchronous interface which provides

access to 32 8-bit registers.

Converts the serial bit stream into National byte-wide

code

Compensates for the differences between the upstream

and local clocks

#

Clock Interface

Decodes Line States

#

The Clock Interface consists of 12.5 MHz and 125 MHz

clocks used by the PLAYER device.

Detects link errors

#

Finally, the Receiver Block presents data symbol pairs to

the Configuration Switch Block.

The clocks are generated by either the Clock Distribution

Device (CDD device) or the Clock Recovery Device (CRD

device).

The Receiver Block consists of the following functional

blocks:

Miscellaneous Interface

NRZI to NRZ Decoder

Shift Register

Framing Logic

The Miscellaneous Interface consists of:

A reset signal

#

User definable sense signals

#

Symbol Decoder

Line State Detector

Elasticity Buffer

User definable enable signals

Synchronization for cascaded PLAYER devices (a high-

performance non-FDDI mode)

Link Error Detector

See Figure 3-1.

CMOS power and ground, and ECL ground and power

#

TL/F/10386–3

FIGURE 3-1. Receiver Block Diagram

5

3.0 Functional Description (Continued)

NRZI TO NRZ DECODER

Idle Line State

The NRZI to NRZ Decoder converts Non-Return-To-Zero-

Invert-On-Ones data to Non-Return-To-Zero data.

This function can be enabled and disabled through bit 7

(RNRZ) of the Mode Register (MR). When the bit is cleared,

it converts the incoming bit stream from NRZI to NRZ.

When the bit is set the incoming NRZ bit stream is passed

unchanged.

The Line State Detector recognizes the incoming data to be

in the Idle Line State upon the reception of 2 Idle symbol

pairs nominally (plus up to 9 bits of 1 in start up cases).

Idle Line State indicates the preamble of a frame or the lack

for frame transmission during normal operation. Idle Line

State is also used in the handshake sequence of the PHY

Connection Management process.

SHIFT REGISTER

TABLE 3-1. Symbol Decoding

The Shift Register converts the serial bit stream into sym-

bol-wide data for the 5B/4B Decoder.

The Shift Register also provides byte-wide data for the

Framing Logic.

Symbol

Incoming 5B

Decoded 4B

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

11110

01001

10100

10101

01010

01011

01110

01111

10010

10011

10110

10111

11010

11011

11100

11101

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

FRAMING LOGIC

The Framing Logic performs the Framing function by detect-

ing the beginning of a frame or the Halt-Halt or Halt-Quiet

symbol pair.

The J-K symbol pair (11000 10001) indicates the beginning

of a frame during normal operation. The Halt-Halt (00100

00100) and Halt-Quiet (00100 00000) symbol pairs are de-

tected during Connection Management (CMT).

Framing can be temporarily suspended (i.e. framing hold), in

order to maintain data integrity. The Framing Hold rules are

explained in Section 8.1.

SYMBOL DECODER

The Symbol Decoder is a two level system. The first level is

a 5-bit to 4-bit converter, and the second level is a 4-bit

symbol pair to the NSC byte-wide code converter.

The first level latches the received 5-bit symbols and de-

codes them into 4-bit symbols. Symbols are decoded into

two types: data and control. The 4-bit symbols are sent to

the Line State Detector and the second level of the Symbol

Decoder. See Table 3-1 for the 5B/4B Symbol Decoding

list.

I (Idle)

11111

00100

11000 &

10001

01101

1010

0001

1101

H (Halt)

JK (Starting

Delimiter)

T (Ending

0101

Delimiter)

The second level translates two 4-bit symbols from the 5B/

4B converter and the line state information from the Line

State Detector into the National byte-wide code. More de-

tails on the National byte-wide code can be found in Section

8.6.

R (Reset)

00111

11001

00000

00001

00010

00011

00101

00110

01000

01100

10000

0110

0111

0010

0011

1011

S (Set)

Q (Quiet)

V (Violation)

V

LINE STATE DETECTOR

The FDDI Physical Layer (PHY) standard specifies eight

Line States that the Physical Layer can transmit. These Line

States are used in the Connection Management process.

They are also used to indicate data within a frame during the

normal operation.

The Line State Detector detects nine Line States, one more

than the required Line States specified in the standard.

The Line States are reported through the Current Receive

Ê

V

Ê

I

State Register (CRSR), Receive Condition Register

(RCRA), and Receive Condition Register B (RCRB).

A

Notes:

Ê

V

denotes PHY Invalid or an Elasticity Buffer stuff byte.

Line States Description

Active Line State

Ê

I

denotes Idle symbol in ILS or an Elasticity Buffer stuff byte.

The Line State Detector recognizes the incoming data to be

in the Active Line State upon the reception of the Starting

Delimiter (JK symbol pair).

Super Idle Line State

The Line State Detector recognizes the incoming data to be

in the Super Idle Line State upon the reception of eight con-

secutive Idle symbol pairs nominally (plus 1 symbol pair).

The Line State Detector continues to indicate Active Line

State while receiving data symbols, Ending Delimiter (T

symbols), and Frame Status symbols (R and S) after the JK

symbol pair.

The Super Idle Line State is used to insure synchronization.

6

3.0 Functional Description (Continued)

ceive Clock, while data is read from the registers with the

Local Byte Clock.

No Signal Detect

The Line State Detector recognizes the incoming data to be

in the No Signal Detect state upon the deassertion of the

Signal Detect signal. No Signal Detect indicates that the

incoming link is inactive.

The Elasticity Buffer will recenter (i.e. set the read and write

pointers to a predetermined distance from each other) upon

the detection of a JK or every four byte times during PHY

Invalid (i.e. MLS, HLS, QLS, NLS, NSD) and Idle Line State.

To resolve metastability problems, the Elasticity Buffer is

designed such that a given register cannot be written and

read simultaneously under normal operating conditions. In a

symbol-wide station, a 5-bit off boundary JK following after a

maximum size frame situation may be produced which may

result in a small increase in the probability of an error

caused by a metastability condition.

Master Line State

The Line State Detector recognizes the incoming data to be

in the Master Line State upon the reception of eight consec-

utive Halt-Quiet symbol pairs nominally (plus up to 2 symbol

pairs in start up cases).

The Master Line State is used in the handshake sequence

of the PHY Connection Management process.

LINK ERROR DETECTOR

Halt Line State

The Link Error Detector provides continuous monitoring of

an active link (i.e. during Active and Idle Line States) to

insure that it meets the minimum Bit Error Rate requirement

as set by the standard or user to remain on the ring.

The Line State Detector recognizes the incoming data to be

in the Halt Line State upon the reception of eight consecu-

tive Halt symbol pairs nominally (plus up to 2 symbol pairs in

start up cases).

Upon detecting a link error, the internal 8-bit Link Error Mon-

itor Counter is decremented. The start value for the Link

Error Monitor Counter is programmed through the Link Error

Threshold Register (LETR). When the Link Error Monitor

Counter reaches zero, bit 4 (LEMT) of the Interrupt Condi-

tion Register (ICR) is set to 1. The current value of the Link

Error Monitor Counter can be read through the Current Link

Error Count Register (CLECR). For higher error rates the

current value is an approximate count because the counter

rolls over.

The Halt Line State is used in the handshake sequence of

the PHY Connection Management process.

Quiet Line State

The Line State Detector recognizes the incoming data to be

in the Quiet Line State upon the reception of eight consecu-

tive Quiet symbol pairs nominally (plus up to 9 bits of 0 in

start up cases).

The Quiet Line State is used in the handshake sequence of

the PHY Connection Management process.

There are two ways to determine Link Error Rate: polling

and interrupt.

Noise Line State

The Line State Detector recognizes the incoming data to be

in the Noise Line State upon the reception of 16 noise sym-

bol pairs.

Polling

The Link Error Monitor Counter is set to the value of FF.

This start value is programmed through the Link Error

Threshold Register (LETR).

The Noise Line State indicates that data is not received

correctly. A detailed description of a noise event can be

found in Section 8.2.

Upon detecting a link error, the Current Link Error Counter is

decremented.

Line State Unknown

The Host System reads the current value of the Link Error

Monitor Counter via the Current Link Error Count Register

(CLECR). The Counter is then reset to FF.

The Line State Detector recognizes the incoming data to be

in the Line State Unknown state upon the reception of one

inconsistent symbol pair (i.e. data that is not expected). This

may be the beginning of a new line state.

Interrupt

The Link Error Monitor Counter is set to the value of FF.

This start value is programmed through the Link Error

Threshold Register (LETR).

Line State Unknown indicates that data is not received cor-

rectly. If the condition persists the noise line state may be

entered.

Upon detecting a link error, the Line Error Monitor Counter

is decremented. When the counter reaches zero, bit 4

(LEMT) of the Interrupt Condition Register (ICR) is set to 1,

and the interrupt signal goes low.

ELASTICITY BUFFER

The Elasticity Buffer performs the function of a ‘‘variable

depth’’ FIFO to compensate for clock skews between the

g

Receive Clock (RXC ) and the Local Byte Clock (LBC).

The Host System is interrupted when the Link Error Monitor

Counter reaches 0.

Bit 5 (EBOU) of the Receive Condition Register B (RCRB) is

set to 1 to indicate an error condition when the Elasticity

Buffer cannot compensate for the clock skews.

A state table describing Link Errors in more detail can be

found in Section 8.3.

The Elasticity Buffer will support maximum clock skews of

g

Miscellaneous Items

50 ppm with a maximum packet length of 4500 bytes.

When bit 0 (RUN) of the Mode Register (MR) is set to zero,

or when the PLAYER device is reset through the Reset pin

(RST), the Signal Detect line (TTLSD) is internally forced to

zero and the Line State Detector is set to Line State Un-

known.

To make up for the accumulation of frequency disparity be-

tween the two clocks, the Elasticity Buffer will insert or de-

lete Idle symbol pairs in the preamble. Data is written into

the byte-wide registers of the Elasticity Buffer with the Re-

7

3.0 Functional Description (Continued)

While in the External Loopback mode, the Transmitter Block

presents serial data to the Clock Recovery Device.

3.2 TRANSMITTER BLOCK

The Transmitter Block accepts 10-bit bytes from the Config-

uration Switch.

The Transmitter Block consists of the following functional

blocks:

The Transmitter Block performs the following operations:

Data Registers

Parity Checker

4B/5B Encoder

Repeat Filter

Smoother

Encodes the data from 4B to 5B coding

#

Filters out code violations from the data stream

Is capable of generating Idle, Master, Halt, Quiet, or oth-

er user defined symbol pairs

Line State Generator

Injection Control Logic

Shift Register

Converts the data stream from NRZ to NRZI ready for

transmission

#

Serializes data

#

During normal operation, the Transmitter Block presents se-

rial data to the fiber optic transmitter.

NRZ to NRZI Encoder

See Figure 3-2.

TL/F/10386–4

FIGURE 3-2. Transmitter Block Diagram

8

3.0 Functional Description (Continued)

DATA REGISTERS

LINE STATE GENERATOR

Data from the Configuration Switch is stored in the Data

Registers. The 10-bit byte-wide data consists of a parity bit,

a control bit, and two 4-bit symbols as shown in Figure 3-3.

The Line State Generator allows the transmission of the

PHY Request data and can also generate and transmit Idle,

Master, Halt, or Quiet symbol pairs which can be used to

implement the Connection Management procedures as

specified in the FDDI Station Management (SMT) docu-

ment.

b9

b8

b7

b0

Parity Bit

Control Bit

Data Bits

The Line State Generator is programmed through Transmit

l

k

FIGURE 3-3. Byte-Wide Data

PARITY CHECKER

bits 0 to 2 (TM 2:0 ) of the Current Transmit State Regis-

ter (CTSR).

Based on the setting of these bits, the Transmitter Block

operates in the Transmit Modes where the Line State Gen-

erator overwrites the Repeat Filter and Smoother outputs.

The Parity Checker verifies that the parity bit in the Data

Register represents odd parity (i.e. odd number of 1s).

The parity checking is enabled and disabled through bit 6

(PRDPE) of the Current Transmit State Register (CTSR).

See Table 3-3 for the listing of the Transmit Modes.

TABLE 3-2. 4B/5B Symbol Encoding

If a parity error occurs, the Parity Checker will set bit 0 (DPE)

in the Interrupt Condition Register (ICR) and report the error

to the Repeat Filter.

Symbol

4B Code

Outgoing 5B

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

11110

01001

10100

10101

01010

01011

01110

01111

10010

10011

10110

10111

11010

11011

11100

11101

4B/5B ENCODER

The 4B/5B Encoder converts the two 4-bit symbols from

the Configuration Switch into their respective 5-bit codes.

See Table 3-2 for the Symbol Encoding list.

REPEAT FILTER

The Repeat Filter is used to prevent the propagation of

code violations in data frames, to the downstream station.

Upon receiving violations in data frames, the Repeat Filter

replaces them with two Halt symbol pairs followed by Idle

symbols. Thus the code violations are isolated and recov-

ered at each link and will not be propagated throughout the

entire ring.

Details on Repeat Filter operation are described in Section

8.4.

SMOOTHER

The Smoother is used to keep the preamble length of a

frame to a minimum of 6 Idle symbol pairs.

N

JK

T

0000

1101

11110 or

11111

Idle symbols in the preamble of a frame may have been

added or deleted by each station to compensate for the

difference between the Receive Clock and its Local Clock.

The preamble needs to be maintained at a minimum length

to allow stations enough time to complete processing of one

frame and prepare to receive another. Without the Smooth-

er function, the minimum preamble length (6 Idle symbol

pairs) may not be maintained as several stations may con-

secutively delete Idle symbols.

(Starting

11000 and

10001

Delimiter)

(Ending

Delimiter)

(Reset)

(Set)

0100 or

0101

01101

R

S

0110

00111

11001

0111

TABLE 3-3. Transmit Modes

The Smoother attempts to keep the number of Idle symbol

pairs in the preamble at 7 by:

Active Transmit Mode

Normal Transmission Mode

Off Transmit Mode

Transmit Quiet symbol pairs

and disable the Fiber Optic

Transmitter

Deleting an Idle symbol pair in preambles which have

more than 7 Idle symbol pairs

#

and/or

Idle Transmit Mode

Transmit Idle symbol pairs

Inserting an Idle symbol pair in preambles which have

less than 7 idle symbol pairs (i.e. Extend State).

#

Master Transmit Mode

Transmit Halt-Quiet symbol

pairs

The Smoother Counter starts counting upon detecting an

Idle symbol pair. It stops counting upon detecting a JK sym-

bol pair.

Quiet Transmit Mode

Transmit Quiet symbol pairs

Reserved Transmit

Mode

Reserved for future use. If

selected, Quiet symbol pairs

will be transmitted.

More details on the operation of the Smoother can be found

in Section 8.5.

Halt Transmit Mode

Transmit Halt symbol pairs

9

3.0 Functional Description (Continued)

In the No Injection mode, the data stream is transmitted

unchanged.

INJECTION CONTROL LOGIC

The Injection Control Logic replaces the data stream with a

programmable symbol pair. This function is used to transmit

data other than the normal data frame or Line States.

In the One Shot mode, ISRA and ISRB are injected once on

the nth byte after a JK, where n is the programmed value

specified in the Injection Threshold Register.

The Injection Symbols overwrite the Line State Generator

(Transmit Modes) and the Repeat Filter and Smoother out-

puts.

In the Periodic mode, ISRA and ISRB are injected every nth

symbol.

In the Continuous mode, all data symbols are replaced with

the contents of ISRA and ISRB. This is the same as periodic

These programmable symbol pairs are stored in the Injec-

tion Symbol Register A (ISRA) and Injection Symbol Regis-

ter B (ISRB). The Injection Threshold Register (IJTR) deter-

mines where the Injection Symbol pair will replace the data

symbols.

e

mode with IJTR

0.

SHIFT REGISTER

The Shift Regiser converts encoded parallel data to serial

data. The parallel data is clocked into the Shift Register by

g

the Transmit Byte Clock (TBC ), and clocked out by the

The Injection Control Logic is programmed through the bits

k

l

0 and 1 (IC 1:0 ) of the Current Transmit State Register

(CTSR) to one of the following Injection Modes (see Figure

3-4):

g

Transmit Bit Clock (TXC ).

NRZ TO NRZI ENCODER

1. No Injection (i.e. normal operation)

2. One Shot

The NRZ to NRZI Encoder converts the serial Non-Return-

To-Zero data to Non-Return-To-Zero-Invert-On-One data.

3. Periodic

This function can be enabled and disabled through bit 6

(TNRZ) of the Mode Register (MR). When programmed to

‘‘0’’, it converts the bit stream from NRZ to NRZI. When

programmed to ‘‘1’’, the bit stream is transmitted NRZ.

4. Continuous

One Shot (Notes 1, 3)

TL/F/10386–5

Periodic (Notes 2, 3)

TL/F/10386–6

Continuous (Note 3)

TL/F/10386–33

Where

ISRA: Injection Symbol Register A

ISRB: Injection Symbol Register B

IJTR: Injection Threshold Register

a

Note 1: In one shot when n

Note 2: In periodic when n

0 the JK is replaced.

e

0 all symbols are replaced.

255.

e

Note 3: Max value on n

FIGURE 3-4. Injection Modes

10

3.0 Functional Description (Continued)

PHY Port Interface output data paths,

A Indicate and

Ð

Indicate, that can drive output data paths of the external

3.3 CONFIGURATION SWITCH

B

Ð

The Configuration Switch consists of a set of multiplexors

and latches which allow the PLAYER device to configure

the data paths without the need of external logic. The Con-

figuration Switch is controlled through the Configuration

Register (CR).

PHY Port Interface. The third output data path is connected

internally to the Transmit Block.

The Configuration Switch is the same on both the DP83251

device and the DP83255 device. However, the DP83255

has two PHY Port interfaces connected to the Configuration

Switch, whereas the DP83251 has one PHY Port Interface.

The DP83255 uses the A Request and A Indicate paths

The Configuration Switch has four internal buses, the

Request bus, the B Request bus, the Receive bus, and

A

the PHY Invalid bus. The two Request buses can be driv-

Ð

as one PHY Port Interface and the B Request and B Indi-

Ð

cate paths as the other PHY Port interface (see Figure 3-

en by external input data connected to the external PHY

Port Interface. The Receive bus is internally connected to

the Receive Block of the PLAYER device, while the PHY

Invalid bus has a fixed 10-bit LSU pattern, useful during the

connection process. The configuration switch also has three

internal multiplexors, each can select any of the four buses

to connect to its respective data path. The first two are

5a). The DP83251, having only one port interface, uses the

Ð

B

A

Request and A Indicate paths as its external port. The

Ð

Request and B Indicate paths of the DP83251 are null

Ð

connections and are not used by this device (see Figure 3-

5b).

TL/F/10386–7

FIGURE 3-5a. Configuration Switch Block

Diagram for DP83255

TL/F/10386–34

FIGURE 3-5b. Configuration Switch Block

Diagram for DP83251

11

3.0 Functional Description (Continued)

STATION CONFIGURATIONS

Although two DP83251s can be connected together to build

a Dual Attach Station, it is recommended that the DP83255

is to be used for this type of station configuration.

Single Attach Station (SAS)

The Single Attach Station can be connected to either the

Primary or Secondary ring via a Concentrator. Only 1 MAC

is needed in a SAS.

A DAS with Single MAC can be configured as follows:

B

input of PHY B. B Request input of PHY A is con-

Indicate data of PHY A is connected to A Request

Ð Ð

#

Ð

Ð Ð

nected to A Indicate output of PHY B.

Ð

Both the DP83251 and DP83255 can be used in a Single

Attach Station. The DP83251 can be connected to the MAC

via its only PHY Port Interface. The DP83255 can be con-

nected to the MAC via either of the 2 PHY Port Interfaces.

Ð

The MAC can be connected to either the A Request

Ð

input and the

B

Ð

of PHY B.

A

Request input and the

Indicate output of PHY

B

Ð

A

Indicate output

or the

Ð

See Figures 3-6 and 3-7.

Ð

The DAS with Dual MACs can be configured as follows:

Dual Attach Station (DAS)

A Dual Attach Station can be connected directly to the dual

ring. There are two types of Dual Attach Stations: DAS with

a Single MAC and DAS with Dual MACs. See Figures 3-8

and 3-9.

B

input of PHY B. B Request input of PHY A is con-

Indicate data of PHY A is connected to A Request

Ð Ð

#

Ð

Ð Ð Ð

nected to A Indicate output of PHY B.

Ð Ð

The MAC 1 is connected to the B Indicate output and

#

Ð

the B Request Input of PHY B.

Ð

Ð Ð

The MAC 2 is connected to the A Indicate output and

Ð

the A Request Input of PHY A.

Ð

TL/F/10386–8

FIGURE 3-6. Single Attach Station Using the DP83251

TL/F/10386–9

FIGURE 3-7. Single Attachment Station (SAS)

Using the DP83255

TL/F/10386–10

FIGURE 3-8. Dual Attachment Station (DAS), Single MAC

TL/F/10386–11

FIGURE 3-9. Dual Attachment Station (DAS), Dual MACs

12

3.0 Functional Description (Continued)

CONCENTRATOR CONFIGURATIONS

Single Attach Concentrator

There are 2 types of Concentrators: Single Attach and Dual

Attach. These Concentrators can be designed with or with-

out the MAC(s). Its configuration is determined based upon

its type and the number of active MACs in the Concentrator.

A Single Attach Concentrator is a Concentrator that has

only one PHY at the Dual Ring Connect side. It cannot,

therefore, be connected directly to the Dual Ring. A Single

Attach Concentrator is a Branch to the Dual Ring Tree. It is

connected to the ring as a Slave of another Concentrator.

Using the PLAYER devices, a Concentrator can be built with

many different configurations without the need of any exter-

nal logic.

Multiple Single Attach Concentrators can be connected to-

gether hierarchically to build multiple levels of branches in a

Dual Ring.

Both the DP83251 and DP83255 can be used to build a

Single Attach Concentrator. Only the DP83255 is recom-

mended for the Dual Attach Concentrator design.

The Single Attach Concentrator can be connected to either

the Primary or Secondary ring depending on the connection

with its Concentrator (the Concentrator that it is connected

to a slave).

See Application Note 675, Designing FDDI Concentrators

and Application Note 741, Differentiating FDDI Concentra-

tors for futher information.

Figure 3-10 shows a Single Attach Concentrator with a Sin-

gle MAC.

Concepts

Dual Attach Concentrator

A Concentrator is comprised of 2 parts: the Dual Ring Con-

nect portion and the Master Ports.

A Dual Attach Concentrator is a Concentrator that has two

PHYs at the Dual Ring Connect side. It is connected directly

to the dual ring and is a part of the Dual Ring Tree.

The Dual Ring Connection portion connects the Concentra-

tor to the dual ring directly or to another Concentrator. If the

Concentrator is connected directly to the dual ring, it is a

part of the ‘‘Dual Ring Tree’’. If the Concentrator is connect-

ed to another Concentrator, it is a ‘‘Branch’’ of the ‘‘Dual

Ring Tree’’.

The Dual Attach Concentrator is connected to both the Pri-

mary and Secondary rings.

Dual Attach Concentrator with Single MAC

Figure 3-11 shows a Dual Attach Concentrator with a Single

MAC.

The Master Ports connect the Concentrator to its ‘‘Slaves’’.

A Slave could be a Single Attach Station or another Con-

centrator (thus forming another Branch of the Dual Ring

Tree).

Because the Concentrator has one MAC, it can only trans-

mit and receive frames on the ring where the MAC is con-

nected. The Concentrator can only repeat frames on the

other ring.

When a MAC in a concentrator is connected to the Primary

or Secondary Ring, it is required to be situated at the exit

port of that concentrator (i.e. its PH IND is connected to

Dual Attach Concentrator with Dual MACs

Ð

the IND Interface of the last Master Port in the Concentrator

(PHY M n) that is connected to that ring).

Ð

Figure 3-12 shows Dual Attach Concentrator wih Dual

MACs.

A Concentrator can have two MACs connected to both the

Primary and Secondary rings. In addition, a Roving MAC can

be included in the Concentrator configuration. A Roving

MAC can be used to test the stations connected to the Con-

centrator before allowing them to join the Dual Ring. This

may require external multiplexers.

Because the Concentrator has two MACs, it can transmit

and receive frames on both the Primary and Secondary

rings.

13

3.0 Functional Description (Continued)

TL/F/10386–12

TL/F/10386–13

TL/F/10386–14

FIGURE 3-10. Single Attach Concentrator (SAC), Single MAC

FIGURE 3-11. Dual Attach Concentrator (DAC), Single MAC

FIGURE 3-12. Dual Attach Concentrator (DAC), Dual MACs

14

4.0 Modes of Operation

The PLAYER device can operate in 4 basic modes: RUN,

STOP, LOOPBACK, and CASCADE.

4.1 RUN MODE

RUN is the normal mode of operation.

In this mode, the PLAYER device is configured to be con-

nected to the media via the Fiber Optic Transmitter and

Receiver at the Serial Interface. It is also connected to other

PLAYER device(s) and/or BMAC device(s) via the Port A

and Port B Interfaces.

While operating in the Run mode, the PLAYER device re-

ceives and transmits Line States (Quiet, Halt, Master, Idle)

and frames (Active Line State).

4.2 STOP MODE

The PLAYER device operates in the STOP mode while it is

being initialized or configured.

The PLAYER device is also reset to the STOP mode auto-

matically when the RST pin (pin 71 on the DP83251 and pin

111 on the DP83255) is set to ground.

When in STOP mode, the PLAYER device performs the fol-

lowing functions:

Resets the Repeat Filter.

#

Resets the Smoother.

#

Resets the Receiver Block Line State Counters.

#

Flushes the Elasticity Buffer.

#

Forces Line State Unknown in the Receiver Block.

#

TL/F/10386–42

Outputs LSU symbol pairs (0

the PHY Data Indicate pins (AIP, AIC, AID 7:0 , BIP,

1 0011 1010) through

l

#

FIGURE 4-1a. Configuration Switch

Loopback for DP83255

k

l

BIC, BID 7:0 ).

Outputs Quiet symbol pairs through the PMD Data Re-

g

quest pins (TXD ).

#

Resets all Control Bus register contents to zero or de-

fault values.

4.3 LOOPBACK MODE

The PLAYER device provides three types of loopback tests:

Configuration Switch Loopback, Internal Loopback, and Ex-

ternal Loopback. These Loopback modes can be used to

test different portions of the device.

4.3.1 Configuration Switch Loopback

The Configuration Switch Loopback can be used to test the

data paths of the BMAC device(s) that are connected to the

PLAYER device before transmitting and receiving data

through the network.

In the Configuration Switch Loopback mode, the PLAYER

device performs the following functions:

Selects Port A PHY Request Data, Port B PHY Request

Data, or PHY Invalid to connect to Port A PHY Indicate

#

Data via the A IND Mux.

Ð

Selects Port A PHY Request Data, Port B PHY Request

#

Data, or PHY Invalid to connect to Port B PHY Indicate

Data via the B IND Mux.

Ð

Connects data from the Receiver Block to the Transmit-

ter Block via the Transmitter Mux. (The PLAYER device

Ð

#

is repeating incoming data from the media in the Configu-

ration Switch Loopback mode.)

TL/F/10386–43

FIGURE 4-1b. Configuration Switch

Loopback for DP83251

FIGURE 4-1.

See Figure 4-1a and 4-1b for block diagrams.

15

4.0 Modes of Operation (Continued)

Outputs Quiet symbols through the External Loopback

g

Data pins (LBD ).

#

4.3.2 Internal Loopback

The Internal Loopback mode can be used to test the func-

tionality of the PLAYER device and to test the data paths

between the PLAYER and BMAC devices before ring inser-

tion.

The level of the Quiet symbols transmitted through the

g

TXC pins is programmable through the Transmit Quiet

Level bit of the Mode Register.

The level of the Quiet symbols transmitted through the

g

LBD pins is always high, regardless of the Transmit Quiet

Level bit of the Mode Register.

When in the Internal Loopback mode, the PLAYER device

performs the following functions:

Directs the output data of the Transmitter Block to the

input of the Receiver Block through internal paths (see

Figure 2-1 PLAYER Device Block Diagram).

#

If both Internal Loopback and External Loopback modes are

selected, Internal Loopback mode will have priority over Ex-

ternal Loopback mode.

g

Ignores the PMD Data Indicate pins (RXD and RXC ),

#

See Figure 4-2 for a block diagram.

Outputs Quiet symbols through the PMD Data Request

g

pins (TXD ), and

TL/F/10386–16

FIGURE 4-2. Internal Loopback

16

4.0 Modes of Operation (Continued)

Outputs Quiet symbols through the PMD Data Request

g

pins (TXD ).

#

4.3.3 External Loopback

The External Loopback mode can be used to test the func-

tionality of the PLAYER device and to test the data paths

between the PLAYER, CRD, and BMAC devices before

transmitting and receiving data through the network.

The level of the Quiet symbols transmitted through the

g

TXC pins is programmable through the Transmit Quiet

Level bit of the Mode Register.

If both Internal Loopback and External Loopback modes are

selected, Internal Loopback mode will have priority over Ex-

ternal Loopback mode.

When in the External Loopback mode, the PLAYER device

performs the following functions:

Directs the output data of the Transmitter Block to the

g

#

See Figure 4-3 for a block diagram.

external Loopback Data pins (LBD ), which are normal-

ly connected to the Clock Recovery Device (see Figure

2. PLAYER Device Block Diagram).

TL/F/10386–17

FIGURE 4-3. External Loopback

17

4.0 Modes of Operation (Continued)

Data frames must be a minimum of three bytes long (in-

cluding the JK symbol pair). Smaller frames will cause

Elasticity Buffer errors.

#

4.4 CASCADE MODE

The PLAYER device can operate in the Cascade (parallel)

modeÐFigure 4-4Ðwhich is used in high bandwidth, point-

to-point data transfer applications. This is a non-FDDI mode

of operation.

Data frames must have a maximum size of 4500 bytes,

with a JK starting delimiter and a (T or R or S)x or x(T or

R or S) ending delimiter byte.

CONCEPTS

3. Due to the different clock rates, the JK symbol pair may

arrive at different times at each PLAYER device. The total

skew between the fastest and slowest cascaded PLAY-

ER devices receiving the JK starting delimiter must not

exceed 80 ns.

In the Cascade mode, multiple PLAYER devices are con-

nected together to provide data transfer at multiples of the

FDDI data rate. Two cascaded PLAYER devices provide a

data rate twice the FDDI data rate; three cascaded PLAYER

devices provide a data rate three times the FDDI data rate,

etc.

4. The first PLAYER device to receive a JK symbol pair will

present it to the host system and assert the Cascade

Ready signal. The PLAYER device will present one more

JK as it waits for the other PLAYER devices to recognize

their JK. The maximum number of consecutive JKs that

can be presented to the host is 2.

Multiple data streams are transmitted in parallel over each

pair of cascaded PLAYER devices. All data streams start

simultaneously and begin with the JK symbol pair on each

PLAYER device.

Data is synchronized at the receiver of each PLAYER de-

vice by the JK symbol pair. Upon receiving a JK symbol pair,

a PLAYER device asserts the Cascade Ready signal to indi-

cate the beginning of data reception.

5. The Cascade Start signal is set to 1 when all the cascad-

ed PLAYER devices release their Cascade Ready sig-

nals.

6. Bit 4 (CSE) of the Receive Condition Register B (RCRB)

is set to 1 if the Cascade Start signal (CS) is not set

before the second falling edge of clock signal LBC from

when Cascade Ready (CR) was released. CS has to be

set within approximately 80 ns of CR release. This condi-

tion signifies that not all cascaded PLAYERs have re-

ceived their respective JK symbol pair within the allowed

skew range.

The Cascade Ready signals of all PLAYER devices are

open drain ANDed together to create the Cascade Start

signal. The Cascade Start signal is used as the input to

indicate that all PLAYER devices have received the JK sym-

bol pair. Data is now being received at every PLAYER de-

vice and can be transferred from the cascaded PLAYER

devices to the host system.

See Figure 4-5 for more information.

7. If the JK symbols are corrupted in the point-to-point links,

some PLAYER devices may not report a Cascaded Syn-

chronization Error.

OPERATING RULES

When the PLAYER device is operating in Cascade mode,

the following rules apply:

8. To guarantee integrity of the interframe information, the

user must put at least 8 Idle symbol pairs between

frames. The PLAYER device will function properly with

only 4 Idle symbol pairs, however the interframe symbols

may be corrupted with random non-JK symbols.

1. Data integrity can be guaranteed if the worst case fiber

optic transmission skew between parallel fiber cables is

less than 40 ns. This amounts to about 785 meters of

fiber, assuming a 1% worst case variance.

The BMAC device could be used to provide required fram-

ing and optical FCS support.

2. Even though this is a non-FDDI application, the general

rules for FDDI frames must be obeyed.

18

4.0 Modes of Operation (Continued)

TL/F/10386–18

FIGURE 4-4. Parallel Transmission

TL/F/10386–19

FIGURE 4-5. Cascade Mode of Operation

Note: N is recommended to be less than 3 for this mode. See Application Note 679 for larger values of N.

19

5.0 Registers

The PLAYER device is initialized, configured, and monitored via 32 8-bit registers. These registers are accessible through the

Control Bus Interface.

Table 5-1 is a Register Summary List. Table 5-2 shows the contents of each register.

TABLE 5-1. Register Summary

Register

Address

Register

Symbol

Access Rules

Write

Always

Register Name

Read

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

MR

Mode Register

Always

CR

Configuration Register

Always

ICR

Interrupt Condition Register

Conditional

Always

ICMR

CTSR

IJTR

Interrupt Condition Mask Register

Current Transmit State Register

Injection Threshold Register

Conditional

Always

ISRA

Injection Symbol Register A

Always

ISRB

Injection Symbol Register B

Always

CRSR

RCRA

RCRB

RCMRA

RCMRB

NTR

Current Receive State Register

Receive Condition Register A

Receive Condition Register B

Receive Condition Mask Register A

Receive Condition Mask Register B

Noise Threshold Register

Write Reject

Conditional

Always

NPTR

CNCR

CNPCR

STR

Noise Prescale Threshold Register

Current Noise Count Register

Current Noise Prescale Count Register

State Threshold Register

Always

Write Reject

Always

SPTR

CSCR

CSPCR

LETR

CLECR

UDR

State Prescale Threshold Registger

Current State Count Register

Current State Prescale Count Register

Link Error Threshold Register

Current Link Error Count Register

User Definable Register

Always

Write Reject

Always

Write Reject

Always

IDR

Device ID Register

Write Reject

Always

CIJCR

ICCR

CTSCR

RCCRA

RCCRB

RR0

Current Injection Count Register

Interrupt Condition Comparison Register

Current Transmit State Comparison Register

Receive Condition Comparison Register A

Receive Condition Comparison Register B

Reserved Register 0

Always

Write Reject

RR1

Reserved Register 1

20

5.0 Registers (Continued)

TABLE 5-2. Register Content Summary

Bit Symbols

Register

Address

Register

Symbol

D7

RNRZ

BIE

D6

TNRZ

AIE

D5

TE

D4

TQL

D3

CM

D2

EXLB

BIS0

CCR

D1

ILB

D0

RUN

AIS0

DPE

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

MR

CR

TRS1

RCA

TRS0

LEMT

LEMTM

IC1

BIS1

AIS1

CPE

ICR

UDI

RCB

CWI

ICMR

CTSR

IJTR

UDIM

RES

RCBM

PRDPE

IJT6

RCAM

SE

CWIM

IC0

CCRM

TM2

CPEM

TM1

DPEM

TM0

IJT7

IIJ5

IJT4

IJT3

IJT2

IJT1

IJT0

ISRA

RES

IJS4

IJS3

IJS2

IJS1

IJS0

ISRB

RES

IJS9

IJS8

IJS7

IJS6

IJS5

CRSR

RCRA

RCRB

RCMRA

RCMRB

NTR

RES

LSU

LS2

LS1

LS0

LSUPI

RES

LSC

NT

NLS

MLS

HLS

QLS

NSD

ILS

SILS

EBOU

NTM

EBOUM

NT5

CSE

LSUPV

NLSM

LSUPVM

NT3

ALS

ST

LSUPIM

RES

LSCM

SILSM

NT6

NLSM

CSEM

NT4

HLSM

ALSM

NT2

QLSM

STM

NT1

NSDM

ILSM

NT0

RES

NPTR

CNCR

CNPCR

STR

NPT7

NCLSCD

CNPC7

RES

NPT6

CNC6

CNPC6

ST6

NPT5

CNC5

CNPC5

ST5

NPT4

CNC4

CNPC4

ST4

NPT3

CNC3

CNPC3

ST3

NPT2

CNC2

CNPC2

ST2

NPT1

CNC1

CNPC1

ST1

NPT0

CNC0

CNPC0

ST0

SPTR

CSCR

CSPCR

LETR

CLECR

UDR

SPT7

SCLSCD

CSPC7

LET7

LEC7

RES

SPT6

CSC6

CSPC6

LET6

LEC6

RES

SPT5

CSC5

CSPC5

LET5

LEC5

RES

SPT4

CSC4

CSPC4

LET4

LEC4

RES

SPT3

CSC3

CSPC3

LET3

LEC3

EB1

SPT2

CSC2

CSPC2

LET2

LEC2

EB0

SPT1

CSC1

CSPC1

LET1

LEC1

SB1

SPT0

CSC0

CSPC0

LET0

LEC0

SB0

IDR

DID7

DID6

IJC6

DID5

IJC5

DID4

IJC4

DID3

IJC3

DID2

IJC2

DID1

IJC1

DID0

IJC0

CIJCR

ICCR

CTSCR

RCCRA

RCCRB

RR1

IJC7

UDIC

RESC

LSUPIC

RESC

RES

RCBC

PRDPEC

LSCC

SILSC

RES

RCAC

SEC

LEMTC

IC1C

NLSC

CSEC

RES

CWIC

IC0C

MLSC

LSUPVC

RES

CCRC

TM2C

HLSC

ALSC

RES

CPEC

TM1C

QLSC

STC

DPEC

TM0C

NSDC

ILSC

RES

NTC

EBOUC

RES

RR2

RES

21

5.0 Registers (Continued)

MODE REGISTER (MR)

The Mode Register is used to initialize and configure the PLAYER device.

In order to minimize interruptions on the network, it is recommended that the PLAYER device first be put in STOP mode (i.e. set

the RUN bit to zero) before programming the Mode Register, the Configuration Register, or the Current Transmit State Register.

ACCESS RULES

ADDRESS

READ

WRITE

00h

Always

D7

D6

D5

TE

D4

TQL

D3

D2

D1

D0

RNRZ

TNRZ

CM

EXLB

ILB

RUN

Bit

Symbol

Description

D0

RUN

RUN /STOP

0: Enables the STOP mode. Refer to Section 4.2, STOP Mode of Operation, for more

information.

1: Normal Operation (i.e. RUN mode).

Note: The RUN bit is automatically set to 0 when the RST pin is asserted (i.e. set to ground).

D1

D2

D3

D4

ILB

INTERNAL LOOPBACK:

0: Disables Internal Loopback mode (i.e. normal operation).

1: Enables Internal Loopback mode.

Refer to Section 4.3, Loopback Mode of Operation, for more information.

EXLB

CM

EXTERNAL LOOPBACK

0: Disables External Loopback mode (i.e. normal operation).

1: Enables External Loopback mode.

Refer to Section 4.3, Loopback Mode of Operation, for more information.

CASCADE MODE:

0: Disables synchronization of cascaded PLAYER devices.

1: Enables the synchronization of cascaded PLAYER devices.

Refer to Section 4.4, Cascade Mode of Operation, for more information.

TQL

TRANSMIT QUIET LEVEL: This bit is used to program the transmission level of the Quiet

symbols.

0: Low level Quiet symbols are transmitted through the PMD Data Request pins

a e

b e

high).

(i.e. TXD

1: High level Quiet symbols are transmitted through the PMD Data Request pins

a e b e

low, TXD

(i.e. TXD

high, TXD

low).

D5

TE

TRANSMIT ENABLE: The TE bit controls the action of FOTX Enable (TXE) pin independent

of the current transmit mode. When TE is 0, the TXE output disables the optical transmitter;

when TE is 1, the optical transmitter is disabled during the Off Transmit Mode (OTM) and

enabled otherwise. The On and Off level of the TXE is dependent on the FOTX Enable Level

(TEL) pin to the PLAYER device. The following rules summarizes the output of TXE:

e

Off

(1) If TE

(2) If TE

(3) If TE

0, then TXE

1 and OTM, then TXE

1 and not OTM, then TXE

e

0ff

e

On.

D6

D7

TNRZ

RNRZ

TRANSMIT NRZ DATA:

0: Transmits data in Non-Return-To-Zero-Invert-On-Ones format.

1: Transmits data in Non-Return-To-Zero format.

RECEIVE NRZ DATA:

0: Receives data in Non-Return-To-Zero-Invert-On-Ones format.

1: Receives data in Non-Return-To-Zero format.

22

5.0 Registers (Continued)

CONFIGURATION REGISTER (CR)

The Configuration Register controls the Configuration Switch Block and enables/disables both the A and B Indicate output

ports.

Note that the B Indicate output port is offered only on the DP83255 (for Dual Attach Stations), and not in the DP83251 (for

Ð

Single Attach Stations).

For further information, refer to Section 3.3, Configuration Switch.

ACCESS RULES

ADDRESS

READ

WRITE

01h

Always

D7

BIE

D6

D5

D4

TRS0

D3

D2

D1

D0

AIE

TRS1

BIS1

BIS0

AIS1

AIS0

Bit

D0, D1

Symbol

Description

A INDICATE SELECTOR 0, 1 : The A Indicate Selector 0, 1 bits select one of the four

Ð

k

l

k

l

AIS0, AIS1

Ð

k

l

Configuration Switch data buses for the A Indicate output port (AIP, AIC, AID 7:0 ).

Ð

AIS1

AIS0

0

1

0

1

0

1

PHY Invalid Bus

Receiver Bus

A

B

Request Bus

Ð

k l k l

B INDICATE SELECTOR 0, 1 : The B Indicate Selector 0, 1 bits select one of the four

Ð Ð

D2, D3

BIS0, BIS1

k

l

Configuration Switch data buses for the B Indicate output port (BIP, BIC, BID 7:0 ).

Ð

BIS1

BIS0

0

1

0

1

0

1

PHY Invalid Bus

Receiver Bus

A

B

Request Bus

Ð

Note: Even though this bit can be set and/or cleared in the DP83251 (for Single Attach Stations), it will not affect

any I/Os since the DP83251 does not offer a B Indicate port.

Ð

k

l

k

TRANSMIT REQUEST SELECTOR 0, 1 : The Transmit Request Selector 0, 1 bits select

one of the four Configuration Switch data buses for the input to the Transmitter Block.

l

D4, D5

TRS0, TRS1

TRS1

TRS0

0

1

0

1

0

1

PHY Invalid Bus

Receiver Bus

A

B

Request Bus

Ð

k

l

Note: If the PLAYER device is in Active Transmit Mode (i.e. the Transmit Mode bits (TM 2:0 ) of the Current

Transmit State Register (CTSR) are set to 000) and the PHY Invalid Bus is selected, then the PLAYER device will

transmit a maximum of four Halt symbol pairs and then continuous Idle symbols due to the Repeat Filter.

D6

D7

AIE

BIE

A

INDICATE ENABLE:

Ð

0: Disables the A Indicate output port. The A Indicate port pins will be at TRI-STATE when

Ð

the port is disabled.

k

l

1: Enables the A Indicate output port (AIP, AIC, AID 7:0 ).

Ð

B

INDICATE ENABLE:

Ð

0: Disable the B Indicate output port. The B Indicate port pins will be at TRI-STATE

Ð

when the port is disabled.

k

l

1: Enables the B Indicate output port (BIP, BIC, BID 7:0 ).

Ð

Note: Even though this bit can be set and/or cleared in the DP83251 (for Single Attach Stations), it will not affect

any I/Os since the DP83251 does not offer a B Indicate port.

Ð

23

5.0 Registers (Continued)

INTERRUPT CONDITION REGISTER (ICR)

The Interrupt Condition Register records the occurrence of an internal error event, the detection of Line State, an unsuccessful

write by the Control Bus Interface, the expiration of an internal counter, or the assertion of one or more of the User Definable

Sense pins.

The Interrupt Condition Register will assert the Interrupt pin (INT) when one or more bits within the register are set to 1 and the

corresponding mask bits in the Interrupt Condition Mask Register (ICMR) are also set to 1.

ACCESS RULES

ADDRESS

READ

WRITE

02h

Always

Conditional

D7

D6

D5

D4

D3

D2

D1

D0

UDI

RCB

RCA

LEMT

CWI

CCR

CPE

DPE

Bit

Symbol

Description

PHY REQUEST DATA PARITY ERROR: This bit will be set to 1 when:

D0

DPE

Ð

(1) The PHY Request Data Parity Enable bit (PRDPE) of the Current Transmit State Register

(CTSR) is set to 1 and

(2) The Transmitter Block detects a parity error in the incoming PHY Request Data.

The source of the data can be from the PHY Invalid Bus, the Receiver Bus, the A Bus, or the

Ð

B

Bus of the Configuration Switch.

Ð

D1

D2

CPE

CCR

CONTROL BUS DATA PARITY ERROR: This bit will be set to 1 when:

e

(2) The Control Bus Interface detects a parity error in the incoming Control Bus Data

(1) The Control Bus Parity Enable pin is asserted (CBPE

V ) and

CC

k

l

(CBD 7:0 ) during a write cycle.

CONTROL BUS WRITE COMMAND REJECT: This bit will be set to 1 when an attempt to

write into one of the following read-only registers is made:

Current Receive State Register (Register 08, CRSR)

Current Noise Count Register (Register 0F, CNCR)

Current Noise Prescale Count Register (Register 10, CNPCR)

Current State Count Register (Register 13, CSCR)

Current State Prescale Count Register (Register 14, CSPCR)

Current Link Error Count Register (Register 16, CLECR)

Device ID Register (Register 18, IDR)

Current Injection Count Register (Register 19, CIJCR)

Reserved Register 0 (Register 1E, RR0)

Reserved Register 1 (Register 1F, RR1)

D3

CWI

CONDITIONAL WRITE INHIBIT: Set to 1 when bits within mentioned registers do not match

bits in compare register. This bit ensures that new (i.e. unread) data is not inadvertently

cleared while old data is being cleared through the Control Bus Interface.

This bit is set to 1 to prevent the setting or clearing of any bit within the following registers:

Interrupt Condition Register (Register 02, ICR)

Current Transmit State Register (Register 04, CTSR)

Receive Condition Register A (Register 09, RCRA)

Receive Condition Register B (Register 0A, RCRB)

when they differ from the value of the corresponding bit in the following registers respectively:

Interrupt Condition Compare Register (Register 1A, ICCR)

Current Transmit State Compare Register (Register 1B, CTSCR)

Receive Condition Compare Register A (Register 1C, RCCRA)

Receive Condition Compare Register B (Register 1D, RCCRB)

This bit must be cleared by software. Note that this differs from the BMAC device bit of the

same name.

24

5.0 Registers (Continued)

INTERRUPT CONDITION REGISTER (ICR) (Continued)

Bit

Symbol

Description

D4

LEMT

LINK ERROR MONITOR THRESHOLD: This bit is set to 1 when the internal 8-bit Link Error Monitor

Counter reaches zero. It will remain set until cleared by software.

e

Link Error Monitor Counter is initialized to zero.

During the reset process (i.e. RST

GND), the Link Error Monitor Threshold bit is set to 1 because the

D5

D6

D7

RCA

RCB

UDI

RECEIVE CONDITION A: This bit is set to 1 when:

(1) One or more bits in the Receive Condition Register A (RCRA) is set to 1 and

(2) The corresponding mask bits in the Receive Condition Mask Register A (RCMRA) are also set to 1.

In order to clear (i.e. set to 0) the Receive Condition A bit, the bits within the Receive Condition Register

A that are set to 1 must first be either cleared or masked.

RECEIVE CONDITION B: This bit is set to 1 when:

(1) One or more bits in the Receive Condition Register B (RCRB) is set to 1 and

(2) The corresponding mask bits in the Receive Condition Mask Register B (RCMRB) are also set to 1.

In order to clear (i.e. set to 0) the Receive Condition B bit, the bits within the Receive Condition Register

B that are set to 1 must first be either cleared or masked.

USER DEFINABLE INTERRUPT: This bit is set to 1 when one or both of the Sense Bits (SB0 or SB1) in

the User Definable Register (UDR) is set to 1.

In order to clear (i.e. set to 0) the User Definable Interrupt Bit, both Sense Bits must be set to 0.

25

5.0 Registers (Continued)

INTERRUPT CONDITION MASK REGISTER (ICMR)

The Interrupt Condition Mask Register allows the user to dynamically select which events will generate an interrupt.

e

1 and the corresponding mask bits in this register are also set to 1.

The Interrupt pin will be asserted (i.e. INT

GND) when one or more bits within the Interrupt Condition Register (ICR) are set to

This register is cleared (i.e. set to 0) and all interrupts are initially masked during the reset process.

ACCESS RULES

ADDRESS

READ

WRITE

03h

Always

D7

UDIM

D6

D5

D4

LEMTM

D3

D2

D1

D0

RCBM

RCAM

CWIM

CCRM

CPEM

DPEM

Bit

Symbol

Description

D0

DPEM

CPEM

CCRM

CWIM

LEMTM

RCAM

RCBM

UDIM

PHY REQUEST DATA PARITY ERROR MASK: The mask bit for the PHY Request Data Parity

Ð Ð Ð

Error bit (DPE) of Interrupt Condition Register (ICR).

D1

D2

D3

D4

D5

D6

D7

CONTROL BUS DATA PARITY ERROR MASK: The mask bit for the Control Bus Data Parity Error bit

(CPE) of the Interrupt Condition Register (ICR).

CONTROL BUS WRITE COMMAND REJECT MASK: The mask bit for the Control Bus Write

Command Reject bit (CCR) of the Interrupt Condition Register (ICR).

CONDITIONAL WRITE INHIBIT MASK: The mask bit for the Conditional Write Inhibit bit (CWI) of the

Interrupt Condition Register (ICR).

LINK ERROR MONITOR THRESHOLD MASK: The mask bit for the Link Error Monitor Threshold bit

(LEMT) of the Interrupt Condition Register (ICR).

RECEIVE CONDITION A MASK: The mask bit for the Receive Condition A bit (RCA) of the Interrupt

Condition Register (ICR).

RECEIVE CONDITION B MASK: The mask bit for the Receive Condition B bit (RCB) of the Interrupt

Condition Register (ICR).

USER DEFINABLE INTERRUPT MASK: The mask bit for the User Definable Interrupt bit (UDI) of the

Interrupt Condition Register (ICR).

26

5.0 Registers (Continued)

CURRENT TRANSMIT STATE REGISTER (CTSR)

The Current Transmit State Register can program the Transmitter Block to internally generate and transmit Idle, Master, Halt,

Quiet, or user programmable symbol pairs, in addition to the normal transmission of incoming PHY Request data. The Smoother

and PHY Request Data Parity may also be enabled and disabled through this register.

The Transmit Modes overwrite the Repeat Filter and Smoother outputs, while the Injection Symbols overwrite the Transmit

Modes.

k

l

e

is set to 1), and the Reserved bit (b7) is set to 1. All other bits of this register are cleared (i.e. set to 0) during the reset process.

e

During the reset process (i.e. RST

GND) the Transmit Mode is set to Off (TM 2:0

010), the Smoother is enabled (i.e. SE

ACCESS RULES

ADDRESS

READ

WRITE

04h

Always

Conditional

D7

D6

D5

D4

D3

D2

D1

D0

RES

PRDPE

SE

IC1

IC0

TM2

TM1

TM0

Bit

Symbol

Description

k l

Transmit Mode 0, 1, 2 : These bits select one of the 6 transmission modes for the PMD Request

g

Data output port (TXD ).

D0, D1,

D2

TM0, TM1,

TM2

TM1

TM0

0

Active Transmit Mode (ATM): Normal

transmission of incoming PHY Request data.

0

1

0

Idle Transmit Mode (ITM): Transmission of

Idle symbol pairs (11111 11111).

Off Transmit Mode (OTM): Transmission of

Quiet symbol pairs (00000 00000) and

deassertion of the FOTX Enable pin (TXE).

0

1

0

1

0

Reserved: Reserved for future use. Users

are discouraged from using this transmit

mode. If selected, however, the transmitter

will generate Quiet symbol pairs (00000

00000).

Master Transmit Mode (MTM):

Transmission of Halt and Quiet symbol pairs

(00100 00000).

1

0

1

0

1

Halt Transmit Mode (HTM): Transmission of

Halt symbol pairs (00100 00100).

Quiet Transmit Mode (QTM): Transmission

of Quiet symbol pairs (00000 00000).

Reserved: Reserved for future use. Users

are discouraged from using this transmit

mode. If selected, however, the transmitter

will generate Quiet symbol pairs (00000

00000).

27

5.0 Registers (Continued)

CURRENT TRANSMIT STATE REGISTER (CTSR) (Continued)

Bit

Symbol

Description

k

l

Injection Control 0, 1 : These bits select one of the 4 injection modes. The injection modes

overwrite data from the Smoother, Repeat Filter, Encoder, and Transmit Modes.

D3, D4

IC0, IC1

IC0 is the only bit of the register that is automatically cleared by the PLAYER device after the One Shot

Injection is executed. The automatic clear of IC0 during the One Shot mode can be interpreted as an

acknowledgment that the One Shot has been completed.

IC1

IC0

0

No Injection: The normal transmission of

incoming PHY Request data (i.e. symbols are

not injected).

0

1

One Shot: In one shot mode, Injection

Symbol Register A (ISRA) and Injection

Symbol Register B (ISRB) are injected n

symbol pairs after a JK, where n is the

programmed value of the Injection Count

Register (IJCR). If IJCR is set to 0, the JK

symbol pair is replaced by ISRA and ISRB.

Once the One Shot is executed, the PLAYER

device automatically sets IC0 to 0, thereby

returning to normal transmission of data.

1

0

Periodic: In Periodic mode, Injection Symbol

Register A (ISRA) and Injection Symbol

a

Register B (ISRB) are injected every (n 1)th

symbol pair, where n is the programmed

value of the Injection Count Register (IJCR).

If IJCR is set to 0, all data symbols are

replaced with ISRA and ISRB.

1

Continuous: In Continuous mode, all data

symbols are replaced with Injection Symbol

Register A (ISRA) and Injection Symbol

Register B (ISRB).

D5

SE

SMOOTHER ENABLE:

0: Disables the Smoother.

1: Enables the Smoother.

When enabled, the Smoother can redistribute Idle symbol pairs which were added or deleted by

the local or upstream receivers.

Note: Once the counter has started, it will continue to count irrespective of the incoming symbols with the exception of a

JK symbol pair. This bit should be enabled for interoperable operation.

D6

D7

PRDPE

RES

PHY REQUEST DATA PARITY ENABLE:

Ð

0: Disables PHY Request Data parity.

Ð

1: Enables PHY Request Data parity.

Ð

RESERVED: Reserved for future use.

Note: Users are discouraged from using this bit. The reserved bit is set to 1 during the reset process. It may be set or

cleared without any effects to the functionality of the PLAYER device.

28

5.0 Registers (Continued)

INJECTION THRESHOLD REGISTER (IJTR)

k

l

The Injection Threshold Register, in conjunction with the Injection Control bits (IC 1:0 ) in the Current Transmit State Register

(CTSR), set the frequency at which the Injection Symbol Register A (ISRA) and Injection Symbol Register B (ISRB) are inserted

into the data stream. It contains the start value for the Injection Counter.

The Injection Threshold Register value is loaded into the Injection Counter when the counter reaches zero or during every

Control Bus Interface write-cycle of this register.

The Injection Counter is an 8-bit down-counter which decrements every 80 ns. Its current value is read for CIJCR.

k

l

k

l

The counter is active only during One Shot or Periodic Injection Modes (i.e. Injection Control 1:0 bits (IC 1:0 ) of the

Current Transmit State Register (CTSR) are set to either 01 or 10). The Transmitter Block will replace a data symbol pair with

ISRA and ISRB when the counter reaches 0 and the Injection Mode is either One Shot or Periodic.

If the Injection Threshold Register is set to 0 during the One Shot mode, the JK will be replaced with ISRA and ISRB. If the

Injection Threshold Register is set to 0 during the Periodic mode, all data symbols are replaced with ISRA and ISRB.

e

The counter is initialized to 0 during the reset process (i.e. RST

GND).

For further information, see the Injection Control Logic subsection within Section 3.2.

ACCESS RULES

ADDRESS

READ

WRITE

05h

Always

D7

D6

D5

D4

IJT4

D3

D2

D1

D0

IJT7

IJT6

IJT5

IJT3

IJT2

IJT1

IJT0

Bit

Symbol

Description

k

l

: Least significant bit (LSB) of the start

D0

IJT0

INJECTION THRESHOLD BIT

0

value for the Injection Counter.

k

l

INJECTION THRESHOLD BIT 1–6 : Intermediate bits of start value for the

D1–6

D7

IJT1–6

IJT7

Injection Counter.

k

l

: Most significant bit (MSB) of the start

INJECTION THRESHOLD BIT

7

value for the Injection Counter.

29

5.0 Registers (Continued)

INJECTION SYMBOL REGISTER A (ISRA)

The Injection Symbol Register A, along with Injection Symbol Register B, contains the programmable value (already in 5B code)

that will replace the data symbol pairs.

The One Shot mode, ISRA and ISRB are injected n bytes after the next JK, where n is the programmed value of the Injection

Threshold Register. In the Periodic mode, ISRA and ISRB are injected every nth symbol pair. In the Continuous mode, all data

symbols are replaced with ISRA and ISRB.

ACCESS RULES

ADDRESS

READ

WRITE

06h

Always

D7

D6

D5

D4

IJS4

D3

D2

D1

D0

RES

IJS3

IJS2

IJS1

IJS0

Bit

Symbol

Description

k

l

: Least significant bit (LSB) of Injection

D0

IJS0

INJECTION THRESHOLD BIT

0

Symbol Register A.

k

l

INJECTION THRESHOLD BIT 1–3 : Intermediate bits of Injection Symbol

D1–3

D4

IJS1–3

IJS4

Register A.

k

l

: Most significant bit (MSB) of Injection

INJECTION THRESHOLD BIT

4

Symbol Register A.

D5

RES

RESERVED: Reserved for future use.

Note: Users are discouraged from using this bit. The reserved bit is set to 1 during the reset

process. It may be set or cleared without any effects to the functionality of the PLAYER

device.

D6

D7

RES

RESERVED: Reserved for future use.

Note: Users are discouraged from using this bit. The reserved bit is set to 1 during the reset

process. It may be set or cleared without any effects to the functionality of the PLAYER

device.

RESERVED: Reserved for future use.

Note: Users are discouraged from using this bit. The reserved bit is set to 1 during the reset

process. It may be set or cleared without any effects to the functionality of the PLAYER

device.

30

5.0 Registers (Continued)

INJECTION SYMBOL REGISTER B (ISRB)

The Injection Symbol Register B, along with Injection Symbol Register A, contains the programmable value (already in 5B code)

that will replace the data symbol pairs.

The One Shot mode, ISRA and ISRB are injected n bytes after the next JK, where n is the programmed value of the Injection

Threshold Register. In the Periodic mode, ISRA and ISRB are injected every nth symbol pair. In the Continuous mode, all data

symbols are replaced with ISRA and ISRB.

ACCESS RULES

ADDRESS

READ

WRITE

07h

Always

D7

D6

D5

D4

IJS9

D3

D2

D1

D0

RES

IJS8

IJS7

IJS6

IJS5

Bit

Symbol

Description

k

l

: Least significant bit (LSB) of Injection

D0

IJS5

INJECTION THRESHOLD BIT

5

Symbol Register B.

k

l

INJECTION THRESHOLD BIT 6–8 : Intermediate bits of Injection Symbol

D1–3

D4

IJS6–8

IJS9

Register B.

k

l

: Most significant bit (MSB) of Injection

INJECTION THRESHOLD BIT

9

Symbol Register B.

D5

RES

RESERVED: Reserved for future use.

Note: Users are discouraged from using this bit. The reserved bit is set to 1 during the reset

process. It may be set or cleared without any effects to the functionality of the PLAYER

device.

D6

D7

RES

RESERVED: Reserved for future use.

Note: Users are discouraged from using this bit. The reserved bit is set to 1 during the reset

process. It may be set or cleared without any effects to the functionality of the PLAYER

device.

RESERVED: Reserved for future use.

Note: Users are discouraged from using this bit. The reserved bit is set to 1 during the reset

process. It may be set or cleared without any effects to the functionality of the PLAYER

device.

31

5.0 Registers (Continued)

CURRENT RECEIVE STATE REGISTER (CRSR)

The Current Receive State Register represents the current line state being detected by the Receiver Block. Once the Receiver

Block recognizes a new Line State, the bits corresponding to the previous line state are cleared, and the bits corresponding to

the new line state are set.

e

During the reset process (RST

(LSU) is set to 1).

GND), the Receiver Block is forced to Line State Unknown (i.e. the Line State Unknown bit

ACCESS RULES

ADDRESS

READ

Always

WRITE

08h

Write Reject

D7

D6

D5

RES

D4

D3

D2

D1

D0

RES

LSU

LS2

LS1

LS0

Bit

Symbol

Description

k

l

D0, D1

D2

LS0, LS1,

LS2

LINE STATE 0, 1, 2 : These bits represent the current Line State being detected by the Receiver

Block. Once the Receiver Block recognizes a new line state, the bits corresponding to the previous

line state are cleared, and the bits corresponding to the new line state are set.

LS2

LS1

LS0

0

Active Line State (ALS): Received a JK

symbol pair (11000 10001), and possibly

followed by data symbols.

0

1

0

Idle Line State (ILS): Received a minimum

of two consecutive Idle symbol pairs (11111

11111).

No Signal Detect (NSD): The Signal Detect

pin (TTLSD) has been deasserted, indicating

that the Clock Recovery Device is not

receiving data from the Fiber Optic Receiver.

0

1

0

1

0

Reserved: Reserved for future use.

Master Line State (MLS): Received a

minimum of 8 consecutive Halt-Quiet symbol

pairs (00100 00000).

1

0

1

0

1

Halt Line State (HLS): Received a minimum

of 8 consecutive Halt symbol pairs (00100

00100).

Quiet Line State (QLS): Received a

minimum of 8 consecutive Quiet symbol pairs

(00000 00000).

Noise Line State (NLS): Detected a

minimum of 16 noise events. Refer to the

Receiver Block for further information on

noise events.

D3

D4

LSU

RES

LINE STATE UNKNOWN: The Receiver Block has not detected the minimum conditions to enter a

l

k

known line state. When the Line State Unknown bit is set, LS 2:0 represent the most recently

known line state.

RESERVED: Reserved for future use. The reserved bit is set to 0.

Note: Users are discouraged from using this bit. An attempt to write into this bit will cause the PLAYER device to ignore

the Control Bus write cycle and set the Control Bus Write Command Reject bit (CCR) of the Interrupt Condition

Register (ICR) to 1.

32

5.0 Registers (Continued)

CURRENT RECEIVE STATE REGISTER (CRSR) (Continued)

Bit

Symbol

Description

D5

RES

RESERVED: Reserved for future use. The reserved bit is set to 0.

Note: Users are discouraged from using this bit. An attempt to write into this bit will cause the PLAYER device to ignore the

CBUS write cycle and set the Control Bus Write Command Reject bit (CCR) of the Interrupt Condition Register (ICR) to 1.

D6

D7

RES

RESERVED: Reserved for future use. The reserved bit is set to 0.

Note: Users are discouraged from using this bit. An attempt to write into this bit will cause the PLAYER device to ignore the

CBUS write cycle and set the Control Bus Write Command Reject bit (CCR) of the Interrupt Condition Register (ICR) to 1.

RESERVED: Reserved for future use. The reserved bit is set to 0.

Note: Users are discouraged from using this bit. An attempt to write into this bit will cause the PLAYER device to ignore the

CBUS write cycle and set the Control Bus Write Command Reject bit (CCR) of the Interrupt Condition Register (ICR) to 1.

33

5.0 Registers (Continued)

RECEIVE CONDITION REGISTER A (RCRA)

The Receive Condition Register A maintains a historical record of the Line States recognized by the Receiver Block.

When a new Line State is entered, the bit corresponding to that line state is set to 1. The bits corresponding to the previous Line

States are not cleared by the PLAYER device, thereby maintaining a record of the Line States detected.

The Receive Condition A bit (RCA) of the Interrupt Condition Register (ICR) will be set to 1 when one or more bits within the

Receive Condition Register A is set to 1 and the corresponding mask bit(s) in Receive Condition Mask Register A (RCMRA) is

also set to 1.

ACCESS RULES

ADDRESS

READ

WRITE

09h

Always

Conditional

D7

D6

D5

NT

D4

D3

D2

D1

D0

LSUPI

LSC

NLS

MLS

HLS

QLS

NSD

Bit

Symbol

NSD

Description

D0

NO SIGNAL DETECT: Indicates that the Signal Detect pin (TTLSD) has been

deasserted and that the Clock Recovery Device is not receiving data from the

Fiber Optic Receiver.

D1

D2

D3

QLS

HLS

MLS

QUIET LINE STATE: Received a minimum of eight consecutive Quiet symbol

pairs (00000 00000).

HALT LINE STATE: Received a minimum of eight consecutive Halt symbol

pairs (00100 00100).

MASTER LINE STATE: Received a minimum of eight consecutive Halt-Quiet

symbol pairs (00100 00000).

D4

D5

NLS

NT

NOISE LINE STATE: Detected a minimum of sixteen noise events.

NOISE THRESHOLD: This bit is set to 1 when the internal Noise Counter

reaches 0. It will remain set until a value equal to or greater than one is

loaded into the Noise Threshold Register or Noise Prescale Threshold

Register.

e

initialized to 0, the Noise Threshold bit will be set to 1.

During the reset process (i.e. RST

GND), since the Noise Counter is

D6

D7

LSC

LINE STATE CHANGE: A line state change has been detected.

LSUPI

LINE STATE UNKNOWN & PHY INVALID: The Receiver Block has not

detected the minimum conditions to enter a known line state.

In addition, the most recently known line state was one of the following line

states: No Signal Detect, Quiet Line State, Halt Line State, Master Line State,

or Noise Line State.

34

5.0 Registers (Continued)

RECEIVE CONDITION REGISTER B (RCRB)

The Receive Condition Register B maintains a historical record of the Line States recognized by the Receiver Block.

When a new Line State is entered, the bit corresponding to that line state is set to 1. The bits corresponding to the previous Line

States are not clear by the PLAYER device, thereby maintaining a record of the Line States detected.

The Receive Condition B bit (RCB) of the Interrupt Condition Register (ICR) will be set to 1 when one or more bits within the

Receive Condition Register B is set to 1 and the corresponding mask bits in Receive Condition Mask Register B (RCMRB) is

also set to 1.

ACCESS RULES

ADDRESS

READ

WRITE

0Ah

Always

Conditional

D7

D6

D5

D4

D3

D2

D1

D0

RES

SILS

EBOU

CSE

LSUPV

ALS

ST

ILS

Bit

Symbol

ILS

Description

D0

IDLE LINE STATE: Received a minimum of two consecutive Idle symbol

pairs (11111 11111).

D1

ST

STATE THRESHOLD: This bit will be set to 1 by the PLAYER device when

the internal State Counter reaches zero. It will remain set until a value equal

to or greater than one is loaded into the State Threshold Register or State

Prescale Threshold Register, and this register is cleared.

e

initialized to 0, the State Threshold bit is set to 1.

During the reset process (i.e. RST

GND), since the State Counter is

D2

D3

ALS

ACTIVE LINE STATE: Received a JK symbol pair (11000 10001), and

possibly data symbols following.

LSUPV

LINE STATE UNKNOWN & PHY VALID: Receiver Block has not detected

the minimum conditions to enter a know line state when the most recently

known line state was one of the following line states: Active Line State or Idle

Line State

D4

D5

CSE

CASCADE SYNCHRONIZATION ERROR: When a synchronization error

occurs, the Cascade Synchronization Error bit is set to 1.

A synchronization error occurs if the Cascade Start signal (CS) is not asserted

within approximately 80 ns of Cascade Ready (CR) release.

EBOU

ELASTICITY BUFFER UNDERFLOW/OVERFLOW: The Elasticity Buffer

has either overflowed or underflowed. The Elasticity Buffer will automatically

recover if the condition which caused the error is only transient.

D6

D7

SILS

RES

SUPER IDLE LINE STATE: Received a minimum of eight Idle symbol pairs

(11111 11111).

RESERVED: Reserved for future use. The reserved bit is set to 0 during the

reset process.

Note: Users are discouraged from using this bit. It may be set or cleared without any

effects to the functionality of the PLAYER device.

35

5.0 Registers (Continued)

RECEIVE CONDITION MASK REGISTER A (RCMRA)

The Receive Condition Mask Register A allows the user to dynamically select which events will generate an interrupt.

The Receive Condition A bit (RCA) of the Interrupt Condition Register (ICR) will be set to 1 when one or more bits within the

Receive Condition Register A (RCRA) is set to 1 and the corresponding mask bit(s) in this register is also set to 1.

Since this register is cleared (i.e. set to 0) during the reset process, all interrupts are initially masked.

ACCESS RULES

ADDRESS

READ

WRITE

0Bh

Always

D7

D6

D5

D4

NLSM

D3

D2

D1

D0

LSUPIM

LSCM

NTM

MLSM

HLSM

QLSM

NSDM

Bit

Symbol

NSDM

Description

D0

NO SIGNAL DETECT MASK: The mask bit for the No Signal Detect bit (NSD)

of the Receive Condition Register A (RCRA).

D1

D2

D3

D4

D5

D6

D7

QLSM

HLSM

MLSM

NLSM

NTM

QUIET LINE STATE MASK: The mask bit for the Quiet Line State bit (QLS) of

the Receive Condition Register A (RCRA).

HALT LINE STATE MASK: The mask bit for the Halt Line State bit (HLS) of

the Receive Condition Register A (RCRA).

MASTER LINE STATE MASK: The mask bit for the Master Line State bit

(MLS) of the Receive Condition Register A (RCRA).

NOISE LINE STATE MASK: The mask bit for the Noise Line State bit (NLS)

of the Receive Condition Register A (RCRA)

NOISE THRESHOLD MASK: The mask bit for the Noise Threshold bit (NT) of

the Receive Condition Register A (RCRA).

LSCM

LSUPIM

LINE STATE CHANGE MASK: The mask bit for the Line State Change bit

(LSC) of the Receive Condition Register A (RCRA).

LINE STATE UNKNOWN & PHY INVALID MASK: The mask bit for the line

State Unknown & PHY Invalid bit (LSUPI) of the Receive Condition Register A

(RCRA).

36

5.0 Registers (Continued)

RECEIVE CONDITION MASK REGISTER B (RCMRB)

The Receive Condition Mask Register B allows the user to dynamically select which events will generate an interrupt.

The Receiver Condition B bit (RCB) of the Interrupt Condition Register (ICR) will be set to 1 when one or more bits within the

Receive Condition B (RCRA) is set to 1 and the corresponding mask bits in this register is also set to 1.

Since this register is cleared (i.e. set to 0) during the reset process, all interrupts are initially masked.

ACCESS RULES

ADDRESS

READ

WRITE

0Ch

Always

D7

RES

D6

D5

D4

CSEM

D3

D2

D1

D0

SILSM

EBOUM

LSUPVM

ALSM

STM

ILSM

Bit

Symbol

ILSM

Description

D0

IDLE LINE STATE MASK: The mask bit for the Idle Line State bit (ILS) of the

Receive Condition Register B (RCRB).

D1

D2

D3

STM

STATE THRESHOLD MASK: The mask bit of the State Threshold bit (ST) of

the Receive Condition Register B (RCRB).

ALSM

LSUPVM

ACTIVE LINE STATE MASK: The mask bit for the Active Line State bit (ALS)

of the Receive Condition Register B (RCRB).

LINE STATE UNKNOWN & PHY VALID MASK: The mask bit for the Line

State Unknown & PHY Valid bit (LSUPV) of the Receive Condition Register B

(RCRB).

D4

D5

CSEM

CASCADE SYNCHRONIZATION ERROR MASK: The mask bit for the

Cascade Synchronization Error bit (CSE) of the Receive Condition Register B

(RCRB).

EBOUM

ELASTICITY BUFFER OVERFLOW/UNDERFLOW MASK: The mask bit for

the Elasticity Buffer Overflow/Underflow bit (EBOU) of the Receive Condition

Register B (RCRB).

D6

D7

SILSM

RESM

SUPER IDLE LINE STATE MASK: The mask bit for the Super Idle Line State

bit (SILS) of the Receive Condition Register B (RCRB).

RESERVED MASK: The mask bit for the Reserved bit (RES) of the Receive

Condition Register B (RCRB).

37

5.0 Registers (Continued)

NOISE THRESHOLD REGISTER (NTR)

The Noise Threshold Register contains the start value for the Noise Counter. This counter may be used in conjunction with the

Noise Prescale Counter for counting the Noise events. Definiton of Noise event is explained in detail in Section 8.2. The Noise

Counter decrements once every 80 ns if the noise Prescale counter is zero and there is a noise event. As a result, the internal

noise counter takes

a

((NPTR 1) x (NTR 1)) x 80 ns

to reach zero in the event of continuous Noise event.

The threshold values for the Noise Counter and Noise Prescale Counter are simultaneously loaded into both counters if one of

the following conditions is true:

(1) Both the Noise Counter and Noise Prescale Counter reach zero and the current Line State is either Noise Line State, Active

Line State, or Line State Unknown.

or

(2) The current Line State is either Halt Line State, Idle Line State, Master Line State, Quiet Line State, or No Signal Detect

or

(3) The Noise Threshold Register or Noise Prescale Threshold Register goes through a Control Bus Interface write cycle.

In addition, the value of the Noise Prescale Threshold register is loaded into the Noise Prescale Counter if the Noise Prescale

Counter reaches zero.

The Noise Counter and Noise Prescale Counter will continue to count, without resetting or reloading the threshold values, if a

Line State change occurs and the new line state is either Noise Line State, Active Line State or Line State Unknown.

When both the Noise Threshold Counter and Noise Counter both reach zero, the Noise Threshold bit of the Receive Condition

Register A will be set.

ACCESS RULES

ADDRESS

READ

WRITE

0Dh

Always

D7

D6

D5

D4

NT4

D3

D2

D1

D0

NT7

NT6

NT5

NT3

NT2

NT1

NT0

Bit

Symbol

Description

k

l

: Least significant bit (LSB) of the start value

D0

NT0

NOISE THRESHOLD BIT

0

for the Noise Counter.

k

l

NOISE THRESHOLD BIT 1–5 : Intermediate bits of start value for the

D1–5

D6

NT1–5

NT6

Noise Counter.

k

l

: Most significant bit (MSB) of the start value

NOISE THRESHOLD BIT

6

for the Noise Counter.

D7

RES

RESERVED: Reserved for future use.

Note: Users are discouraged from using this bit. Write data is ignored since the reserved

bit is permanently set to 0.

38

5.0 Registers (Continued)

NOISE PRESCALE THRESHOLD REGISTER (NPTR)

The Noise Prescale Threshold Register contains the start value for the Noise Prescale Counter. The Noise Prescale Counter is a

count-down counter and it is used in conjunction with the Noise Counter for counting the Noise events. The Noise Prescale

Counter decrements once every 80 ns while there is a noise event. When the Noise Prescale Counter reaches zero, it reloads

the count with the content of the Noise Prescale Threshold Register and also causes the Noise Counter to decrement.

The threshold values for the Noise Counter and Noise Prescale Counter are simultaneously loaded into both counters if one of

the following conditions is true:

(1) Both the Noise Counter and Noise Prescale Counter reach zero and the current Line State is either Noise Line State, Active

Line State, or Line State Unknown.

or

(2) The current Line State is either Halt Line State, Idle Line State, Master Line State, Quiet Line State, or No Signal Detect

or

(3) The Noise Threshold Register or Noise Prescale Threshold Register goes through a Control Bus Interface write cycle.

In addition, the value of the Noise Prescale Threshold register is loaded into the Noise Prescale Counter if the Noise Prescale

Counter reaches zero.

The Noise Counter and Noise Prescale Counter will continue to count, without resetting or reloading the threshold values, if a

Line State change occurs and the new line state is either Noise Line State, Active Line State, or Line State Unknown.

When both the Noise Threshold Counter and Noise Counter both reach zero, the Noise Threshold bit of the Receive Condition

Register A will be set.

ACCESS RULES

ADDRESS

READ

WRITE

0Eh

Always

D7

D6

D5

D4

NPT4

D3

D2

D1

D0

NPT7

NPT6

NPT5

NPT3

NPT2

NPT1

NPT0

Bit

Symbol

NPT0

Description

k

l

: Least significant bit (LSB) of the

D0

NOISE PRESCALE THRESHOLD BIT

0

start value of the Noise Prescale Counter.

k

l

NOISE PRESCALE THRESHOLD BIT 1–6 : Intermediate bits of start

D1–6

D7

NPT1–6

value for the Noise Prescale Counter.

k

l

: Most significant bit (MSB) of the

NPT7

NOISE PRESCALE THRESHOLD BIT

7

start value for the Noise Prescale Counter.

39

5.0 Registers (Continued)

CURRENT NOISE COUNT REGISTER (CNCR)

The Current Noise Count Register takes a snap-shot of the Noise Counter during every Control Bus Interface read-cycle of this

register.

During a Control Bus Interface write-cycle to the Current Noise Count Register, the PLAYER device will set the Control Bus

Write Command Reject bit (CCR) of the Interrupt Condition Register (ICR) to 1 and will ignore a write-cycle.

ACCESS RULES

ADDRESS

READ

WRITE

0Fh

Always

Write Reject

D7

D6

D5

CNC5

D4

D3

D2

D1

D0

NCLSCD

CNC6

CNC4

CNC3

CNC2

CNC1

CNC0

Bit

D0–6

D7

Symbol

Description

k l

CURRENT NOISE COUNT BIT 0–6

CNC0–6

NCLSCD

NOISE COUNTER LINE STATE CHANGE DETECTION

40

5.0 Registers (Continued)

CURRENT NOISE PRESCALE COUNT REGISTER (CNPCR)

The Current Noise Prescale Count Register takes a snap-shot of the Noise Prescale Counter during every Control Bus Interface

read-cycle of this register.

During a Control Bus Interface write-cycle to the Current Noise Prescale Count Register, the PLAYER device will set the Control

Bus Write Command Reject bit (CCR) of the Interrupt Condition Register (ICR) to 1 and will ignore a write-cycle.

ACCESS RULES

ADDRESS

READ

WRITE

10h

Always

Write Reject

D7

D6

D5

D4

D3

D2

D1

D0

CNPC7

CNPC6

CNPC5

CNPC4

CNPC3

CNPC2

CNPC1

CNPC0

Bit

Symbol

Description

k

CURRENT NOISE PRESCALE COUNT BY 0–7

l

D0–7

CNPC0–7

41

5.0 Registers (Continued)

STATE THRESHOLD REGISTER (STR)

The State Threshold Register contains the start value of the State Counter. This counter is used in conjunction with the State

Prescale Counter to count the Line State duration. The State Counter will decrement every 80 ns if the State Prescale Counter is

zero and the current Line State is Halt Line, Idle Line State, Master Line State, Quiet Line State, or No Signal Detect. State The

State Counter takes

a

((SPTR 1) x (STR 1)) x 80 ns

to reach zero during a continuous line state condition.

The threshold values for the State Counter and State Prescale Counter are simultaneously loaded into both counters if one of

the following conditions is true:

(1) Both the State Counter and State Prescale Counter reach zero and the current Line State is Halt Line State, Idle Line State,

Master Line State, Quiet Line State, or No Signal Detect

or

(2) A line state change occurs and the new Line State is Halt Line State, Idle Line State, Master Line State, Quiet Line State, or

No Signal Detect

or

(3) The State Threshold Register or State Prescale Threshold Register goes through a Control Bus Interface write cycle.

In addition, the value of the State Prescale Threshold register is loaded into the State Prescale Counter if the State Prescale

Counter reaches zero.

The State Counter and State Prescale Counter will reset by reloading the threshold values, if a Line State change occurs and the

new Line State is Halt Line State, Idle Line State, Master Line State, Quiet Line State, or No Signal Detect.

ACCESS RULES

ADDRESS

READ

WRITE

11h

Always

D7

D6

D5

D4

ST4

D3

D2

D1

D0

ST7

ST6

ST5

ST3

ST2

ST1

ST0

Bit

Symbol

Description

k

l

: Least significant bit (LSB) of the start value

D0

ST0

STATE THRESHOLD BIT

0

for the State Counter.

k

l

STATE THRESHOLD BIT 1–5 : Intermediate bits of start value for the

D1–5

D6

ST1–5

ST6

State Counter.

k

l

: Most significant bit (MSB) of the start value

STATE THRESHOLD BIT

6

for the State Counter.

D7

RES

RESERVED: Reserved for future use.

Note: Users are discouraged from using this bit. Write data is ignored since the reserved

bit is permanently set to 0.

42

5.0 Registers (Continued)

STATE PRESCALE THRESHOLD REGISTER (SPTR)

The State Prescale Threshold Register contains the start value for the State Prescale Counter. The State Prescale Counter is a

down counter. The Register is used in conjunction with the State Counter to count the Line State duration.

The State Prescale Counter will decrement every 80 ns if the current Line State is Halt Line, Idle Line State, Master Line State,

Quiet Line State, or No Signal Detect. As a result, the State Prescale Counter takes SPTR x 80 ns to reach zero during a

continuous line state condition. When the State Prescale Counter reaches zero, the State Prescale Threshold Register will be

reloaded into the State Prescale Counter.

The threshold values for the State Counter and State Prescale Counter are simultaneously loaded into both counters if one of

the following conditions is true:

(1) Both the State Counter and State Prescale Counter reach zero and the current Line State is Halt Line State, Idle Line State,

Master Line State, Quiet Line State, or No Signal Detect.

or

(2) A Line State change occurs and the new Line State is Halt Line State, Idle Line State, Master Line State, Quiet Line State, or

No Signal Detect

or

(3) The State Threshold Register or State Prescale Threshold Register goes through a Control Bus Interface write cycle.

The State Counter and State Prescale Counter will reset by reloading the threshold values, if a Line State change occurs and the

new Line State is Halt Line State, Idle Line State, Master Line State, Quiet Line State, or No Signal Detect.

ACCESS RULES

ADDRESS

READ

WRITE

12h

Always

D7

D6

D5

D4

SPT4

D3

D2

D1

D0

SPT7

SPT6

SPT5

SPT3

SPT2

SPT1

SPT0

Bit

Symbol

Description

k

l

: Least significant bit (LSB) of

D0

SPT0

STATE PRESCALE THRESHOLD BIT

0

the start value for the State Prescale Counter.

k

l

STATE PRESCALE THRESHOLD BIT 1–6 : Intermediate bits of start

D1–6

D7

SPT1–6

SPT7

value for the State Prescale Counter.

k

l

: Most significant bit (MSB) of

STATE PRESCALE THRESHOLD BIT

7

the start value for the State Prescale Counter.

43

5.0 Registers (Continued)

CURRENT STATE COUNT REGISTER (CSCR)

The Current State Count Register takes a snap-shot of the State Counter during every Control Bus Interface read-cycle of this

register.

During a Control Bus Interface write-cycle to the Current State Count Register, the PLAYER device will set the Control Bus Write

Command Reject bit (CCR) of the Interrupt Condition Register (ICR) to 1 and will ignore a write-cycle.

ACCESS RULES

ADDRESS

READ

WRITE

13h

Always

Write Reject

D7

D6

D5

CSC5

D4

D3

D2

D1

D0

SCLSCD

CSC6

CSC4

CSC3

CSC2

CSC1

CSC0

Bit

D0–6

D7

Symbol

Description

k

CURRENT STATE COUNT BIT 0–6

l

CSC0–6

SCLSCD

STATE COUNTER LINE STATE CHANGE DETECTION

44

5.0 Registers (Continued)

CURRENT STATE PRESCALE COUNT REGISTER (CSPCR)

The Current State Prescale Count Register takes a snap-shot of the State Prescale Counter during every Control Bus interface

read-cycle of this register.

During a Control Bus Interface write-cycle to the Current State Prescale Count Register, the PLAYER device will set the Control

Bus Write Command Reject bit (CCR) of the Interrupt Condition Register (ICR) to 1 and will ignore a write-cycle.

ACCESS RULES

ADDRESS

READ

WRITE

14h

Always

Write Reject

D7

CSPC7

D6

D5

D4

D3

D2

D1

D0

CSPC6

CSPC5

CSPC4

CSPC3

CSPC2

CSPC1

CSPC0

Bit

D0–7

Symbol

CSPC0–7

Description

CURRENT STATE PRESCALE COUNT 0–7

k

l

45

5.0 Registers (Continued)

LINK ERROR THRESHOLD REGISTER (LETR)

The Link Error Threshold Register contains the start value for the Link Error Monitor Counter, which is an 8-bit down-counter that

decrements if link errors are detected.

When the Counter reaches 0, the Link Error Monitor Threshold Register value is loaded into the Link Error Monitor Counter and

the Link Error Monitor Threshold bit (LEMT) of the Interrupt Condition Register (ICR) is set to 1.

The Link Error Monitor Threshold Register value is also loaded into the Link Error Monitor Counter during every Control Bus

Interface write-cycle of LETR.

e

The Counter is initialized to 0 during the reset process (i.e. RST

GND).

ACCESS RULES

ADDRESS

READ

WRITE

15h

Always

D7

D6

D5

D4

LET4

D3

D2

D1

D0

LET7

LET6

LET5

LET3

LET2

LET1

LET0

Bit

Symbol

Description

k

l

: Least significant bit of the start value

D0

LET0

LINK ERROR THRESHOLD BIT

0

for the Link Error Monitor Counter.

k

l

LINK ERROR THRESHOLD BIT 1–6 : Intermediate bits of start value for

D1–6

D7

LET1–6

LET7

the Link Error Monitor Counter.

k

l

: Most significant bit of the start value

LINK ERROR THRESHOLD BIT

7

for the Link Error Monitor Counter.

46

5.0 Registers (Continued)

CURRENT LINK ERROR COUNT REGISTER (CLECR)

The Current Link Error Count Register takes a snap-shot of the Link Error Monitor Counter during every Control Bus Interface

read-cycle of this register.

During a Control Bus Interface write-cycle, the PLAYER device will set the Control Bus Write Command Reject bit (CCR) of the

Interrupt Condition Register (ICR) to 1 and will ignore a write-cycle.

ACCESS RULES

ADDRESS

READ

WRITE

16h

Always

Write Reject

D7

LEC7

D6

D5

D4

D3

D2

D1

D0

LEC6

LEC5

LEC4

LEC3

LEC2

LEC1

LEC0

Bit

Symbol

Description

k l

LINK ERROR COUNT BIT 0–7

D0–7

LEC0–7

47

5.0 Registers (Continued)

USER DEFINABLE REGISTER (UDR)

The User Definable Register is used to monitor and control events which are external to the PLAYER device.

The value of the Sense Bits reflects the asserted/deasserted state of their corresponding Sense pins. On the other hand, the

Enable bits assert/deassert the Enable pins.

ACCESS RULES

ADDRESS

READ

WRITE

17h

Always

D7

RES

D6

D5

D4

RES

D3

D2

D1

D0

RES

EB1

EB0

SB1

SB0

Bit

D0

Symbol

Description

e

SB0

SB1

EB0

SENSE BIT 0: This bit is set to 1 if the Sense Pin 0 (SP0) is asserted (i.e. SP0

V

) for a minimum of

CC

160 ns. Once the asserted signal is latched, Sense Bit 0 can only be cleared through the Control Bus

Interface, even if the signal is deasserted. This ensures that the Control Bus Interface will record the

source of events which can cause interrupts in a traceable manner.

e

D1

D2

SENSE BIT 1: This bit is set to 1 if the Sense Pin 1 (SP1) is asserted (i.e. SP1

V

CC

) for a minimum of

160 ns. Once the asserted signal is latched, Sense Bit 1 can only be cleared through the Control Bus

Interface, even if the signal is deasserted. This ensures that the Control Bus Interface will record the

source of events which can cause interrupts in a traceable manner.

ENABLE BIT 0: The Enable Bit 0 allows control of external logic through the Control Bus Interface. The

User Definable Enable Pin 0 (EP0) is asserted/deasserted by this bit.

e

0: EP0 is deasserted (i.e. EP0

e

GND).

V ).

CC

1: EP0 is asserted (i.e. EP0

D3

EB1

RES

ENABLE BIT 1: This bit allows control of external logic through the Control Bus Interface. The User

Definable Enable Pin 0 (EP0) is asserted/deasserted by this bit.

e

0: EP1 is deasserted (i.e. EP1

e

GND).

V ).

1: EP1 is asserted (i.e. EP1

CC

D4–7

RESERVED: Reserved for future use. The reserved bit is set to 0 during the initialization process

e

(i.e. RST

GND).

Note: Users are discouraged from using this bit. It may be set or cleared without any effects to the functionality of the

PLAYER device.

48

5.0 Registers (Continued)

DEVICE ID REGISTER (IDR)

The Device ID Register contains the binary equivalent of the revision number for this device. It can be used to ensure proper

software and hardware versions are matched.

During the Control Bus Interface write-cycle, the PLAYER device will set the Control Bus Write Command Register bit (CCR) of

the Interrupt Condition Register (ICR) to 1, and will ignore write-cycle.

ACCESS RULES

ADDRESS

READ

WRITE

18h

Always

Write Reject

D7

D6

D5

DID5

D4

D3

D2

D1

D0

DID7

DID6

DID4

DID3

DID2

DID1

DID0

Bit

Symbol

DID0

Description

k

l

: Least significant bit (LSB) of the revision number.

D0

DEVICE ID BIT

0

k l

DEVICE ID BIT 1-0-6 : Intermediate bits of the revision number.

D1–6

D7

DID1–6

DID7

k

l

: Most significant bit (MSB) of the revision number.

DEVICE ID BIT

7

49

5.0 Registers (Continued)

CURRENT INJECTION COUNT REGISTER (CIJCR)

The Current Injection Count Register takes a snap-shot of the Injection Counter during every Control Bus Interface read-cycle of

this register.

During a Control Bus Interface write-cycle, the PLAYER device will set the Control Bus Write Command Reject bit (CCR) of the

Interrupt Condition Register (ICR) to 1 and will ignore a write-cycle.

The Injection Counter is an 8-bit down-counter which decrements every 80 ns.

k

l

k

l

The counter is active only during One Shot or Periodic Injection Modes (i.e. Injection Control 1:0 bits (IC 1:0 ) of the

Current Transmit State Register (CTSR) are set to either 01 or 10).

The Injection Threshold Register (IJTR) value is loaded into the Injection Counter when the counter reaches zero and during

every Control Bus Interface write-cycle of IJTR.

e

The counter is initialized to 0 during the reset process (i.e. RST

GND).

ACCESS RULES

ADDRESS

READ

WRITE

19h

Always

Write Reject

D7

D6

D5

IJC5

D4

D3

D2

D1

D0

IJC7

IJC6

IJC4

IJC3

IJC2

IJC1

IJC0

Bit

Symbol

IJC0

Description

k

l

: Least significant bit (LSB) of the current value

D0

INJECTION COUNT BIT

0

of the Injection Counter.

k

l

INJECTION COUNT BIT 1–6 : Intermediate bits representing the current

D1–6

D7

IJC1–6

IJC7

value of the Injection Counter.

k

l

: Most significant bit (MSB) of the current

INJECTION COUNT BIT

7

value of the Injection Counter.

50

5.0 Registers (Continued)

INTERRUPT CONDITION COMPARISON REGISTER (ICCR)

The Interrupt Condition Comparison Register ensures that the Control Bus must first read a bit modified by the PLAYER device

before it can be written to by the Control Bus Interface.

The current state of the Interrupt Condition Register (ICR) is automatically written into the Interrupt Condition Comparison

e

Register (i.e. ICCR

ICR) during a Control Bus Interface read-cycle of ICR.

During a Control Bus Interface write-cycle, the PLAYER device will set the Conditional Write Inhibit bit (CWI) of the Interrupt

Condition Register (ICR) to 1 and disallow the setting or clearing of a bit within ICR when the value of a bit in ICR differs from the

value of the corresponding bit in the Interrupt Condition Comparison Register.

ACCESS RULES

ADDRESS

READ

WRITE

1Ah

Always

D7

D6

D5

D4

LEMTC

D3

D2

D1

D0

UDIC

RCBC

RCAC

CWIC

CCRC

CPEC

DPEC

Bit

Symbol

Description

D0

DPEC

PHY REQUEST DATA PARITY ERROR COMPARISON: The comparison

Ð

bit for the PHY Request Data Parity Error bit (DPE) of the Interrupt Condition

Ð

Register (ICR).

D1

D2

CPEC

CCRC

CONTROL BUS DATA PARITY ERROR COMPARISON: The comparison bit

for the Control Bus Data Parity Error bit (CPE) of the Interrupt Condition

Register (ICR).

CONTROL BUS WRITE COMMAND REJECT COMPARISON: The

comparison bit for the Control Bus Write Command Reject bit (CCR) of the

Interrupt Condition Register (ICR).

D3

D4

CWIC

CONDITIONAL WRITE INHIBIT COMPARISON: The comparison bit for the

Conditional Write Inhibit bit (CWI) of the Interrupt Condition Register (ICR).

LEMTC

LINK ERROR MONITOR THRESHOLD COMPARISON: The comparison bit

for the Link Error Monitor Threshold bit (LEMT) of the Interrupt Condition

Register (ICR).

D5

D6

D7

RCAC

RCBC

UDIC

RECEIVE CONDITION A COMPARISON: The comparison bit for the

Receive Condition A bit (RCA) of the Interrupt Condition Register (ICR).

RECEIVE CONDITION B COMPARISON.: The comparison bit for the

Receive Condition B bit (RCB) of the Interrupt Condition Register (ICR).

USER DEFINABLE INTERRUPT COMPARISON: The comparison bit for the

User Definable Interrupt bit (UDIC) of the Interrupt Condition Register (ICR).

51

5.0 Registers (Continued)

CURRENT TRANSMIT STATE COMPARISON REGISTER (CTSCR)

The Current Transmit State Comparison Register ensures that the Control Bus must first read a bit modified by the PLAYER

device before it can be written to by the Control Bus Interface.

The current state of the Current Transmit State Register (CTSR) is automatically written into the Current Transmit State

e

Comparison Register A (i.e. CTSCR

CTSR) during a Control Bus Interface read-cycle of CTSR.

During a Control Bus Interface write-cycle, the PLAYER device will set the Conditional Write Inhibit bit (CWI) of the Interrupt

Condition Register (ICR) to 1 and disallow the setting or clearing of a bit within the CTSR when the value of a bit in the CTSR

differs from the value of the corresponding bit in the Current Transmit State Comparison Register.

ACCESS RULES

ADDRESS

READ

WRITE

1Bh

Always

D7

D6

D5

SEC

D4

IC1C

D3

D2

D1

D0

RESC

PRDPEC

IC0C

TM2C

TM1C

TM0C

Bit

Symbol

TM0C

Description

k

l

D0

TRANSMIT MODE

k

0

COMPARISON: The comparison bit for the

l

(TM0) of the Current Transmit State Register (CTSR).

Transmit Mode

0

k

l

D1

D2

D3

TM1C

TM2C

IC0C

TRANSMIT MODE

k

1

COMPARISON: The comparison bit for the

l

bit (TM1) of the Current Transmit State Register

Transmit Mode

(CTSR).

1

k

l

TRANSMIT MODE

k

2

COMPARISON: The comparison bit for the

l

bit (TM2) of the Current Transmit State Register

Transmit Mode

(CTSR).

2

k

l

INJECTION CONTROL

0

COMPARISON: The comparison bit for the

l

bit (IC0) of the Current Transmit State Register

k

Injection Control

(CTSR).

0

k

l

D4

D5

D6

IC1C

INJECTION CONTROL

1

COMPARISON: The comparison bit for the

l

bit (IC1) of the Current Transmit Register (CTSR).

k

Injection Control

1

SEC

SMOOTHER ENABLE COMPARISON: The comparison bit for the Smoother

Enable bit (SE) to the Current Transmit State Register (CTSR).

PRDPEC

PHY REQUEST DATA PARITY ENABLE COMPARISON: The comparison

Ð

bit for the PHY Request Data Parity Enable bit (PRDPE) of the Current

Ð

Transmit State Register (CTSR).

D7

RESC

RESERVED COMPARISON: The comparison bit for the Reserved bit (RES)

of the Current Transmit State Register (CTSR).

52

5.0 Registers (Continued)

RECEIVE CONDITION COMPARISON REGISTER A (RCCRA)

The Receive Condition Comparison Register A ensures that the Control Bus must first read a bit modified by the PLAYER device

before it can be written to by the Control Bus Interface.

e

The current state of RCRA is automatically written into the Receive Condition Comparison Register A (i.e. RCCRA

during a Control Bus Interface read-cycle of RCRA.

RCRA)

During a Control Bus Interface write-cycle, the PLAYER device will set the Conditional Write Inhibit bit (CWI) of the Interrupt

Condition Register (ICR) to 1 and prevent the setting or clearing of a bit within RCRA when the value of a bit in RCRA differs

from the value of the corresponding bit in the Receive Condition Comparison Register A.

ACCESS RULES

ADDRESS

READ

WRITE

1Ch

Always

D7

LSUPIC

D6

D5

D4

NLSC

D3

D2

D1

D0

LSCC

NTC

MLSC

HLSC

QLSC

NSDC

Bit

Symbol

Description

D0

D1

D2

D3

D4

D5

D6

D7

NSDC

NO SIGNAL DETECT COMPARISON: The comparison bit for the No Signal Detect bit

(NSD) of the Receive Condition Register A (RCRA).

QLSC

HLSC

MLSC

NLSC

NTC

QUIET LINE STATE COMPARISON: The comparison bit for the Quiet Line State bit

(QLS) of the Receive Condition Register A (RCRA).

HALT LINE STATE COMPARISON: The comparison bit for the Halt Line State bit (HLS)

of the Receive Condition Register A (RCRA).

MASTER LINE STATE COMPARISON: The comparison bit for the Master Line State bit

(MLS) of the Receive Condition Register A (RCRA).

NOISE LINE STATE COMPARISON: The comparison bit for the Noise Line State bit

(NLS) of the Receive Condition Register A (RCRA).

NOISE THRESHOLD COMPARISON: The comparison bit for the Noise Threshold bit

(NT) of the Receive Condition Register A (RCRA).

LSCC

LSUPIC

LINE STATE CHANGE COMPARISON: The comparison bit for the Line State Change

bit (LSC) of the Receive Condition Register A (RCRA).

LINE STATE UNKNOWN & PHY INVALID COMPARISON: The comparison bit for the

Line State Unknown & PHY Invalid bit (LSUPI) of the Receive Condition Register A

(RCRA).

53

5.0 Registers (Continued)

RECEIVE CONDITION COMPARISON REGISTER B (RCCRB)

The Receive Condition Comparison Register B ensures that the Control Bus must first read a bit modified by the PLAYER device

before it can be written to by the Control Bus Interface.

e

The current state of RCRB is automatically written into the Receive Condition Comparison Register B (i.e. RCCRB

during a Control Bus Interface read-cycle RCRB.

RCRB)

During a Control Bus Interface write-cycle, the PLAYER device will set the Conditional Write Inhibit bit (CWI) of the Interrupt

Condition Register (ICR) to 1 and prevent the setting or clearing of a bit within RCRB when the value of a bit in RCRB differs

from the value of the corresponding bit in the Receive Condition Comparison Register B.

ACCESS RULES

ADDRESS

READ

WRITE

1Dh

Always

D7

RESC

D6

D5

D4

CSEC

D3

D2

D1

D0

SILSC

EBOUC

LSUPVC

ALSC

STC

ILSC

Bit

Symbol

Description

D0

D1

D2

D3

D4

D5

ILSC

IDLE LINE STATE COMPARISON: The comparison bit for the Idle State bit (ILS) of the

Receive Condition Register B (RCRB).

STC

STATE THRESHOLD COMPARISON: The comparison bit for the State Threshold bit

(ST) of the Receive Condition Register B (RCRB).

ALSC

ACTIVE LINE STATE COMPARISON: The comparison bit for the Active Line State bit

(ALS) of the Receive Condition Register B (RCRB).

LSUPVC

CSEC

EBOUC

LINE STATE UNKNOWN & PHY VALID COMPARISON: The comparison bit for the Line

State Unknown & PHY Valid bit (LSUPV) of the Receive Condition Register B (RCRB).

CASCADE SYNCHRONIZATION ERROR COMPARISON: The comparison bit for the

Cascade Synchronization Error bit (CSE) of the Receive Condition Register B (RCRB).

ELASTICITY BUFFER OVERFLOW/UNDERFLOW COMPARISON: The comparison bit

for the Elasticity Buffer Overflow/Underflow bit (EBOU) of the Receive Condition

Register B (RCRB).

D6

D7

SILSC

RESC

SUPER IDLE LINE STATE COMPARISON: The comparison bit for the Super Idle Line

State bit (SILS) of the Receive Condition Register B (RCRB).

RESERVED COMPARISON: The comparison bit for the Reserved bit (RES) of the

Receive Condition Register B (RCRB).

RESERVED REGISTER 0 (RR0) ADDRESS 1EhÐDO NOT USE

RESERVED REGISTER 1 (RR1) ADDRESS 1FhÐDO NOT USE

54

6.0 Pin Descriptions

6.1 DP83251

The pin descriptions for the DP83251 are divided into 5 functional interfaces: Serial Interface, PHY Port Interface, Control Bus

Interface, Clock Interface, and Miscellaneous Interface.

For a Pinout Summary List, refer to Table 6-1.

TL/F/10386–20

Order Number DP83251V

See NS Package Number V84A

FIGURE 6-1. DP83251 84-Pin PLCC Pinout

55

6.0 Pin Descriptions (Continued)

TABLE 6-1. DP83251 Pinout Summary

ECL/TTL/Open

Drain/Power

Pin No.

Signal Name

Symbol

I/O

k

l

1

Control Bus Data

2

3

CBD2

CBD3

GND

I/O

TTL

2

a

0V

3

CMOS I/O Ground

k

l

4

Control Bus Data

4

5

CBD4

CBD5

I/O

TTL

5

a

5V

6

CMOS I/O Power

V

CC

k

l

7

Control Bus Data

6

7

CBD6

CBD7

CBP

EP0

I/O

O

TTL

k

8

9

Control Bus Data Parity

Enable Pin 0

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

Enable Pin 1

EP1

O

a

0V

CMOS Logic Ground

Control Bus Data Parity Enable

Sense Pin 0

GND

CBPE

SP0

I

TTL

I

Sense Pin 1

SP1

I

PHY Port A Indicate Parity

PHY Port A Indicate Control

AIP

O

AIC

k

l

PHY Port A Indicate Data

CMOS I/O Ground

PHY Port A Indicate Data

CMOS I/O Power

7

6

AID7

AID6

GND

AID5

a

0V

k

l

5

4

O

TTL

a

V

CC

5V

PHY Port A Indicate Data

CMOS Logic Ground

PHY Port A Indicate Data

Cascade Start

AID4

GND

AID3

AID2

AID1

AID0

CS

TTL

a

0V

k

l

3

2

1

0

O

I

TTL

Cascade Ready

CR

Open Drain

No Connect

N/C

CD

No Connect

Clock Detect

I

TTL

Signal Detect

TTLSD

ELB

External Loopback Enable

O

56

6.0 Pin Descriptions (Continued)

TABLE 6-1. DP83251 Pinout Summary (Continued)

ECL/TTL/Open

Drain/Power

Pin No.

Signal Name Symbol

I/O

a

b

a

b

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

Receive Bit Clock

ECL Logic Power

RXC

I

ECL

a

V

CC

5V

a

b

a

b

Receive Data

RXD

I

ECL

a

0V

ECL Logic Ground

GND

a

b

a

External Loopback Data

ECL I/O Power

LBD

O

ECL

b

a

V

CC

5V

a

b

Transmit Data

TXD

O

ECL

a

0V

ECL Logic Ground

Transmit Bit Clock

ECL Logic Power

GND

a

b

a

TXC

I

ECL

b

a

V

CC

5V

a

b

a

b

Transmit Byte Clock

FOTX Enable Level

No Connect

TBC

TEL

N/C

TXE

LBC

I

ECL

TTL

No Connect

FOTX Enable

O

I

TTL

Local Byte Clock

k

l

PHY Port B Request Data

CMOS Logic Ground

0

1

2

3

BRD0

BRD1

BRD2

BRD3

GND

I

a

0V

k

l

PHY Port B Request Data

CMOS I/O Power

4

5

BRD4

I

TTL

a

V

CC

5V

PHY Port B Request Data

CMOS I/O Ground

BRD5

GND

BRD6

BRD7

BRC

TTL

a

0V

k

l

PHY Port B Request Data

6

7

I

TTL

PHY Port B Request Control

PHY Port B Request Parity

I

BRP

O

57

6.0 Pin Descriptions (Continued)

TABLE 6-1. DP83251 Pinout Summary (Continued)

ECL/TTL/Open

Drain/Power

Pin No.

Signal Name

Symbol

I/O

E

71

72

73

74

75

76

77

78

79

80

81

82

83

84

PLAYER Device Reset

RST

I

TTL

E

Read/ Write

R/W

CE

Chip Enable

I

TTL

E

Interrupt

INT

O

I

Open Drain

TTL

E

Acknowledge

ACK

CBA0

CBA1

CBA2

CBA3

CBA4

k

l

Control Bus Address

CMOS Logic Power

0

1

2

3

4

I

TTL

I

TTL

I

TTL

I

TTL

a

V

CC

5V

k

l

Control Bus Data

0

1

CBD0

CBD1

GND

I/O

TTL

a

CMOS Logic Ground

0V

58

6.0 Pin Descriptions (Continued)

SERIAL INTERFACE

The Serial Interface consists of I/O signals used to connect the PLAYER device to the Physical Medium Dependent (PMD)

sublayer.

The PLAYER device uses these signals to interface to a Fiber Optic Transmitter (FOTX), Fiber Optic Receiver (FOXR), Clock

Recovery Device (CRD device), and Clock Distribution Device (CDD device).

Symbol

Pin No.

I/O

Description

CD

33

I

Clock Detect: A TTL input signal from the Clock Recovery Device indicating that the

g

Receive Clock (RXC ) is properly synchronized with the Receive Data RXD ).

TTLSD

34

I

Signal Detect: A TTL signal from the clock Recovery Device indicating that a signal is

being received by the Fiber Optic Receiver.

a

b

RXD

39

40

I

Receive Data: Differential 100K ECL, 125 Mbps serial data input signals from the Clock

Recovery Device.

a

b

TXD

45

46

O

Transmit Data: Differential, 100K ECL, 125 Mbps serial data output signals to the Fiber

Optic Transmitter.

ELB

35

External Loopback Enable: A TTL output signal to the Clock Recovery Device which

enables/disables loopback data through the Clock Recovery Device. This signal is

controlled by the Mode Register.

a

b

LBD

42

43

O

Loopback Data: Differential, 100K ECL, 125 Mbps, external serial loopback data output

signals to the Clock Recovery Device.

a

When the PLAYER device is not in external loopback mode, the LBD signal is kept

b

high and the LBD signal is kept low.

TEL

TXE

53

56

I

FOTX Enable Level: A TTL input signal to select the Fiber Optic Transmitter Enable

(TXE) signal level.

O

FOTX Enable: A TTL output signal to enable/disable the Fiber Optic Transmitter. The

output level of the TXE pin is determined by three parameters, the Transmit Enable (TE)

bit in the Mode Register, the TM2–TM0 bits in the Current Transmit State Register, and

also the input to the TEL pin.

The following rules summarizes the output of the TXE pin:

e

GND, then TXE V

(1) If TE

(2) If TE

(3) If TE

(4) If TE

(5) If TE

(6) If TE

0 and TEL

CC

GND

GND, then TXE

e

V , then TXE

CC

e

V

1 and OTM and TEL

CC

GND

e

GND, then TXE

V

, then TXE

CC

e

GND

e

V

CC

1 and not OTM and TEL

V , then TXE

CC

59

6.0 Pin Descriptions (Continued)

PHY PORT INTERFACE

The PHY Port Interface consists of I/O signals used to connect the PLAYER Device to the Media Access Control (MAC)

sublayer or other PLAYER Devices. The DP83251 Device has one PHY Port Interface which consists of the B Request and the

Ð

A

Indicate paths.

Ð

Each path consists of an odd parity bit, a control bit, and two 4-bit symbols.

Refer to Section 3.3, the Configuration Switch, for further information.

Symbol

Pin No.

I/O

Description

AIP

16

O

PHY Port A Indicate Parity: A TTL output signal representing odd parity for the 10-bit

k

l

wide Port A Indicate signals (AIP, AIC, and AID 7:0 ).

AIC

17

O

PHY Port A Indicate Control: A TTL output signal indicating that the two 4-bit symbols

e

k

l

k

(AID 7:4 and AID 3:0 ) are either control symbols (AIC

l

1) or data symbols (AIC

e

0).

AID7

AID6

AID5

AID4

18

19

21

23

PHY Port A Indicate Data: TTL output signals representing the first 4-bit data/control

symbol.

AID7 is the most significant bit and AID4 is the least significant bit of the first symbol.

AID3

AID2

AID1

AID0

25

26

27

28

O

PHY Port A Indicate Data: TTL output signals representing the second 4-bit data/

control symbol.

AID3 is the most significant bit and AID0 is the least significant bit of the second symbol.

BRP

70

I

PHY Port B Request Parity: A TTL input signal representing odd parity for the 10-bit

k

l

wide Port A Request signals (BRP, BRC, and BRD 7:0 ).

BRC

69

PHY Port B Request Control: A TTL input signal indicating that the two 4-bit symbols

e

k

l

k

(BRD 7:4 ) and BRD 3:0 ) are either control symbols (BRC

l

1) or data symbols

e

(BRC

0).

BRD7

BRD6

BRD5

BRD4

68

67

65

63

I

PHY Port B Request Data: TTL input signals representing the first 4 bit data/control

symbol.

BRD7 is the most significant bit and BRD4 is the least significant bit of the first symbol.

BRD3

BRD2

BRD1

BRD0

61

60

59

58

PHY Port B Request Data: TTL input signals representing the second 4-bit data/control

symbol.

BRD3 is the most significant bit and BRD0 is the least significant bit of the second

symbol.

60

6.0 Pin Descriptions (Continued)

CONTROL BUS INTERFACE

The Control Bus Interface consists of I/O signals used to connect the PLAYER device to Station Management (SMT).

The Control Bus is an asynchronous interface between the PLAYER device and a general purpose microprocessor. It provides

access to 32 8-bit internal registers.

Refer to Figure 22, Control Bus Timing Diagram, for more information.

Symbol

Pin No.

I/O

Description

CE

73

I

Chip Enable: An active-low, TTL, input signal which enables the Control Bus port for a read

k

l

k

or write cycle. R/W, CBA 4:0 , CBP, and CBD 7:0 must be valid at the time CE is low.

l

E

e

0). This signal must be valid when CE is low and held

R/W

ACK

72

75

I

Read/ Write: A TTL input signal which indicates a read Control Bus cycle (R/W

e

1), or

a write Control Bus cycle (R/W

valid until ACK becomes low.

E

Acknowledge: An active low, TTL, open drain output signal which indicates the

completion of a read or write cycle.

O

k

l

During a read cycle, CBD 7:0 are valid as long as ACK is low (ACK

e

During a write cycle, a microprocessor must hold CBD 7:0 valid until ACK becomes low.

0).

k

l

e

Once ACK is low, it will remain low as long as CE remains low (CE

0).

E

INT

74

O

I

Interrupt: An active low, open drain, TTL, output signal indicating that an interrupt

condition has occurred. The Interrupt Condition Register (ICR) should be read in order to

find out the source of the interrupt. Interrupts can be masked through the use of the

Interrupt Condition Mask Register (ICMR).

CBA4

CBA3

CBA2

CBA1

CBA0

80

79

78

77

76

Control Bus Address: TTL input signals used to select the address of the register to be

read or written.

CBA4 is the most significant bit (MSB), CBA0 is the least significant bit (LSB) of the address

signals.

These signals must be valid when CE is low and held valid until ACK becomes low.

CBPE

13

I

Control Bus Parity Enable: A TTL input signal which, during write cycles, will enable or

disable the Control Bus parity checker. Note that the Control Bus will always generate

parity during read cycles, regardless of the state of this signal.

CBP

9

I/O

Control Bus Parity: A bidirectional, TTL signal representing odd parity for the Control Bus

k

l

data (CBD 7:0 ).

During a read cycle, the signal is held valid by the PLAYER device as long as ACK is low.

During a write cycle, the signal must be valid when CE is low, and must be held valid until

ACK becomes low. If incorrect parity is used during a write cycle, the PLAYER device will

inhibit the write cycle and set the Control Bus Data Parity Error (CPE) bit in the Interrupt

Condition Register (ICR).

CBD7

CBD6

CBD5

8

7

5

I/O

Control Bus Data: Bidirectional, TTL signals containing the data to be read from or written

to a register.

During a read cycle, the signal is held valid by the PLAYER device as long as ACK is low.

During a write cycle, the signal must be valid when CE is low, and must be held valid until

ACK becomes low.

CBD4

CBD3

CBD2

CBD1

CBD0

4

2

1

83

82

61

6.0 Pin Descriptions (Continued)

CLOCK INTERFACE

The Clock Interface consists of 12.5 MHz and 125 MHz clocks used by the PLAYER device. The clocks are generated by either

the Clock Distribution Device or Clock Recovery Device.

Symbol

Pin No.

I/O

Description

LBC

57

I

Local Byte Clock: A TTL, 12.5 MHz, 50% duty cycle, input clock from the Clock

Distribution Device. The Local Byte Clock is used by the PLAYER device’s internal

CMOS logic and to latch incoming/outgoing data of the Control Bus Interface, Port A

Interface, Port B Interface, and other miscellaneous I/Os.

a

b

RXC

36

37

I

Receive Bit Clock: Differential 100k ECL, 125 MHz clock input signals from the Clock

Recovery Device. The Receive Bit Clock is used by the Serial Interface to latch the

g

Receive Data (RXD ).

a

b

TXC

48

49

Transmit Bit Clock: Differential 100k ECL, 125 MHz clock input signals from the Clock

Distribution Device. The Transmit Bit Clock is used by the Serial Interface to latch the

g

Transmit Data (TXD ).

TXC

a

b

TBC

51

52

Transmit Byte Clock: Differental 100k ECL, 12.5 MHz clock input signals from the Clock

Distribution Device. The Transmit Byte Clock is used by the PLAYER device’s internal

Shift Register Block.

62

6.0 Pin Descriptions (Continued)

MISCELLANOUS INTERFACE

The Miscellaneous Interface consists of a reset signal, user definable sense signals, user definable enable signals, Cascaded

PLAYER devices synchronization signals, ground signals, and power signals.

Symbol

RST

Pin No.

I/O

Description

71

I

Reset: An active low, TTL, input signal which clears all registers. The signal

must be kept asserted for a minimum of 160 ns.

Once the RST signal is asserted, the PLAYER device should be allowed 960

ns to reset internal logic. Note that bit zero of the Mode Register will be set to

zero (i.e. Stop Mode). See Section 4.2, Stop Mode of Operation for more

information.

SP0

14

I

User Definable Sense Pin 0: A TTL input signal from a user defined source.

Bit zero (Sense Bit 0) of the User Definable Register (UDR) will be set to one

if the signal is asserted for a minimum of 160 ns.

Once the asserted signal is latched, Sense Bit 0 can only be cleared through

the Control Bus Interface, even if the signal is deasserted. This ensures that

the Control Bus Interface will record the source of events which can cause

interrupts.

SP1

15

I

User Definable Sense Pin 1: A TTL input signal from a user defined source.

Bit one (Sense Bit 1) of the User Definable Register (UDR) will be set to one if

the signal is asserted for a minimum of 160 ns.

Once the asserted signal is latched, Sense Bit 1 can only be cleared through

the Control Bus Interface, even if the signal is deasserted. This ensures that

the Control Bus Interface will record the source of events which can cause

interrupts.

EP0

EP1

CS

10

11

29

O

I

User Definable Enable Pin 0: A TTL output signal allowing control of

external logic through the CBUS Interface. EP0 is asserted/deasserted

through bit two (Enable Bit 0) of the User Definable Register (UDR). When

Enable Bit 0 is set to zero, EP0 is deasserted. When Enable Bit 0 is set to

one, EP0 is asserted.

User Definable Enable Pin 1: A TTL output signal allowing control of

external logic through the CBUS Interface. EP1 is asserted/deasserted

through bit two (Enable Bit 1) of the User Definable Register (UDR). When

Enable Bit 1 is set to zero, EP1 is deasserted. When Enable Bit 1 is set to

one, EP1 is asserted.

Cascade Start: A TTL input signal used to synchronize cascaded PLAYER

devices in point-to-point applications.

The signal is asserted when all of the cascaded PLAYER devices have the

Cascade Mode (CM) bit of Mode Register (MR) set to one, and all of the

Cascade Ready pins of the cascaded PLAYER devices have been released.

For further information, refer to Section 4.4, Cascade Mode of Operation.

CR

30

O

Cascade Ready: An Open Drain output signal used to synchronize cascaded

PLAYER devices in point-to-point applications.

The signal is released (i.e. an Open Drain line is released) when all the

cascaded PLAYER devices have the Cascade Mode (CM) bit of the Mode

Register (MR) set to one and a JK symbol pair has been received.

For further information, refer to Section 4.4, Cascade Mode of Operation.

63

6.0 Pin Descriptions (Continued)

POWER AND GROUND

All power pins should be connected to a single 5V power supply. All ground pins should be connected to a common 0V supply.

Symbol

Pin No.

I/O

Description

GND

3

6

Ground: Power supply return for Control Bus Interface CMOS I/Os.

g

Power: Positive 5V power supply ( 5% relative to ground) for Control Bus Interface

CMOS I/Os.

V

CC

GND

12

20

22

Ground: Power supply return for internal CMOS logic.

Ground: Power supply return for Port A Interface CMOS I/Os.

g

Power: Positive 5V power supply ( 5% relative to ground) for the Port A Interface

CMOS I/Os.

V

CC

GND

24

38

41

44

Ground: Power supply return to internal CMOS logic.

g

Power: Positive 5V power supply ( 5% relative to ground) for internal ECL logic.

V

CC

GND

Ground: Power supply return for internal ECL logic.

g

Power: Positive 5V power supply ( 5% relative to ground) for the Serial Interface ECL I/

Os.

V

CC

GND

47

50

Ground: Power supply return for internal ECL logic.

g

Power: Positive 5V power supply ( 5% relative to ground) for the Serial Interface ECL I/

Os.

V

CC

GND

62

64

Ground: Power supply return for internal CMOS logic.

g

Power: Positive 5V power supply ( 5% relative to ground) for the Port A Interface

CMOS I/Os.

V

CC

GND

66

81

84

Ground: Power supply return for Port A Interface CMOS I/Os.

g

Power: Positive 5V power supply ( 5% relative to ground) for internal CMOS logic.

V

CC

GND

Ground: Power supply return for internal CMOS logic.

NO CONNECT PINS

Symbol

N/C

Pin No.

31

I/O

Description

No Connect: Not used by the PLAYER device

N/C

32

N/C

54

N/C

55

64

6.0 Pin Descriptions (Continued)

6.2 DP83255

The pin descriptions for the DP83255 are divided into six functional interfaces; Serial Interface, PHY Port Interface, Control Bus

Interface, Clock Interface, and Miscellaneous Interface.

For a Pinout Summary List, refer to Table 6-2.

TL/F/10386–21

Order Number DP83255AVF

See NS Package Number VF132A

FIGURE 6-2. DP83255 132-Pin PQFP Pinout

65

6.0 Pin Descriptions (Continued)

TABLE 6-2. DP83255 Pinout Summary

ECL/TTL/Open

Drain/Power

Pin No.

Signal Name

Symbol

I/O

a

0V

1

CMOS Logic Ground

GND

k

l

2

Control Bus Data

2

3

CBD2

CBD3

GND

I/O

TTL

3

a

0V

4

CMOS I/O Ground

k

l

5

Control Bus Data

4

5

CBD4

CBD5

I/O

TTL

6

a

5V

7

CMOS I/O Power

V

CC

k

l

8

Control Bus Data

6

7

CBD6

CBD7

CBP

EP0

I/O

O

TTL

k

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

Control Bus Data Parity

Enable Pin 0

Enable Pin 1

EP1

O

No Connect

N/C

GND

CBPE

SP0

No Connect

a

CMOS Logic Ground

Control Bus Data Parity Enable

Sense Pin 0

0V

I

TTL

Sense Pin 1

SP1

I

PHY Port A Indicate Parity

PHY Port A Request Parity

PHY Port A Indicate Control

PHY Port A Request Control

AIP

O

I

ARP

AIC

O

I

ARC

AID7

ARD7

AID6

ARD6

GND

AID5

ARD5

k

l

PHY Port A Indicate Data

PHY Port A Request Data

7

O

I

k

l

7

k

l

PHY Port A Indicate Data

PHY Port A Request Data

CMOS I/O Ground

6

O

I

k

l

6

a

0V

k

l

PHY A Indicate Data

PHY A Request Data

CMOS I/O Power

5

O

I

TTL

k

l

5

a

V

CC

5V

66

6.0 Pin Descriptions (Continued)

TABLE 6-2. DP83255 Pinout Summary (Continued)

ECL/TTL/Open

Drain/Power

Pin No.

Signal Name

Symbol

I/O

k

l

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

PHY A Indicate Data

PHY A Request Data

CMOS Logic Ground

4

AID4

ARD4

GND

AID3

ARD3

AID2

ARD2

AID1

ARD1

AID0

ARD0

CS

O

I

TTL

k

l

4

a

0V

k

l

PHY Port A Indicate Data

3

O

I

TTL

k

l

PHY Port A Request Data

3

k

l

PHY Port A Indicate Data

2

O

I

TTL

k

l

PHY Port A Request Data

2

TTL

k

l

PHY Port A Indicate Data

1

O

I

TTL

k

l

PHY Port A Request Data

1

TTL

k

l

PHY Port A Indicate Data

0

O

I

TTL

k

l

Port A Request Data

Cascade Start

Cascade Ready

No Connect

0

TTL

I

TTL

CR

O

Open Drain

N/C

No Connect

N/C

No Connect

N/C

No Connect

N/C

No Connect

N/C

No Connect

N/C

No Connect

N/C

No Connect

N/C

Clock Detect

Signal Detect

CD

I

TTL

ECL

TTLSD

ELB

External Loopback Enable

O

I

a

b

a

b

Receive Bit Clock

ECL Logic Power

RXC

I

a

V

CC

5V

a

b

a

b

Receive Data

RXD

I

ECL

a

0V

ECL Logic Ground

GND

a

b

a

External Loopback Data

ECL I/O Power

LBD

O

ECL

b

a

V

CC

5V

a

b

a

b

Transmit Data

TXD

O

ECL

67

6.0 Pin Descriptions (Continued)

TABLE 6-2. DP83255 Pinout Summary (Continued)

ECL/TTL/Open

Drain/Power

Pin No.

Signal Name

ECL Logic Ground

Symbol

I/O

a

0V

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

GND

a

b

a

b

Transmit Bit Clock

ECL Logic Power

TXC

I

ECL

a

V

CC

5V

a

b

a

b

Transmit Byte Clock

FOTX Enable Level

No Connect

TBC

TEL

N/C

TXE

LBC

I

ECL

TTL

No Connect

FOTX Enable

Local Byte Clock

O

I

TTL

k

l

PHY Port B Indicate Data

0

BID0

BRD0

BID1

BRD1

BID2

BRD2

BID3

BRD3

GND

BID4

BRD4

O

I

k

l

PHY Port B Request Data

0

k

l

PHY Port B Indicate Data

1

O

I

k

l

PHY Port B Request Data

1

k

l

PHY Port B Indicate Data

2

O

I

k

l

PHY Port B Request Data

2

k

l

PHY Port B Indicate Data

PHY Port B Request Data

CMOS Logic Ground

3

O

I

k

l

3

a

0V

k

l

PHY Port B Indicate Data

PHY Port B Request Data

CMOS I/O Power

4

O

I

TTL

k

l

4

a

V

CC

5V

k

l

PHY Port B Indicate Data

PHY Port B Request Data

CMOS I/O Ground

5

BID5

BRD5

GND

BID6

BRD6

BID7

O

I

TTL

k

l

5

a

0V

k

l

PHY Port B Indicate Data

PHY Port B Request Data

6

O

I

TTL

k

l

6

k

l

PHY Port B Indicate Data

7

O

68

6.0 Pin Descriptions (Continued)

TABLE 6-2. DP83255 Pinout Summary (Continued)

ECL/TTL/Open

Drain/Power

Pin No.

Signal Name

Symbol

I/O

k

l

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

PHY Port B Request Data

7

BRD7

BIC

I

O

I

TTL

PHY Port B Indicate Control

PHY Port B Request Control

PHY Port B Indicate Parity

PHY Port B Request Parity

BRC

BIP

TTL

O

I

TTL

BRP

RST

R/W

CE

TTL

E

PLAYER Device Reset

I

TTL

E

Read/ Write

I

TTL

Chip Enable

I

TTL

E

Interrupt

INT

O

Open Drain

No Connect

N/C

ACK

CBA0

CBA1

CBA2

CBA3

CBA4

E

Acknowledge

O

I

Open Drain

TTL

k

l

Control Bus Address

CMOS Logic Power

0

1

2

3

4

I

TTL

I

TTL

I

TTL

I

TTL

a

V

CC

5V

k

l

Control Bus Data

0

1

CBD0

CBD1

GND

I/O

TTL

a

CMOS Logic Ground

0V

69

6.0 Pin Descriptions (Continued)

SERIAL INTERFACE

The Serial Interface consists of I/O signals used to connect the PLAYER device to the Physical Medium Dependent (PMD)

sublayer.

The PLAYER device uses these signals to interface to a Fiber Optic Transmitter (FOTX), Fiber Optic Receiver (FORX), Clock

Recovery Device (CRD device), and Clock Distribution Device (CDD device).

Symbol

Pin No.

I/O

Description

CD

57

I

Clock Detect: A TTL input signal from the Clock Recovery Device indicating that the

g

Receive Clock (RXC ) is properly synchronized with the Receive Data (RXD ).

TTLSD

58

I

Signal Detect: A TTL input signal from the Clock Recovery Device indicating that a

signal is being received by the Fiber Optic Receiver.

a

b

RXD

63

64

I

Receive Data: Differential 100K ECL, 125 Mbps serial data input signals from the Clock

Recovery Device.

a

b

TXD

69

70

O

Transmit Data: Differential, 100K ECL, 125 Mbps serial data output signals to the Fiber

Optic Transmitter.

ELB

59

External Loopback Enable: A TTL output signal to the Clock Recovery Device which

enables/disables loopback data through the Clock Recovery Device. This signal is

controlled by the Mode Register.

a

b

LBD

66

67

O

Loopback Data: Differential, 100K ECL, 125 Mbps, serial external loopback data output

signals to the Clock Recovery Device.

a

When the PLAYER device is not in external loopback mode, the LBD signal is kept

b

high and the LBD signal is kept low.

TEL

TXE

77

86

I

FOTX Enable Level: A TTL input signal to select the Fiber Optic Transmitter Enable

(TXE) signal level.

O

FOTX Enable: A TTL output signal to enable/disable the Fiber Optic Transmitter. The

output level of the TXE pin is determined by three parameters, the Transmit Enable (TE)

bit in the Mode Register, the TM2–TM0 bits in the Current Transmit State Register, and

also the input to the TEL pin.

The following rules summarizes the output of the TXE pin:

e

GND, then TXE V

(1) If TE

(2) If TE

(3) If TE

(4) If TE

(5) If TE

(6) If TE

0 and TEL

CC

GND

GND, then TXE

e

V , then TXE

CC

e

V

1 and OTM and TEL

CC

GND

e

GND, then TXE

V

, then TXE

CC

e

GND

e

V

CC

1 and not OTM and TEL

V , then TXE

CC

70

6.0 Pin Descriptions (Continued)

PHY PORT INTERFACE

The PHY Port Interface consists of I/O signals used to connect the PLAYER Device to the Media Access Control (MAC)

sublayer or other PLAYER Devices. The DP83255 Device has two PHY Port Interfaces. The A Request and A Indicate paths

form one PHY Port Interface and the B Request and B Indicate paths form the second PHY Port Interface. Each path

Ð

consists of an odd parity bit, a control bit, and two 4-bit symbols.

Refer to Section 3.3, the Configuration Switch, for more information.

Symbol

Pin No.

I/O

Description

AIP

24

O

PHY Port A Indicate Parity: A TTL output signal representing odd parity for the 10-bit

k

l

wide Port A Indicate signals (AIP, AIC, and AID 7:0 ).

AIC

26

O

PHY Port A Indicate Control: A TTL output signal indicating that the two 4-bit symbols

e

k

l

k

(AID 7:4 and AID 3:0 ) are either control symbols (AIC

l

1) or data symbols (AIC

e

0).

AID7

AID6

AID5

AID4

28

30

33

36

PHY Port A Indicate Data: TTL output signals representing the first 4-bit data/control

symbol.

AID7 is the most significant bit and AID4 is the least significant bit of the first symbol.

AID3

AID2

AID1

AID0

39

41

43

45

O

PHY Port A Indicate Data: TTL output signals representing the second 4-bit data/

control symbol.

AID3 is the most significant bit and AID0 is the least significant bit of the second symbol.

ARP

25

I

PHY Port A Request Parity: A TTL input signal representing odd parity for the 10-bit

k

l

wide Port A Request signals (ARP, ARC, and ARD 7:0 ).

ARC

27

PHY Port A Request Control: A TTL input signal indicating that the two 4-bit symbols

e

k

l

k

(ARD 7:4 and ARD 3:0 ) are either control symbols (ARC

l

1) or data symbols

e

(ARC

0).

ARD7

ARD6

ARD5

ARD4

29

31

34

37

I

PHY Port A Request Data: TTL input signals representing the first 4 bit data/control

symbol.

ARD7 is the most significant bit and ARD4 is the least significant bit of the first symbol.

ARD3

ARD2

ARD1

ARD0

40

42

44

46

PHY Port A Request Data: TTL input signals representing the second 4-bit data/control

symbol.

ARD3 is the most significant bit and ARD0 is the least significant bit of the second

symbol.

71

6.0 Pin Descriptions (Continued)

PHY PORT INTERFACE (Continued)

Symbol

Pin No.

I/O

Description

BIP

109

O

PHY Port B Indicate Parity: A TTL output signal representing odd parity for the 10-bit

k

l

wide Port B Indicate signals (BIP, BIC, and BID 7:0 ).

BIC

107

O

PHY Port B Indicate Control: A TTL output signal indicating that the two 4-bit symbols

e

k

l

k

(BID 7:4 and BID 3:0 ) are either control symbols (BIC

l

1) or data symbols (BIC

e

0).

BID7

BID6

BID5

BID4

105

103

100

97

PHY Port B Indicate Data: TTL output signals representing the first 4-bit data/control

symbol.

BID7 is the most significant bit and BID4 is the least significant bit of the first symbol.

BID3

BID2

BID1

BID0

94

92

90

88

O

PHY Port B Indicate Data: TTL output signals representing the second 4-bit data/

control symbol.

BID3 is the most significant bit and BID0 is the least significant bit of the second symbol.

BRP

110

I

PHY Port B Request Parity: A TTL input signal representing odd parity for the 10-bit

k

l

wide Port B Request signals (BRP, BRC, and BRD 7:0 ).

BRC

108

PHY Port B Request Control: A TTL input signal indicating that the two 4-bit symbols

e

k

l

k

(BRD 7:4 ) and BRD 3:0 ) are either control symbols (BRC

l

1) or data symbols

e

(BRC

0).

BRD7

BRD6

BRD5

BRD4

106

104

101

98

I

PHY Port B Request Data: TTL input signals representing the first 4-bit data/control

symbol.

BRD7 is the most significant bit and BRD4 is the least significant bit of the first symbol.

BRD3

BRD2

BRD1

BRD0

95

93

91

89

PHY Port B Request Data: TTL input signals representing the second 4-bit data/control

symbol.

BRD3 is the most significant bit and BRD0 is the least significant bit of the second

symbol.

72

6.0 Pin Descriptions (Continued)

CONTROL BUS INTERFACE

The Control Bus Interface consists of I/O signals used to connect the PLAYER device to Station Management (SMT).

The Control Bus is an asynchronous interface between the PLAYER device and a general purpose microprocessor. It provides

access to 32 8-bit internal registers.

Refer to Figure 22, Control Bus Timing Diagram, for further information.

Symbol

Pin No.

I/O

Description

CE

113

I

Chip Enable: An active-low, TTL, input signal which enables the Control Bus port for a

k

l

read or write cycle. R/W, CBA 4:0 , CBP, and CBD 7:0 must be valid at the time CE

is low.

E

e

0). This signal must be valid when CE is low and

R/W

ACK

112

123

I

Read/ Write: A TTL input signal which indicates a read Control Bus cycle (R/W

e

1),

or a write Control Bus cycle (R/W

held valid until ACK becomes low.

E

Acknowledge: An active low, TTL, open drain output signal which indicates the

completion of a read or write cycle.

O

k

l

During a read cycle, CBD 7:0 are valid as long as ACK is low (ACK

e

0).

k

l

During a write cycle, a microprocessor must hold CBD 7:0 valid until ACK becomes

low.

e

Once ACK is low, it will remain low as long as CE remains low (CE

0).

E

INT

114

O

I

Interrupt: An active low, open drain, TTL, output signal indicating that an interrupt

condition has occurred. The Interrupt Condition Register (ICR) should be read in order to

determine the source of the interrupt. Interrupts can be masked through the use of the

Interrupt Condition Mask Register (ICMR)

CBA4

CBA3

CBA2

CBA1

CBA0

128

127

126

125

124

Control Bus Address: TTL input signals used to select the address of the register to be

read or written.

CBA4 is the most significant bit and CBA0 is the least significant bit of the address

signals.

These signals must be valid when CE is low and held valid until ACK becomes low.

CBPE

21

I

Control Bus Parity Enable: A TTL input signal which, during write cycles, will enable or

disable the Control Bus parity checker. Note that the Control Bus will always generate

parity during read cycles, regardless of the state of this signal.

CBP

10

I/O

Control Bus Parity: A bidirectional, TTL signal representing odd parity for the Control

k

l

Bus data (CBD 7:0 ).

During a read cycle, the signal is held valid by the PLAYER device as long as ACK is low.

During a write cycle, the signal must be valid when CE is low, and must be held valid until

ACK becomes low. If incorrect parity is used during a write cycle, the PLAYER device will

inhibit the write cycle and set the Control Bus Data Parity Error (CPE) bit in the Interrupt

Condition Register (ICR).

CBD7

CBD6

CBD5

CBD4

CBD3

CBD2

CBD1

CBD0

9

8

I/O

Control Bus Data: Bidirectional, TTL signals containing the data to be read from or

written to a register.

6

During a read cycle, the signal is held valid by the PLAYER device as long as ACK is low.

5

During a write cycle, the signal must be valid when CE is low, and must be held valid until

ACK becomes low.

3

2

131

130

73

6.0 Pin Descriptions (Continued)

CLOCK INTERFACE

The Clock Interface consists of 12.5 MHz and 125 MHz clocks used by the PLAYER device. The clocks are generated by either

the Clock Distribution Device or Clock Recovery Device.

Symbol

Pin No.

I/O

Description

LBC

87

I

Local Byte Clock: A TTL, 12.5 MHz, 50% duty cycle, input clock from the Clock

Distribution Device. The Local Byte Clock is used by the PLAYER device’s internal

CMOS logic and to latch incoming/outgoing data of the Control Bus Interface, Port A

Interface, Port B Interface, and other miscellaneous I/Os.

a

b

RXC

60

61

I

Receive Bit Clock: Differential, 100k ECL, 125 MHz clock input signals from the Clock

Recovery Device. The Receive Bit Clock is used by the Serial Interface to latch the

g

Receive Data (RXD ).

a

b

TXC

72

73

Transmit Bit Clock: Differential, 100k ECL, 125 MHz clock input signals from the Clock

Distribution Device. The Transmit Bit Clock is used by the Serial Interface to latch the

g

Transmit Data (TXD ).

a

b

TBC

75

76

Transmit Byte Clock: Differental, 100k ECL, 12.5 MHz clock input signals from the

Clock Distribution Device. The Transmit Byte Clock is used by the PLAYER device’s

internal Shift Register Block.

74

6.0 Pin Descriptions (Continued)

MISCELLANEOUS INTERFACE

The Miscellaneous Interface consists of a reset signal, user definable sense signals, user definable enable signals, Cascaded

PLAYER device’s synchronization signals, ground signals, and power signals.

Symbol

Pin No.

I/O

Description

RST

111

I

Reset: An active low, TTL, input signal which clears all registers. The signal must be kept

asserted for a minimum of 160 ns.

Once the RST signal is asserted, the PLAYER device should be allowed 960 ns to reset

internal logic. Note that bit zero of the Mode Register will be set to zero (i.e. Stop Mode).

See Section 4.2, Stop Mode of Operation for more information.

SP0

SP1

22

23

I

User Definable Sense Pin 0: A TTL input signal from a user defined source. Bit zero

(Sense Bit 0) of the User Definable Register (UDR) will be set to one if the signal is

asserted for a minimum of 160 ns.

Once the asserted signal is latched, Sense Bit 0 can only be cleared through the Control

Bus Interface, even if the signal is deasserted. This ensures that the Control Bus

Interface will record the source of events which can cause interrupts.

User Definable Sense Pin 1: A TTL input signal from a user defined source. Bit one

(Sense Bit 1) of the User Definable Register (UDR) will be set to one if the signal is

asserted for a minimum of 160 ns.

Once the asserted signal is latched, Sense Bit 0 can only be cleared through the Control

Bus Interface, even if the signal is deasserted. This ensures that the Control Bus

Interface will record the source of events which can cause interrupts.

EP0

EP1

CS

11

12

47

O

I

User Definable Enable Pin 0: A TTL output signal allowing control of external logic

through the Control Bus Interface. EP0 is asserted/deasserted through bit two (Enable

Bit 0) of the User Definable Register (UDR). When Enable Bit 0 is set to zero, EP0 is

deasserted. When Enable Bit 0 is set to one, EP0 is asserted.

User Definable Enable Pin 1: A TTL output signal allowing control of external logic

through the Control Bus Interface. EP1 is asserted/deasserted through bit two (Enable

Bit 1) of the User Definable Register (UDR). When Enable Bit 1 is set to zero, EP1 is

deasserted. When Enable Bit 1 is set to one, EP1 is asserted.

Cascade Start: A TTL input signal used to synchronize cascaded PLAYER devices in

point-to-point applications.

The signal is asserted when all of the cascaded PLAYER devices have the Cascade

Mode (CM) bit of the Mode Register (MR) set to one, and all of the Cascade Ready (CR)

pins of the cascaded PLAYER devices have been released.

For further information, refer to Section 4.4, Cascade Mode of Operation.

CR

48

O

Cascade Ready: An Open Drain output signal used to synchronize cascaded PLAYER

devices in point-to-point applications.

The signal is released when all the cascaded PLAYER devices have the Cascade Mode

(CM) bit of the Mode Register (MR) set to one and a JK symbol pair has been received.

For further information, refer to section 4.4, Cascade Mode of Operation.

75

6.0 Pin Descriptions (Continued)

POWER AND GROUND

All power pins should be connected to a single 5V power supply. All ground pins should be connected to a common 0V ground

supply.

Symbol

GND

Pin No.

I/O

Description

1

4

7

Ground: Power supply return for internal CMOS logic.

Ground: Power supply return for Control Bus Interface CMOS I/Os.

GND

g

Power: Positive 5V power supply ( 5% relative to ground) for Control Bus Interface

CMOS I/Os.

V

CC

GND

20

32

35

Ground: Power supply return for internal CMOS logic.

Ground: Power supply return for Port A Interface CMOS I/Os.

g

Power: Positive 5V power supply ( 5% relative to ground) for the Port A Interface

CMOS I/Os.

V

CC

GND

38

62

65

68

Ground: Power supply return for internal CMOS logic.

g

Power: Positive 5V power supply ( 5% relative to ground) for internal ECL logic.

V

CC

GND

Ground: Power supply return for internal ECL logic.

g

Power: Positive 5V power supply ( 5% relative to ground) for the Serial Interface ECL I/

Os.

V

CC

GND

71

74

96

99

Ground: Power supply return for internal ECL logic.

g

Power: Positive 5V power supply ( 5% relative to ground) for internal ECL logic.

V

CC

GND

Ground: Power supply return for internal CMOS logic.

g

Power: Positive 5V power supply ( 5% relative to ground) for Port B Interface CMOS I/

Os.

V

CC

GND

102

129

132

Ground: Power supply return for Port B Interface CMOS I/Os.

g

Power: 5V power supply ( 5% relative to ground) for internal CMOS logic.

V

CC

GND

Ground: Power supply return for internal CMOS logic.

76

6.0 Pin Descriptions (Continued)

NO CONNECT PINS

Symbol

N/C

Pin No.

13

I/O

Description

No Connect: Not used by the PLAYER device

14

No Connect: Not used by the PLAYER device

15

16

17

18

19

49

50

51

52

53

54

55

56

78

79

80

81

82

83

84

85

115

116

117

118

119

120

121

122

77

7.0 Electrical Characteristics

7.1 ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Supply Voltage

Input Voltage

Conditions

Min

Typ

Max

7.0

a

Units

b

V

CC

0.5

V

b

DC

V

0.5

IN

CC

a

Output Voltage

Storage Temperature

OUT

CC

150

b

65

C

§

7.2 RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Supply Voltage

Conditions

Min

Typ

Max

Units

V

T

4.75

0

5.25

70

V

CC

Operating Temperature

C

§

A

7.3 DC ELECTRICAL CHARACTERISTICS

The DC characteristics are over the operating range, unless otherwise specified.

DC electrical characteristics for the TTL, TRI-STATE output signals of PHY, Port Interfaces, and CBUS Interface.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

e

I

TRI-STATE Leakage

(CBP & CBD7–0)

V

OZ1

OZ2

OZ3

OZ4

OUT

CC

10

mA

TRI-STATE Leakage

(CBP & CBD7–0)

GND

CC

b

10

mA

TRI-STATE Leakage

(AID & BID)

60

(Note 1)

e

GND

TRI-STATE Leakage

(AID & BID)

V

OUT

b

500

Note 1: Output buffer has a p-channel pullup device.

DC electrical characteristics for all TTL input signals and the following TTL output signals: External Loopback (ELB), Fiber Optic

Transmitter Enable (TXE), Enable Pin 0 (EP0), and Enable Pin 1 (EP1).

Symbol

Parameter

Conditions

Min

Typ

Max

Units

V

e b

b

V

Output High Voltage

Output Low Voltage

Input High Voltage

Input Low Voltage

Input Clamp Voltage

Input Low Current

Input High Current

I

2 mA

V

CC

0.5

OH

OL

IH

OH

e

4 mA

0.5

V

OL

2.0

V

0.8

V

IL

e b

IN

b

1.5

I

18 mA

V

IC

e

b

a

I

V

GND

10

mA

IL

IH

IN

V

CC

78

7.0 Electrical Characteristics (Continued)

DC electrical characteristics for all Open Drain output signals (INT, ACK and CR).

Symbol

Parameter

Conditions

Min

Typ

Max

0.5

10

Units

V

e

V

OL

Output Low Voltage

TRI-STATE Leakage

I

8 mA

OL

e

I

V

OUT

V

CC

mA

OZ

DC electrical characteristics for all 100k ECL input and output signals.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

e

b

V

Output High Voltage

Output Low Voltage

Input High Voltage

Input Low Voltage

Input Low Current

Input High Current

V

(max)

V

CC

V

CC

V

CC

V

CC

1.025

1.810

1.165

1.810

V

CC

V

CC

V

CC

V

CC

0.880

1.620

0.880

1.475

V

OH

OL

IH

IN

IH

(min)

IN

IL

V

IL

e

b

10

100

I

V

GND

mA

L

IN

V

CC

H

IN

Supply Current electrical characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Units

e

I

Total Supply

Current

LBC

TXC

12.5 MHz

125 MHz

CC

440*

mA

*Note: The PLAYER device has two pairs of differential ECL outputs, therefore 60 mA of the total supply current is actually consumed by external termination

resistors and the maximum current consumed by the PLAYER device alone is only 380 mA. The ECL termination current is calculated as follows:

e

b

V

0.88V

1.62V

OH max

Ð

CC

V

OL max

Ð

CC

b

2V, therefore the external load current

Since the outputs are differential, the average output level is V

1.25V. The test load per output is 50X at V

CC

through the 50X resistor is:

e

b

2) /50

CC

[

]

I

(V

1.25)

(V

LOAD

CC

0.015A

15 mA.

As result, two pairs of ECL outputs consume 60 mA.

79

7.0 Electrical Characteristics (Continued)

7.4 AC ELECTRICAL CHARACTERISTICS

The AC Electrical characteristics are over the operating range, unless otherwise specified.

AC Characteristics for the Control Bus Interface

Symbol

T1

Parameter

CE Setup to LBC

Min

5

Max

Units

ns

T2

LBC Period

80

ns

T3

LBC to ACK Low

45

540

60

ns

T4

CE Low to ACK Low

290

ns

T5

LBC Low to CBD(7-0) and CBP Valid

LBC to CBD(7-0) and CBP Active

CE Low to CBD(7-0) and CBP Active

CE Low to CBD(7-0) and CBP Valid

LBC Pulse Width High

ns

T6

60

ns

T7

225

265

35

475

515

45

ns

T8

ns

T9

ns

T10

T11

T12

LBC Pulse Width Low

35

45

ns

CE High to ACK High

45

ns

R/W, CBA(7-0), CBD(7-0) and

CBP Set up to CE Low

5

0

ns

T13

CE HIgh to R/W, CBA(7-0),

CBD(7-0) and CBP Hold Time

T14a

T14b

T14c

T15

R/W to LBC Setup Time

0

10

0

ns

CBA to LBC Setup Time

CBD and CBP to LBC Setup Time

ACK Low to CE High Lead Time

CE Minimum Pulse Width High

CE High to CBD(7-0) and CBP TRI-STATE

ACK High to CE Low

0

T16

20

T17

55

T18

0

T19

CBD(7-0) Valid to ACK Low Setup

LBC to R/W Hold Time

20

10

20

T20a

T20b

T20c

T21

LBC to CBA Hold Time

LBC to CBD and CBP Hold Time

LBC to INT Low

55

60

T22

LBC to INT High

Asynchronous Definitions

a

T4 (min)

T4 (max)

T7 (min)

T7 (max)

T8 (min)

T8 (max)

T1

(3 * T2)

(4 * T2)

(2 * T2)

(3 * T2)

(2 * T2)

(3 * T2)

T3

T6

T9

T1

a

T5

e

T10 40ns.

Note: Min/Max numbers are based on T2

80 ns and T9

80

7.0 Electrical Characteristics (Continued)

TL/F/10386–23

TL/F/10386–22

FIGURE 7-1. Control Bus Write Cycle Timing

FIGURE 7-2. Control Bus Read Cycle Timing

TL/F/10386–35

FIGURE 7-3. Control Bus Synchronous Write Cycle Timing

TL/F/10386–24

FIGURE 7-4. Control Bus Synchronous Read Cycle Timing

TL/F/10386–44

FIGURE 7-5. Control Bus Interrupt Timing

81

7.0 Electrical Characteristics (Continued)

AC Characteristics for the Clock Signals

Symbol

T23

Parameter

TBC to TXC Hold Time

TBC to TXC Setup Time

TBC to LBC Skew

RXC Duty Cycle

Conditions

(Note 1)

Min

2

Typ

Max

Units

ns

T24

(Note 1)

2.5

10

3.0

3.5

37

35

ns

T25

22

5.0

4.5

43

ns

T26

(Note 1)

ns

T27

TXC Duty Cycle

ns

T28

TBC Duty Cycle

ns

T29

LBC Duty Cycle

45

ns

Note 1: RXC duty cycle, TXC duty cycle, and TBC to TXC setup time are not tested, but are assured by correlation with characterization data.

Note 2: When PLAYER is used in FDDI applications, TBC and LBC periods will be 80 ns and RXC and TXC periods will be 8 ns.

TL/F/10386–36

FIGURE 7-6. Clock Signals

82

7.0 Electrical Characteristics (Continued)

AC Characteristics for PHY Port Interfaces

Symbol

Parameter

Conditions

Min

Typ

Max

Units

T30

LBC to Indicate Data Changes

from TRI-STATE to Data Valid

70

ns

T31

LBC to Indicate Data Changes

from Active to TRI-STATE

70

45

ns

T32

T33

T34

T35

LBC to Indicate Data Sustain

LBC to Valid Indicate Data

7

ns

Request Data to LBC Setup Time

Request Data to LBC Hold Time

15

5

TL/F/10386–37

FIGURE 7-7. PHY Port Interface Timing

83

7.0 Electrical Characteristics (Continued)

AC Characteristics for the Serial Interface

Symbol

T36

Parameter

Conditions

Min

2

Typ

Max

Units

ns

RXD to RXC Setup Time

RXD to RXC Hold Time

TXC to TXD Change Time

TXC to LBD Change Time

CD Min Pulse Width

T37

2

ns

T38

8

ns

T39

ns

T40

120

ns

T41

SD Min Pulse Width

ns

TL/F/10386–38

FIGURE 7-8. Serial Interface Timing

84

7.0 Electrical Characteristics (Continued)

7.5 AC TEST CIRCUITS

TL/F/10386–28

FIGURE 7-10. Switching Test Circuit

for All TTL Output Signals

TL/F/10386–26

Note: S is closed for T

1

and T

PZL

PLZ

S

2

S

1

is closed for T

PZH

PHZ

and S are open otherwise

2

FIGURE 7-9. Switching Test Circuit

for All TRI-STATE Output Signals

TL/F/10386–30

e

Note: C

L

test fixture

30 pF includes scope and all stray capacitance without device in

TL/F/10386–29

FIGURE 7-11. Switching Test Circuit

for All Open Drain Output Signals

(INT, ACK and CR)

FIGURE 7-12. Switching Test Circuit

for All ECL Input and Output Signals

85

Test Waveforms

TL/F/10386–39

FIGURE 7-13. ECL Output Test Waveform

TL/F/10386–40

Note: All CMOS inputs and outputs are TTL compatible

FIGURE 7-14. TTL Output Test Waveform

TL/F/10386–41

FIGURE 7-15. TRI-STATE Output Test Waveform

86

8.0 Detailed Descriptions

This section describes in detail several functions that had

been discussed previously in Section 3.0, Functional De-

scriptions.

8.2 NOISE EVENTS

A Noise Event is defined as follows:

A noise event is a noise byte, a byte of data which is not in

line with the current line state, indicating error or corruption.

8.1 FRAMING HOLD RULES

DETECTING JK

e

E

a

]

CD

[

Noise Event

SD

#

The JK symbol pair can be used to detect the beginning of a

frame during Active Line State (ALS) and Idle Line State

(ILS).

E

#

PI (PB

a

]

AB)

SD CD PI

#

SD CD

(II

JK

E

e

II) AB

]

#

While the Line State Detector is in the Idle Line State the

PLAYER device ‘‘reframes’’ upon detecting a JK symbol

pair and enters the Active Line State.

Where:

e

Logical AND

Logical OR

Logical NOT

#

a

During Active Line State, acceptance of a JK symbol (re-

framing) is allowed on any on-boundary JK which is detect-

ed at least 1.5 byte times after the previous JK.

E

e

SD

CD

PB

PLS

PI

Signal Detect

Clock Detect

Previous Byte

During Active Line State, once reframed on a JK, the subse-

quent off-boundary JK is ignored, even if it is detected be-

yond 1.5 byte times after the previous JK.

Previous Line State

During Active Line State, an Idle or Ending Delimiter (T)

symbol will allow reframing on any subsequent JK, if a JK is

detected at least 1.5 bytes times after the previous JK.

e

a

#

a

MLS

PHY Invalid

HLS

NLS

(ALS

QLS

À

ILS)

e

[

ULS

PLS

Ó

]

DETECTING HALT-HALT & HALT-QUIET

During Idle Line State, the detection of a Halt-Halt, or Halt-

Quiet symbol pair will still allow the reframing of any subse-

quent on-boundary JK.

e

ILS

Idle Line State

ALS

ULS

HLS

QLS

MLS

NLS

ULS

Active Line State

Unknown Line State

Halt Line State

Once a JK is detected during Active Line State, off-bounda-

ry Halt-Halt, or Halt-Quiet symbol pairs are ignored until the

Elasticity Buffer (EB) has an opportunity to recenter. They

are treated as violations.

Quiet Line State

Master Line State

Noise Line State

Unknown Line State

After recentering on a Halt-Halt, or Halt-Quiet symbol pair,

all off-boundary Halt-Halt or Halt-Quiet symbol pairs are ig-

nored until the EB has a chance to recenter during a line

state other than Active Line State (which may be as long as

2.8 byte times).

e

I

Idle symbol

J

First symbol of start delimiter

K

R

S

T

A

B

n

Second symbol of start delimiter

Reset symbol

Set symbol

End delimiter

a

n

R

S

T

a

I

Any data symbol

87

8.0 Detailed Descriptions (Continued)

8.3 LINK ERRORS

A Link Error is defined as follows:

e

E

[

a

Vx

[

H

E

[

ror Flag

Ð

II

Link Error Event

ALS

E

(II

ULS

(I

a

I

ALS

xV

E

SD

ILS

#

a

E

]

[

SD)

H)

ILS

#

a

#

a

]

(PLS

[

]

JK)

#

e

SB

ALS)

Link Er-

#

(HH

Ð

a

HI

E

a

#

a

]

JK)

e

a

NH RH

[

SH

Set Link Error Flag

Ð Ð

ALS (HH

#

a

]

TH)

e

a

(PLS

a

[

]

[

]

ALS

Clear Link Error Flag

Ð Ð

ALS JK

ILS JK

e

#

ULS

#

E

JK)

Link Error Flag

Ð

SB

#

Ð

(HH

E

a

]

HI

II

Where:

E

a

e

Logical NOT

Logical OR

Logical AND

e

#

e

ILS

Idle Line State

ALS

ULS

Active Line State

Unknown Line State

e

x

Any symbol

Idle symbol

Halt symbol

I

H

J

First Symbol of start delimiter

K

V

R

S

T

N

Second symbol of start delimiter

Violation symbol

Reset symbol

Set symbol

End delimiter symbol

Data symbol converted to 0000 by the PLAY-

ER device Receiver Block in symbol pairs that

contain a data and a control symbol

e

PLS

SD

Previous Line State

Signal Detect

SB

Stuff Byte: Byte inserted by EB before a JK

symbol pair for recentering or due to off-axis

JK

88

8.0 Detailed Description (Continued)

8.4 REPEAT FILTER

The repeat filter prevents the propagation of code violations to the downstream station.

TL/F/10386–31

Note: Inputs to the Repeat Filter state machine are shown above the transition lines, while outputs from the state machine are shown below the transition lines.

Note: Abbreviations used in the Repeat Filter State Diagram are shown in Table VIII.

FIGURE 8-1. Repeat Filter State Diagram

89

8.0 Detailed Descriptions (Continued)

The Repeat Filter complies with the FDDI standard by ob-

serving the following:

TABLE 8-1. Abreviations used in

the Repeat Filter State Diagram

1. In Repeat State, violations cause transitions to the Halt

State and two Halt symbol pairs are transmitted (unless

JK or Ix occurs) followed by transition to the Idle State.

F

IDLE:

Force IdleÐTrue when not in Active

Transmit Mode

Ð

2. When Ix is encountered, the Repeat Filter goes to the Idle

State, during which Idle symbol pairs are transmitted until

a JK is encountered.

W:

Represents the symbols R, or S, or T

E

TPARITY: Parity error

Data symbols (for C

Interface)

e

nn:

0 in the PHY-MAC

3. The Repeat Filter goes to the Repeat State following a JK

from any state.

N:

X:

Data portion of a control and data symbol

mixture

The END State, which is not part of the FDDI standard,

allows an R or S prior to a T within a frame to be recognized

as a violation. It also allows NT to end a frame as opposed

to being treated as a violation.

Any symbol (i.e. don’t care)

V :

Ê

Violation symbols or symbols inserted by

the Receiver Block

I :

Ê

Idle symbols or symbols inserted by the

Receiver Block

ALSZILSZ:

Active Line State or Idle Line State (i.e.

PHY Invalid)

E

ALSZILSZ: Not in Active Line State nor in Idle Line

State (i.e. PHY Valid)

H:

R:

S:

T:

Halt symbol

Reset symbol

Set symbol

Frame ending delimiter

JK:

I:

Frame start delimiter

Idle symbol (Preamble)

Code violations

V:

90

8.0 Detailed Descriptions (Continued)

8.5 SMOOTHER

Notes:

TL/F/10386–32

SE: Smoother Enable

C: Preamble Counter

F

IDLE: Force Idle (Stop or ATM)

Ð

X : Current Byte

Ð

n

X

: Previous Byte

1

b

W: RST

n

FIGURE 8-2. Smoother State Diagram

91

8.0 Detailed Descriptions (Continued)

8.6 NATIONAL BYTE-WIDE CODE FOR PHY-MAC IN-

TERFACE

Line State are Idle symbols, then the Symbol Decoder gen-

erates I’kILS as its output. Note that in this case the coded

byte is represented in the form Receive State (b7–4),

Known/Unknown Bit (b3) and the Last Known Line State

(b2–0). The Receive State is 4 bits long and it represents

either the PHY Invalid (0011) or the Idle Line State (1011)

condition. The Known/Unknown Bit shows if the symbols

received match the line state information in the last 3 bits.

The PLAYER device outputs the National byte-wide code

from its PHY Port Indicate Output to the MAC device. Each

National byte-wide code may contain data or control codes

or the line state information of the connection. Table 8-2

lists all the possible outputs.

During Active Line State all data and control symbols are

being repeated to the PHY Port Indicate Output with the

exception of data in data-control mixture bytes. That data

sybmol is replaced by zero. If only one symbol in a byte is a

control symbol, the data symbol will be replaced by 0000

and the whole byte will be presented as control code. Note

that the Line State Detector recognizes the incoming data

to be in the Active Line State upon reception of the Starting

Delimiter (JK symbol pair).

During any line state other than Idle Line State or Active

Line State, the Symbol Decoder generates the code V kLS

Ê

if the incoming symbols match the current line state. The

symbol decoder generates V’uLS if the incoming symbols

do not match the current line state.

During Idle Line State any non Idle symbols will be reflected

as the code I’uILS. If both symbols received during Idle

92

8.0 Detailed Descriptions (Continued)

Table 8-2.

Symbol 1

Symbol 2

Control Bit Data

National Code

Control Bit Data

Current Line State

Control Bit

Data

ALS

ILS

0,

1,

x,

1,

x,

n

0,

1,

0,

1,

x,

1,

x,

1,

x,

1,

x,

n

0,

1,

n-n

n

C

N-C

C

n

C-N

C

C-C

I

I’-k-LS

I’-u-LS

I’-k-ILS

V’-k-LS

V’-u-LS

ILS

I

Not I

ILS

Not I

x

I

ILS

Not I

x

Stuff Byte during ILS

Not ALS and Not ILS

M

Not M

M

Not M

x

Not M

x

Stuff Byte during

Not ILS

V’-k-LS, V’-u-LS

or I’-u-ILS

EB Overflow/Underflow

SMT PI Connnection (LSU)

Where:

1,

0011 1011

0011 1010

e

À

Any data symbol in 0, 1, 2, ... F

Any control symbol in V, R, S, T, I, H

Ó

n

À Ó

C

N

I

M

I’

e

Idle Symbol

0000

Code for data symbol in a data control mixture byte

Any symbol that matches the current line state

e

1011

0011

First symbols of the byte in Idle Line State

PHY Invalid

V’

LS

Line State

e

ALS

ILS

000

001

010

100

101

110

111

NSD

MLS

HLS

QLS

NLS

e

u

k

x

1

0

Indicates symbol received does not match current line state

Indicates symbol received matches current line state

Don’t care

93

8.0 Detailed Descriptions (Continued)

Example:

Incoming 5B Code

98765 43210

Decoded 4B Code

National Byte-Wide Code (w/o parity)

C 7653 3210

C3210 C 3210

11111 11111 (II)

11000 10001 (JK)

- - - - - - - - - - (xx)

(More data ...)

1 1010 1 1010 (II)

1 1101 1 1101 (JK)

0 - - - - 0 - - - - (xx)

1 1011 0001 (I’-k-ILS)*

1 1011 0001 (I’-k-ILS)

1 1101 1101 (JK Symbols)

0 - - - - - - - - (Data Symbols)

- - - - - - - - - - (xx)

01101 00111 (TR)

00111 00111 (RR)

11111 11111 (II)

00100 00100 (HH)

11111 11111 (II)

0 - - - - 0 - - - - (xx)

1 0101 1 0110 (TR)

1 0110 1 0110 (RR)

1 1010 1 1010 (II)

1 0001 1 0001 (HH)

1 1010 1 1010 (II)

0 - - - - - - - - (Data Symbols)

1 0101 0110 (T and R Symbols)

1 0110 0110 (Two R Symbols)

1 1010 1010 (Idle Symbols)

1 1011 0001 (I’-k-ILS)

1 1011 1001 (I’-u-ILS)

1 0011 0101 (V’-k-HLS)

1 0011 1101 (V’-u-HLS)

1 1011 0001 (I’-k-ILS)

11111 11111 (II)

1 1011 0001 (I’-k-ILS)

*Assume the receiver is in the Idle Line State.

94

Physical Dimensions inches (millimeters)

Plastic Leaded Chip Carrier

Order Number DP83251V

NS Package Number V84A

95

Physical Dimensions inches (millimeters) (Continued)

Plastic Quad Pack (VF)

Order Number DP83255AVF

NS Package Number VF132A

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or

systems which, (a) are intended for surgical implant

into the body, or (b) support or sustain life, and whose

failure to perform, when properly used in accordance

with instructions for use provided in the labeling, can

be reasonably expected to result in a significant injury

to the user.

2. A critical component is any component of a life

support device or system whose failure to perform can

be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or

effectiveness.

National Semiconductor

Corporation

National Semiconductor

Europe

National Semiconductor

Hong Kong Ltd.

National Semiconductor

Japan Ltd.

a

1111 West Bardin Road

Arlington, TX 76017

Tel: 1(800) 272-9959

Fax: 1(800) 737-7018

Fax:

(

49) 0-180-530 85 86

@

13th Floor, Straight Block,

Ocean Centre, 5 Canton Rd.

Tsimshatsui, Kowloon

Hong Kong

Tel: (852) 2737-1600

Fax: (852) 2736-9960

Tel: 81-043-299-2309

Fax: 81-043-299-2408

Email: cnjwge tevm2.nsc.com

a

Deutsch Tel:

English Tel:

Fran3ais Tel:

Italiano Tel:

(

49) 0-180-530 85 85

49) 0-180-532 78 32

49) 0-180-532 93 58

49) 0-180-534 16 80

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.


型号：	DP83255
厂家：	National Semiconductor
描述：	PLAYER Device (FDDI Physical Layer Controller) 播放器设备（ FDDI的物理层控制器）电信集成电路信息通信管理控制器
文件：	总96页 (文件大小：654K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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