DS10CP154A [NSC]
1.5 Gbps 4x4 LVDS Crosspoint Switch; 1.5 Gbps的LVDS 4×4交叉点开关
| 型号： | DS10CP154A |
| 厂家： | 
National Semiconductor |
| 描述： | 1.5 Gbps 4x4 LVDS Crosspoint Switch |
| 文件： | 总18页 (文件大小：328K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 23, 2009
DS10CP154A
1.5 Gbps 4x4 LVDS Crosspoint Switch
General Description
Features
The DS10CP154A is a 1.5 Gbps 4x4 LVDS crosspoint switch
optimized for high-speed signal routing and switching over
FR-4 printed circuit board backplanes and balanced cables.
Fully differential signal paths ensure exceptional signal in-
tegrity and noise immunity. The non-blocking architecture
allows connections of any input to any output or outputs. The
switch configuration can be accomplished via external pins or
the System Management Bus (SMBus) interface. In addition,
the SMBus circuitry enables the loss of signal (LOS) monitors
that can inform a system of the presence of an open inputs
condition (e.g. disconnected cable).
DC - 1.5 Gbps low jitter, low skew, low power operation
■
■
Pin and SMBus configurable, fully differential, non-
blocking architecture
Wide input common mode range enables DC coupled
interface to CML or LVPECL drivers
■
LOS circuitry detects open inputs fault condition
■
■
On-chip 100 Ω input and output termination minimizes
insertion and return losses, reduces component count and
minimizes board space
8 kV ESD on LVDS I/O pins protects adjoining
components
Small 6 mm x 6 mm LLP-40 space saving package
■
■
Wide input common mode range allows the switch to accept
signals with LVDS, CML and LVPECL levels; the output levels
are LVDS. A very small package footprint requires a minimal
space on the board while the flow-through pinout allows easy
board layout. Each differential input and output is internally
terminated with a 100Ω resistor to lower return losses, reduce
component count and further minimize board space.
Applications
High-speed channel select applications
■
■
■
Clock and data buffering and muxing
SD / HD SDI Routers
Typical Application
30073703
© 2009 National Semiconductor Corporation
300737
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Ordering Code
NSID
Function
DS10CP154ATSQ
Crosspoint Switch
Block Diagram
30073701
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Connection Diagram
30073702
DS10CP154A Pin Diagram
3
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Pin Descriptions
Pin Name
Pin
I/O, Type
Pin Description
Number
IN0+, IN0- ,
IN1+, IN1-,
IN2+, IN2-,
IN3+, IN3-
1, 2,
4, 5,
6, 7,
9, 10
I, LVDS
Inverting and non-inverting high speed LVDS input pins.
OUT0+, OUT0-,
OUT1+, OUT1-,
OUT2+, OUT2-,
OUT3+, OUT3-
29, 28,
27, 26,
24, 23,
22, 21
O, LVDS
Inverting and non-inverting high speed LVDS output pins.
EN_smb
17
I, LVCMOS
I/O, LVCMOS
I/O, LVCMOS
I/O, LVCMOS
I, LVCMOS
I, LVCMOS
System Management Bus (SMBus) mode enable pin. The pin has
an internal 20k pull down. When the pin is set to a [1], the device
is in the SMBus mode. All SMBus registers are reset when the pin
is toggled.
S00/SCL,
S01/SDA
37,
36
For EN_smb = [0], these pins select which LVDS input is routed
to the OUT0.
In the SMBus mode, when the EN_smb = [1], these pins are the
SMBus clock input and data I/O pins respectively.
S10/ADDR0,
S11/ADDR1
35,
34
For EN_smb = [0], these pins select which LVDS input is routed
to the OUT1.
In the SMBus mode, when the EN_smb = [1], these pins are the
User-Set SMBus Slave Address inputs.
S20/ADDR2,
S21/ADDR3
33,
32
For EN_smb = [0], these pins select which LVDS input is routed
to the OUT2.
In the SMBus mode, when the EN_smb = [1], these pins are the
User-Set SMBus Slave Address inputs.
S30, S31
PWDN
13, 14
38
For EN_smb = [0], these pins select which LVDS input is routed
to the OUT3.
In the SMBus mode, when the EN_smb = [1], these pins are non-
functional and should be tied to either logic [0] or [1].
For EN_smb = [0], this is the power down pin. When the PWDN is
set to a [0], the device is in the power down mode. The SMBus
circuitry can still be accessed provided the EN_smb pin is set to a
[1].
In the SMBus mode, the device is powered up by either setting the
PWDN pin to [1] OR by writing a [1] to the Control Register D[7]
bit ( SoftPWDN). The device will be powered down by setting the
PWDN pin to [0] AND by writing a [0] to the Control Register D[7]
bit ( SoftPWDN).
NC
11, 12,
18, 19,
20, 31,
39, 40
No connect pins. May be left floating.
VDD
GND
3, 8,
15,25, 30
Power
Power supply pins.
16, DAP Power
Ground pin and pad (DAP - die attach pad).
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Package Thermal Resistance
Absolute Maximum Ratings (Note 4)
ꢀθJA
+26.9°C/W
+3.8°C/W
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
ꢀθJC
ESD Susceptibility
HBM (Note 1)
Supply Voltage
−0.3V to +4V
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
−0.3V to +4V
≥8 kV
≥250V
≥1250V
LVCMOS Input Voltage
LVCMOS Output Voltage
LVDS Input Voltage
MM (Note 2)
CDM (Note 3)
Note 1: Human Body Model, applicable std. JESD22-A114C
Note 2: Machine Model, applicable std. JESD22-A115-A
LVDS Differential Input Voltage
LVDS Output Voltage
0V to 1.0V
−0.3V to (VCC + 0.3V)
0V to 1.0V
Note 3: Field Induced Charge Device Model, applicable std.
JESD22-C101-C
LVDS Differential Output Voltage
LVDS Output Short Circuit Current
Duration
Junction Temperature
Storage Temperature Range
Lead Temperature Range
Soldering (4 sec.)
Maximum Package Power Dissipation at 25°C
SQA Package
Derate SQA Package
5 ms
Recommended Operating
Conditions
+150°C
−65°C to +150°C
Min
3.0
0
Typ
Max Units
Supply Voltage (VCC
)
3.3
3.6
1.0
V
V
+260°C
Receiver Differential Input
Voltage (VID)
4.65W
37.2 mW/°C above +25°C
Operating Free Air
Temperature (TA)
−40
+25
+85
3.6
°C
V
SMBus (SDA, SCL)
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 5, 6, 7)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LVCMOS DC SPECIFICATIONS
VIH
VIL
IIH
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
2.0
VDD
0.8
V
GND
V
VIN = 3.6V
VCC = 3.6V
0
175
0
±10
250
±10
μA
μA
μA
EN_smb pin
40
IIL
Low Level Input Current
VIN = GND
VCC = 3.6V
VCL
VOL
Input Clamp Voltage
ICL = −18 mA, VCC = 0V
IOL= 4 mA SDA pin
−0.9
−1.5
0.4
V
V
Low Level Output Voltage
LVDS INPUT DC SPECIFICATIONS
VID
Input Differential Voltage
0
1
V
mV
mV
V
VCM = +0.05V or VCC-0.05V
VID = 100 mV
VTH
VTL
Differential Input High Threshold
Differential Input Low Threshold
Common Mode Voltage Range
0
0
+100
−100
0.05
VCMR
VCC -
0.05
±10
VIN = 3.6V or 0V
VCC = 3.6V or 0V
±1
μA
IIN
Input Current
CIN
RIN
1.7
pF
Input Capacitance
Any LVDS Input Pin to GND
Between IN+ and IN-
100
Input Termination Resistor
Ω
5
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Symbol
Parameter
Conditions
Min
Typ
Max
Units
LVDS OUTPUT DC SPECIFICATIONS
VOD
Differential Output Voltage
250
-35
350
450
35
mV
mV
V
RL = 100Ω
RL = 100Ω
Change in Magnitude of VOD for Complimentary
Output States
ΔVOD
VOS
Offset Voltage
1.05
-35
1.2
1.375
35
Change in Magnitude of VOS for Complimentary
Output States
ΔVOS
mV
IOS
Output Short Circuit Current (Note 8)
OUT to GND
-25
7
-55
55
mA
mA
pF
Ω
OUT to VCC
COUT
ROUT
Output Capacitance
Any LVDS Output Pin to GND
Between OUT+ and OUT-
1.2
100
Output Termination Resistor
SUPPLY CURRENT
ICC1 Supply Current
ICC2
PWDN = 0
40
50
mA
mA
Supply Current
Supply Current
PWDN = 1
Broadcast Mode (1:4)
103
125
ICC3
PWDN = 1
115
140
mA
Quad Buffer Mode (4:4)
Note 4: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 5: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 6: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD and
ΔVOD
.
Note 7: Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 8: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
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AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 9, 10)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LVDS OUTPUT AC SPECIFICATIONS (Note 11)
tPLHD
tPHLD
Differential Propagation Delay Low to
High
500
460
675
675
ps
ps
RL = 100Ω
Differential Propagation Delay High to
Low
tSKD1
tSKD2
tSKD3
tLHT
Pulse Skew |tPLHD − tPHLD| , (Note 12)
Channel to Channel Skew , (Note 13)
Part to Part Skew , (Note 14)
Rise Time
40
40
50
145
145
7
100
125
225
350
350
20
ps
ps
ps
ps
ps
RL = 100Ω
tHLT
Fall Time
tON
Power Up Time
Time from PWDN = LH to OUTn active
μs
tOFF
Power Down Time
Time from PWDN = HL to OUTn
inactive
6
25
ns
tSEL
Select Time
Time from Sn = LH or HL to new signal
at OUTn
8
12
ns
JITTER PERFORMANCE (Note 11)
tRJ1
VID = 350 mV
VCM = 1.2V
Clock (RZ)
135 MHz
311 MHz
503 MHz
750 MHz
270 Mbps
622 Mbps
1.06 Gbps
1.5 Gbps
270 mbps
622 Mbps
1.06Gbps
1.5 Gbps
1
0.5
0.5
0.5
7
2.0
1.2
1.0
1.0
30
ps
ps
Random Jitter
(RMS Value)
(Note 15)
tRJ2
tRJ3
ps
tRJ4
tDJ1
ps
VID = 350 mV
VCM = 1.2V
ps
Deterministic Jitter
(Peak to Peak Value)
(Note 16)
tDJ2
12
9
26
ps
K28.5 (NRZ)
tDJ3
24
ps
tDJ4
12
28
ps
tTJ1
VID = 350 mV
VCM = 1.2V
UIP-P
UIP-P
UIP-P
UIP-P
0.008 0.036
0.007 0.043
0.008 0.064
0.007 0.072
Total Jitter
tTJ2
(Peak to Peak Value)
(Note 17)
PRBS-23 (NRZ)
tTJ3
tTJ4
7
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Symbol
Parameter
Conditions
Min
Typ
Max
Units
SMBus AC SPECIFICATIONS
fSMB
tBUF
SMBus Operating Frequency
10
100
kHz
Bus free time between Stop and Start
Conditions
4.7
μs
tHD:SDA
Hold time after (Repeated) Start
Condition. After this period, the first clock
is generated.
4.0
μs
tSU:SDA
tSU:SDO
tHD:DAT
tSU:DAT
tTIMEOUT
tLOW
Repeated Start Condition setup time.
Stop Condition setup time
Data hold time
4.7
4.0
300
250
25
μs
μs
ns
ns
ms
μs
μs
Data setup time
Detect clock low timeout
Clock low period
35
4.7
4.0
tHIGH
Clock high period
50
tPOR
Time in which a device must be
operational after power-on reset
500
ms
Note 9: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 10: Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 11: Specification is guaranteed by characterization and is not tested in production.
Note 12: tSKD1, |tPLHD − tPHLD|, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and the negative
going edge of the same channel.
Note 13: tSKD2, Channel to Channel Skew, is the difference in propagation delay (tPLHD or tPHLD) among all output channels in Broadcast mode (any one input to
all outputs).
Note 14: tSKD3, Part to Part Skew, is defined as the difference between the minimum and maximum differential propagation delays. This specification applies to
devices at the same VCC and within 5°C of each other within the operating temperature range.
Note 15: Measured on a clock edge with a histogram and an acummulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically.
Note 16: Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is subtracted
algebraically.
Note 17: Measured on an eye diagram with a histogram and an acummulation of 3500 histogram hits. Input stimulus jitter is subtracted.
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DC Test Circuits
30073720
FIGURE 1. Differential Driver DC Test Circuit
AC Test Circuits and Timing Diagrams
30073721
FIGURE 2. Differential Driver AC Test Circuit
30073722
FIGURE 3. Propagation Delay Timing Diagram
30073723
FIGURE 4. LVDS Output Transition Times
9
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Functional Description
The DS10CP154A is a 1.5 Gbps 4x4 LVDS digital crosspoint
switch optimized for high-speed signal routing and switching
over lossy FR-4 printed circuit board backplanes and bal-
anced cables. The DS10CP154A operates in two modes: Pin
Mode (EN_smb = 0) and SMBus Mode (EN_smb = 1).
and S31 pins become non-functional (tieing these two pins to
either H or L is recommended if the device will function only
in the SMBus mode).
In the SMBus Mode, the PWDN pin remains functional. How
this pin functions in each mode is detailed in the following
sections.
When in the Pin Mode, the switch is fully configurable with
external pins. This is possible with two input select pins per
output (e.g. S00 and S01 pins for OUT0).
DS10CP154A OPERATION IN THE PIN MODE
Power Up
In the Pin Mode, feedback from the LOS (Loss Of Signal)
monitor circuitry is not available (there is not an LOS output
pin).
In the Pin Mode, when the power is applied to the device
power suppy pins, the DS10CP154A enters the Power Up
mode when the PWDN pin is set to logic H. When in the Power
Down mode (PWDN pin is set to logic L), all circuitry is shut
down except the minimum required circuitry for the LOS and
SMBus Slave operation.
When in the SMBus Mode, the full switch configuration and
SoftPWDN can be programmed via the SMBus interface. In
addition, by using the SMBus interface, a user can obtain the
feedback from the built-in LOS circuitry which detects an open
inputs fault condition.
Switch Configuration
In the SMBus Mode, the S00 and S01 pins become SMBus
clock (SCL) input and data (SDA) input pins respectively; the
S10, S11, S21 and S21 pins become the User-Set SMBus
Slave Address input pins (ADDR0, 1, 2 and 3) while the S30
In the Pin Mode, the DS10CP154A operates as a fully pin-
configurable crosspoint switch. The following truth tables il-
lustrate how the swich can be configured with external pins.
Switch Configuration Truth Tables
TABLE 1. Input Select Pins Configuration for the Output OUT0
S01
0
S00
0
INPUT SELECTED
IN0
IN1
IN2
IN3
0
1
1
0
1
1
TABLE 2. Input Select Pins Configuration for the Output OUT1
S11
0
S10
0
INPUT SELECTED
IN0
IN1
IN2
IN3
0
1
1
0
1
1
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TABLE 3. Input Select Pins Configuration for the Output OUT2
S21
0
S20
0
INPUT SELECTED
IN0
IN1
IN2
IN3
0
1
1
0
1
1
TABLE 4. Input Select Pins Configuration for the Output OUT3
S31
0
S30
0
INPUT SELECTED
IN0
IN1
IN2
IN3
0
1
1
0
1
1
DS10CP154A OPERATION IN THE SMBUS MODE
slave address are hard wired inside the DS10CP154A and
are “101”. The four least significant bits of the address are
assigned to pins ADDR3-ADDR0 and are set by connecting
these pins to GND for a low (0) or to VCC for a high (1). The
complete slave address is shown in the following table:
The DS10CP154A operates as a slave on the System Man-
agement Bus (SMBus) when the EN_smb pin is set to a high
(1). Under these conditions, the SCL pin is a clock input while
the SDA pin is a serial data input pin.
Device Address
Based on the SMBus 2.0 specification, the DS10CP154A has
a 7-bit slave address. The three most significant bits of the
TABLE 5. DS10CP154A Slave Address
1
0
1
ADDR3
ADDR2
ADDR1
ADDR0
LSB
MSB
This slave address configuration allows up to sixteen
DS10CP154A devices on a single SMBus bus.
2) The Device (Slave) drives an ACK bit (“0”).
3) The Host drives the 8-bit Register Address.
4) The Device drives an ACK bit (“0”).
5) The Host drives the 8-bit data byte.
6) The Device drives an ACK bit “0”.
Transfer of Data via the SMBus
During normal operation the data on SDA must be stable dur-
ing the time when SCK is high.
7) The Host drives a STOP condition.
There are three unique states for the SMBus:
The WRITE transaction is completed, the bus goes Idle and
communication with other SMBus devices may now occur.
START: A HIGH to LOW transition on SDA while SCK is high
indicates a message START condition.
STOP: A LOW to HIGH transition on SDA while SCK is high
indicates a message STOP condition.
Reading From a Register
To read a register, the following protocol is used (see SMBus
2.0 specification):
IDLE: If SCK and SDA are both high for a time exceeding
tBUF from the last detected STOP condition or if they are high
for a total exceeding the maximum specification for tHIGH
then the bus will transfer to the IDLE state.
1) The Host drives a START condition, the 7-bit SMBus ad-
dress, and a “0” indicating a WRITE.
2) The Device (Slave) drives an ACK bit (“0”).
3) The Host drives the 8-bit Register Address.
4) The Device drives an ACK bit (“0”).
SMBus Transactions
A transaction begins with the host placing the DS10CP154A
SMBus into the START condition, then a byte (8 bits) is trans-
ferred, MSB first, followed by a ninth ACK bit. ACK bits are ‘0’
to signify an ACK, or ‘1’ to signify NACK, after this the host
holds the SCL line low, and waits for the receiver to raise the
SDA line as an ACKnowledge that the byte has been re-
ceived.
5) The Host drives a START condition.
6) The Host drives the 7-bit SMBus Address, and a “1” indi-
cating a READ.
7) The Device drives an ACK bit “0”.
8) The Device drives the 8-bit data value (register contents).
9) The Host drives a NACK bit “1” indicating end of READ
transfer.
Writing to a Register
To write a register, the following protocol is used (see SMBus
2.0 specification):
10) The Host drives a STOP condition.
The READ transaction is completed, the bus goes Idle and
communication with other SMBus devices may now occur.
1) The Host drives a START condition, the 7-bit SMBus ad-
dress, and a “0” indicating a WRITE.
11
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REGISTER DESCRIPTIONS
There are three data registers in the DS10CP154A accessible via the SMBus interface.
TABLE 6. DS10CP154A SMBus Data Registers
Address
Name
Access
Description
(hex)
0
3
4
Switch Configuration
R/W
R/W
RO
Switch Configuration Register
Control
LOS
Powerdown, LOS Enable and Pin Control Register
Loss Of Signal (LOS) Reporting Register
30073710
FIGURE 5. DS10CP154A Registers Block Diagram
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Switch Configuration Register
The Switch Configuration register is utilized to configure the switch. The following two tables show the Switch Configuration Register
mapping and associated truth table.
Bit
Default
00
Bit Name
Access
R/W
Description
D[1:0]
D[3:2]
D[5:4]
D[7:6]
Input Select 0
Input Select 1
Input Select 2
Input Select 3
Selects which input is routed to the OUT0.
Selects which input is routed to the OUT1.
Selects which input is routed to the OUT2.
Selects which input is routed to the OUT3.
00
R/W
00
R/W
00
R/W
TABLE 7. Switch Configuration Register Truth Table
Input Routed to the OUT0
D1
0
D0
0
IN0
IN1
IN2
IN3
0
1
1
0
1
1
The truth tables for the OUT1, OUT2, and OUT3 outputs are identical to this table.
The switch configuration logic has a SmartPWDN circuitry which automatically optimizes the device's power consumption based
on the switch configuration (i.e. It places unused I/O blocks and other unused circuitry in the power down state).
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Control Register
The Control register enables SoftPWDN control, individual output power down (PWDNn) control and LOS Circuitry Enable control
via the SMBus. The following table shows the register mapping.
Bit
Default
Bit Name
Access Description
D[3:0]
1111
PWDNn
R/W
Writing a [0] to the bit D[n] will power down the output OUTn
when either the PWDN pin OR the Control Register bit D[7]
(SoftPWDN) is set to a high [1].
D[4]
D[5]
D[6]
x
x
0
n/a
R/W
R/W
R/W
Undefined.
Undefined.
n/a
EN_LOS
Writing a [1] to the bit D[6] will enable the LOS circuitry and
receivers on all four inputs. The SmartPWDN circuitry will not
disable any of the inputs nor any supporting LOS circuitry
depending on the switch configuration.
D[7]
0
SoftPWDN
R/W
Writing a [0] to the bit D[7] will place the device into the power
down mode. This pin is ORed together with the PWDN pin.
TABLE 8. DS10CP154A Power Modes Truth Table
PWDN
SoftPWDN
PWDNn
DS25CP104 Power Mode
0
0
x
Power Down Mode. In this mode, all circuitry is shut down except the
minimum required circuitry for the LOS and SMBus Slave operation. The
SMBus circuitry allows enabling the LOS circuitry and receivers on all inputs
in this mode by setting the EN_LOS bit to a [1].
0
1
1
1
0
1
x
x
x
Power Up Mode. In this mode, the SmartPWDN circuitry will automatically
power down any unused I/O and logic blocks and other supporting circuitry
depending on the switch configuration.
An output will be enabled only when the SmartPWDN circuitry indicates that
that particular output is needed for the particular switch configuration and
the respective PWDNn bit has logic high [1].
An input will be enabled when the SmartPWDN circuitry indicates that that
particular input is needed for the particular switch configuration or the
EN_LOS bit is set to a [1].
LOS Register
The LOS register reports an open inputs fault condition for each of the inputs. The following table shows the register mapping.
Bit
Default
Bit Name
Access Description
D[0]
0
LOS0
RO
RO
RO
RO
RO
Reading a [0] from the bit D[0] indicates an open inputs fault condition on
the IN0. A [1] indicates presence of a valid signal.
D[1]
D[2]
0
LOS1
Reading a [0] from the bit D[1] indicates an open inputs fault condition on
the IN1. A [1] indicates presence of a valid signal.
0
LOS2
Reading a [0] from the bit D[2] indicates an open inputs fault condition on
the IN2. A [1] indicates presence of a valid signal.
D[3]
0
LOS3
Reading a [0] from the bit D[3] indicates an open inputs fault condition on
the IN3. A [1] indicates presence of a valid signal.
D[7:4]
0000
Reserved
Reserved for future use. Returns undefined value when read.
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14
INPUT INTERFACING
ferential drivers (i.e. LVPECL, LVDS, CML). The following
three figures illustrate typical DC-coupled interface to com-
mon differential drivers. Note that the DS10CP154A inputs
are internally terminated with a 100Ω resistor.
The DS10CP154A accepts differential signals and allows
simple AC or DC coupling. With a wide common mode range,
the DS10CP154A can be DC-coupled with all common dif-
30073731
Typical LVDS Driver DC-Coupled Interface to DS10CP154A Input
30073732
Typical CML Driver DC-Coupled Interface to DS10CP154A Input
30073733
Typical LVPECL Driver DC-Coupled Interface to DS10CP154A Input
15
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OUTPUT INTERFACING
and assumes that the receivers have high impedance inputs.
While most differential receivers have a common mode input
range that can accomodate LVDS compliant signals, it is rec-
ommended to check respective receiver's data sheet prior to
implementing the suggested interface implementation.
The DS10CP154A outputs signals that are compliant to the
LVDS standard. Its outputs can be DC-coupled to most com-
mon differential receivers. The following figure illustrates typ-
ical DC-coupled interface to common differential receivers
Typical DS10CP154A Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver30073734
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16
Physical Dimensions inches (millimeters) unless otherwise noted
Order Number DS10CP154ATSQ
NS Package Number SQA40A
(See AN-1187 for PCB Design and Assembly Recommendations)
17
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