LM3661_05 [NSC]
450mA Subminiature, Micropower Step-Down DC-DC Converter for Ultra Low-Voltage Circuits; 450毫安微型，微功耗降压型DC -DC转换器，用于超低电压电路
| 型号： | LM3661_05 |
| 厂家： | 
National Semiconductor |
| 描述： | 450mA Subminiature, Micropower Step-Down DC-DC Converter for Ultra Low-Voltage Circuits |
| 文件： | 总17页 (文件大小：842K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 2005
LM3661
450mA Subminiature, Micropower Step-Down DC-DC
Converter for Ultra Low-Voltage Circuits
n
3% output voltage precision in PWM mode
General Description
n Miniature 10-pin micro SMD package
n Only three tiny surface-mount external components
required
n Uses small ceramic capacitors
n 8 mV typ. PWM output voltage ripple
The LM3661 step-down DC-DC converter is optimized for
powering ultra-low voltage circuits from a single Lithium-Ion
cell. The device provides two pin-selectable output voltages.
See ordering information for a list of voltage options avail-
able . This allows adjustment for DSP or CPU voltage op-
tions, as well as dynamic output voltage switching for re-
n Internal synchronous rectification for high efficiency
(92% at 2.7 VIN, 1.35 VOUT
)
duced
power
consumption.
Internal
synchronous
rectification provides high efficiency (92% typ. at 1.35VOUT).
n 29 µA typ. quiescent current (Linear mode)
n 0.5 µA typ. shutdown current
n SYNC/MODE input for frequency synchronization from
500 kHz to 750 kHz
n Current and Thermal overload protection
n High gain control loop with internal compensation
n Up to 450mA IOUT capability for LM3661-1.35/1.4
n Up to TBDmA IOUT capability for LM3661-1.25
The LM3661 offers superior features and performance for
mobile phones and similar portable applications. Pin-
selectable PWM and Linear modes provide improved system
control for maximizing battery life. During full-load, fixed
frequency PWM operation reduces interference in RF and
data acquisition applications by minimizing noise harmonics
at sensitive IF and sampling frequencies. The SYNC/MODE
input allows synchronization of the switching frequency in a
range of below 500 kHz to 750 kHz to prevent noise from
intermodulation with system frequencies. Linear operation
reduces quiescent current to 29 µA (typ.) during system
standby for extended battery life, while supplying up to
15 mA. Shutdown turns the device off and reduces battery
consumption to 0.5 µA (typ.). This device offers a selectable
over Current Limit to protect a variety of inductors.
Applications
n Mobile phones
n Hand-Held radios
n Personal Digital Assistants
n Palm-top PC’s and Pocket PC’s
n Portable Instruments
n Battery Powered Device
The LM3661 is available in a 10 pin micro SMD package.
This packaging uses National’s chip-scale micro SMD tech-
nology and offers the smallest possible size. A high (600
kHz) switching frequency allows use of tiny surface-mount
components; only three are required—an inductor and two
ceramic capacitors.
Features
n Operates from a single Li-ION cell
n Pin selectable output voltages
n Pin selectable Inductor Current Limit
Typical Application Circuit
20098802
© 2005 National Semiconductor Corporation
DS200988
www.national.com
Block Diagram
20098801
FIGURE 1. Simplified Functional Diagram
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2
Connection Diagrams
10-Bump micro SMD Package
20098804
20098805
Top View
Bottom View
Ordering Information
Order Number
Output Voltage
Package
NSC Package Marking
Supplied As
LM3661TLX - 1.25 1.05V/1.25V
LM3661TL - 1.25
10Bump Wafer Level
SHVB
SHVB
SDYB
SDYB
SHCB
SHCB
3000 Units, Tape and Reel
250 Units, Tape and Reel
3000 Units, Tape and Reel
250 Units, Tape and Reel
3000 Units, Tape and Reel
250 Units, Tape and Reel
Chip Scale (micro SMD)
LM3661TLX - 1.35 1.05V/1.35V
LM3661TL - 1.35
LM3661TLX - 1.40 1.05V/1.40V
LM3661TL - 1.40
Pin Description
Pin Number
Name
Function
A1
FB
Feedback Analog Input. Connect to the output at the output filter capacitor (see
Typical Application Circuit)
B1
VSEL
Output Voltage Selection Input. Set this digital input to select the desired output
voltage. Set:
•VSEL = high programmed ouput voltage
•VSEL = low for low programmed output voltage
>
C1
D1
ISEL
ISEL = High ( 1.2V) for set current limit to low value
ISEL = Low (GND) for set current limit to high value
SYNC/MODE
Synchronization Input. Use this digital input for frequency selection or modulation
control. Set:
•SYNC/MODE = high for low-noise 600 kHz PWM mode
•SYNC/MODE = low for micropower linear mode
•SYNC/MODE = a 500 kHz -750 kHz external oscillator for synchronization to an
external clock in PWM mode.
The LM3661 synchronizes with the rising edge of the external clock.
D2
EN
Enable Input. It has an internal pull down resistor of 1 Mohms. Set this digital input
high for normal operation. For shutdown, set low.
D3
C3
PGND
SW
Power Ground
Switching Node connection to the internal PFET switch and NFET synchronous
rectifier. Connect to an inductor with a saturation current rating that exceeds the peak
current limit.
B3
PVIN
Power Supply Input to the internal PFET switch. Connect to the input filter capacitor
(See Typical Application Circuit).
3
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Pin Description (Continued)
Pin Number
Name
VDD
SGND
Function
A3
A2
Analog Supply Input.
Analog and Control Ground.
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4
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature Range
Lead Temperature
−45˚C to 150˚C
260˚C
(Soldering, 10 sec.)
Operating Ratings
Supply Voltage
Input Voltage Range
2.7V to 5.5V
-30˚C to 85˚C
PVIN, VDD to SGND
PGND to SGND
EN, SYNC/MODE, VSEL to
SGND
−0.2V to +6V
Operating Temperature
Junction Temperature (Note 3)
Minimum ESD Rating
(Human Body Model, C = 100 pF,
R = 1.5 kΩ)
−0.2V to +0.2V
−30˚C to +125˚C
−0.2V to +6V
−0.2V to (VDD
+0.2V)
FB, ISEL, SW
2 kV
Thermal properties
Thermal Resistance (θJA
)
170˚C/W
Electrical Characteristics (Note 2)
Specifications with standard typeface are for TJ = 25˚C, and those in bold face type apply over the full Operating Temperature
Range (TA = TJ = −30˚C to +85˚C). Unless otherwise specified, PVIN = VDD = EN = SYNC/MODE = VSEL = 3.6V, ISEL= 0V,
COUT = 22 µF.
Symbol
Parameter
Feedback Voltage, PWM Mode
VIN = 2.7V to 5.5V
Remarks
Min
Typ
1.05
1.25
1.05
1.35
1.05
1.40
1.05
1.25
1.05
1.35
1.05
1.4
Max
1.082
1.288
1.082
1.391
1.082
1.442
1.103
1.313
1.103
1.418
1.103
1.47
Units
V
VFB, PWM
LM3661TL-1.25, VSEL = 0
LM3661TL-1.25, VSEL= VIN
LM3661TL-1.35, VSEL = 0
LM3661TL-1.35, VSEL = VIN
LM3661TL-1.40, VSEL = 0
LM3661TL-1.40, VSEL = VIN
1.019
1.213
1.019
1.310
1.019
1.358
0.998
1.188
0.998
1.283
0.998
1.33
V
V
V
V
V
VFB, LINEAR Feedback Voltage, Linear Mode LM3661TL-1.25, VSEL = 0
V
VIN= 2.7V to 5.5V, IOUT = 1mA
LM3661TL-1.25, VSEL= VIN
LM3661TL-1.35, VSEL = 0
LM3661TL-1.35, VSEL = VIN
LM3661TL-1.4, VSEL= 0
LM3661TL-1.4, VSEL= VIN
SYNC/MODE = VIN
V
V
V
V
V
VOVP
OVP Comparator Hysteresis
Voltage (Note 5)
64
70
90
90
mV
mV
VIN = 2.7V to 5.5V
OVP Trip point
SYNC/MODE = VIN
50
VIN = 3.6V
ISHDN
Shutdown Supply Current
DC Bias Current into VDD
(VOUT set to 1.35V)
EN = 0V
0.5
5
µA
µA
IQ,PWM
PWM mode, no switching
(SYNC/MODE = VDD, VFB=2V)
No-Load, Linear mode
(SYNC/MODE = 0V)
425
IQ,LIN
DC Bias Current into VDD
29
40
µA
RDSON(P)
RDSON(N)
Ilim_-1.25
Pin-pin Resistance for PFET
Pin-pin Resistance for NFET
Switch Peak Current Limit
250
180
mΩ
mΩ
PWM mode
TBD
TBD
454
TBD
TBD
mA
mA
ISEL=VIN, VIN = 2.7V to 4.5V
PWM mode
TBD
ISEL = 0, VIN = 2.7V to 4.5V
PWM mode
Ilim_-1.35/-1.4
Switch Peak Current Limit
Max Current in Linear Mode
473
565
518
615
550
650
mA
mA
ISEL=VIN, VIN = 2.7V to 4.5V
PWM mode
ISEL = 0, VIN = 2.7V to 4.5V
SYNC/MODE = 0V, FB = 0V
VIN = 2.7V to 5.5V
Ilim_LIN
35
60
90
mA
5
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Electrical Characteristics (Note 2) (Continued)
Specifications with standard typeface are for TJ = 25˚C, and those in bold face type apply over the full Operating Temperature
Range (TA = TJ = −30˚C to +85˚C). Unless otherwise specified, PVIN = VDD = EN = SYNC/MODE = VSEL = 3.6V, ISEL= 0V,
COUT = 22 µF.
Symbol
VEN,H
VEN,L
Parameter
EN Logic High Input (Note 4)
EN Logic Low Input
Remarks
VIN = 2.7V to 5.5V
Min
Typ
Max
1.2
Units
V
V
0.4
VSYNC/MODE, SYNC/MODE Logic High Input
1.2
V
V
H
VSYNC/MODE, SYNC/MODE Logic Low Input
0.4
L
VSEL, H
VSEL, L
ISEL,H
ISEL, L
REN
VSEL Logic High Input
VSEL Logic Low Input
ISEL Logic High Input
1.2
1.2
V
V
V
0.4
0.4
ISEL Logic Low Input
Enable pin input resistance
SYNC/MODE Clock Frequency
Range (Note 6)
1
MΩ
fSYNC
VIN = 2.7V to 5.5V
500
535
750
675
kHz
fOSC
Internal Oscillator Frequency
PWM mode (SYNC/MODE = VIN
)
600
kHz
VIN = 2.7V to 5.5V
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of
the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the
Electrical Characteristics tables.
Note 2: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm. Due
to the pulsed nature of the testing T =T for the electrical characteristics table.
A
J
Note 3: Thermal shutdown will occur if the junction temperature exceeds 150˚C. This function is only active in PWM mode.
Note 4: The LM3202 is designed for mobile phone applications where turn-on after power-up is controlled by the system controller and where requirements for a
small package size overrule increased die size for internal Under Voltage Lock-Out (UVLO) circuitry. Thus, it should be kept in shutdown by holding the EN pin low
until the input voltage exceeds 2.7V.
Note 5: The hysteresis voltage is the minimum voltage swing on FB that causes the internal feedback and control circuitry to turn the internal PFET switch on and
then off, during test mode.
Note 6: SYNC/MODE driven with an external clock switching between V and GND. When an external clock is present at SYNC/MODE, the IC is forced to PWM
IN
mode at the external clock frequency.
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6
Typical Performance Characteristics (Circuit in Fig.2, PVIN = VDD = EN=3.6V, TA = 25˚C, unless
otherwise noted)
Quiescent Supply Current vs. Supply Voltage
(PWM MODE)
Quiescent Supply Current vs. Supply Voltage
(LDO MODE)
20098810
20098811
Output Voltage vs. Output Current
(PWM MODE, ISEL=L, VOUT = 1.05V)
Output Voltage vs. Output Current
(PWM MODE, ISEL=L, VOUT = 1.35V)
20098814
20098815
Output Voltage vs. Output Current
(LDO MODE, VOUT=1.05V)
Output Voltage vs. Output Current
(LDO MODE, VOUT=1.35V)
20098816
20098817
7
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Typical Performance Characteristics (Circuit in Fig.2, PVIN = VDD = EN=3.6V, TA = 25˚C, unless
otherwise noted) (Continued)
Output Voltage vs. Supply Voltage
(PWM MODE, ISEL = L, VOUT = 1.05V)
Output Voltage vs. Supply Voltage
(PWM MODE, ISEL = L, VOUT = 1.35V)
20098818
20098819
Output Voltage vs. Supply Voltage
(LDO MODE, VOUT = 1.05V)
Output Voltage vs. Supply Voltage
(LDO MODE, VOUT = 1.35V )
20098848
20098849
Switching Frequency vs. Temperature
Efficiency vs. Output Current
(PWM MODE, SYNC/MODE = VIN
)
(SYNC/MODE = VIN, VOUT = 1.05V)
20098822
20098821
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Typical Performance Characteristics (Circuit in Fig.2, PVIN = VDD = EN=3.6V, TA = 25˚C, unless
otherwise noted) (Continued)
Efficiency vs. Output Current
(PWM MODE, ISEL = L, VOUT = 1.35V)
PWM Load Transient Response
(ISEL=L, VIN = 3.6V, VOUT = 1.35V)
20098824
20098823
LDO Load Transient Response
(VIN = 3.6V & VOUT = 1.35V)
PWM Line Transient Response
20098838
20098839
PWM Start-up Respsonse
(VIN = 3.6V & VOUT = 1.05V)
PWM Start-up Respsonse
(VIN = 3.6V & VOUT = 1.35V)
20098825
20098826
9
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Typical Performance Characteristics (Circuit in Fig.2, PVIN = VDD = EN=3.6V, TA = 25˚C, unless
otherwise noted) (Continued)
LDO Start-up Respsonse
(VIN = 3.6V & VOUT = 1.05V)
LDO Start-up Respsonse
(VIN = 3.6V & VOUT = 1.35V)
20098842
20098843
VSEL Transition in PWM Mode
(LM3661-1.35)
VSEL Transition in LDO Mode
(LM3661-1.35)
20098847
20098827
TYP Waveform
VSEL & SYNC/MODE Transition in PWM Mode
(PWM Mode, IOUT = 100mA)
20098828
20098829
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Typical Performance Characteristics (Circuit in Fig.2, PVIN = VDD = EN=3.6V, TA = 25˚C, unless
otherwise noted) (Continued)
TYP Waveform
(PWM Mode, IOUT = 450mA)
External SYNC/MODE at 600kHz
( IOUT = 100mA)
20098830
20098831
External SYNC/MODE at 600kHz
( IOUT = 450mA )
20098832
11
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the inductor’ magnetic field collapse, generating a voltage
that forces current from ground through the synchronous
rectifier to the output filter capacitor and load. As the stored
energy is transferred back into the circuit and depleted, the
inductor current ramps down with a slope of VOUT/L. If the
inductor current reaches zero before the next cycle, the
synchronous rectifier is turned off to prevent current reversal.
The output filter capacitor stores charge when the inductor
current is high, and release it when low, smoothing the
voltage across the load.
Circuit Operation
The LM3661 operates as follows: During the first part of
each switching cycle, the control block in the LM3661 turns
on the internal PFET switch. This allows current to flow from
the input through the inductor to the output filter capacitor
and load. The inductor limits the current to a ramp with the
slope of (VIN − VOUT)/L, by storing energy in a magnetic field.
During the second part of each cycle, the controller turns the
PFET switch off, blocking current flow from the input, and
then turns the NFET synchronous rectifier on. In response,
20098803
FIGURE 2. Typical Operating Circuit
PWM Operation
LDO Operation
The LM3661 can be set to current-mode PWM operation by
connecting the SYNC/MODE pin to VDD. While in PWM
(Pulse Width Modulation) mode, the output voltage is regu-
lated by switching at a constant frequency and then modu-
lating the energy per cycle to control power to the load.
Energy per cycle is set by modulating the PFET switch
on-time pulse-width to control the peak inductor current. This
is done by controlling the PFET switch using a flip-flop driven
by an oscillator and a comparator that compares a ramp
from the current-sense amplifier with an error signal from a
voltage-feedback error amplifier. At the beginning of each
cycle, the oscillator sets the flip-flop and turns on the PFET
switch, causing the inductor current to ramp up. When the
current sense signal ramps past the error amplifier signal,
the PWM comparator resets the flip-flop and turns off the
PFET switch, ending the first part of the cycle. The NFET
synchronous rectifier turns on until the next clock pulse or
the inductor current ramps to zero. If an increase in load
pulls the output voltage down, the error amplifier output
increases, which allows the inductor current to ramp higher
before the comparator turns off the PFET switch. This in-
creases the average current sent to the output and adjusts
for the increase in the load. Before going to the PWM com-
parator, the current sense signal is summed with a slope
compensation ramp from the oscillator for stability of the
current feedback loop. During the second part of the cycle, a
zero crossing detector turns off the NFET synchronous rec-
tifier if the inductor current ramps to zero.
Connecting the SYNC/MODE pin to GND sets the LM3661
in Linear Mode operation. While in Linear mode (LDO) the
device consumes only 29 µA (typ.) quiescent current for
system standby operation. It is capable of delivering up to
15 mA. This is done by using an internal pass transistor and
an error amplifier to sense the output voltage and maintain
the desire output voltage. During LDO mode, the PFET and
NFET of the network switch off to reduce quiescent current.
Frequency Synchronization
The SYNC/MODE input can also be used for frequency
synchronization. To synchronize the LM3661 to an external
clock, supply a digital signal to the SYNC/MODE pin with a
voltage swing exceeding 0.4V to 1.2V. During synchroniza-
tion, the LM3661 initiates cycles on the rising edge of the
clock. When synchronized to an external clock, it operates in
PWM mode. The device can synchronize to an external
clock over frequencies from 500 kHz to 750 kHz. Use the
following waveform and duty-cycle guidelines when applying
an external clock to the SYNC/MODE pin. The duty cycle
can be between 30% and 70%. Clock under/overshoot
should be less than 100 mV below GND or above VDD
.
When applying noisy clock signals, especially sharp edged
signals from a long cable during evaluation, terminate the
cable at its characteristic impedance; add an RC filter to the
SYNC/MODE pin, if necessary, to soften the slew rate and
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12
parator. In PWM mode, cycle-by-cycle current limiting is
normally used. If an excessive load pulls the output voltage
down to approximately 0.45V, then the device switches to a
timed current limit mode. In timed current limit mode the
internal PFET switch is turned off after the current compara-
tor trips and the beginning of the next cycle is inhibited for
2.5 µs to force the instantaneous inductor current to ramp
down to a safe value. Timed current limit prevents the loss of
current control seen in some products when the output volt-
age is pulled low in serious overload conditions.
Frequency Synchronization
(Continued)
over/undershoot. Note that sharp edged signals from a pulse
or function generator can develop under/overshoot as high
as 10V at the end of an improperly terminated cable.
Over-voltage Protection
The LM3661 has an over-voltage comparator that prevents
the output voltage from rising too high when the device is left
in PWM mode under low-load conditions. Otherwise, the
output voltage could rise out of regulation from the minimum
energy transferred per cycle due to about 250 ns minimum
on-time of the PFET switch while in PWM mode. When the
output voltage rises by 70 mV over its regulation threshold,
the OVP comparator inhibits PWM operation to skip pulses
until the output voltage returns to the regulation threshold. In
over voltage protection, output voltage and ripple increase
slightly.
Application Information
PIN SELECTABLE OUTPUT
The LM3661 features pin-selectable output voltage to elimi-
nate the need for external feedback resistors. Select an
output voltage of 1.05V or 1.25V/1.35V/1.4V by setting the
VSEL pin low or high. VSEL may be set high by connecting to
VDD or low by connecting to GND. Alternatively, VSEL may be
driven off digitally by a logic gates that provide over 1.2V for
high state and less than 0.4V for a low state to ensure valid
logic levels. VSEL input has no internal pull down that pulls
the input low, this pin must be set to a known state.
Shutdown Mode
Setting the EN input low, to SGND, places the LM3661 in a
0.5 µA (typ) shutdown mode. During shutdown, the PFET
switch, NFET synchronous rectifier, reference, control and
bias of the LM3661 are turned off. Setting EN high to VDD
enables normal operation. While turning on, soft start is
activated. EN is a Schmidt trigger digital input with thresh-
olds that are independent of the input voltage at VDD. EN
must be set low to turn off the LM3661 during under voltage
conditions when the supply is less than the 2.7V minimum
operating voltage. The LM3661 is designed for mobile
phones and similar applications where power sequencing is
determined by the system controller and internal UVLO (Un-
der Voltage Lock Out) circuitry is unnecessary. The LM3661
has no UVLO circuitry. Although the LM3661 exhibits good
behavior while enabled at low input voltages, this is not
guaranteed.
Isel Pin
>
Connecting the ISEL pin high ( 1.2V or Vin ) sets the internal
<
current limit comparator to low value and low ( 0.4 or GND)
to high value. Note that ISEL pin has no internal pull down
and this pin must connect to a known state of normal opera-
tion.
Table 1 shows selected IOUT capability information.
Table 1. ISEL condition and IOUT capability
(Applies to both VSEL = H and VSEL = L)
VOUT option
1.05V/1.25V
1.05V/1.25V
1.05V/1.35V
1.05V/1.35V
1.05V/1.40V
1.05V/1.40V
ISEL
H
IOUT capability
300mA
L
TBDmA
350mA
Start-up
H
The LM3661 is designed to be started in LDO mode. Under
these conditions, the output voltage will increase at a rate
determined by the LDO current limit and the output capacitor
and load. This ramp time is typically about 600 µs. The
LM3661 may be started in PWM mode as well. Under these
conditions, the reference voltage for the error amplifier is
ramped up time is about 300µs and the output voltage will
follow. In this way, the input inrush current and output voltage
over shoot can be minimized.
L
450mA
H
350mA
L
450mA
Mode Transition
The LM3661 is designed to operate in two modes, LDO(Low
Dropout Regulator) mode for light load (15mA Max.) and
PWM Mode (Pulse Width Modulation) . As described in the
Device Operation Section, setting the SYNC/MODE pin low
yields LDO mode or high yields PWM mode. When mode
transitions from LDO to PWM and vice versa, harsh transient
conditions such as ramping the output load should be
avoided. To maintain a smooth transition, it is recommended
to keep the load to a minimum of 3mA or less for about 40us
before ramping into heavy load to avoid a large dip at the
output. Similarly, the same care must be applied when
changing output voltage from 1.05V to 1.25V/1.35V/1.40V
and vice versa (setting Vsel pin high or low) during full load.
Figure 3 below shows the mode transition from LDO to PWM
and PWM to LDO, and the load transient transition from light
load to heavy load is delayed by 40µs to allow the PWM loop
to respond properly.
Thermal Shutdown Protection
The LM3661 has thermal shutdown protection in PWM mode
to protect from short-term misuse and overload conditions.
When the junction temperature exceeds 150˚C, the device
shuts down and re-starts in soft start after the temperature
drops below 130˚C. Prolonged operation in thermal overload
conditions may damage the device and is considered bad
practice.
Current Limiting Protection
A current limit feature allows the LM3661 to protect itself and
external components during overload conditions. Current
limiting is implemented using an independent internal com-
13
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Application Information (Continued)
20098833
FIGURE 3.
INDUCTOR SELECTION
There are a few things that one must consider when select-
ing an inductor for an application. They are the inductor DC
current rating, inductor ripple current, DC-resistance of the
inductor and value of the inductor. The DC current rating of
the inductor denotes the maximum current before the induc-
tor core enters saturation. Before selecting the DC current
rating of the inductor, an inductor ripple current must be
determined using Equation (1). The DC current of the induc-
tor should be the maximum output current of the circuit plus
half of the peak to peak current ripple of the inductor using
Equation (2).
(3)
Where f is the operating frequency, ∆IL is the inductor current
ripple and Vo is the desired output.
Finally, the DC resistance (DCR) of the inductor also affect
the overall efficiency of the solution. Lower DCR is recom-
mended for better efficiency in handheld and battery oper-
ated applications. Consult inductor manufacture for this
specification. Table 2 lists suggested inductors and suppli-
ers.
Table2. Suggested Inductor and Suppliers
(1)
(2)
Part Number
D01608C-103
P1174.103T
P0770.103T
Ell6GM100M
Vendor
Coilcraft
Pulse
Web
www.coilcraft.com
www.pulseeng.com
Panasonic
www.panasonic.com
A good estimate for the inductor ripple current would be
using a operation condition or assume the inductor ripple
current to be about 30% of the maximum output current of
the device. Consider the following example for LM3661
(when ISEL = L); a 10 µH, 450 mA load current with 1.4V
output operates at 4.5V input and 600kHz in an application,
solving for ∆IL using Equation (2) yields ∆IL = 160 mA.
Therefore the maximum peak current (Equation (1)) in the
application will be 530 mA (IO + 1/2∆IL). Thus, an inductor
with DC current rating of 600 mA or higher should suffice for
the application when ISEL = L. For a more conservative
approach, it is best to select an inductor with a current rating
of the maximum switch peak current of the device. Note that
If smaller inductor is used in the application, the larger the
inductor ripple current (Equation (1)). Care must be taken to
select the inductor such that the peak current rating of the
inductor accounts for minimum inductance and maximum
current for the operating condition. Equation (3) can be used
to calculate the inductor value if the application conditions
are known:
INPUT AND OUTPUT CAPACITOR
The LM3661 is designed for ceramic capacitor for its input
and output filters. Ceramic capacitors such as X5R and X7R
are recommended to use for input and output filters. These
provide an optimal balance between small size, cost, reliabil-
ity and performance. Do not use Y5V ceramic capacitors as
they have poor dielectrics performance over temperature
and voltage characteristics for a given value. Table 2 lists
suggested capacitors and suppliers.
A 10 µF input and 22 µF output ceramic capacitors are
suggested in figure 2 (Typical application circuit) for optimal
performance.
The input filter capacitor supplies current to the PFET switch
of the LM3661 in the first part of each cycle and reduces
voltage ripple imposed on the input power source. The out-
put filter capacitor smooths out current flow from the inductor
and reduce output voltage ripple. These capacitors must be
selected with sufficient capacitance and sufficiently low ESR
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14
BOARD LAYOUT CONSIDERATION
Application Information (Continued)
PC board layout is an important part of DC-DC converter
design. Poor board layout can disrupt the performance of a
DC-DC converter and surrounding circuitry by contributing
EMI, ground bounce, and resistive voltage loss in the traces.
Below are layout recommendation to maximize device per-
formance: 1) Place the inductor and filter capacitors close
together and minimize the traces between components as
they carry relatively high switching current and act as anten-
nas. 2) Use wide traces between the power components and
for power connections to DC-DC converters circuit. 3) Route
noise sensitive traces such as the voltage feedback path
away from noisy power components. 4) Connect the ground
pins and filter capacitors together via a ground plane to
prevent switching current circulating through the ground
plane. Additional information regarding Micro SMD package
layout can be found in Application note AN-1112.
to perform these functions. The ESR, or equivalent series
resistance, of the filter capacitors is a major factor in voltage
ripple. Table 3 lists suggested capacitors suppliers.
Table 3. Suggested capacitors and Suppliers
Model
Size (EIA)
Vendor
Input Filter Capacitor (10µF, 6.3V, X5R or X7R9
C2012X5R0J106M
JMK212BJ106MG
GRM21BR60J106K
2012 (0805)
2012 (0805)
2012 (0805)
TDK
Taiyo-Yuden
muRata
Output Filter Capacitor (22µF, 6.3V, X5R or X7R9
C3225X5R0J226M
JMK325BJ226MG
GRM32DR60J226K
3225(1210)
3225(1210)
3225(1210)
TDK
Taiyo-Yuden
muRata
15
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Physical Dimensions inches (millimeters) unless otherwise noted
NOTES: UNLESS OTHERWISE SPECIFIED
1. EPOXY COATING
2. 63Sn/37Pb EUTECTIC BUMP
3. RECOMMEND NON-SOLDER MASK DEFINED LANDING PAD.
4. PIN A1 IS ESTABLISHED BY LOWER LEFT CORNER WITH RESPECT TO TEXT ORIENTATION. REMAINING PINS ARE NUMBERED COUNTER
CLOCKWISE.
5. XXX IN DRAWING NUMBER REPRESENTS PACKAGE SIZE VARIATION WHERE X1 IS PACKAGE WIDTH, X2 IS PACKAGE LENGTH AND X3 IS
PACKAGE HEIGHT.
10-Bump micro SMD Package
NS Package Number TLP10QTA
The dimensions for X1, X2 and X3 are as given:
X1 = 1.869 0.030 mm
X2 = 2.428 0.030 mm
X3 = 0.600 0.075 mm
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16
Notes
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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