LM4548AVHX [NSC]
IC,SOUNDCARD CIRCUITS,CMOS,QFP,48PIN,PLASTIC;
| 型号： | LM4548AVHX |
| 厂家： | 
National Semiconductor |
| 描述： | IC,SOUNDCARD CIRCUITS,CMOS,QFP,48PIN,PLASTIC 商用集成电路 |
| 文件： | 总19页 (文件大小：337K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 2002
LM4548A
AC ’97 Rev 2 Codec with Sample Rate Conversion and
National 3D Sound
General Description
Key Specifications
n Analog Mixer Dynamic Range
n D/A Dynamic Range
97dB (typ)
89dB (typ)
90dB (typ)
The LM4548A is an audio codec for PC systems which is
fully PC98 compliant and performs the analog intensive
functions of the AC97 Rev2 architecture. Using 18-bit
Sigma-Delta A/D’s and D/A’s, the LM4548A provides 90dB of
Dynamic Range.
n A/D Dynamic Range
Features
The LM4548A was designed specifically to provide a high
quality audio path and provide all analog functionality in a PC
audio system. It features full duplex stereo A/D’s and D/A’s
and an analog mixer with 4 stereo and 3 mono inputs, each
of which has separate gain, attenuation and mute control.
The LM4548A also provides the additional True Line-Level
output and National’s 3D Sound stereo enhancement.
n AC’97 Rev2 compliant
n National’s 3D Sound circuitry
n High quality Sample Rate Conversion (SRC) from 4kHz
to 48kHz in 1Hz increments.
n Multiple Codec Support
n True Line Level Output with volume control in addition to
standard Line Out
n Advanced power management support
n Digital 3V and 5V compliant
The LM4548A supports variable sample rate conversion as
defined in the AC97 Rev2 specification. The sample rate for
the A/D and D/A can be programmed separately to convert
any rate between 4kHz - 48kHz with a resolution of 1Hz. The
AC97 architecture separates the analog and digital functions
of the PC audio system allowing both for system design
flexibility and increased performance.
Applications
n Desktop PC Audio Systems
n Portable PC Systems
n Mobile PC Systems
Block Diagram
20030001
FIGURE 1. LM4548A Block Diagram
© 2002 National Semiconductor Corporation
DS200300
www.national.com
Absolute Maximum Ratings (Note 3)
Vapor Phase (60 sec.)
215˚C
220˚C
Infrared (15 sec.)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
See AN-450 "Surface Mounting and their Effects on
Product Reliability" for other methods of
soldering surface mount devices.
θJA (typ)—VBH48A
Supply Voltage
6.0V
−40˚C to +150˚C
−0.3V to VDD +0.3V
2500V
Storage Temperature
Input Voltage
74˚C/W
ESD Susceptibility (Note 5)
pins 27, 28
Operating Ratings
Temperature Range
1500V
pin 3
750V
TMIN ≤ TA ≤ TMAX
Analog Supply Range
Digital Supply Range
−40˚C ≤ TA ≤ 85˚C
4.2V ≤ AVDD ≤ 5.5V
3.0V ≤ DVDD ≤ 5.5V
ESD Susceptibility (Note 6)
pin 3
200V
100V
Junction Temperature
Soldering Information
LQFP Package
150˚C
Electrical Characteristics (Notes 1, 3)
The following specifications apply for AVDD = 5V, DVDD = 5V, Fs = 48kHz, single codec configuration, unless otherwise noted.
Limits apply for TA= 25˚C. The reference for 0dB is 1Vrms unless otherwise specified.
Units
(Limits)
LM4548A
Symbol
Parameter
Conditions
Typical
Limit
(Note 7) (Note 8)
AVDD
DVDD
Analog Supply Range
4.2
5.5
3.0
5.5
V (min)
V (max)
V (min)
V (max)
Digital Supply Range
Digital Quiescent Power Supply
Current
DIDD
DVDD = 5V
43
20
53
mA
mA
mA
DVDD = 3.3V
Analog Quiescent Power Supply
Current
AIDD
IDSD
Digital Shutdown Current
Analog Shutdown Current
Reference Voltage
500
30
µA
µA
V
IASD
VREF
PSRR
2.23
40
Power Supply Rejection Ratio
dB
Analog Loopthru Mode
CD Input to Line Output, -60dB Input
THD+N, A-Weighted
Dynamic Range (Note 2)
97
90
dB (min)
% (max)
THD
Total Harmonic Distortion
VO = -3dB, f = 1kHz, RL = 10kΩ
0.01
0.02
Analog Input Section
VIN
Line Input Voltage
1
0.1
1
Vrms
Vrms
Vrms
dB
Mic Input with 20dB Gain
Mic Input with 0dB Gain
Crosstalk
Xtalk
ZIN
CD Left to Right
-95
40
Input Impedance(Note 2)
Input Capacitance
10
kΩ (min)
pF
CIN
15
Interchannel Gain Mismatch
CD Left to Right
0dB to 22.5dB
0.01
dB
Record Gain Amplifier - A/D
AS
Step Size
1.5
1.5
dB
dB
Mixer Section
AS
Step Size
+12dB to -34.5dB
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2
Electrical Characteristics (Notes 1, 3) (Continued)
The following specifications apply for AVDD = 5V, DVDD = 5V, Fs = 48kHz, single codec configuration, unless otherwise noted.
Limits apply for TA= 25˚C. The reference for 0dB is 1Vrms unless otherwise specified.
Units
(Limits)
LM4548A
Symbol
Parameter
Conditions
Typical
Limit
(Note 7) (Note 8)
86
AM
Mute Attenuation
dB
Analog to Digital Converters
Resolution
18
Bits
dB (min)
kHz
Dynamic Range (Note 2)
Frequency Response
Digital to Analog Converters
-60dB Input THD+N, A-Weighted
-1dB Bandwidth
90
20
86
Resolution
18
89
Bits
dB (min)
%
Dynamic Range (Note 2)
Total Harmonic Distortion
Frequency Response
Group Delay (Note 2)
Out of Band Energy
Stop Band Rejection
Discrete Tones
-60dB Input THD+N, A-Weighted
85
2
THD
VIN = -3dB, f=1kHz, RL = 10kΩ
0.01
20 - 21k
Hz
mS (max)
dB
-40
70
dB
DT
-96
dB
True Line Level Output Volume Section
AS
Step Size
0dB to -46.5dB
1.5
86
dB
dB
AM
Mute Attenuation
Digital I/O (Note 2)
0.30 x
DVDD
0.40 x
DVDD
0.50 x
DVDD
0.20 x
DVDD
10
VIL
Low level input voltage
V (max)
V (min)
V (min)
V (max)
VHI
VOH
VOL
High level input voltage
High level output voltage
Low level output voltage
IL
Input Leakage Current
Tri state Leakage Current
Output drive current
AC Link inputs
µA
µA
IL
High impedance AC Link outputs
AC Link outputs
10
IDR
5
mA
Digital Timing Specifications (Note 2)
FBC
BIT_CLK frequency
BIT_CLK period
12.288
81.4
MHz
nS
TBCP
Variation of BIT_CLK period from 50%
duty cycle
TCH
BIT_CLK high
20
% (max)
FSYNC
TSP
SYNC frequency
48
kHz
µS
SYNC period
20.8
1.3
TSH
SYNC high pulse width
SYNC low pulse width
µS
TSL
19.5
µS
SDATA_IN, SDATA_OUT to falling edge
of BIT_CLK
TSETUP
THOLD
TRISE
Setup Time
Hold Time
Rise Time
Fall Time
15
5
nS (min)
nS (min)
nS (max)
nS (max)
Hold time of SDATA_IN, SDATA_OUT
from falling edge of BIT_CLK
BIT_CLK, SYNC, SDATA_IN or
SDATA_OUT
6
BIT_CLK, SYNC, SDATA_IN or
SDATA_OUT
TFALL
6
3
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Electrical Characteristics (Notes 1, 3) (Continued)
The following specifications apply for AVDD = 5V, DVDD = 5V, Fs = 48kHz, single codec configuration, unless otherwise noted.
Limits apply for TA= 25˚C. The reference for 0dB is 1Vrms unless otherwise specified.
Units
(Limits)
LM4548A
Symbol
Parameter
Conditions
Typical
Limit
(Note 7) (Note 8)
TRST_LOW
TRST2CLK
TSH
RESET# active low pulse width
For cold reset
1.0
µS (min)
nS (min)
µS
RESET# inactive to BIT_CLK start up For cold reset
162.8
SYNC active high pulse width
SYNC inactive to BIT_CLK start up
Setup to trailing edge of RESET#
Rising edge of RESET# to Hi-Z
For warm reset
1.3
TSYNC2CLK
TSU2RST
TRST2HZ
For warm reset
162.8
15
nS (min)
nS (min)
nS (max)
For ATE Test Mode
For ATE Test Mode
25
Note 1: All voltages are measured with respect to the ground pin, unless otherwise specified.
Note 2: These specifications are guaranteed by design and characterization; they are not production tested.
Note 3: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which
guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit
is given, however, the typical value is a good indication of device performance.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
, θ , and the ambient temperature T . The maximum
A
JMAX JA
allowable power dissipation is P
= (T
–T )/θ or the number given in Absolute Maximum Ratings, whichever is lower. For the LM4548A, T
= 150˚C.
DMAX
JMAX
A
JA
JMAX
The typical junction-to-ambient thermal resistance is 74˚C/W for package number VBH48A.
Note 5: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 6: Machine Model, 220 pF–240 pF discharged through all pins.
Note 7: Typicals are measured at 25˚C and represent the parametric norm.
Note 8: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
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4
Timing Diagrams
Clocks
20030010
Data Setup and Hold
20030011
Digital Rise and Fall
20030012
Cold Reset
20030013
Warm Reset
20030014
5
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Typical Application
20030003
FIGURE 2. LM4548A Typical Application Circuit
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6
Connection Diagram
20030002
Top View
Order Number LM4548AVH
See NS Package Number VBH48A
Pin Descriptions
Analog I/O
Name
Pin
I / O
Functional Description
This is a mono input which gets summed into both the stereo line out and the true line level
out after the National 3D Sound block. The PC_BEEP level can be adjusted from 0dB to
−45dB in 3dB steps, or muted, via register 0Ah.
PC_BEEP
12
I
This is a mono input which gets summed into both the stereo line out and the true line level
out after the National 3D Sound block. The PHONE level can be adjusted from +12dB to
−34.5dB in 1.5dB steps as well as muted via register 0Ch.
PHONE
AUX_L
13
14
I
I
This line level input can be routed through the Input Mux and recorded by the left ADC. In
addition, this analog input gets summed into the left output stream. The amount of AUX_L
signal mixed in the left output stream can be adjusted from +12dB to −34.5dB in 1.5dB steps
as well as muted via register 16h.
7
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Pin Descriptions (Continued)
Analog I/O (Continued)
Name
Pin
I / O
Functional Description
This line level input can be routed through the Input Mux and recorded by the right ADC. In
addition, this analog input gets summed into the right output stream. The amount of AUX_R
signal mixed in the right output stream can be adjusted from +12dB to −34.5dB in 1.5dB
steps as well as muted via register 16h.
AUX_R
15
I
This line level input can be routed through the Input Mux and recorded by the left ADC. In
addition, this analog input gets summed into the left output stream. The amount of VIDEO_L
signal mixed in the left output stream can be adjusted from +12dB to −34.5dB in 1.5dB steps
as well as muted via register 14h.
VIDEO_L
VIDEO_R
16
17
I
I
This line level input can be routed through the Input Mux and recorded by the right ADC. In
addition, this analog input gets summed into the right output stream. The amount of VIDEO_R
signal mixed in the right output stream can be adjusted from +12dB to −34.5dB in 1.5dB
steps as well as muted via register 14h.
This line level input can be routed through the Input Mux and recorded by the left ADC. In
addition, this analog input gets summed into the left output stream. The amount of CD_L
signal mixed in the left output stream can be adjusted from +12dB to −34.5dB in 1.5dB steps
as well as muted via register 12h.
CD_L
CD_GND
CD_R
18
19
20
I
I
I
This input can be used to reject common mode signals on the CD_L and CD_R inputs.
CD_GND is an AC ground point and not a DC ground point. This input must be AC-coupled
to the source signal’s ground.
This line level input can be routed through the Input Mux and recorded by the right ADC. In
addition, this analog input gets summed into the right output stream. The amount of CD_R
signal mixed in the right output stream can be adjusted from +12dB to −34.5dB in 1.5dB
steps as well as muted via register 12h.
Either MIC1 or MIC2 can be selected via software and routed through the Input Mux for
recording. The 20dB boost circuit is enabled/disabled via register 0Eh. Also, the amount of
mic signal mixed in the output stream can be adjusted from +12dB to −34.5dB in 1.5dB steps
as well as muted via register 0Eh.
MIC1
MIC2
21
22
23
24
I
I
I
I
Either MIC1 or MIC2 can be selected via software and routed through the Input Mux for
recording. The 20dB boost circuit is enabled/disabled via register 0Eh. Also, the amount of
mic signal mixed in the output stream can be adjusted from +12dB to −34.5dB in 1.5dB steps
as well as muted via register 0Eh.
This line level input can be routed through the Input Mux and recorded by the left ADC. In
addition, this analog input gets summed into the left output stream. The amount of LINE_IN_L
signal mixed in the left output stream can be adjusted from +12dB to −34.5dB in 1.5dB steps
as well as muted via register 10h.
LINE_IN_L
LINE_IN_R
This line level input can be routed through the Input Mux and recorded by the right ADC. In
addition, this analog input gets summed into the right output stream. The amount of
LINE_IN_R signal mixed in the right output stream can be adjusted from +12dB to −34.5dB in
1.5dB steps as well as muted via register 10h.
This is a post-mixed output for the left audio channel. The level of this output can be adjusted
from 0dB to −45dB in 1.5dB steps as well as muted via register 02h.
LINE_OUT_L
LINE_OUT_R
MONO_OUT
35
36
37
39
41
O
O
O
O
O
This is a post-mixed output for the right audio channel. The level of this output can be
adjusted from 0dB to −45dB in 1.5dB steps as well as muted via register 02h.
This line level output is either the post-mixed output or the mic input. The level of this output
can be adjusted from 0dB to −45dB in 1.5dB steps as well as muted via register 06h.
This is a post-mixed output for the left audio channel. The level of this output can be adjusted
from 0dB to −45dB in 1.5dB steps as well as muted via register 04h.
LNLVL_OUT_L
LNLVL_OUT_R
This is a post-mixed output for the right audio channel. The level of this output can be
adjusted from 0dB to −45dB in 1.5dB steps as well as muted via register 04h.
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Pin Descriptions (Continued)
Digital I/O and Clocking
Name
Pin
I / O
Functional Description
24.576 MHz crystal input. Use a fundamental-mode type crystal. When operating from a
crystal, a 1MΩ resistor must be connected across pins 2 and 3.
XTL_IN
2
I
24.576 MHz crystal output. When operating from a crystal, a 1MΩ resistor must be connected
across pins 2 and 3.
XTL_OUT
3
5
O
I
This data stream contains both control data and DAC audio data. This input is sampled by the
LM4548A on the falling edge of BIT_CLK.
SDATA_OUT
OUTPUT when in Primary Codec Mode: This pin outputs a 12.288 MHz clock which is
derived (internally divided by two) from the 24.576MHz crystal input (XTL_IN).
INPUT when in Secondary Codec Mode (Multiple Codec configurations only): 12.288MHz
clock is to be supplied from an external source, such as from the BIT_CLK of a Primary
Codec.
BIT_CLK
6
I/O
This data stream contains both control data and ADC audio data. This output is clocked out
by the LM4548A on the rising edge of BIT_CLK.
SDATA_IN
SYNC
8
O
I
48kHz sync pulse which signifies the beginning of both the SDATA_IN and SDATA_OUT
serial streams. SYNC must be synchronous to BIT_CLK.
10
11
This active low signal causes a hardware reset which returns the control registers to their
default conditions.
RESET#
I
ID0 and ID1 set the codec address for multiple codec use where ID0 is the LSB. Connect
these pins to DVdd or GND as required. If these pins are not connected (NC), they default to
Master Codec setting (same as connecting both pins to GND). These pins are of the same
polarity as their internal ID0, ID1 registers. If pin 45 is connected to GND, then ID0 will be set
to "0" internally. Connection to DVdd corresponds to a "1" internally.
ID0 and ID1 set the codec address for multiple codec use where ID1 is the MSB. Connect
these pins to DVdd or GND as required. If these pins are not connected (NC), they default to
Master Codec setting (same as connecting both pins to GND). These pins are of the same
polarity as their internal ID0, ID1 registers. If pin46 is connected to GND, then ID1 will be set
to "0" internally. Connection to DVdd corresponds to a "1" internally.
ID0
ID1
45
46
I
I
Power Supplies and References
Name
AVDD
AVSS
DVDD
DVSS
Pin
I / O
Functional Description
25
I
I
I
I
Analog supply.
Analog ground.
Digital supply.
Digital ground.
26
1,9
4,7
Nominal 2.2V reference output. Not intended to sink or source current. Bypassing of this pin
should be done with short traces to maximize performance.
VREF
VREFOUT
AFILT1
27
28
29
30
O
O
O
O
Nominal 2.2V reference output. Can source up to 5mA of current and can be used to bias a
microphone.
This pin is not used and should be left open (NC). However, a capacitor to ground on this pin
is permitted - it will not affect performance.
This pin is not used and should be left open (NC). However, a capacitor to ground on this pin
is permitted - it will not affect performance.
AFILT2
These pins are used to complete the National 3D Sound circuit. Connect a 0.022µF capacitor
between pins 3DP and 3DN. The National 3D Sound can be turned on and off via bit D13 in
control register 20h. This is a fixed-depth type stereo enhance circuit, thus writing to register
22h has no effect. If National 3D Sound is not needed, then these pins should be left as no
connect (NC).
3DP, 3DN
33,34
O
9
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Typical Performance
Characteristics
ADC Noise Floor
DAC Noise Floor
20030015
20030016
Analog Loopthru
Noise Floor
ADC Frequency
Response
20030018
20030019
DAC Frequency
Response
True Line Level Out
Noise Floor (Analog Loopthrough)
20030018
20030020
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11
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12
Application Information
AC Link Serial Interface Protocol
20030004
FIGURE 3. AC 97 Bidirectional Audio Frame
20030006
FIGURE 4. AC Link Audio Output Frame
AC Link Output Frame: SDATA_OUT (output from
controller, input to LM4548A)
_CLK. The AC ’97 Controller will continue outputting the
SDATA_OUT stream on each successive rising edge of
BIT_CLK.
The audio output frame (output from AC ’97 Controller)
contains control and PCM data targeted for the LM4548A
control registers and stereo DAC. The Tag slot, slot 0, con-
tains 16 bits that tell the AC Link interface circuitry on the
LM4548A the validity of the following data slots.
SDATA_OUT Slot 0: Tag Phase
The first bit of slot 0 is designated the "Valid Frame" bit. If this
bit is 1, it indicates that the current data frame contains at
least one slot of valid data and the LM4548A will further
sample the next four bits to determine which frames do in
fact have valid data. Valid slots are signified by a 1 in their
respective slot bit position.
A new audio output frame is signaled with a low to high
transition of SYNC. SYNC is synchronous to the rising edge
of BIT_CLK. On the next rising edge of BIT_CLK, the AC ’97
Controller drives SDATA_OUT with the first bit of slot 0. The
LM4548A samples SDATA_OUT on the falling edge of BIT-
13
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Application Information (Continued)
20030005
FIGURE 5. Start of Audio Output Frame
zeros.
Bits
Bit
Description
Comment
1 = This frame has valid
data.
Description
Control
Comment
15
Valid Frame
Set bits to "0" if read
operation
19:4
3:0
Register Write
Data
Control register
address
1 = Control Address is
valid.
14
13
12
11
Reserved
Set to "0"
Control register
data
1 = Control Data is valid.
1 = Left PCM Data is valid.
Left Playback
PCM Data
SDATA_OUT Slot 3: PCM Playback Left Channel
Slot 3 is a 20 bit field used to transmit data intended for the
left DAC on the LM4548A. Any unused bits should be pad-
ded with zeros. The LM4548A DAC’s have 18 bit resolution
and thus will use the first 18 bits of the 20 bit PCM stream.
Right Playback
PCM Data
1 = Right PCM Data is
valid.
Bits
Description
PCM Audio
Data for Left
DAC
Comment
SDATA_OUT Slot 1: Control Address
Slot 1 is used both to write to the LM4548A registers as well
as read back a register’s current value. The MSB of Slot 1
(bit 19) signifies whether the current control operation is a
read or a write. Bits 18 through 12 are used to specify the
register address of the read or write operation. The least
significant twelve bits are reserved and should be stuffed
with zeros by the AC’97 controller.
19:0
Set unused bits to "0"
SDATA_OUT Slot 4: PCM Playback Right Channel
Slot 4 is a 20 bit field used to transmit data intended for the
right DAC on the LM4548A. Any unused bits should be
padded with zeros. The LM4548A DAC’s have 18 bit reso-
lution and thus will use the first 18 bits of the 20 bit PCM
stream.
Bits
Description
Read/Write
Control
Comment
1 = Read, 0 = Write
Identifies the Control
Register
19
18:12
11:0
Register
Bits
Description
PCM Audio
Data for Right
DAC
Comment
Reserved
Set to "0"
19:0
Set unused bits to "0"
SDATA_OUT Slot 2: Control Data
Slot 2 is used to transmit 16 bit control data to the LM4548A
in the event that the current operation is a write operation.
The least significant four bits should be stuffed with zeros by
the AC ’97 controller. If the current operation is a register
read, the entire slot, bits 19 through 0 should be stuffed with
SDATA_OUT Slots 5-12: Reserved
Set these SDATA_OUT slots to "0" as they are not currently
implemented and are reserved for future use.
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14
Application Information (Continued)
20030008
FIGURE 6. AC Link Audio Input Frame
AC Link Input Frame: SDATA_IN (input to controller,
output from LM4548A)
Bit
Description
Slot 2 data
valid
Comment
The audio input frame (input to the AC ’97 Digital Controller)
contains status and PCM data from the LM4548A control
registers and stereo ADC. The Tag slot, slot 0, contains 16
bits that tell the AC ’97 Digital Controller whether the
LM4548A is ready and the validity of data from certain device
subsections.
13
Status Data is valid
Slot 3 data
valid
Left Audio PCM Data is
12
11
valid
Right Audio PCM Data is
valid
Slot 4 data
valid
A new audio input frame is signaled with a low to high
transition of SYNC. SYNC is synchronous to the rising edge
of BIT_CLK. On the next rising edge of BIT_CLK, the
LM4548A drives SDATA_IN with the first bit of slot 0. The
Digital Controller samples SDATA_IN on the falling edge of
BIT_CLK. The LM4548A will continue outputting the
SDATA_IN stream on each successive rising edge of BIT-
_CLK. The LM4548A outputs data MSB first, in a MSB
justified format. All reserved bits and slots are stuffed with "0"
’s by the LM4548A.
SDATA_IN Slot 1: Status Address / Slot Request Bits
This slot echoes the control register which a read was re-
quested on. The address echoed was initiated by a read
request in the previous SDATA_OUT frame, slot 1. Bits 11
and 10 are slot request bits that support Sample Rate Con-
version (SRC) functionality. If bit 11 is set to 0, then the
controller should respond with a valid PCM left sample in slot
3 of the next frame. If bit 10 is set to 0, then the controller
should respond with a valid PCM right sample in slot 4 of the
next frame. If bits 11 or 10 are set to 1, the controller should
not send data in the next frame. Bits 9 through 2 are unused.
Bits 1 and 0 are reserved and should be set to 0.
SDATA_IN Slot 0: Codec Status Bits
The first bit of SDATA_IN Slot 0 (bit 15) indicates when the
Codec is ready. The digital controller must probe further to
see which other subsections are ready.
Bits
Description
Comment
19
Reserved
Stuffed with "0"
Echo of Control Register
for which data is being
returned.
Control
18:12
11
Register Index
0 = Controller should send
valid slot 3 data in the next
frame, 1 = Controller
should not send slot 3 data
in the next frame
Slot 3 Request
bit (PCM left)
0 = Controller should send
valid slot 4 data in the next
frame, 1 = Controller
should not send slot 4 data
in the next frame
Slot 4 Request
bit (PCM right)
10
20030007
FIGURE 7. Start of Audio Input Frame
Other Slot
Request bits
Reserved
9:2
1,0
Unused
Bit
Description
Codec Ready
Bit
Comment
Stuff with "0"
15
0=Not Ready, 1=Ready
Slot 1 data
valid
14
Status Address is valid
15
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Register Descriptions
Reset Register (00h)
Application Information (Continued)
SDATA_IN Slot 2: Status Data
Writing any value to this register causes a register reset
which changes all of the registers back to their default val-
ues. If a read is performed on this register, the LM4548A will
return a value of 0D50h indicating that National 3D Sound is
implemented, 18bit data is supported for both the ADC’s and
DAC’s, and the volume control for True Line Level Out is
supported.
The slot returns the control register data. The data returned
was initiated by a read request in the previous SDATA_OUT
frame, slot 1.
Bits
19:4
3:0
Description
Control
Comment
Register Read
Data
Master Volume Registers (02h, 04h, 06h)
Reserved
Stuffed with "0" ’s
These registers allow the output levels from LINE_OUT,
LNLVL_OUT and MONO_OUT to be attenuated or muted.
There are 6-bits of volume control, plus one mute bit. It is a
5-bit volume range, where each step is nominally 1.5dB and
each output can be individually muted by either setting the
most significant bit (Mx5), and/or the mute bit (D15) to "1."
SDATA_IN Slot 3: PCM Record Left Channel
This slot contains the left ADC sample data. The signal to be
digitized is selected via register 1Ah and subsequently
routed through the Input Mux for recording by the left ADC.
This is a 20-bit slot, where the digitized 18-bit PCM data is
output from the codec MSB first and the last remaining 2 bits
will zeros.
Mute
Mx5:Mx0
00 0000
01 1111
Function
0dB attenuation
46.5dB attenuation
46.5dB attenuation
mute
0
0
Bits
19:2
1:0
Description
PCM Record
Left Channel
data
Comment
0
1X XXXX
XX XXXX
18 bit audio sample from
left ADC
1
Default: 8000h
Reserved
Stuffed with "0"’s
PC Beep Register (0Ah)
This register controls the level of the PC_BEEP input. The
PC_BEEP can be both attenuated and muted via register
0Ah. Step size is nominally 3dB. The signal present after the
attenuation and mute block is summed into both the left and
right channels.
SDATA_IN Slot 4: PCM Record Right Channel
This slot contains the right ADC sample data. The signal
digitized is selected via register 1Ah and subsequently
routed through the Input Mux for recording by the right ADC.
This is a 20-bit slot, where the digitized 18-bit PCM data is
output from the codec MSB first and the last remaining 2 bits
will zeros.
Mute
PV3:0
0000
1111
Function
0dB attenuation
45dB attenuation
mute
0
0
Bits
19:2
1:0
Description
PCM Record
Right Channel
data
Comment
1
XXXX
18 bit audio sample from
right ADC
Default: 0000h
Reserved
Stuffed with "0"’s
Mixer Input Volume Registers (Index 0Ch - 18h)
These registers set the input volume levels including mute.
Each volume control is 5 bit which provides from a range of
+12dB gain to 34.5dB attenuation in 1.5dB steps. For stereo
ports, the left and right levels can be independently set.
Muting a given port is accomplished by setting the MSB to 1.
Setting the MSB to 1 for stereo ports mutes both the left and
right channel. Register 0Eh has an additional 20dB boost for
a microphone level input. This is enabled by setting bit 6 of
register 0Eh to 1.
SDATA_IN Slots 5-12: Reserved
These SDATA_IN slots are set to "0" as they are reserved for
future use.
AC Link Low Power Mode
Mute
Gx4:Gx0
00000
Function
+12dB gain
0dB gain
0
0
0
1
01000
11111
34.5dB attenuation
mute
XXXXX
20030009
Default: 8008h (mono regs.), 8808h (stereo regs.)
FIGURE 8. AC Link Powerdown Timing
Record Select Register (1Ah)
This register independently controls the source for the right
and left channel which will be recorded by the stereo ADC.
The default value is 0000h which corresponds to Mic in.
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16
Application Information (Continued)
BIT
Function
PCM out path and mute, 0 = pre 3D, 1 =
post 3D
POP
SL2:SL0
Left Record Source
Mic
0
1
2
3
4
5
6
7
3D
MIX
MS
National 3D Sound on / off 1 = on
Mono output select 0 = Mix, 1 = Mic
Mic select 0 = Mic1 1 = Mic2
ADC/DAC loopback
CD In (L)
Video In (L)
Aux In (L)
LPBK
Line In (L)
Stereo Mix (L)
Mono Mix (L)
Phone
Powerdown Control / Status Register (26h)
This read/write register is used to monitor subsystem readi-
ness and also to program the LM4548A powerdown states.
The lower half of this register is read only with a "1", indicat-
ing the subsection is ready. Writing to the lower 8 bits will
have no effect.
SR2:SR0
Right Record Source
Mic
0
1
2
3
4
5
6
7
When the AC Link "Codec Ready" indicator bit (SDATA_IN
slot 0, bit 15) is a "1", it indicates that the AC Link and AC ’97
registers are in a fully operational state. The AC ’97 Control-
ler must further probe the Powerdown Control / Status Reg-
ister to determine exactly which subsections are ready.
CD In (R)
Video In (R)
Aux In (R)
Line In (R)
Stereo Mix (R)
Mono Mix (R)
Phone
BIT
REF
ANL
DAC
ADC
Function
Vref’s up to nominal level
Analog mixers ready
DAC section ready to accept data
ADC section ready to transmit data
Record (Input) Gain Register (1Ch)
This registers controls the Record (Input) Gain level for the
stereo input selected via the Record Select Control Register
(1Ah). The gain can be programmed from 0dB to +22.5dB in
1.5dB steps. The level for the left and right channel can be
individually controlled. The input can also be muted by set-
ting the MSB to 1.
Supported powerdown modes.
BIT
Function
PRO
PR1
PR2
PR3
PCM in ADC’s and Input Mux powerdown
PCM out DAC’s powerdown
Analog Mixer powerdown (VREF still on)
Analog Mixer powerdown (VREF off)
Digital Interface (AC Link) powerdown
(external clk off)
Mute
Gx3:Gx0
1111
Function
22.5dB gain
0dB gain
mute
0
0
0000
PR4
1
XXXX
PR5
PR6
Internal Clk disable
Default: 8000h
not used
General Purpose Register (20h)
This register controls many miscellaneous functions imple-
mented on the LM4548A. The miscellaneous functions in-
clude POP which allows the PCM to bypass the National 3D
Sound circuitry, 3D which enables or disables the National
3D Sound circuitry, MIX which selects the MONO_OUT
source, MS which selects the microphone mux source and
LPBK which connects the output of the stereo ADC to input
of the stereo DAC. LPBK provides for a digital loopthru path
when enabled.
Extended Audio ID Register (28h)
This read only register identifies which AC97 Extended Au-
dio features are supported. The LM4548A provides for VRA
(Variable Rate Audio) and Multiple Codec support. VRA is
indicated by a "1" in the LSB of register 28h. The two MSB’s,
ID1 and ID0, show the current codec configuration as con-
nected via external pins 45 and 46.
Pin46 (ID1)
Pin45 (ID0)
Reg 28h ID1
Reg 28h ID0
Codec Mode
Primary
Slots
NC (not connected) NC (not connected)
0
0
0
0
0
1
3 and 4
3 and 4
3 and 4
NC/DVdd
NC/DVdd
NC/DVdd
GND
Primary
Secondary 1
Note: Secondary modes 10 and 11 also decode slots 3 and 4.
Extended Audio Status/Control Register (2Ah)
registers 2Ch and 32h.
This read/write register provides status and control of the
Variable Sample Rate function. Setting the LSB of this reg-
ister to "1" enables Variable Rate Audio (VRA) mode and
allows DAC and ADC sample rates to be programmed via
BIT
Function
0 = VRA off (48kHz fixed), 1 = VRA on
VRA
17
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Application Information (Continued)
Sample Rate Control Registers (2Ch, 32h)
SR15:SR0
2B11h
Sample Rate (Hz)
11025
3E80h
16000
These read/write registers are used to set the sample rate
for the left and right channels of the DAC (2Ch) and the ADC
(32h). When Variable Rate Audio is enabled via bit-0 of
Register 2Ah, the sample rates can be programmed, in 1Hz
increments, to be any value from 4kHz to 48kHz. Below is a
list of the most common sample rates and their correspond-
ing register values.
5622h
22050
AC44h
BB80h
44100
48000
Reserved Registers
Do not write to these registers as they are reserved.
SR15:SR0
Sample Rate (Hz)
1F40h
8000
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18
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead , LQFP, 7 X 7 X 1.4mm, JEDEC (M)
Order Number LM4548AVH
NS Package Number VBH48A
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相关型号：
LM4549B
AC ’97 Rev 2.1 Multi-Channel Audio Codec with Sample Rate Conversion and National 3D Sound
NSC
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