LM4819MMX/NOPB [NSC]
IC 0.35 W, 1 CHANNEL, AUDIO AMPLIFIER, PDSO8, MSOP-8, Audio/Video Amplifier;
| 型号： | LM4819MMX/NOPB |
| 厂家： | 
National Semiconductor |
| 描述： | IC 0.35 W, 1 CHANNEL, AUDIO AMPLIFIER, PDSO8, MSOP-8, Audio/Video Amplifier 放大器 光电二极管 商用集成电路 |
| 文件： | 总21页 (文件大小：615K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 2002
LM4819
350mW Audio Power Amplifier with Shutdown Mode
General Description
Key Specifications
n THD+N at 1kHz, 350mW continuous average output
The LM4819 is a mono bridged power amplifier that is ca-
pable of delivering 350mWRMS output power into a 16Ω load
or 300mWRMS output power into an 8Ω load with 10%
THD+N from a 5V power supply.
power into 16Ω
n THD+N at 1kHz, 300mW continuous average output
power into 8Ω
10% (max)
10% (max)
n Shutdown Current
0.7µA (typ)
The LM4819 Boomer audio power amplifier is designed
specifically to provide high quality output power and mini-
mize PCB area with surface mount packaging and a minimal
amount of external components. Since the LM4819 does not
require output coupling capacitors, bootstrap capacitors or
snubber networks, it is optimally suited for low-power por-
table applications.
Features
n LLP, SOP, and MSOP surface mount packaging.
n Switch on/off click suppression.
n Unity-gain stable.
n Minimum external components.
The closed loop response of the unity-gain stable LM4819
can be configured using external gain-setting resistors. The
device is available in LLP, MSOP, and SO package types to
suit various applications.
Applications
n General purpose audio
n Portable electronic devices
n Information Appliances (IA)
Typical Application
DS200136-1
FIGURE 1. Typical Audio Amplifier Application Circuit
Boomer® is a registered trademark of National Semiconductor Corporation.
© 2002 National Semiconductor Corporation
DS200136
www.national.com
Connection Diagrams
SO Marking
Small Outline (SO) Package
DS200136-72
Top View
XY - Date Code
DS200136-35
TT - Die Traceability
Bottom 2 lines - Part Number
Top View
Order Number LM4819M
See NS Package Number M08A
MSOP Marking
Mini Small Outline (MSOP) Package
DS200136-71
Top View
G - Boomer Family
19 - LM4819MM
DS200136-36
Top View
Order Number LM4819MM
See NS Package Number MUA08A
LLP Package
DS200136-74
Top View
Order Number LM4819LD
See NS Package Number LDA08B
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2
Absolute Maximum Ratings (Notes 2, 3)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Infrared (15 seconds)
Thermal Resistance
220˚C
θJC (MSOP)
θJA (MSOP)
θJC (SOP)
θJA (SOP)
θJA (LLP)
56˚C/W
210˚C/W
Supply Voltage
6.0V
−65˚C to +150˚C
−0.3V to VDD +0.3V
Internally Limited
3.5kV
35˚C/W
Storage Temperature
170˚C/W
Input Voltage
117˚C/W (Note 10)
150˚C/W (Note 11)
Power Dissipation (PD) (Note 4)
ESD Susceptibility (Note 5)
ESD Susceptibility (Note 6)
Junction Temperature (TJ)
Soldering Information (Note 1)
Small Outline Package
Vapor Phase (60 seconds)
θJA (LLP)
Operating Ratings (Notes 2, 3)
250V
150˚C
Temperature Range
TMIN ≤ TA ≤ TMAX
−40˚C ≤ TA ≤ 85˚C
2.0V ≤ VCC ≤ 5.5V
Supply Voltage
215˚C
Electrical Characteristics VDD = 5V (Notes 2, 3)
The following specifications apply for VDD = 5V, RL = 16Ω unless otherwise stated. Limits apply for TA = 25˚C.
LM4819
Units
Symbol
Parameter
Conditions
Typical
(Note 7)
1.5
Limit
(Limits)
(Notes 8, 9)
IDD
Quiescent Power Supply Current
Shutdown Current
VIN = 0V, Io = 0A
3.0
5.0
4.0
1.0
50
mA (max)
µA (max)
V (min)
V (max)
mV (max)
mW
ISD
VPIN1 = VDD (Note 12)
1.0
VSDIH
VSDIL
VOS
Shutdown Voltage Input High
Shutdown Voltage Input Low
Output Offset Voltage
VIN = 0V
5
THD = 10%, fIN = 1kHz
THD = 10%, fIN = 1kHz, RL = 8Ω
350
300
1
PO
Output Power
mW
THD+N
Total Harmonic Distortion + Noise
PO = 270mWRMS, AVD = 2, fIN
1kHz
=
%
Electrical Characteristics VDD = 3V (Notes 2, 3)
The following specifications apply for VDD = 3V and RL = 16Ω load unless otherwise stated. Limits apply to TA = 25˚C.
LM4819
Units
Symbol
Parameter
Conditions
Typical
(Note 7)
1.0
Limit
(Limits)
(Notes 8, 9)
IDD
Quiescent Power Supply Current
Shutdown Current
VIN = 0V, Io = 0A
3.0
5.0
2.4
0.6
50
mA (max)
µA (max)
V (min)
V (max)
mV
ISD
VPIN1 = VDD (Note 12)
0.7
VSDIH
VSDIL
VOS
Shutdown Voltage Input High
Shutdown Voltage Input Low
Output Offset Voltage
VIN = 0V
5
110
90
1
THD = 10%, fIN = 1kHz
THD = 10%, fIN = 1kHz, RL = 8Ω
mW
PO
Output Power
mW
THD+N
Total Harmonic Distortion + Noise
PO = 80mWRMS, AVD = 2, fIN
1kHz
=
%
3
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Electrical Characteristics VDD = 3V (Notes 2, 3)
The following specifications apply for VDD = 3V and RL = 16Ω load unless otherwise stated. Limits apply to TA
=
25˚C. (Continued)
Note 1: See AN-450 ’Surface Mounting and their Effects on Product Reliability’ for other methods of soldering surface mount devices.
Note 2: All voltages are measured with respect to the ground pin, unless otherwise specified.
Note 3: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which
guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit
is given. However, the typical value is a good indication of device’s performance.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
, θ , and the ambient temperature T . The maximum
A
JMAX JA
allowable power dissipation is P
= (T
–T )/θ . For the LM4819, T
= 150˚C and the typical junction-to-ambient thermal resistance (θ ) when board
JMAX JA
DMAX
JMAX
A
JA
mounted is 210˚C/W for the MSOP package and 170˚C/W for the SOP package.
Note 5: Human body model, 100pF discharged through a 1.5 kΩ resistor.
Note 6: Machine Model, 220pF–240pF capacitor is discharged through all pins.
Note 7: Typical specifications are specified at 25˚C and represent the parametric norm.
Note 8: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 9: Datasheet min/max specification limits are guaranteed by designs, test, or statistical analysis.
Note 10: The given θ is for an LM4819 package in an LDA08B with the Exposed-DAP soldered to a printed circuit board copper pad with an area equivalent to
JA
that of the Exposed-DAP itself. The Exposed-DAP of the LDA08B package should be electrically connected to GND or an electrically isolated copper area.
Note 11: The given θ is for an LM4819 package in an LDA08B with the Exposed-DAP not soldered to any printed circuit board copper.
JA
Note 12: The shutdown pin (pin1) should be driven as close as possible to V
for minimum current in Shutdown Mode.
DD
External Components Description (Figure 1)
Components
Functional Description
1.
Ri
Combined with Rf, this inverting input resistor sets the closed-loop gain. Ri also forms a high pass filter with
Ci at fc = 1/(2πRiCi).
2.
Ci
This input coupling capacitor blocks DC voltage at the amplifier’s terminals. Combined with Ri, it creates a
high pass filter with Ri at fc = 1/(2πRiCi). Refer to the section, Proper Selection of External Components
for an explanation of how to determine the value of Ci.
3.
4.
Rf
Combined with Ri, this is the feedback resistor that sets the closed-loop gain: Av = 2(RF/Ri).
CS
This is the power supply bypass capacitor that filters the voltage applied to the power supply pin. Refer to
the Application Information section for proper placement and selection of Cs.
5.
CB
This is the bypass pin capacitor that filters the voltage at the BYPASS pin. Refer to the section, Proper
Selection of External Components, for information concerning proper placement and selection of CB.
Typical Performance Characteristics
THD+N vs Frequency
THD+N vs Frequency
DS200136-37
DS200136-38
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4
Typical Performance Characteristics (Continued)
THD+N vs Frequency
THD+N vs Frequency
THD+N vs Output Power
THD+N vs Frequency
DS200136-39
DS200136-41
DS200136-43
DS200136-40
DS200136-42
DS200136-44
THD+N vs Frequency
THD+N vs Output Power
5
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Typical Performance Characteristics (Continued)
THD+N vs Output Power
THD+N vs Output Power
DS200136-45
DS200136-73
THD+N vs Output Power
THD+N vs Output Power
DS200136-47
DS200136-46
Output Power vs Supply Voltage
Output Power vs Supply Voltage
RL = 8Ω
RL = 16Ω
DS200136-49
DS200136-48
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6
Typical Performance Characteristics (Continued)
Output Power vs Supply Voltage
Output Power vs Load Resistance
RL = 32Ω
DS200136-51
DS200136-50
Power Dissipation vs
Output Power
VDD = 5V
Power Dissipation vs
Output Power
VDD = 3V
DS200136-53
DS200136-52
Power Derating Curves
Frequency Response vs
Input Capacitor Size
DS200136-55
DS200136-54
7
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Typical Performance Characteristics (Continued)
Supply Current vs
Supply Voltage
DS200136-69
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8
For the micro MUA08A package, θJA = 210˚C/W, for the
M08A package, θJA = 170˚C/W , and TJMAX = 150˚C for the
LM4819. For a given ambient temperature, TA, Equation (4)
can be used to find the maximum internal power dissipation
supported by the IC packaging. If the result of Equation (3) is
greater than the result of Equation (4), then decrease the
supply voltage, increase the load impedance, or reduce the
ambient temperature. For a typical application using the
M08A packaged LM4819 with a 5V power supply and an 8Ω
load, the maximum ambient temperature that does not vio-
late the maximum junction temperature is approximately
42˚C. If a MUA08A packaged part is used instead with the
same supply voltage and load, the maximum ambient tem-
perature is 17˚C. In both cases, it is assumed that a device
is a surface mount part operating around the maximum
power dissipation point. The assumption that the device is
operating around the maximum power dissipation point is
incorrect for an 8Ω load. The maximum power dissipation
point occurs when the output power is equal to the maximum
power dissipation or 50% efficiency. The LM4819 is not
capable of the output power level (633mW) required to op-
erate at the maximum power dissipation point for an 8Ω load.
To find the maximum power dissipation, the graph Power
Dissipation vs. Output Power must be used. From the
graph, the maximum power dissipation for an 8Ω load and a
5V supply is approximately 575mW. Substituting this value
back into equation (4) for PDMAX and using θJA = 210˚C/W
for the MUA08A package, the maximum ambient tempera-
ture is calculated to be 29˚C. Using θJA = 170˚C/W for the
M08A package, the maximum ambient temperature is 52˚C.
Refer to the Typical Performance Characteristics curves
for power dissipation information for lower output powers
and maximum power dissipation for each package at a given
ambient temperature.
Application Information
BRIDGE CONFIGURATION EXPLANATION
As shown in Figure 1, the LM4819 consist of two operational
amplifiers. External resistors, Ri and RF set the closed-loop
gain of the first amplifier (and the amplifier overall), whereas
two internal 20kΩ resistors set the second amplifier’s gain at
-1. The LM4819 is typically used to drive a speaker con-
nected between the two amplifier outputs.
Figure 1 shows that the output of Amp1 servers as the input
to Amp2, which results in both amplifiers producing signals
identical in magnitude but 180˚ out of phase. Taking advan-
tage of this phase difference, a load is placed between V01
and V02 and driven differentially (commonly referred to as
’bridge mode’). This results in a differential gain of
A
VD= 2 *(Rf/Ri)
(1)
Bridge mode is different from single-ended amplifiers that
drive loads connected between a single amplifier’s output
and ground. For a given supply voltage, bridge mode has a
distinct advantage over the single-ended configuration: its
differential output doubles the voltage swing across the load.
This results in four times the output power when compared
to a single-ended amplifier under the same conditions. This
increase in attainable output assumes that the amplifier is
not current limited or the output signal is not clipped. To
ensure minimum output signal clipping when choosing an
amplifier’s closed-loop gain, refer to the Audio Power Am-
plifier Design Example section.
Another advantage of the differential bridge output is no net
DC voltage across the load. This results from biasing V01
and V02 at half-supply. This eliminates the coupling capacitor
that single supply, single-ended amplifiers require. Eliminat-
ing an output coupling capacitor in a single-ended configu-
ration forces a single supply amplifier’s half-supply bias volt-
age across the load. The current flow created by the half-
supply bias voltage increases internal IC power dissipation
and may permanently damage loads such as speakers.
POWER SUPPLY BYPASSING
As with any power amplifier, proper supply bypassing is
critical for low noise performance and high power supply
rejection. The capacitors connected to the bypass and power
supply pins should be placed as close to the LM4819 as
possible. The capacitor connected between the bypass pin
and ground improves the internal bias voltage’s stability,
producing improved PSRR. The improvements to PSRR
increase as the bypass pin capacitor value increases. Typi-
cal applications employ a 5V regulator with 10µF and 0.1µF
filter capacitors that aid in supply stability. Their presence,
however, does not eliminate the need for bypassing the
supply nodes of the LM4819. The selection of bypass ca-
pacitor values, especially CB , depends on desired PSRR
requirements, click and pop performance as explained in the
section, Proper Selection of External Components, as
well as system cost and size constraints.
POWER DISSIPATION
Power dissipation is a major concern when designing a
successful bridged or single-ended amplifier. Equation (2)
states the maximum power dissipation point for a single-
ended amplifier operating at a given supply voltage and
driving a specified load.
2
PDMAX = (VDD
)
/(2π2RL ) (W) Single-ended
(2)
However, a direct consequence of the increased power de-
livered to the load by a bridged amplifier is an increase in the
internal power dissipation point for a bridge amplifier oper-
ating at the same given conditions. Equation (3) states the
maximum power dissipation point for a bridged amplifier
operating at a given supply voltage and driving a specified
load.
SHUTDOWN FUNCTION
PDMAX = 4(VDD)2/(2π2 RL ) (W) Bridge Mode
(3)
The voltage applied to the LM4819’s SHUTDOWN pin con-
trols the shutdown function. Activate micro-power shutdown
by applying VDD to the SHUTDOWN pin. When active, the
LM4819’s micro-power shutdown feature turns off the ampli-
fier’s bias circuitry, reducing the supply current. The logic
threshold is typically 1/2VDD. The low 0.7µA typical shut-
down current is achieved by applying a voltage that is as
near as VDD as possible to the SHUTDOWN pin. A voltage
that is less than VDD may increase the shutdown current.
Avoid intermittent or unexpected micro-power shutdown by
ensuring that the SHUTDOWN pin is not left floating but
connected to either VDD or GND.
The LM4819 has two operational amplifiers in one package
and the maximum internal power dissipation is four times
that of a single-ended amplifier. However, even with this
substantial increase in power dissipation, the Lm4819 does
not require heatsinking. From Equation (3), assuming a 5V
power supply and an 8Ω load, the maximum power dissipa-
tion point is 633mW. The maximum power dissipation point
obtained from Equation (3) must not exceed the power dis-
sipation predicted by Equation (4):
PDMAX = (TJMAX - TA)/θJA (W)
(4)
9
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f-3dB = 1/(2 πRiCi) (Hz)
(5)
Application Information (Continued)
As an example when using a speaker with a low frequency
limit of 150Hz, Ci, using Equation (5) is 0.063µF. The 0.39µF
Ci shown in Figure 1 allows the LM4819 to drive a high
efficiency, full range speaker whose response extends down
to 20Hz.
There are a few ways to activate micro-power shutdown.
These included using a single-pole, single-throw switch, a
microcontroller, or a microprocessor. When using a switch,
connect an external 10kΩ to 100kΩ pull-up resistor between
the SHUTDOWN pin and VDD. Connect the switch between
the SHUTDOWN pin and ground. Select normal amplifier
operation by closing the switch. Opening the switch con-
nects the shutdown pin to VDD through the pull-up resistor,
activating micro-power shutdown. The switch and resistor
guarantee that the SHUTDOWN pin will not float. This pre-
vents unwanted state changes. In a system with a micropro-
cessor or a microcontroller, use a digital output to apply the
control voltage to the SHUTDOWN pin. Driving the SHUT-
DOWN pin with active circuitry eliminates the pull-up resistor
Besides optimizing the input capacitor value, the bypass
capacitor value, CB requires careful consideration. The by-
pass capacitor’s value is the most critical to minimizing
turn-on pops because it determines how fast the LM4819
turns on. The slower the LM4819’s outputs ramp to their
quiescent DC voltage (nominally 1/2VDD), the smaller the
turn-on pop. While the device will function properly (no os-
cillations or motorboating), with CB less than 1.0µF, the
device will be much more susceptible to turn-on clicks and
pops. Thus, a value of CB equal to or greater than 1.0µF is
recommended in all but the most cost sensitive designs.
PROPER SELECTION OF EXTERNAL COMPONENTS
Optimizing the LM4819’s performance requires properly se-
lecting external components. Though the LM4819 operates
well when using external components with wide tolerances,
best performance is achieved by optimizing component val-
ues.
Bypass Capacitor Value Selection
Besides minimizing the input capacitor size, careful consid-
eration should be paid to the value of CB, the capacitor
connected to the BYPASS pin. Since CB determines how
fast the LM4819 settles to quiescent operation, its value is
critical when minimizing turn-on pops. The slower the
LM4819’s outputs ramp to their quiescent DC voltage (nomi-
nally 1/2VDD), the smaller the turn-on pop. Choosing CB
equal to 1.0µF along with a small value of Ci (in the range of
0.1µF to 0.39µF) produces a click-less and pop-less shut-
down function. As discussed above, choosing Ci no larger
than necessary for the desired bandwidth helps minimize
clicks and pops.
The LM4819 is unity gain stable, giving the designer maxi-
mum design flexibility. The gain should be set to no more
than a given application requires. This allows the amplifier to
achieve minimum THD+N and maximum signal-to-noise ra-
tio. These parameters are compromised as the closed-loop
gain increases. However, low gain demands input signals
with greater voltage swings to achieve maximum output
power. Fortunately, many signal sources such as audio CO-
DECs have outputs of 1VRMS (2.83VP-P). Please refer to the
Audio Power Amplifier Design section for more informa-
tion on selecting the proper gain.
Optimizing Click and Pop Reduction Performance
The LM4819 contains circuitry that minimizes turn-on and
shutdown transients or ’clicks and pops’. For this discussion,
turn on refers to either applying the power or supply voltage
or when the shutdown mode is deactivated. While the power
supply is ramping to it’s final value, the LM4819’s internal
amplifiers are configured as unity gain buffers. An internal
current source charges the voltage of the bypass capacitor,
CB, connected to the BYPASS pin in a controlled, linear
manner. Ideally, the input and outputs track the voltage
charging on the bypass capacitor. The gain of the internal
amplifiers remains unity until the bypass capacitor is fully
charged to 1/2VDD. As soon as the voltage on the bypass
capacitor is stable, the device becomes fully operational.
Although the BYPASS pin current cannot be modified,
changing the size of the bypass capacitor, CB, alters the
device’s turn-on time and magnitude of ’clicks and pops’.
Increasing the value of CB reduces the magnitude of turn-on
pops. However, this presents a tradeoff: as the size of CB
increases, the turn-on time (Ton) increases. There is a linear
relationship between the size of CB and the turn on time.
Below are some typical turn-on times for various values of
CB:
Another important consideration is the amplifier’s close-loop
bandwidth. To a large extent, the bandwidth is dictated by
the choice of external components shown in Figure 1. The
input coupling capacitor, Ci, forms a first order high pass filter
that limits low frequency response. This value should be
chosen based on needed frequency response for a few
distinct reasons discussed below
Input Capacitor Value Selection
Amplifying the lowest audio frequencies requires a high
value input coupling capacitor (Ci in Figure 1). A high value
capacitor can be expensive and may compromise space
efficiency in portable designs. In many cases the speakers
used in portable systems, whether internal or external, have
little ability to reproduce signals below 150Hz. Applications
using speakers with limited frequency response reap little
improvement by using a large input capacitor.
Besides affecting system cost and size, Ci has an effect on
the LM4819’s click and pop performance. When the supply
voltage is first applied, a transient (pop) is created as the
charge on the input capacitor changes from zero to a quies-
cent state. The magnitude of the pop is directly proportional
to the input capacitor’s value. Higher value capacitors need
CB
TON
20ms
0.01µF
0.1µF
0.22µF
0.47µF
1.0µF
more time to reach a quiescent DC voltage (usually 1/2 VDD
)
when charged with a fixed current. The amplifier’s output
charges the input capacitor through the feedback resistor,
RF. Thus, selecting an input capacitor value that is no higher
than necessary to meet the desired -3dB frequency can
minimize pops.
200ms
440ms
940ms
2S
As shown in Figure 1, the input resistor (Ri) and the input
capacitor, Ci produce a -3dB high pass filter cutoff frequency
that is found using Equation (5).
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10
The last step in this design example is setting the amplifier’s
Application Information (Continued)
±
-3dB frequency bandwidth. To achieve the desired 0.25dB
In order to eliminate ’clicks and pops’, all capacitors must be
discharged before turn-on. Rapidly switching VDD may not
allow the capacitors to fully discharge, which may cause
’clicks and pops’.
pass band magnitude variation limit, the low frequency re-
sponse must extend to at least one-fifth the lower bandwidth
limit and the high frequency response must extend to at least
five times the upper bandwidth limit. The gain variation for
±
both response limits is 0.17dB, well with in the 0.25dB
desired limit.
AUDIO POWER AMPLIFIER DESIGN EXAMPLE
The results are:
The following are the desired operational
parameters:
fL = 100Hz/5 = 20Hz
fH = 20 kHz*5 = 100kHz
Given:
As mentioned in the External Components section, Ri and
Ci create a high pass filter that sets the amplifier’s lower
band pass frequency limit. Find the coupling capacitor’s
value using Equation (8).
Power Output
Load Impedance
Input Level
100mW
16Ω
1Vrms (max)
20kΩ
Input Impedance
Bandwidth
Ci ≥ 1/(2πRifc) (F)
(8)
±
100Hz–20kHz 0.25dB
Ci ≥ 0.398µF, a standard value of 0.39µF will be used. The
product of the desired high frequency cutoff (100kHz in this
example) and the differential gain, AVD, determines the up-
The design begins by specifying the minimum supply voltage
necessary to obtain the specified output power. To find this
minimum supply voltage, use the Output Power vs. Supply
Voltage graph in the Typical Performance Characteristics
section. From the graph for a 16Ω load, (graphs are for 8Ω,
16Ω, and 32Ω loads) the supply voltage for 100mW of output
power with 1% THD+N is approximately 3.15 volts.
per pass band response limit. With AVD = 1.27 and fH
=
100kHz, the closed-loop gain bandwidth product (GBWP) is
127kHz. This is less than the LM4819’s 900kHz GBWP. With
this margin the amplifier can be used in designs that require
more differential gain while avoiding performance restricting
bandwidth limitations.
Additional supply voltage creates the benefit of increased
headroom that allows the LM4819 to reproduce peaks in
excess of 100mW without output signal clipping or audible
distortion. The choice of supply voltage must also not create
a situation that violates maximum dissipation as explained
above in the Power Dissipation section. For example, if a
3.3V supply is chosen for extra headroom then according to
Equation (3) the maximum power dissipation point with a
16Ω load is 138mW. Using Equation (4) the maximum am-
bient temperature is 121˚C for the MUA08A package and
126˚C for the M08A package.
After satisfying the LM4819’s power dissipation require-
ments, the minimum differential gain is found using Equation
(6).
(6)
Thus a minimum gain of 1.27 V/V allows the LM4819 to
reach full output swing and maintain low noise and THD+N
performance. For this example, let AVD = 1.27. The amplifi-
er’s overall gain is set using the input (Ri) and feedback (RF)
resistors. With the desired input impedance set to 20kΩ, the
feedback resistor is found using Equation (7).
RF/Ri = AVD/2 (V/V)
The value of RF is 13kΩ.
(7)
11
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Application Information (Continued)
HIGHER GAIN AUDIO AMPLIFIER
DS200136-24
Figure 2
The LM4819 is unity-gain stable and requires no external
components besides gain-setting resistors, an input coupling
capacitor, and proper supply bypassing in the typical appli-
cation. However, if a closed-loop differential gain of greater
than 10 is required, a feedback capacitor (C4) may be
needed as shown in Figure 2 to bandwidth limit the amplifier.
This feedback capacitor creates a low pass filter that elimi-
nates possible high frequency oscillations. Care should be
taken when calculating the -3dB frequency in that an incor-
rect combination of R3 and C4 will cause rolloff before
20kHz. A typical combination of feedback resistor and ca-
pacitor that will not produce audio band high frequency rolloff
is R3 = 20kΩ and C4 = 25pF. These components result in a
-3dB point of approximately 320 kHz. It is not recommended
that the feedback resistor and capacitor be used to imple-
ment a band limiting filter below 100kHz.
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12
Application Information (Continued)
DIFFERENTIAL AMPLIFIER CONFIGURATION FOR LM4819
DS200136-29
Figure 3
13
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Application Information (Continued)
REFERENCE DESIGN BOARD and PCB LAYOUT GUIDELINES
DS200136-68
Figure 4
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14
Application Information (Continued)
LM4819 SO DEMO BOARD ARTWORK
Silk Screen
Top Layer
DS200136-62
DS200136-63
Bottom Layer
DS200136-64
15
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Application Information (Continued)
LM4819 MSOP DEMO BOARD ARTWORK
Silk Screen
Top Layer
DS200136-65
DS200136-66
Bottom Layer
DS200136-67
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16
Application Information (Continued)
LM4819 LD DEMO BOARD ARTWORK
Silk Screen
Composite View
DS200136-31
DS200136-32
Bottom Layer
Top Layer
DS200136-30
DS200136-33
17
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Application Information (Continued)
Mono LM4819 Reference Design Boards
Bill of Material for all Demo Boards
Item
Part Number
Part Description
Qty
1
Ref Designator
1
551011208-001 LM4819 Mono Reference Design Board
10
20
21
25
30
35
482911183-001
151911207-001
151911207-002
152911207-001
472911207-001
210007039-002
LM4819 Audio AMP
Tant Cap 1uF 16V 10
1
U1
C1
1
Cer Cap 0.39uF 50V Z5U 20% 1210
Tant Cap 1uF 16V 10
1
C2
1
C3
Res 20K Ohm 1/10W 5
3
R1, R2, R3
J1, J2
Jumper Header Vertical Mount 2X1
0.100
2
PCB LAYOUT GUIDELINES
Single-Point Power / Ground Connections
This section provides practical guidelines for mixed signal
PCB layout that involves various digital/analog power and
ground traces. Designers should note that these are only
’rule-of-thumb’ recommendations and the actual results will
depend heavily on the final layout.
The analog power traces should be connected to the digital
traces through a single point (link). A ’Pi-filter’ can be helpful
in minimizing high frequency noise coupling between the
analog and digital sections. It is further recommended to put
digital and analog power traces over the corresponding digi-
tal and analog ground traces to minimize noise coupling.
General Mixed Signal Layout Recommendation
Placement of Digital and Analog Components
Power and Ground Circuits
All digital components and high-speed digital signals traces
should be located as far away as possible from analog
components and circuit traces.
For two layer mixed signal design, it is important to isolate
the digital power and ground trace paths from the analog
power and ground trace paths. Star trace routing techniques
(bringing individual traces back to a central point rather than
daisy chaining traces together in a serial manner) can have
a major impact on low level signal performance. Star trace
routing refers to using individual traces to feed power and
ground to each circuit or even device. This technique will
take require a greater amount of design time but will not
increase the final price of the board. The only extra parts
required will be some jumpers.
Avoiding Typical Design / Layout Problems
Avoid ground loops or running digital and analog traces
parallel to each other (side-by-side) on the same PCB layer.
When traces must cross over each other do it at 90 degrees.
Running digital and analog traces at 90 degrees to each
other from the top to the bottom side as much as possible will
minimize capacitive noise coupling and cross talk.
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18
Physical Dimensions inches (millimeters) unless otherwise noted
MSOP
Order Number LM4819MM
NS Package Number MUA08A
19
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
SO
Order Number LM4819M
NS Package Number M08A
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20
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
LLP
Order Number LM4819LD
NS Package Number LDA08B
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