LM4936 [NSC]
Stereo 2W Audio Power Amplifiers with Volume Control and Selectable Control Interface (SPI or I2C); 2W立体声音频功率放大器，带有音量控制和可选控制接口（ SPI或I2C ）
| 型号： | LM4936 |
| 厂家： | 
National Semiconductor |
| 描述： | Stereo 2W Audio Power Amplifiers with Volume Control and Selectable Control Interface (SPI or I2C) |
| 文件： | 总28页 (文件大小：1484K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 2005
LM4936
Stereo 2W Audio Power Amplifiers with Volume Control
and Selectable Control Interface (SPI or I2C)
General Description
Key Specifications
n PO at 1% THD+N
The LM4936 is a monolithic integrated circuit that provides
volume control, and stereo bridged audio power amplifiers
capable of producing 2W into 4Ω (Note 1) with less than 1%
THD or 2.2W into 3Ω (Note 2) with less than 1% THD.
n
n
n
into 3Ω
into 4Ω
into 8Ω
2.2W (typ)
2.0W (typ)
1.25W (typ)
Boomer® audio integrated circuits were designed specifically
to provide high quality audio while requiring a minimum
amount of external components. The LM4936 incorporates a
SPI or I2C Control Interface that runs the volume control,
stereo bridged audio power amplifiers and a selectable gain
or bass boost. All of the LM4936’s features (i.e. SD, Mode,
Mute, Gain Sel) make it optimally suited for multimedia
monitors, portable radios, desktop, and portable computer
applications.
n Single-ended mode - THD+N at 90mW into 32Ω 1%(typ)
n Shutdown current
0.7µA (typ)
Features
n Selectable SPI or I2C Control Interface
n System Beep Detect
n Stereo switchable bridged/single-ended power amplifiers
n Selectable internal/external gain and bass boost
n “Click and pop” suppression circuitry
n Thermal shutdown protection circuitry
n Headphone Sense
The LM4936 features an externally controlled, low-power
consumption shutdown mode, and both a power amplifier
and headphone mute for maximum system flexibility and
performance.
Note 1: When properly mounted to the circuit board, LM4936MH will deliver
2W into 4Ω. See Application Information section Exposed-DAP package
PCB Mounting Considerations for more information.
Applications
n Portable and Desktop Computers
n Multimedia Monitors
Note 2: An LM4936MH that has been properly mounted to the circuit board
and forced-air cooled will deliver 2.2W into 3Ω.
n Portable Radios, PDAs, and Portable TVs
Connection Diagram
TSSOP Package
20117802
Top View
Order Number LM4936MH
See NS Package Number MXA28A for Exposed-DAP TSSOP
Boomer® is a registered trademark of NationalSemiconductor Corporation.
© 2005 National Semiconductor Corporation
DS201178
www.national.com
Block Diagram
20117801
FIGURE 1. LM4936 Block Diagram
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2
Absolute Maximum Ratings (Note 10)
θJC (typ) - MXA28A
2˚C/W
41˚C/W
54˚C/W
59˚C/W
93˚C/W
θJA (typ) - MXA28A (exposed DAP) (Note 4)
θJA (typ) - MXA28A (exposed DAP) (Note 3)
θJA (typ) - MXA28A (exposed DAP) (Note 5)
θJA (typ) - MXA28A (exposed DAP) (Note 6)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
6.0V
-65˚C to +150˚C
−0.3V to VDD +0.3V
Internally limited
2000V
Storage Temperature
Input Voltage
Operating Ratings
Temperature Range
Power Dissipation (Note 11)
ESD Susceptibility (Note 12)
ESD Susceptibility (Note 13)
Junction Temperature
Soldering Information
Small Outline Package
Vapor Phase (60 sec.)
Infrared (15 sec.)
TMIN ≤ TA ≤TMAX
−40˚C ≤ TA ≤ 85˚C
2.7V ≤ VDD ≤ 5.5V
I2C/SPI VDD ≤ VDD
2.4V ≤ I2C/SPI VDD ≤ 5.5V
200V
Supply Voltage (Note 17)
150˚C
215˚C
220˚C
See AN-450 “Surface Mounting and their Effects on
Product Reliability” for other methods of soldering surface
mount devices.
Electrical Characteristics for Entire IC (Notes 7, 10)
The following specifications apply for VDD = 5V unless otherwise noted. Limits apply for TA = 25˚C.
LM4936
Units
Symbol
VDD
Parameter
Supply Voltage
Conditions
Typical
Limit
(Note 15)
2.7
(Limits)
(Note 14)
V (min)
V (max)
mA (max)
µA (max)
V (min)
5.5
IDD
ISD
VIH
VIL
Quiescent Power Supply Current
Shutdown Current
VIN = 0V, IO = 0A
Vshutdown = VDD
10
25
0.7
2.0
Headphone Sense High Input Voltage
Headphone Sense Low Input Voltage
4
0.8
V (max)
Electrical Characteristics for Volume Control (Notes 7, 10)
The following specifications apply for VDD = 5V. Limits apply for TA = 25˚C.
LM4936
Units
(Limits)
Symbol
Parameter
Conditions
Maximum gain setting
Typical
(Note 14)
0
Limit
(Note 15)
0.75
CRANGE
Volume Control Range
dB (max)
dB (min)
dB
Minimum gain setting
fIN = 1kHz
-91
-75
ACh-Ch
AM
Channel to Channel Gain Mismatch
Mute Attenuation
0.35
Mute Mode
-78
dB (min)
Electrical Characteristics for Control Interface (Notes 7, 10)
The following specifications apply for VDD = 5V, VDD = 3V and 2.4V ≤ I2C/SPI VDD ≤ 5.5V. Limits apply for TA = 25˚C.
LM4936
Units
(Limits)
Symbol
Parameter
Conditions
Typical
Limit
(Note 15)
2.5
(Note 14)
t1
t2
t3
t4
t5
SCL period
µs (min)
ns (min)
ns (min)
ns (min)
ns (min)
SDA Set-up Time
SDA Stable Time
Start Condition Time
Stop Condition Time
100
0
100
100
3
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Electrical Characteristics for Control Interface (Notes 7, 10) (Continued)
The following specifications apply for VDD = 5V, VDD = 3V and 2.4V ≤ I2C/SPI VDD ≤ 5.5V. Limits apply for TA = 25˚C.
LM4936
Units
(Limits)
Symbol
VIH
Parameter
Digital Input High Voltage
Digital Input Low Voltage
Conditions
Typical
Limit
(Note 14)
(Note 15)
0.7 X
V (min)
V (max)
I2C/SPIVDD
VIL
0.3 X
I2C/SPIVDD
tES
tEH
tEL
SPI ENABLE Setup Time
SPI ENABLE Hold Time
SPI ENABLE High Time
SPI DATA Setup Time
50
50
50
50
50
50
100
100
5
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
MHz (max)
tDS
tDH
tCS
tCH
tCL
fCLK
SPI DATA HOLD Time
SPI CLOCK Setup Time
SPI CLOCK High Pulse Width
SPI CLOCK Low Pulse Width
SPI CLOCK Frequency
Electrical Characteristics for Single-Ended Mode Operation (Notes 7, 10)
The following specifications apply for VDD = 5V. Limits apply for TA = 25˚C.
LM4936
Units
(Limits)
Symbol
PO
Parameter
Output Power
Conditions
Typical
(Note 14)
90
Limit
(Note 15)
THD = 1%; f = 1kHz; RL = 32Ω
THD = 10%; f = 1 kHz; RL = 32Ω
POUT = 20mW, f = 1kHz, RL = 32Ω,
AVD = 1, 80kHz BW
mW
mW
%
110
THD+N
PSRR
Total Harmonic Distortion+Noise
Power Supply Rejection Ratio
0.02
CB = 1µF, f = 120Hz,
57
dB
Input Terminated
VRIPPLE = 200mVp-p
NOUT
Xtalk
Output Noise
A-Wtd Filter
18
63
µV
dB
Channel Separation (Note 17)
f = 1kHz, CB = 1µF
Electrical Characteristics for Bridged Mode Operation (Notes 7, 10)
The following specifications apply for VDD = 5V, unless otherwise noted. Limits apply for TA = 25˚C.
LM4936
Units
(Limits)
Symbol
VOS
Parameter
Conditions
VIN = 0V, No Load
Typical
(Note 14)
10
Limit
(Note 15)
50
Output Offset Voltage
Output Power
mV (max)
W
PO
THD + N = 1%; f = 1kHz; RL = 3Ω
(Note 8)
2.2
THD + N = 1%; f = 1kHz; RL = 4Ω
(Note 9)
2
W
THD+N = 1% (max); f = 1kHz;
RL = 8Ω
1.25
1.0
W (min)
THD+N = 10%; f = 1kHz; RL = 8Ω
PO = 0.4W, f = 1kHz
1.6
W
%
THD+N
PSRR
Total Harmonic Distortion+Noise
Power Supply Rejection Ratio
0.06
RL = 8Ω, AVD = 2, 80kHz BW
CB = 1µF, f = 120Hz,
Input Terminated
55
dB
VRIPPLE = 200mVp-p; RL = 8Ω
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4
Electrical Characteristics for Bridged Mode Operation (Notes 7, 10) (Continued)
The following specifications apply for VDD = 5V, unless otherwise noted. Limits apply for TA = 25˚C.
LM4936
Units
(Limits)
Symbol
Parameter
Conditions
Typical
(Note 14)
36
Limit
(Note 15)
NOUT
Xtalk
Output Noise
Channel Separation (Note 17)
A-Wtd Filter
f = 1kHz, CB = 1µF
µV
dB
63
2
Note 3: The θ given is for an MXA28A package whose exposed-DAP is soldered to an exposed 2in piece of 1 ounce printed circuit board copper.
JA
2
Note 4: The θ given is for an MXA28A package whose exposed-DAP is soldered to a 2in piece of 1 ounce printed circuit board copper on a bottom side layer
JA
through 21 8mil vias.
2
Note 5: The θ given is for an MXA28A package whose exposed-DAP is soldered to an exposed 1in piece of 1 ounce printed circuit board copper.
JA
Note 6: The θ given is for an MXA28A package whose exposed-DAP is not soldered to any copper.
JA
Note 7: All voltages are measured with respect to the ground pins, unless otherwise specified. All specifications are tested using the typical application as shown
in Figure 1.
Note 8: When driving 3Ω loads from a 5V supply the LM4936MH must be mounted to the circuit board and forced-air cooled. The demo board shown in the
2
2
2
2
datasheet has planes for heat sinking. The top layer plane is 1.05 in (675mm ), the inner two layers each have a 1.03 in (667mm ) plane and the bottom layer
2
2
has a 3.32 in (2143mm ) plane. The planes are electrically GND and interconnected through six 15 mil vias directly under the package and eight 28 mil vias in
various locations.
Note 9: When driving 4Ω loads from a 5V supply the LM4936MH must be mounted to the circuit board. The demo board shown in the datasheet has planes for heat
2
2
2
2
2
2
sinking. The top layer plane is 1.05 in (675mm ), the inner two layers each have a 1.03 in (667mm ) plane and the bottom layer has a 3.32 in (2143mm ) plane.
The planes are electrically GND and interconnected through six 15 mil vias directly under the package and eight 28 mil vias in various locations.
Note 10: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which
guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit
is given, however, the typical value is a good indication of device performance.
Note 11: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
, θ , and the ambient temperature T . The maximum
JA A
JMAX
allowable power dissipation is P
= (T
− T )/θ . For the LM4936, T
= 150˚C, and the typical junction-to-ambient thermal resistance for each package
DMAX
JMAX
A
JA
JMAX
can be found in the Absolute Maximum Ratings section above.
Note 12: Human body model, 100pF discharged through a 1.5kΩ resistor.
Note 13: Machine Model, 220pF – 240pF discharged through all pins.
Note 14: Typicals are measured at 25˚C and represent the parametric norm.
Note 15: Limits are guaranteed to National’s AOQL ( Average Outgoing Quality Level). Datasheet min/max specification limits are guaranteed by design, test, or
statistical analysis.
2
2
Note 16: I C/SPI V must not be larger than V at any time or damage to the IC may occur. During power up and power down, I C/SPI V must remain equal
DD
DD
DD
to V
or lower.
DD
Note 17: PCB design will affect Crosstalk performance.
5
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Typical Application
20117812
FIGURE 2. Typical Application Circuit
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TABLE 1. I2C/SPI Interface Controls (Note 18)
B7
B6
B5
B4
B3
B2
B1
B0
I2C
1
1
0
1
1
0
ID
0
Address
Mode
HP
Control
Register
Volume
Control
Register
(See
0
1
0
0
0
0
Gain Sel
V3
Mode
V2
Mute
V1
Shutdown
V0
Control
V4
Table 4 )
TABLE 2. Headphone Control
HP Sense Pin
I2C/SPI HP Control (B4)
Output Stage Configuration
0
0
0
1
0
1
BTL
SE
SE
SE
1 (VDD
1 (VDD
)
)
TABLE 3. Logic Controls
Logic Level
B3 (Gain Sel)
Internal Gain
External Gain
B2 (Mode)
B1 (Mute)
Mute Off (Play)
Mute On
B0 (Shutdown)
I2C/SPI Select
I2C mode
0
1
Fixed Volume, 0dB
Adjustable Volume
Device Shutdown
Device Active
SPI mode
Note 18: If system beep is detected on the Beep In pin, the system beep will be passed through the bridged amplifier regardless of the logic of the Mute and HP
Control bits (B1, B4) and HP Sense pin.
7
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Typical Performance Characteristics
THD+N vs Output Power/Channel
VDD = 5V, RL = 3Ω, AV-BTL = 2V/V
f = 1kHz, 80kHz BW
THD+N vs Frequency
VDD = 5V, RL = 3Ω, AV-BTL = 2V/V
POUT = 1.5W/Channel, 80kHz BW
201178B5
201178A4
THD+N vs Output Power/Channel
VDD = 5V, RL = 4Ω, AV-BTL = 2V/V
f = 1kHz, 80kHz BW
THD+N vs Frequency
VDD = 5V, RL = 4Ω, AV-BTL = 2V/V
POUT = 1.5W/Channel, 80kHz BW
201178B6
201178A5
THD+N vs Output Power/Channel
VDD = 5V, RL = 8Ω, AV-BTL = 2V/V
f = 1kHz, 80kHz BW
THD+N vs Frequency
VDD = 5V, RL = 8Ω, AV-BTL = 2V/V
POUT = 1W/Channel, 80kHz BW
201178B7
201178A6
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Typical Performance Characteristics (Continued)
THD+N vs Output Power/Channel
VDD = 5V, RL = 8Ω, AV-SE = 1V/V
f = 1kHz, COUT = 220µF, 80kHz BW
THD+N vs Frequency
VDD = 5V, RL = 8Ω, AV-SE = 1V/V
POUT = 100mW/Channel, 80kHz BW
201178B8
201178A7
THD+N vs Output Power/Channel
VDD = 5V, RL = 32Ω, AV-SE = 1V/V
f = 1kHz, COUT = 220µF, 80kHz BW
THD+N vs Frequency
VDD = 5V, RL = 32Ω, AV-SE = 1V/V
POUT = 40mW/Channel, 80kHz BW
201178B9
201178A9
THD+N vs Output Power/Channel
VDD = 3V, RL = 3Ω, AV-BTL = 2V/V
f = 1kHz, 80kHz BW
THD+N vs Frequency
VDD = 3V, RL = 3Ω, AV-SE = 2V/V
POUT = 500mW/Channel, 80kHz BW
201178B0
20117898
9
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Typical Performance Characteristics (Continued)
THD+N vs Output Power/Channel
VDD = 3V, RL = 4Ω, AV-BTL = 2V/V
f = 1kHz, 80kHz BW
THD+N vs Frequency
VDD = 3V, RL = 4Ω, AV-BTL = 2V/V
POUT = 450mW/Channel, 80kHz BW
201178B1
20117899
THD+N vs Output Power/Channel
VDD = 3V, RL = 8Ω, AV-BTL = 2V/V
f = 1kHz, 80kHz BW
THD+N vs Frequency
VDD = 3V, RL = 8Ω, AV-BTL = 2V/V
POUT = 250mW/Channel, 80kHz BW
201178B2
201178A0
THD+N vs Output Power/Channel
VDD = 3V, RL = 8Ω, AV-SE = 1V/V
f = 1kHz, COUT = 220µF, 80kHz BW
THD+N vs Frequency
VDD = 3V, RL = 8Ω, AV-SE = 1V/V
POUT = 50mW/Channel, 80kHz BW
201178B3
201178A1
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Typical Performance Characteristics (Continued)
THD+N vs Output Power/Channel
VDD = 3V, RL = 32Ω, AV-SE = 1V/V
f = 1kHz, COUT = 220µF, 80kHz BW
THD+N vs Frequency
VDD = 3V, RL = 32Ω, AV-SE = 1V/V
POUT = 20mW/Channel, 80kHz BW
201178B4
201178A3
THD+N vs Output Voltage
VDD = 5V, RLDOCK = 10kΩ, Dock Pins
f = 1kHz, CO = 1µF, 80kHz BW
THD+N vs Frequency
VDD = 5V, RLDOCK = 10kΩ, Dock Pins
VIN = 1Vp-p, CO = 1µF, 80kHz BW
201178C1
201178A8
THD+N vs Output Voltage
VDD = 3V, RLDOCK = 10kΩ, Dock Pins
f = 1kHz, CO = 1µF, 80kHz BW
THD+N vs Frequency
VDD = 3V, RLDOCK= 10kΩ, Dock Pins
VIN = 1Vp-p, CO = 1µF, 80kHz BW
201178C0
201178A2
11
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Typical Performance Characteristics (Continued)
PSRR vs Frequency
PSRR vs Frequency
VDD = 5V, VRIPPLE = 200mVp-p
Inputs Terminated, 80kHz BW
VDD = 3V, VRIPPLE = 200mVp-p
Inputs Terminated, 80kHz BW
20117887
20117869
Crosstalk vs Frequency
VDD = 5V, RL = 8Ω, AV-BTL = 2V/V
POUT = 1W, 80kHz BW
Crosstalk vs Frequency
VDD = 3V, RL = 8Ω, AV-BTL = 2V/V
POUT = 250mW, 80kHz BW
201178C5
201178C3
Crosstalk vs Frequency
VDD = 5V, RL = 32Ω, AV-SE = 1V/V
POUT = 40mW, 80kHz BW
Crosstalk vs Frequency
VDD = 3V, RL = 32Ω, AV-SE = 1V/V
POUT = 20mW, 80kHz BW
201178C6
201178C4
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Typical Performance Characteristics (Continued)
Headphone Sense Threshold vs Supply Voltage
RL = 8Ω, AV-SE = 1V/V
Output Level vs Frequency
External Gain with Bass Boost
COUT = 220µF, 80kHz BW
20117861
201178C2
Output Power/Channel vs Supply Voltage
Output Power/Channel vs Supply Voltage
RL = 3Ω, AV-BTL = 2V/V, 80kHz BW
RL = 4Ω, AV-BTL = 2V/V, 80kHz BW
20117850
20117855
Output Power/Channel vs Supply Voltage
Output Power/Channel vs Supply Voltage
RL = 8Ω, AV-BTL = 2V/V, 80kHz BW
RL = 8Ω, AV-SE = 1V/V, 80kHz BW
20117866
20117867
13
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Typical Performance Characteristics (Continued)
Output Power/Channel vs Supply Voltage
RL = 32Ω, AV-SE = 1V/V, 80kHz BW
Power Derating Curve (Note 19)
20117864
20117868
Power Dissipation vs Output Power/Channel
Power Dissipation vs Output Power/Channel
VDD = 5V, AV-BTL = 2V/V, THD+N ≤ 1%, 80kHz BW
VDD = 3V, AV-BTL = 2V/V, THD+N ≤ 1%, 80kHz BW
20117837
20117835
Power Dissipation vs Output Power/Channel
Power Dissipation vs Output Power/Channel
VDD = 5V, AV-SE = 1V/V, THD+N ≤ 1%, 80kHz BW
VDD = 3V, AV-SE = 1V/V, THD+N ≤ 1%, 80kHz BW
20117838
20117836
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Typical Performance Characteristics (Continued)
Supply Current vs Supply Voltage
Dropout Voltage
RL = 8Ω
20117888
20117853
Output Power/Channel vs Load Resistance
Output Power/Channel vs Load Resistance
20117862
20117807
Output Power/Channel vs Load Resistance
Output Power/Channel vs Load Resistance
20117806
20117808
Note 19: These curves show the thermal dissipation ability of the LM4936MH at different ambient temperatures given these conditions:
15
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Typical Performance Characteristics (Continued)
2
2
500LFPM + 2in : The part is soldered to a 2in , 1 oz. copper plane with 500 linear feet per minute of forced-air flow across it.
2
2
2in on bottom: The part is soldered to a 2in , 1oz. copper plane that is on the bottom side of the PC board through 21 8 mil vias.
2
2
2in : The part is soldered to a 2in , 1oz. copper plane.
2
2
1in : The part is soldered to a 1in , 1oz. copper plane.
Not Attached: The part is not soldered down and is not forced-air cooled.
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careful consideration of necessary thermal design. Failing to
optimize thermal design may compromise the LM4936’s high
power performance and activate unwanted, though neces-
sary, thermal shutdown protection.
Application Information
I2C COMPATIBLE INTERFACE
The LM4936 uses a serial bus, which conforms to the I2C
protocol, to control the chip’s functions with two wires: clock
(SCL) and data (SDA). The clock line is uni-directional. The
data line is bi-directional (open-collector). The maximum
clock frequency specified by the I2C standard is 400kHz. In
this discussion, the master is the controlling microcontroller
and the slave is the LM4936.
The I2C address for the LM4936 is determined using the
ID/CE pin. The LM4936’s two possible I2C chip addresses
are of the form 110110X10 (binary), where X1 = 0, if ID/CE is
logic low; and X1 = 1, if ID/CE is logic high. If the I2C
interface is used to address a number of chips in a system,
the LM4936’s chip address can be changed to avoid any
possible address conflicts.
The packages must have their exposed DAPs soldered to a
grounded copper pad on the PCB. The DAP’s PCB copper
pad is connected to a large grounded plane of continuous
unbroken copper. This plane forms a thermal mass heat sink
and radiation area. Place the heat sink area on either outside
plane in the case of a two-sided PCB, or on an inner layer of
a board with more than two layers. Connect the DAP copper
pad to the inner layer or backside copper heat sink area with
vias. The via diameter should be 0.012in–0.013in with a
1.27mm pitch. Ensure efficient thermal conductivity by
plating-through and solder-filling the vias.
Best thermal performance is achieved with the largest prac-
tical copper heat sink area. If the heatsink and amplifier
share the same PCB layer, a nominal 2.5in2 (min) area is
necessary for 5V operation with a 4Ω load. Heatsink areas
not placed on the same PCB layer as the LM4936 should be
5in2 (min) for the same supply voltage and load resistance.
The last two area recommendations apply for 25˚C ambient
temperature. Increase the area to compensate for ambient
temperatures above 25˚C. In systems using cooling fans, the
LM4936MH can take advantage of forced air cooling. With
an air flow rate of 450 linear-feet per minute and a 2.5in2
exposed copper or 5.0in2 inner layer copper plane heatsink,
the LM4936MH can continuously drive a 3Ω load to full
power. In all circumstances and conditions, the junction tem-
perature must be held below 150˚C to prevent activating the
LM4936’s thermal shutdown protection. The LM4936’s
power de-rating curve in the Typical Performance Charac-
teristics shows the maximum power dissipation versus tem-
perature. Example PCB layouts are shown in the Demon-
stration Board Layout section. Further detailed and
specific information concerning PCB layout, fabrication, and
mounting is available in National Semiconductor’s AN1187.
The bus format for the I2C interface is shown in Figure 5. The
bus format diagram is broken up into six major sections:
The "start" signal is generated by lowering the data signal
while the clock signal is high. The start signal will alert all
devices attached to the I2C bus to check the incoming ad-
dress against their own address.
The 8-bit chip address is sent next, most significant bit first.
The data is latched in on the rising edge of the clock. Each
address bit must be stable while the clock level is high.
After the last bit of the address bit is sent, the master
releases the data line high (through a pull-up resistor). Then
the master sends an acknowledge clock pulse. If the
LM4936 has received the address correctly, then it holds the
data line low during the clock pulse. If the data line is not
held low during the acknowledge clock pulse, then the mas-
ter should abort the rest of the data transfer to the LM4936.
The 8 bits of data are sent next, most significant bit first.
Each data bit should be valid while the clock level is stable
high.
After the data byte is sent, the master must check for another
acknowledge to see if the LM4936 received the data.
PCB LAYOUT AND SUPPLY REGULATION
CONSIDERATIONS FOR DRIVING 3Ω AND 4Ω LOADS
If the master has more data bytes to send to the LM4936,
then the master can repeat the previous two steps until all
data bytes have been sent.
Power dissipated by a load is a function of the voltage swing
across the load and the load’s impedance. As load imped-
ance decreases, load dissipation becomes increasingly de-
pendent on the interconnect (PCB trace and wire) resistance
between the amplifier output pins and the load’s connec-
tions. Residual trace resistance causes a voltage drop,
which results in power dissipated in the trace and not in the
load as desired. For example, 0.1Ω trace resistance reduces
the output power dissipated by a 4Ω load from 2.1W to 2.0W.
This problem of decreased load dissipation is exacerbated
as load impedance decreases. Therefore, to maintain the
highest load dissipation and widest output voltage swing,
PCB traces that connect the output pins to a load must be as
wide as possible.
The "stop" signal ends the transfer. To signal "stop", the data
signal goes high while the clock signal is high. The data line
should be held high when not in use.
I2C/SPI INTERFACE POWER SUPPLY PIN (I2C/SPI VDD
)
The LM4936’s I2C/SPI interface is powered up through the
I2C/SPI VDD pin. The LM4936’s I2C/SPI interface operates at
a voltage level set by the I2C/SPI VDD pin which can be set
independent to that of the main power supply pin VDD. This
is ideal whenever logic levels for the I2C/SPI interface are
dictated by a microcontroller or microprocessor that is oper-
ating at a lower supply voltage than the main battery of a
portable system.
Poor power supply regulation adversely affects maximum
output power. A poorly regulated supply’s output voltage
decreases with increasing load current. Reduced supply
voltage causes decreased headroom, output signal clipping,
and reduced output power. Even with tightly regulated sup-
plies, trace resistance creates the same effects as poor
supply regulation. Therefore, making the power supply
traces as wide as possible helps maintain full output voltage
swing.
EXPOSED-DAP PACKAGE PCB MOUNTING
CONSIDERATIONS
Exposed-DAP (die attach paddle) packages provide a low
thermal resistance between the die and the PCB to which
the part is mounted and soldered. This allows rapid heat
transfer from the die to the surrounding PCB copper traces,
ground plane and, finally, surrounding air. The result is a low
voltage audio power amplifier that produces 2.1W at ≤ 1%
THD with a 4Ω load. This high power is achieved through
17
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mode or bridge mode, respectively due to stereo operation.
Twice the maximum power dissipation point given by Equa-
tion (3) must not exceed the power dissipation given by
Equation (4):
Application Information (Continued)
BRIDGE CONFIGURATION EXPLANATION
As shown in Figure 2, the LM4936 output stage consists of
two pairs of operational amplifiers, forming a two-channel
(channel A and channel B) stereo amplifier. (Though the
following discusses channel A, it applies equally to channel
B.)
P
DMAX' = (TJMAX − TA)/θJA
(4)
The LM4936’s TJMAX = 150˚C. In the MH package soldered
to a DAP pad that expands to a copper area of 2in2 on a
PCB, the LM4936MH’s θJA is 41˚C/W. At any given ambient
temperature TA, use Equation (4) to find the maximum inter-
nal power dissipation supported by the IC packaging. Rear-
ranging Equation (4) and substituting PDMAX for PDMAX' re-
sults in Equation (5). This equation gives the maximum
ambient temperature that still allows maximum stereo power
dissipation without violating the LM4936’s maximum junction
temperature.
Figure 2 shows that the first amplifier’s negative (-) output
serves as the second amplifier’s input. This results in both
amplifiers producing signals identical in magnitude, but 180˚
out of phase. Taking advantage of this phase difference, a
load is placed between −OUTA and +OUTA and driven dif-
ferentially (commonly referred to as “bridge mode”). This
results in a differential gain of
AVD = 2 * (Rf/R )
(1)
i
Bridge mode amplifiers are different from single-ended am-
plifiers that drive loads connected between a single amplifi-
er’s output and ground. For a given supply voltage, bridge
mode has a distinct advantage over the single-ended con-
figuration: its differential output doubles the voltage
swing across the load. This produces four times the output
power when compared to a single-ended amplifier under the
same conditions. This increase in attainable output power
assumes that the amplifier is not current limited or that the
output signal is not clipped. To ensure minimum output sig-
nal clipping when choosing an amplifier’s closed-loop gain,
refer to the Audio Power Amplifier Design section.
TA = TJMAX – 2*PDMAX θJA
(5)
For a typical application with a 5V power supply and an 4Ω
load, the maximum ambient temperature that allows maxi-
mum stereo power dissipation without exceeding the maxi-
mum junction temperature is approximately 45˚C for the MH
package.
TJMAX = PDMAX θJA + TA
(6)
Equation (6) gives the maximum junction temperature
TJMAX. If the result violates the LM4936’s 150˚C TJMAX
reduce the maximum junction temperature by reducing the
power supply voltage or increasing the load resistance. Fur-
ther allowance should be made for increased ambient tem-
peratures.
Another advantage of the differential bridge output is no net
DC voltage across the load. This is accomplished by biasing
channel A’s and channel B’s outputs at half-supply. This
eliminates the coupling capacitor that single supply, single-
ended amplifiers require. Eliminating an output coupling ca-
pacitor in a single-ended configuration forces a single-supply
amplifier’s half-supply bias voltage across the load. This
increases internal IC power dissipation and may perma-
nently damage loads such as speakers.
,
The above examples assume that a device is a surface
mount part operating around the maximum power dissipation
point.
If the result of Equation (3) multiplied by 2 for stereo opera-
tion is greater than that of Equation (4), then decrease the
supply voltage, increase the load impedance, or reduce the
ambient temperature. If these measures are insufficient, a
heat sink can be added to reduce θJA. The heat sink can be
created using additional copper area around the package,
with connections to the ground pin(s), supply pin and ampli-
fier output pins. External, solder attached SMT heatsinks
such as the Thermalloy 7106D can also improve power
dissipation. When adding a heat sink, the θJA is the sum of
POWER DISSIPATION
Power dissipation is a major concern when designing a
successful single-ended or bridged amplifier. Equation (2)
states the maximum power dissipation point for a single-
ended amplifier operating at a given supply voltage and
driving a specified output load.
PDMAX = (VDD)2/(2π2RL) Single-Ended
(2)
θ
JC, θCS, and θSA. (θJC is the junction-to-case thermal im-
pedance, θCS is the case-to-sink thermal impedance, and
θSA is the sink-to-ambient thermal impedance.) Refer to the
Typical Performance Characteristics curves for power dis-
sipation information at lower output power levels.
However, a direct consequence of the increased power de-
livered to the load by a bridge amplifier is higher internal
power dissipation for the same conditions.
The LM4936 has two operational amplifiers per channel. The
maximum internal power dissipation per channel operating in
the bridge mode is four times that of a single-ended ampli-
fier. From Equation (3), assuming a 5V power supply and a
4Ω load, the maximum single channel power dissipation is
1.27W or 2.54W for stereo operation.
POWER SUPPLY BYPASSING
As with any power amplifier, proper supply bypassing is
critical for low noise performance and high power supply
rejection. Applications that employ a 5V regulator typically
use a 10µF in parallel with a 0.1µF filter capacitor to stabilize
the regulator’s output, reduce noise on the supply line, and
improve the supply’s transient response. However, their
presence does not eliminate the need for a local 1µF tanta-
lum bypass capacitance connected between the LM4936’s
supply pins and ground. Do not substitute a ceramic capaci-
tor for the tantalum. Doing so may cause oscillation. Keep
PDMAX = 4 * (VDD)2/(2π2RL) Bridge Mode
(3)
The LM4936’s power dissipation is twice that given by Equa-
tion (2) or Equation (3) when operating in the single-ended
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18
As an example when using a speaker with a low frequency
limit of 150Hz, the input coupling capacitor, using Equation
(7), is 0.053µF. The 0.33µF input coupling capacitor shown
in Figure 2 allows the LM4936 to drive a high efficiency, full
range speaker whose response extends below 30Hz.
Application Information (Continued)
the length of leads and traces that connect capacitors be-
tween the LM4936’s power supply pin and ground as short
as possible. Connecting a 1µF capacitor, CB, between the
BYPASS pin and ground improves the internal bias voltage’s
stability and the amplifier’s PSRR. The PSRR improvements
increase as the BYPASS pin capacitor value increases. Too
large a capacitor, however, increases turn-on time and can
compromise the amplifier’s click and pop performance. The
selection of bypass capacitor values, especially CB, depends
on desired PSRR requirements, click and pop performance
(as explained in the following section, Selecting Proper
External Components), system cost, and size constraints.
OPTIMIZING CLICK AND POP REDUCTION
PERFORMANCE
The LM4936 contains circuitry that minimizes turn-on and
shutdown transients or “clicks and pops”. For this discus-
sion, turn-on refers to either applying the power supply volt-
age or when the shutdown mode is deactivated. While the
power supply is ramping to its final value, the LM4936’s
internal amplifiers are configured as unity gain buffers. An
internal current source changes the voltage of the BYPASS
pin in a controlled, linear manner. Ideally, the input and
outputs track the voltage applied to the BYPASS pin. The
gain of the internal amplifiers remains unity until the voltage
on the BYPASS pin reaches 1/2 VDD . As soon as the voltage
on the BYPASS pin is stable, the device becomes fully
operational. Although the BYPASS pin current cannot be
modified, changing the size of CB alters the device’s turn-on
time and the magnitude of “clicks and pops”. Increasing the
value of CB reduces the magnitude of turn-on pops. How-
ever, this presents a tradeoff: as the size of CB increases, the
turn-on time increases. There is a linear relationship be-
tween the size of CB and the turn-on time. Below are some
typical turn-on times for various values of CB:
SELECTING PROPER EXTERNAL COMPONENTS
Optimizing the LM4936’s performance requires properly se-
lecting external components. Though the LM4936 operates
well when using external components with wide tolerances,
best performance is achieved by optimizing component val-
ues.
The LM4936 is unity-gain stable, giving a designer maximum
design flexibility. The gain should be set to no more than a
given application requires. This allows the amplifier to
achieve minimum THD+N and maximum signal-to-noise ra-
tio. These parameters are compromised as the closed-loop
gain increases. However, low gain circuits demand input
signals with greater voltage swings to achieve maximum
output power. Fortunately, many signal sources such as
audio CODECs have outputs of 1VRMS (2.83VP-P). Please
refer to the Audio Power Amplifier Design section for more
information on selecting the proper gain.
INPUT CAPACITOR VALUE SELECTION
Amplifying the lowest audio frequencies requires a high
value input coupling capacitor (0.33µF in Figure 2), but high
value capacitors can be expensive and may compromise
space efficiency in portable designs. In many cases, how-
ever, the speakers used in portable systems, whether inter-
nal or external, have little ability to reproduce signals below
150 Hz. Applications using speakers with this limited fre-
quency response reap little improvement by using a large
input capacitor.
Besides affecting system cost and size, the input coupling
capacitor has an effect on the LM4936’s click and pop per-
formance. When the supply voltage is first applied, a tran-
sient (pop) is created as the charge on the input capacitor
changes from zero to a quiescent state. The magnitude of
the pop is directly proportional to the input capacitor’s size.
Higher value capacitors need more time to reach a quiescent
DC voltage (VDD/2) when charged with a fixed current. The
amplifier’s output charges the input capacitor through the
feedback resistor, Rf. Thus, pops can be minimized by se-
lecting an input capacitor value that is no higher than nec-
essary to meet the desired −6dB frequency.
As shown in Figure 2, the input resistor (RIR, RIL = 20kΩ)
and the input capacitor (CIR, CIL = 0.33µF) produce a −6dB
high pass filter cutoff frequency that is found using Equation
(7).
(7)
19
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MICRO-POWER SHUTDOWN
Application Information (Continued)
Shutdown mode is activated when a digital 0 is loaded into
the Shutdown bit, B0. When active, the LM4936’s micro-
power shutdown feature turns off the amplifier’s bias circuitry
reducing supply current to a typical 0.7µA. Loading a digital
1 into B0 disables shutdown mode. When the LM4936 has
power applied, all register bits will have a default value of 0.
Because of this, the LM4936 will be in shutdown mode when
power is applied.
CB
TON
2ms
0.01µF
0.1µF
0.22µF
0.47µF
1.0µF
20ms
44ms
94ms
200ms
MODE FUNCTION
The LM4936’s Mode function has two states controlled by bit
B2. A digital 0 in bit B2 disables the volume control and
forces the LM4936 to function as a fixed gain amplifier. The
gain selection is determined by the GAIN SEL bit (B3) While
in the fixed gain mode the volume setting has no effect on
the output. When a digital 1 is loaded into B2 the output level
is determined by the volume control bits. See Table 4 for
volume settings.
DOCKING STATION INTERFACE
Applications such as notebook computers can take advan-
tage of a docking station to connect to external devices such
as monitors or audio/visual equipment that sends or receives
line level signals. The LM4936 has two outputs, Right Dock
and Left Dock, which connect to outputs of the internal input
amplifiers that drive the volume control inputs. These input
>
amplifiers can drive loads of 1kΩ (such as powered speak-
MUTE FUNCTION
ers) with a rail-to-rail signal. Since the output signal present
on the RIGHT DOCK and LEFT DOCK pins is biased to
VDD/2, coupling capacitors should be connected in series
with the load when using these outputs. Typical values for
the output coupling capacitors are 0.33µF to 1.0µF. If polar-
ized coupling capacitors are used, connect their "+" termi-
nals to the respective output pin, see Figure 2.
The LM4936 mutes the amplifier and DOCK outputs when a
digital 1 is loaded in bit B1. Even while muted, the LM4936
will amplify a system alert (beep) signal whose magnitude
satisfies the BEEP DETECT circuitry. Loading a digital 0 into
B1 returns the LM4936 to normal operation.
Since the DOCK outputs precede the internal volume con-
trol, the signal amplitude will be equal to the input signal’s
magnitude and cannot be adjusted. However, the input am-
plifier’s closed-loop gain can be adjusted using external
resistors. These 20kΩ (RDOCK1, RDOCK2) are shown in Fig-
ure 2 and they set each input amplifier’s gain to -1. Use
Equation 8 to determine the input and feedback resistor
values for a desired gain.
- AVR = RDOCK1/RIN1 and - AVL = RDOCK2/RIN2
(8)
Adjusting the input amplifier’s gain sets the minimum gain for
that channel. Although the single ended output of the Bridge
Output Amplifiers can be used to drive line level outputs, it is
recommended that the R & L Dock Outputs simpler signal
path be used for better performance.
BEEP DETECT FUNCTION
Computers and notebooks produce a system “beep“ signal
that drives a small speaker. The speaker’s auditory output
signifies that the system requires user attention or input. To
accommodate this system alert signal, the LM4936’s beep
input pin is a mono input that accepts the beep signal.
Internal level detection circuitry at this input monitors the
beep signal’s magnitude. When a signal level greater than
VDD/2 is detected on the BEEP IN pin, the bridge output
amplifiers are enabled. The beep signal is amplified and
applied to the load connected to the output amplifiers. A valid
beep signal will be applied to the load even when MUTE is
active. Use the input resistors connected between the BEEP
IN pin and the stereo input pins to accommodate different
beep signal amplitudes. These resistors (RBEEP) are shown
as 200kΩ values in Figure 2. Use higher value resistors to
reduce the gain applied to the beep signal. The resistors
must be used to pass the beep signal to the stereo inputs.
The BEEP IN pin is used only to detect the beep signal’s
magnitude: it does not pass the signal to the output amplifi-
ers. The LM4936’s shutdown mode must be deactivated
before a system alert signal is applied to BEEP IN pin.
20117805
FIGURE 3. Headphone Sensing Circuit
HP SENSE FUNCTION ( Headphone In )
Applying a voltage between the VIH threshold shown in the
graph found in the Typical Performance Characteristics and
VDD to the LM4936’s HP SENSE control pin or loading a
digital 1 into the HP Control bit (B4) will change the output
mode. The ’+’ outputs will change to be in phase with the ’-’
outputs instead of 180 degrees out of phase. This action
mutes a bridged-connected load since the differential volt-
age across the load is now close to 0V. The HP SENSE pin
over rides the HP Control bit. See Table 2 for more info.
Quiescent current consumption is reduced when the IC is in
this single-ended mode.
Figure 3 shows the implementation of the LM4936’s head-
phone control function. With no headphones connected to
the headphone jack, the R1-R2 voltage divider sets the
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20
R
BS, and a capacitor, CBS, in parallel, can be placed in series
Application Information (Continued)
with the feedback resistor of the bridged amplifier as seen in
Figure 2.
voltage applied to the HP SENSE pin at approximately
50mV. This 50mV puts the LM4936 into bridged mode op-
eration. The output coupling capacitor blocks the amplifier’s
half supply DC voltage, protecting the headphones.
At low, frequencies CBS is a virtual open circuit and at high
frequencies, its nearly zero ohm impedance shorts RBS. The
result is increased bridge-amplifier gain at low frequencies.
The combination of RBS and CBS form a -6dB corner fre-
quency at
The HP SENSE threshold is set so the output signal cannot
cause an output mode change. While the LM4936 operates
in bridge mode, the DC potential across the load is essen-
tially 0V. Connecting headphones to the headphone jack
disconnects the headphone jack contact pin from R2 and
allows R1 to pull the HP SENSE pin up to VDD through R4.
This enables the headphone function and mutes the bridged
speaker. The single-ended ’-’ outputs then drive the head-
phones, whose impedance is in parallel with resistors R2
and R3. These resistors have negligible effect on the
LM4936’s output drive capability since the typical impedance
of headphones is 32Ω.
fC = 1/(2πRBSCBS
)
(9)
The bridged-amplifier low frequency differential gain is:
AVD = 2(RF + RBS) / Ri
(10)
Figure 3 also shows the suggested headphone jack electri-
cal connections. The jack is designed to mate with a three-
wire plug. The plug’s tip and ring should each carry one of
the two stereo output signals, whereas the sleeve should
carry the ground return. A headphone jack with one control
pin contact is sufficient to drive the HP-IN pin when connect-
ing headphones.
Using the component values shown in Figure 2 (RF = 20kΩ,
RBS = 20kΩ, and CBS = 0.068µF), a first-order, -6dB pole is
created at 120Hz. Assuming R = 20kΩ, the low frequency
i
differential gain is 4V/V or 12dB. The input (Ci) and output
(COUT) capacitor values must be selected for a low fre-
quency response that covers the range of frequencies af-
fected by the desired bass-boost operation.
GAIN SELECT FUNCTION (Bass Boost)
VOLUME CONTROL
The LM4936 features selectable gain, using either internal or
external feedback resistors. The GAIN SEL bit (B3) controls
which gain is selected. Loading a digital 0 into the GAIN SEL
bit sets the gain to internal resulting in a gain of 6dB for BTL
mode or unity for singled-ended mode. Loading a digital 1
into the GAIN SEL bit sets the gain to be determined by the
external resistors, RI and RF.
The LM4936 has an internal stereo volume control whose
setting is a function of the digital values in the V4 – V0 bits.
See Table 4.
The LM4936 volume control consists of 31 steps that are
individually selected. The range of the steps, are from 0dB -
78dB. The gain levels are 1dB/step from 0dB to -6dB, 2dB/
step from -6dB to -36dB, 3dB/step from -36dB to -47dB,
4dB/step from -47dB to -51dB, 5dB/step from -51dB to
-66dB, and 12dB to the last step at -78dB.
In some cases a designer may want to improve the low
frequency response of the bridged amplifier or incorporate a
bass boost feature. This bass boost can be useful in systems
where speakers are housed in small enclosures. A resistor,
21
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Application Information (Continued)
TABLE 4. Volume Control Table
Serial Number
V4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
V3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
V2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
V1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
V0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Gain (dB)
–90
–90
–68
–63
–57
–51
–47
–45
–42
–39
–36
–34
–32
–30
–28
–26
–24
–22
–20
–18
–16
–14
–12
–10
–8
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
–6
–5
–4
–3
–2
–1
0
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22
Thus, a minimum overall gain of 2.83 allows the LM4936’s to
reach full output swing and maintain low noise and THD+N
performance.
Application Information (Continued)
AUDIO POWER AMPLIFIER DESIGN
Audio Amplifier Design: Driving 1W into an 8Ω Load
The last step in this design example is setting the amplifier’s
−6dB frequency bandwidth. To achieve the desired 0.25dB
pass band magnitude variation limit, the low frequency re-
sponse must extend to at least one-fifth the lower bandwidth
limit and the high frequency response must extend to at least
five times the upper bandwidth limit. The gain variation for
both response limits is 0.17dB, well within the 0.25dB
desired limit. The results are an
The following are the desired operational parameters:
Power Output:
Load Impedance:
Input Level:
1 WRMS
8Ω
1 VRMS
Input Impedance:
Bandwidth:
20 kΩ
100 Hz−20 kHz 0.25 dB
fL = 100Hz/5 = 20Hz
(14)
The design begins by specifying the minimum supply voltage
necessary to obtain the specified output power. One way to
find the minimum supply voltage is to use the Output Power
vs Supply Voltage curve in the Typical Performance Char-
acteristics section. Another way, using Equation (10), is to
calculate the peak output voltage necessary to achieve the
desired output power for a given load impedance. To ac-
count for the amplifier’s dropout voltage, two additional volt-
ages, based on the Dropout Voltage vs Supply Voltage in the
Typical Performance Characteristics curves, must be
added to the result obtained by Equation (10). The result is
Equation (11).
and an
fH = 20kHz x 5 = 100kHz
(15)
As mentioned in the Selecting Proper External Compo-
nents section, Ri (Right & Left) and Ci (Right & Left) create
a highpass filter that sets the amplifier’s lower bandpass
frequency limit. Find the input coupling capacitor’s value
using Equation (14).
Ci≥ 1/(2πRifL)
(16)
(11)
The result is
VDD ≥ (VOUTPEAK+ (VOD
+ VODBOT))
(12)
1/(2π*20kΩ*20Hz) = 0.397µF
(17)
TOP
The Output Power vs Supply Voltage graph for an 8Ω load
indicates a minimum supply voltage of 4.6V. This is easily
met by the commonly used 5V supply voltage. The additional
voltage creates the benefit of headroom, allowing the
LM4936 to produce peak output power in excess of 1W
without clipping or other audible distortion. The choice of
supply voltage must also not create a situation that violates
of maximum power dissipation as explained above in the
Power Dissipation section.
Use a 0.39µF capacitor, the closest standard value.
The product of the desired high frequency cutoff (100kHz in
this example) and the differential gain AVD, determines the
upper passband response limit. With AVD = 3 and fH
100kHz, the closed-loop gain bandwidth product (GBWP) is
300kHz. This is less than the LM4936’s 3.5MHz GBWP. With
this margin, the amplifier can be used in designs that require
more differential gain while avoiding performance,restricting
bandwidth limitations.
=
After satisfying the LM4936’s power dissipation require-
ments, the minimum differential gain needed to achieve 1W
dissipation in an 8Ω load is found using Equation (12).
(13)
23
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SPI TIMING DIAGRAM
Application Information (Continued)
20117823
FIGURE 4.
SPI OPERATIONAL REQUIREMENTS
6. ENABLE must be logic-low at least 50ns (tES ) before the
first rising edge of CLK, and ENABLE has to remain logic-
low at least 50ns (tEH ) after the eighth rising edge of CLK.
1. The maximum clock rate is 5MHz for the CLK pin.
2. CLK must remain logic-high for at least 100ns (tCH ) after
the rising edge of CLK, and CLK must remain logic-low for at
least 100ns (tCL ) after the falling edge of CLK.
7. If ENABLE remains logic-high for more than 50ns before
all 8 bits are transmitted then the data latch will be aborted.
8. If ENABLE is logic-low for more than 8 CLK pulses then
only the first 8 data bits will be latched and activated at rising
edge of eighth CLK.
3. Data bits are written to the DATA pin with the most
significant bit (MSB) first.
4. The serial data bits are sampled at the rising edge of CLK.
Any transition on DATA must occur at least 50ns (tDS) before
the rising edge of CLK. Also, any transition on DATA must
occur at least 50ns (tDH) after the rising edge of CLK and
stabilize before the next rising edge of CLK.
9. ENABLE must remain logic-high for at least 50ns (tEL ).
10. Coincidental rising or falling edges of CLK and ENABLE
are not allowed. If CLK is to be held logic-high after the data
transmission, the falling edge of CLK must occur at least
50ns (tCS ) before ENABLE transitions to logic-low for the
next set of data.
5. ENABLE should be logic-low only during serial data trans-
mission.
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24
I2C TIMING DIAGRAMS
Application Information (Continued)
20117895
FIGURE 5. I2C Bus Format
20117896
FIGURE 6. I2C Timing Diagram
25
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LM4936 MH Exposed-DAP Board Artwork (Notes 8, 9)
Composite View
Silk Screen
Internal Layer 1
Bottom Layer
20117844
20117847
20117845
20117843
Top Layer
20117848
Internal Layer 2
20117846
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26
LM4936 Board Bill of Materials
Designator
IN1, RIN2
RI1, RI2
Value
20kΩ
20kΩ
20kΩ
20kΩ
20kΩ
Tolerance
Part Description
Comment
R
1%
1%
1%
1%
1%
1/10W, 0805 Resistor
1/10W, 0805 Resistor
R
R
R
R
R
F1, RF2
1/10W, 0805 Resistor
DOCK1, RDOCK2
BS1, RBS2
BEEP1, RBEEP2
L1, RL2
1/10W, 0805 Resistor
1/10W, 0805 Resistor
200kΩ 1%
1.5kΩ 1%
1/10W, 0805 Resistor
1/10W, 0805 Resistor
RS, RPU
100kΩ 1%
0.33µF 10%
0.068µF 10%
1/10W, 0805 Resistor
C
C
IN1, CIN2, CIN3
BS1, CBS2
10V, Ceramic 1206 Capacitor
10V, Ceramic 1206 Capacitor
10V, Tantalum 1210 Capacitor
10V, Tantalum 1206 Capacitor
10V, Electrolytic 1210 Capacitor
10V, Tantalum 1210 Capacitor
16V, Electrolytic 2220 Capacitor
0.100 1x2 header, vertical mount
RCA Input Jack, PCB Mount
Banana-Jack Red, Analog VDD
Banana-Jack Blck, GND
CS1
10µF
0.1µF
1µF
10%
10%
10%
10%
C
C
S2, CS3, CS4
O1, CO2
CB
1µF
C
OUT1, COUT2
220µF 10%
J1
Docking Outputs
Mouser: 16PJ097
Mouser: 164–6219
Mouser: 164–6218
Mouser: 164–6219
Mouser: 164–6218
Mouser: 164–6219
Mouser: 164–6218
I2C/SPI Inputs
J2, J3, J4
J5A
J5B
J6A
J6B
J7A
J7B
J8
Banana-Jack Red, Right Out +
Banana-Jack Black, Right Out -
Banana-Jack Red, Left Out +
Banana-Jack Black, Left Out -
0.100” 2x3 header, vertical mount
3.5mm Stereo Headphone Jack
J9
Shogyo:
SJS–0354–5P
J10
J11
0.100” 1x3 header, vertical mount
Banana Jack — Red, Digital VDD
Digital Select
Mouser: 164–6219
27
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Physical Dimensions inches (millimeters) unless otherwise noted
Exposed-DAP TSSOP Package
Order Number LM4936MH
NS Package Number MXA28A for Exposed-DAP TSSOP
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
BANNED SUBSTANCE COMPLIANCE
National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products
Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain
no ‘‘Banned Substances’’ as defined in CSP-9-111S2.
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