LM5000SDX-6/NOPB [NSC]
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| 型号： | LM5000SDX-6/NOPB |
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National Semiconductor |
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February 2007
LM5000
High Voltage Switch Mode Regulator
General Description
Features
The LM5000 is a monolithic integrated circuit specifically de-
signed and optimized for flyback, boost or forward power
converter applications. The internal power switch is rated for
a maximum of 80V, with a current limit set to 2A. Protecting
the power switch are current limit and thermal shutdown cir-
cuits. The current mode control scheme provides excellent
rejection of line transients and cycle-by-cycle current limiting.
An external compensation pin and the built-in slope compen-
sation allow the user to optimize the frequency compensation.
Other distinctive features include softstart to reduce stresses
during start-up and an external shutdown pin for remote ON/
OFF control. There are two operating frequency ranges avail-
able. The LM5000-3 is pin selectable for either 300kHz (FS
Grounded) or 700kHz (FS Open). The LM5000-6 is pin se-
lectable for either 600kHz (FS Grounded) or 1.3MHz (FS
Open). The device is available in a low profile 16-lead TSSOP
package or a thermally enhanced 16-lead LLP package.
80V internal switch
■
■
■
Operating input voltage range of 3.1V to 40V
Pin selectable operating frequency
300kHz/700kHz (-3)
600kHz/1.3MHz (-6)
Adjustable output voltage
External compensation
Input undervoltage lockout
Softstart
■
■
■
■
■
■
■
■
Current limit
Over temperature protection
External shutdown
Small 16-Lead TSSOP or 16-Lead LLP package
Applications
Flyback Regulator
■
■
■
■
Forward Regulator
Boost Regulator
DSL Modems
Distributed Power Converters
■
Typical Application Circuit
20031901
LM5000 Flyback Converter
© 2007 National Semiconductor Corporation
200319
www.national.com
Connection Diagram
Top View
20031904
Ordering Information
Order Number
LM5000-3MTC
LM5000-3MTCX
LM5000SD-3
Package Type
TSSOP-16
TSSOP-16
LLP-16
NSC Package Drawing
MTC16
Supplied As
94 Units, Rail
MTC16
2500 Units, Tape and Reel
1000 Units, Rail
SDA16
LM5000SDX-3
LM5000SD-6
LLP-16
SDA16
4500 Units, Tape and Reel
1000 Units, Rail
LLP-16
SDA16
LM5000SDX-6
LLP-16
SDA16
4500 Units, Tape and Reel
Pin Descriptions
Pin
Name
Function
1
COMP
Compensation network connection. Connected to the output of the voltage error amplifier. The RC
compenstion network should be connected from this pin to AGND. An additional 100pF high
frequency capacitor to AGND is recommended.
2
3
FB
Output voltage feedback input.
SHDN
AGND
PGND
PGND
PGND
PGND
SW
Shutdown control input, Open = enable, Ground = disable.
Analog ground, connect directly to PGND.
4
5
Power ground.
6
Power ground.
7
Power ground.
8
Power ground.
9
Power switch input. Switch connected between SW pins and PGND pins
Power switch input. Switch connected between SW pins and PGND pins
Power switch input. Switch connected between SW pins and PGND pins
Bypass-Decouple Capacitor Connection, 0.1µF ceramic capacitor recommended.
Analog power input. A small RC filter is recommended, to suppress line glitches. Typical values of
10Ω and ≥ 0.1µF are recommended.
10
11
12
13
SW
SW
BYP
VIN
14
15
16
-
SS
FS
Softstart Input. External capacitor and internal current source sets the softstart time.
Switching frequency select input. Open = Fhigh. Ground = Flow
Factory test pin, connect to ground.
TEST
Exposed Pad
underside of LLP
package
Connect to system ground plane for reduced thermal resistance.
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2
Infrared (15 sec.)
ESD Susceptibility (Note 3)
Human Body Model
Machine Model
235°C
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
2kV
200V
Storage Temperature
−65°C to +150°C
VIN
-0.3V to 40V
-0.3V to 80V
-0.3V to 5V
-0.3V to 3V
-0.3V to 7V
150°C
SW Voltage
FB Voltage
Operating Conditions
Operating Junction
Temperature Range
(Note 7)
COMP Voltage
All Other Pins
Maximum Junction Temperature
Power Dissipation(Note 2)
Lead Temperature
−40°C to +125°C
3.1V to 40V
Supply Voltage (Note 7)
Internally Limited
216°C
Electrical Characteristics
Specifications in standard type face are for TJ = 25°C and those with boldface type apply over the full Operating Temperature
Range (TJ = −40°C to +125°C) Unless otherwise specified. VIN = 12V and IL = 0A, unless otherwise specified.
Min
(Note 4)
Typ
(Note 5)
Max
(Note 4)
Symbol
Parameter
Conditions
Units
mA
IQ
Quiescent Current
FB = 2V (Not Switching)
FS = 0V
2.0
2.1
2.5
2.5
FB = 2V (Not Switching)
FS = Open
mA
VSHDN = 0V
18
30
1.2840
2.7
µA
V
VFB
Feedback Voltage
1.2330
1.35
1.259
2.0
ICL
Switch Current Limit
A
Feedback Voltage Line
Regulation
0.001
0.04
%/V
%VFB/ΔVIN
3.1V ≤ VIN ≤ 40V
IB
FB Pin Bias Current (Note 6)
55
200
nA
V
BV
Output Switch Breakdown
Voltage
TJ = 25°C, ISW = 0.1µA
80
TJ = -40°C to + 125°C, ISW
0.5µA
=
76
VIN
gm
Input Voltage Range
3.1
40
V
µmho
V/V
%
Error Amp Transconductance
Error Amp Voltage Gain
150
410
280
90
750
ΔI = 5µA
AV
DMAX
Maximum Duty Cycle
LM5000-3
FS = 0V
FS = 0V
85
85
Maximum Duty Cycle
LM5000-6
90
%
TMIN
fS
Minimum On Time
165
300
700
600
1.3
ns
Switching Frequency
LM5000-3
FS = 0V
240
550
360
840
715
1.545
-2
kHz
FS = Open
FS = 0V
Switching Frequency
LM5000-6
485
FS = Open
VSHDN = 0V
VSW = 80V
ISW = 1A
1.055
MHz
µA
ISHDN
IL
Shutdown Pin Current
Switch Leakage Current
Switch RDSON
−1
0.008
160
0.6
5
µA
RDSON
ThSHDN
445
mΩ
V
SHDN Threshold
Output High
Output Low
0.9
0.6
0.3
V
UVLO
On Threshold
Off Threshold
VCOMP Trip
2.74
2.60
2.92
2. 77
0.67
11
3.10
2.96
V
V
OVP
ISS
V
Softstart Current
8
14
µA
3
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Min
(Note 4)
Typ
(Note 5)
Max
(Note 4)
Symbol
θJA
Parameter
Conditions
Units
Thermal Resistance
TSSOP, Package only
LLP, Package only
150
45
°C/W
Note 1: Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the device is intended
to be functional, but device parameter specifications may not be guaranteed. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 2: The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal resistance,
θ
JA, and the ambient temperature, TA. See the Electrical Characteristics table for the thermal resistance of various layouts. The maximum allowable power
dissipation at any ambient temperature is calculated using: PD (MAX) = (TJ(MAX) − TA)/θJA. Exceeding the maximum allowable power dissipation will cause
excessive die temperature, and the regulator will go into thermal shutdown.
Note 3: The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. The machine model is a 200pF capacitor discharged
directly into each pin.
Note 4: All limits guaranteed at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are 100%
production tested. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. All limits are used
to calculate Average Outgoing Quality Level (AOQL).
Note 5: Typical numbers are at 25°C and represent the most likely norm.
Note 6: Bias current flows into FB pin.
Note 7: Supply voltage, bias current product will result in aditional device power dissipation. This power may be significant. The thermal dissipation design should
take this into account.
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4
Typical Performance Characteristics
Iq (non-switching) vs VIN @ fSW = 300kHz
Iq (non-switching) vs VIN @ fSW = 700kHz
20031920
20031921
Iq (switching) vs VIN @ fSW = 300kHz
Iq (switching) vs VIN @ fSW = 700kHz
20031922
20031923
Vfb vs Temperature
RDS(ON) vs VIN @ ISW =1A
20031924
20031925
5
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Current Limit vs Temperature
Current Limit vs VIN
20031926
20031927
fSW vs. VIN @ FS = Low (-3)
fSW vs. VIN @ FS = OPEN (-3)
20031928
20031929
fSW vs. Temperature @ FS = Low (-3)
fSW vs. Temperature @ FS = OPEN (-3)
20031931
20031930
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6
fSW vs. Temperature @ FS = Low (-6)
fSW vs. Temperature @ FS = OPEN (-6)
20031974
20031975
Error Amp. Transconductance vs Temp.
BYP Pin Voltage vs VIN
20031932
20031933
7
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20031953
FIGURE 1. 300 kHz operation, 48V output
20031954
FIGURE 2. 700 kHz operation, 48V output
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8
Block Diagram
20031903
end of the period and current flows through the inductor once
again.
Boost Regulator Operation
The LM5000 utilizes a PWM control scheme to regulate the
output voltage over all load conditions. The operation can best
be understood referring to the block diagram and Figure 3. At
the start of each cycle, the oscillator sets the driver logic and
turns on the NMOS power device conducting current through
the inductor, cycle 1 of Figure 3 (a). During this cycle, the
voltage at the COMP pin controls the peak inductor current.
The COMP voltage will increase with larger loads and de-
crease with smaller. This voltage is compared with the sum-
mation of the SW volatge and the ramp compensation.The
ramp compensation is used in PWM architectures to eliminate
the sub-harmonic oscillations that occur during duty cycles
greater than 50%. Once the summation of the ramp compen-
sation and switch voltage equals the COMP voltage, the PWM
comparator resets the driver logic turning off the NMOS power
device. The inductor current then flows through the output
diode to the load and output capacitor, cycle 2 of Figure 3 (b).
The NMOS power device is then set by the oscillator at the
The LM5000 has dedicated protection circuitry running during
the normal operation to protect the IC. The Thermal Shutdown
circuitry turns off the NMOS power device when the die tem-
perature reaches excessive levels. The UVP comparator pro-
tects the NMOS power device during supply power startup
and shutdown to prevent operation at voltages less than the
minimum input voltage. The OVP comparator is used to pre-
vent the output voltage from rising at no loads allowing full
PWM operation over all load conditions. The LM5000 also
features a shutdown mode. An external capacitor sets the
softstart time by limiting the error amp output range, as the
capacitor charges up via an internal 10µA current source.
The LM5000 is available in two operating frequency ranges.
The LM5000-3 is pin selectable for either 300kHz (FS
Grounded) or 700kHz (FS Open). The LM5000-6 is pin se-
lectable for either 600kHz (FS Grounded) or 1.3MHz (FS
Open)
9
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Operation
20031902
FIGURE 3. Simplified Boost Converter Diagram
(a) First Cycle of Operation (b) Second Cycle Of Operation
CONTINUOUS CONDUCTION MODE
INTRODUCTION TO COMPENSATION
The LM5000 is a current-mode, PWM regulator. When used
as a boost regulator the input voltage is stepped up to a higher
output voltage. In continuous conduction mode (when the in-
ductor current never reaches zero at steady state), the boost
regulator operates in two cycles.
In the first cycle of operation, shown in Figure 3 (a), the tran-
sistor is closed and the diode is reverse biased. Energy is
collected in the inductor and the load current is supplied by
COUT
.
The second cycle is shown in Figure 3 (b). During this cycle,
the transistor is open and the diode is forward biased. The
energy stored in the inductor is transferred to the load and
output capacitor.
The ratio of these two cycles determines the output voltage.
The output voltage is defined approximately as:
where D is the duty cycle of the switch, D and D′ will be re-
quired for design calculations.
20031905
SETTING THE OUTPUT VOLTAGE
FIGURE 4. (a) Inductor current. (b) Diode current.
The output voltage is set using the feedback pin and a resistor
divider connected to the output as shown in Figure 1. The
feedback pin is always at 1.259V, so the ratio of the feedback
resistors sets the output voltage.
The LM5000 is a current mode PWM regulator. The signal
flow of this control scheme has two feedback loops, one that
senses switch current and one that senses output voltage.
To keep a current programmed control converter stable
above duty cycles of 50%, the inductor must meet certain cri-
teria. The inductor, along with input and output voltage, will
determine the slope of the current through the inductor (see
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10
Figure 4 (a)). If the slope of the inductor current is too great,
the circuit will be unstable above duty cycles of 50%.
loop system that must be stabilized to avoid positive feedback
and instability. A value for open-loop DC gain will be required,
from which you can calculate, or place, poles and zeros to
determine the crossover frequency and the phase margin. A
high phase margin (greater than 45°) is desired for the best
stability and transient response. For the purpose of stabilizing
the LM5000, choosing a crossover point well below where the
right half plane zero is located will ensure sufficient phase
margin. A discussion of the right half plane zero and checking
the crossover using the DC gain will follow.
The LM5000 provides a compensation pin (COMP) to cus-
tomize the voltage loop feedback. It is recommended that a
series combination of RC and CC be used for the compensa-
tion network, as shown in Figure 1. The series combination of
RC and CC introduces pole-zero pair according to the follow-
ing equations:
OUTPUT CAPACITOR SELECTION
The choice of output capacitors is somewhat more arbitrary.
It is recommended that low ESR (Equivalent Series Resis-
tance, denoted RESR) capacitors be used such as ceramic,
polymer electrolytic, or low ESR tantalum. Higher ESR ca-
pacitors may be used but will require more compensation
which will be explained later on in the section. The ESR is also
important because it determines the output voltage ripple ac-
cording to the approximate equation:
where RO is the output impedance of the error amplifier,
850kΩ. For most applications, performance can be optimized
by choosing values within the range 5kΩ ≤ RC ≤ 20kΩ and
680pF ≤ CC ≤ 4.7nF.
ΔVOUT ≊ 2ΔiLRESR (in Volts)
After choosing the output capacitor you can determine a pole-
zero pair introduced into the control loop by the following
equations:
COMPENSATION
This section will present a general design procedure to help
insure a stable and operational circuit. The designs in this
datasheet are optimized for particular requirements. If differ-
ent conversions are required, some of the components may
need to be changed to ensure stability. Below is a set of gen-
eral guidelines in designing a stable circuit for continuous
conduction operation (loads greater than 100mA), in most all
cases this will provide for stability during discontinuous oper-
ation as well. The power components and their effects will be
determined first, then the compensation components will be
chosen to produce stability.
Where RL is the minimum load resistance corresponding to
the maximum load current. The zero created by the ESR of
the output capacitor is generally very high frequency if the
ESR is small. If low ESR capacitors are used it can be ne-
glected. If higher ESR capacitors are used see the High
Output Capacitor ESR Compensation section.
INDUCTOR SELECTION
To ensure stability at duty cycles above 50%, the inductor
must have some minimum value determined by the minimum
input voltage and the maximum output voltage. This equation
is:
RIGHT HALF PLANE ZERO
A current mode control boost regulator has an inherent right
half plane zero (RHP zero). This zero has the effect of a zero
in the gain plot, causing an imposed +20dB/decade on the
rolloff, but has the effect of a pole in the phase, subtracting
another 90° in the phase plot. This can cause undesirable
effects if the control loop is influenced by this zero. To ensure
the RHP zero does not cause instability issues, the control
loop should be designed to have a bandwidth of ½ the fre-
quency of the RHP zero or less. This zero occurs at a fre-
quency of:
where fs is the switching frequency, D is the duty cycle, and
RDSON is the ON resistance of the internal switch. This equa-
tion is only good for duty cycles greater than 50% (D>0.5).
The inductor ripple current is important for a few reasons. One
reason is because the peak switch current will be the average
inductor current (input current) plus ΔiL. Care must be taken
to make sure that the switch will not reach its current limit
during normal operation. The inductor must also be sized ac-
cordingly. It should have a saturation current rating higher
than the peak inductor current expected. The output voltage
ripple is also affected by the total ripple current.
where ILOAD is the maximum load current.
SELECTING THE COMPENSATION COMPONENTS
The first step in selecting the compensation components RC
and CC is to set a dominant low frequency pole in the control
loop. Simply choose values for RC and CC within the ranges
given in the Introduction to Compensation section to set this
pole in the area of 10Hz to 100Hz. The frequency of the pole
created is determined by the equation:
DC GAIN AND OPEN-LOOP GAIN
Since the control stage of the converter forms a complete
feedback loop with the power components, it forms a closed-
11
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where RO is the output impedance of the error amplifier,
850kΩ. Since RC is generally much less than RO, it does not
have much effect on the above equation and can be neglected
until a value is chosen to set the zero fZC. fZC is created to
cancel out the pole created by the output capacitor, fP1. The
output capacitor pole will shift with different load currents as
shown by the equation, so setting the zero is not exact. De-
termine the range of fP1 over the expected loads and then set
the zero fZC to a point approximately in the middle. The fre-
quency of this zero is determined by:
mc ≊ 0.072fs (in A/s)
Now RC can be chosen with the selected value for CC. Check
to make sure that the pole fPC is still in the 10Hz to 100Hz
range, change each value slightly if needed to ensure both
component values are in the recommended range. After
checking the design at the end of this section, these values
can be changed a little more to optimize performance if de-
sired. This is best done in the lab on a bench, checking the
load step response with different values until the ringing and
overshoot on the output voltage at the edge of the load steps
is minimal. This should produce a stable, high performance
circuit. For improved transient response, higher values of
RC (within the range of values) should be chosen. This will
improve the overall bandwidth which makes the regulator re-
spond more quickly to transients. If more detail is required, or
the most optimal performance is desired, refer to a more in
depth discussion of compensating current mode DC/DC
switching regulators.
where RL is the minimum load resistance, VIN is the maximum
input voltage, and RDSON is the value chosen from the graph
"RDSON vs. VIN " in the Typical Performance Characteristics
section.
SWITCH VOLTAGE LIMITS
In a flyback regulator, the maximum steady-state voltage ap-
pearing at the switch, when it is off, is set by the transformer
turns ratio, N, the output voltage, VOUT, and the maximum in-
put voltage, VIN (Max):
VSW(OFF) = VIN (Max) + (VOUT +VF)/N
where VF is the forward biased voltage of the output diode,
and is typically 0.5V for Schottky diodes and 0.8V for ultra-
fast recovery diodes. In certain circuits, there exists a voltage
spike, VLL, superimposed on top of the steady-state voltage .
Usually, this voltage spike is caused by the transformer leak-
age inductance and/or the output rectifier recovery time. To
“clamp” the voltage at the switch from exceeding its maximum
value, a transient suppressor in series with a diode is inserted
across the transformer primary.
HIGH OUTPUT CAPACITOR ESR COMPENSATION
When using an output capacitor with a high ESR value, or just
to improve the overall phase margin of the control loop, an-
other pole may be introduced to cancel the zero created by
the ESR. This is accomplished by adding another capacitor,
CC2, directly from the compensation pin VC to ground, in par-
allel with the series combination of RC and CC. The pole
should be placed at the same frequency as fZ1, the ESR zero.
The equation for this pole follows:
If poor circuit layout techniques are used, negative voltage
transients may appear on the Switch pin. Applying a negative
voltage (with respect to the IC's ground) to any monolithic IC
pin causes erratic and unpredictable operation of that IC. This
holds true for the LM5000 IC as well. When used in a flyback
regulator, the voltage at the Switch pin can go negative when
the switch turns on. The “ringing” voltage at the switch pin is
caused by the output diode capacitance and the transformer
leakage inductance forming a resonant circuit at the sec-
ondary(ies). The resonant circuit generates the “ringing” volt-
age, which gets reflected back through the transformer to the
switch pin. There are two common methods to avoid this
problem. One is to add an RC snubber around the output rec-
tifier(s). The values of the resistor and the capacitor must be
chosen so that the voltage at the Switch pin does not drop
below −0.4V. The resistor may range in value between 10Ω
and 1 kΩ, and the capacitor will vary from 0.001 μF to
0.1 μF. Adding a snubber will (slightly) reduce the efficiency
of the overall circuit.
To ensure this equation is valid, and that CC2 can be used
without negatively impacting the effects of RC and CC, fPC2
must be greater than 10fPC
.
CHECKING THE DESIGN
The final step is to check the design. This is to ensure a band-
width of ½ or less of the frequency of the RHP zero. This is
done by calculating the open-loop DC gain, ADC. After this
value is known, you can calculate the crossover visually by
placing a −20dB/decade slope at each pole, and a +20dB/
decade slope for each zero. The point at which the gain plot
crosses unity gain, or 0dB, is the crossover frequency. If the
crossover frequency is at less than ½ the RHP zero, the phase
margin should be high enough for stability. The phase margin
can also be improved some by adding CC2 as discussed ear-
lier in the section. The equation for ADC is given below with
additional equations required for the calculation:
The other method to reduce or eliminate the “ringing” is to
insert a Schottky diode clamp between the SW pin and the
PGND pin. The reverse voltage rating of the diode must be
greater than the switch off voltage.
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12
OUTPUT VOLTAGE LIMITATIONS
Flyback Regulator Operation
The LM5000 is ideally suited for use in the flyback regulator
topology. The flyback regulator can produce a single output
voltage, or multiple output voltages.
The maximum output voltage of a boost regulator is the max-
imum switch voltage minus a diode drop. In a flyback regula-
tor, the maximum output voltage is determined by the turns
ratio, N, and the duty cycle, D, by the equation:
The operation of a flyback regulator is as follows: When the
switch is on, current flows through the primary winding of the
transformer, T1, storing energy in the magnetic field of the
transformer. Note that the primary and secondary windings
are out of phase, so no current flows through the secondary
when current flows through the primary. When the switch
turns off, the magnetic field collapses, reversing the voltage
polarity of the primary and secondary windings. Now rectifier
D5 is forward biased and current flows through it, releasing
the energy stored in the transformer. This produces voltage
at the output.
VOUT ≈ N × VIN × D/(1 − D)
The duty cycle of a flyback regulator is determined by the fol-
lowing equation:
Theoretically, the maximum output voltage can be as large as
desired—just keep increasing the turns ratio of the trans-
former. However, there exists some physical limitations that
prevent the turns ratio, and thus the output voltage, from in-
creasing to infinity. The physical limitations are capacitances
and inductances in the LM5000 switch, the output diode(s),
and the transformer—such as reverse recovery time of the
output diode (mentioned above).
The output voltage is controlled by modulating the peak
switch current. This is done by feeding back a portion of the
output voltage to the error amp, which amplifies the difference
between the feedback voltage and a 1.259V reference. The
error amp output voltage is compared to a ramp voltage pro-
portional to the switch current (i.e., inductor current during the
switch on time). The comparator terminates the switch on time
when the two voltages are equal, thereby controlling the peak
switch current to maintain a constant output voltage.
INPUT LINE CONDITIONING
A small, low-pass RC filter should be used at the input pin of
the LM5000 if the input voltage has an unusually large amount
of transient noise. Additionally, the RC filter can reduce the
dissipation within the device when the input voltage is high.
20031972
FIGURE 5. LM5000 Flyback Converter
13
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ITEM
PART NUMBER
C4532X7R2A105MT
DESCRIPTION
Capacitor, CER, TDK
VALUE
1µ, 100V
C
C
C
C
C
C
C
C
C
C
C
1
2
3
C4532X7R2A105MT
C1206C224K5RAC
C1206C104K5RAC
C1206C104K5RAC
C1206C101K1GAC
C1206C104K5RAC
C4532X7S0G686M
C4532X7S0G686M
C1206C221K1GAC
C1206C102K5RAC
Capacitor, CER, TDK
1µ, 100V
Capacitor, CER, KEMET
Capacitor, CER, KEMET
Capacitor, CER, KEMET
Capacitor, CER, KEMET
Capacitor, CER, KEMET
Capacitor, CER, TDK
0.22µ, 50V
0.1µ, 50V
0.1µ, 50V
100p, 100V
0.1µ, 50V
68µ, 4V
4
5
6
7
8
9
Capacitor, CER, TDK
68µ, 4V
10
11
Capacitor, CER, KEMET
Capacitor, CER, KEMET
220p, 100V
1000p, 500V
D
D
D
D
D
1
2
3
4
5
BZX84C10-NSA
CMZ5930B-NSA
CMPD914-NSA
CMPD914-NSA
CMSH3-40L-NSA
Central, 10V Zener, SOT-23
Central, 16V Zener, SMA
Central, Switching, SOT-23
Central, Switching, SOT-23
Central, Schottky, SMC
T
1
A0009-A
Coilcraft, Transformer
R
R
R
R
R
R
R
1
2
3
4
5
6
7
CRCW12064992F
CRCW12061001F
CRCW12061002F
CRCW12066191F
CRCW120610R0F
CRCW12062003F
CRCW12061002F
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
49.9K
1K
10K
6.19K
10
200K
10K
Q
U
1
1
CXT5551-NSA
LM5000-3
Central, NPN, 180V
Regulator, National
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14
Physical Dimensions inches (millimeters) unless otherwise noted
TSSOP-16 Pin Package (MTC)
For Ordering, Refer to Ordering Information Table
NS Package Number MTC16
15
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LLP-16 Pin Package (SDA)
For Ordering, Refer to Ordering Information Table
NS Package Number SDA16A
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16
Notes
17
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Notes
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