LM5105SD [NSC]
100V Half Bridge Gate Driver with Programmable Dead-time; 100V半桥栅极驱动器，具有可编程死区时间
| 型号： | LM5105SD |
| 厂家： | 
National Semiconductor |
| 描述： | 100V Half Bridge Gate Driver with Programmable Dead-time |
| 文件： | 总12页 (文件大小：742K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 2005
LM5105
100V Half Bridge Gate Driver with Programmable
Dead-time
n 1.8A peak gate drive current
n Bootstrap supply voltage range up to 118V DC
n Integrated bootstrap diode
n Single TTL compatible Input
n Programmable turn-on delays (Dead-time)
n Enable Input pin
n Fast turn-off propagation delays (26ns typical)
n Drives 1000pF with 15ns rise and fall time
n Supply rail under-voltage lockout
n Low power consumption
General Description
The LM5105 is a high voltage gate driver designed to drive
both the high side and low side N –Channel MOSFETs in a
synchronous buck or half bridge configuration. The floating
high-side driver is capable of working with rail voltages up to
100V. The single control input is compatible with TTL signal
levels and a single external resistor programs the switching
transition dead-time through tightly matched turn-on delay
circuits. A high voltage diode is provided to charge the high
side gate drive bootstrap capacitor. The robust level shift
technology operates at high speed while consuming low
power and provides clean output transitions. Under-voltage
lockout disables the gate driver when either the low side or
the bootstrapped high side supply voltage is below the op-
erating threshold. The LM5105 is offered in the thermally
enhanced 10-pin LLP plastic package.
Typical Applications
n Solid State motor drives
n Half and Full Bridge power converters
n Two switch forward power converters
Features
Package
n Drives both a high side and low side N-channel
n LLP-10 (4 mm x 4 mm)
MOSFET
Simplified Block Diagram
20137502
FIGURE 1.
© 2005 National Semiconductor Corporation
DS201375
www.national.com
Connection Diagram
20137501
10-Lead LLP
See NS Number SDC10A
Ordering Information
Ordering Number
Package Type
NSC Package Drawing
Supplied As
LM5105SD
LLP-10
LLP-10
SDC10A
SDC10A
1000 shipped as Tape & Reel
4500 shipped as Tape & Reel
LM5105SDX
Pin Descriptions
Pin
Name
Description
Application Information
1
VDD
Positive gate drive supply
Decouple VDD to VSS using a low ESR/ESL capacitor, placed as
close to the IC as possible.
2
HB
High side gate driver
bootstrap rail
Connect the positive terminal of bootstrap capacitor to the HB pin
and connect negative terminal to HS. The Bootstrap capacitor
should be placed as close to IC as possible.
3
4
HO
HS
High side gate driver
output
Connect to the gate of high side N-MOS device through a short,
low inductance path.
High side MOSFET source
connection
Connect to the negative terminal of the bootststrap capacitor and to
the source of the high side N-MOS device.
5
6
NC
Not Connected
RDT
Deadtime programming pin
A resistor from RDT to VSS programs the turn-on delay of both the
high and low side MOSFETs. The resistor should be placed close
to the IC to minimize noise coupling from adjacent PC board traces.
TTL compatible threshold with hysteresis. LO and HO are held in
the low state when EN is low.
7
8
EN
IN
Logic input for driver
Disable/Enable
Logic input for gate driver
TTL compatible threshold with hysteresis. The high side MOSFET
is turned on and the low side MOSFET turned off when IN is high.
All signals are referenced to this ground.
9
VSS
LO
Ground return
10
Low side gate driver output
Connect to the gate of the low side N-MOS device with a short, low
inductance path.
www.national.com
2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature Range
ESD Rating HBM
(Note 2)
–55˚C to +150˚C
2 kV
VDD to VSS
–0.3V to +18V
–0.3V to +18V
–0.3V to VDD + 0.3V
–0.3V to VDD + 0.3V
HS – 0.3V to HB + 0.3V
−5V to +100V
Recommended Operating
Conditions
HB to HS
IN and EN to VSS
LO to VSS
VDD
+8V to +14V
HS (Note 6)
–1V to 100V
HO to VSS
HB
HS + 8V to HS + 14V
HS to VSS (Note 6)
HB to VSS
<
HS Slew Rate
Junction Temperature
50V/ns
118V
–40˚C to +125˚C
RDT to VSS
–0.3V to 5V
Junction Temperature
+150˚C
Electrical Characteristics Specifications in standard typeface are for TJ = +25˚C, and those in boldface
type apply over the full operating junction temperature range. Unless otherwise specified, VDD = HB = 12V, VSS = HS =
0V, EN = 5V. No load on LO or HO. RDT= 100kΩ(Note 4).
Symbol
Parameter
Conditions
Min
Typ
Max
Units
SUPPLY CURRENTS
IDD
VDD Quiescent Current
VDD Operating Current
IN = EN = 0V
0.34
1.65
0.06
1.3
0.6
3
mA
mA
mA
mA
µA
IDDO
IHB
f = 500 kHz
Total HB Quiescent Current
Total HB Operating Current
HB to VSS Current, Quiescent
HB to VSS Current, Operating
IN = EN = 0V
f = 500 kHz
0.2
3
IHBO
IHBS
IHBSO
HS = HB = 100V
f = 500 kHz
0.05
0.1
10
mA
INPUT IN and EN
VIL
Low Level Input Voltage Threshold
0.8
1.8
1.8
200
V
V
VIH
Rpd
High Level Input Voltage Threshold
2.2
Input Pulldown Resistance Pin IN and EN
100
500
kΩ
DEAD-TIME CONTROLS
VRDT
IRDT
Nominal Voltage at RDT
RDT Pin Current Limit
2.7
3
3.3
V
RDT = 0V
0.75
1.5
2.25
mA
UNDER VOLTAGE PROTECTION
VDDR
VDDH
VHBR
VHBH
VDD Rising Threshold
VDD Threshold Hysteresis
HB Rising Threshold
6.0
5.7
6.9
0.5
6.6
0.4
7.4
7.1
V
V
V
V
HB Threshold Hysteresis
BOOT STRAP DIODE
VDL
VDH
RD
Low-Current Forward Voltage
IVDD-HB = 100 µA
IVDD-HB = 100 mA
IVDD-HB = 100 mA
0.6
0.85
0.8
0.9
1.1
1.5
V
V
Ω
High-Current Forward Voltage
Dynamic Resistance
LO GATE DRIVER
VOLL
VOHL
Low-Level Output Voltage
ILO = 100 mA
ILO = –100 mA,
VOHL = VDD – VLO
LO = 0V
0.25
0.35
0.4
V
V
High-Level Output Voltage
0.55
IOHL
IOLL
Peak Pullup Current
1.8
1.6
A
A
Peak Pulldown Current
LO = 12V
HO GATE DRIVER
VOLH
VOHH
Low-Level Output Voltage
IHO = 100 mA
IHO = –100 mA,
VOHH = HB – HO
HO = 0V
0.25
0.35
1.8
0.4
V
V
A
High-Level Output Voltage
0.55
IOHH
Peak Pullup Current
3
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Electrical Characteristics Specifications in standard typeface are for TJ = +25˚C, and those in boldface type
apply over the full operating junction temperature range. Unless otherwise specified, VDD = HB = 12V, VSS = HS = 0V, EN
= 5V. No load on LO or HO. RDT= 100kΩ(Note 4). (Continued)
Symbol
IOLH
THERMAL RESISTANCE
θJA Junction to Ambient
Parameter
Conditions
HO = 12V
Min
Typ
Max
Units
Peak Pulldown Current
1.6
A
(Note 3), (Note 5)
40
˚C/W
Switching Characteristics Specifications in standard typeface are for TJ = +25˚C, and those in boldface
type apply over the full operating junction temperature range. Unless otherwise specified, VDD = HB = 12V, VSS = HS =
0V, No Load on LO or HO (Note 4).
Symbol
tLPHL
Parameter
Conditions
Min
Typ
26
Max
56
Units
ns
Lower Turn-Off Propagation Delay
Upper Turn-Off Propagation Delay
Lower Turn-On Propagation Delay
Upper Turn-On Propagation Delay
Lower Turn-On Propagation Delay
Upper Turn-On Propagation Delay
Enable and Shutdown propagation delay
Dead-time LO OFF to HO ON & HO OFF
to LO ON
tHPHL
tLPLH
tHPLH
tLPLH
tHPLH
26
56
ns
RDT = 100k
485
485
75
595
595
105
105
28
705
705
150
150
ns
RDT = 100k
RDT = 10k
RDT = 10k
ns
ns
75
ns
t
en, tsd
ns
DT1, DT2
RDT = 100k
RDT = 10k
570
80
µs
MDT
tR, tF
tBS
Dead-time matching
RDT = 100k
CL = 1000pF
50
Either Output Rise/Fall Time
15
Bootstrap Diode Turn-On or Turn-Off Time IF = 20 mA, IR = 200 mA
50
ns
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of
the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the
Electrical Characteristics tables.
Note 2: The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. Pin 2, Pin 3 and Pin 4 are rated at 500V.
Note 3: 4 layer board with Cu finished thickness 1.5/1.0/1.0/1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50 x 50mm ground and power
planes embedded in PCB. See Application Note AN-1187.
Note 4: Min and Max limits are 100% production tested at 25˚C. Limits over the operating temperature range are guaranteed through correlation using Statistical
Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL).
Note 5: The θ is not a constant for the package and depends on the printed circuit board design and the operating conditions.
JA
Note 6: In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally not exceed -1V.
However in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage transiently.
If negative transients occur on HS, the HS voltage must never be more negative than V - 15V. For example, if V = 10V, the negative transients at HS must not
DD
DD
exceed -5V.
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4
Typical Performance Characteristics
VDD Operating Current vs Frequency
Operating Current vs Temperature
20137511
20137510
Quiescent Current vs Supply Voltage
Quiescent Current vs Temperature
20137513
20137512
HB Operating Current vs Frequency
HO & LO Peak Output Current vs Output Voltage
20137517
20137516
5
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Typical Performance Characteristics (Continued)
Diode Forward Voltage
Undervoltage Hysteresis vs Temperature
20137515
20137518
Undervoltage Rising Threshold vs Temperature
LO & HO - High Level Output Voltage vs Temperature
20137519
20137520
LO & HO - Low Level Output Voltage vs Temperature
Input Threshold vs Temperature
20137521
20137522
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6
Typical Performance Characteristics (Continued)
Dead-Time vs RT Resistor Value
Dead-Time vs Temperature (RT = 10k)
20137514
20137526
Dead-Time vs Temperature (RT = 100k)
20137527
7
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Timing Diagrams
20137503
LM5105 Input - Output Waveforms
FIGURE 2.
20137504
LM5105 Switching Time Definitions: tLPLH, tLPHL, tHPLH, tHPHL
FIGURE 3.
Operational Notes
The LM5105 is a single PWM input Gate Driver with Enable
that offers a programmable deadtime. The deadtime is set
with a resistor at the RDT pin and can be adjusted from
100ns to 600ns. The wide deadtime programming range
provides the flexibility to optimize drive signal timing for a
wide range of MOSFETS and applications.
The RDT pin is biased at 3V and current limited to 1 mA
maximum programming current. The time delay generator
will accommodate resistor values from 5k to 100k with a
deadtime time that is proportional to the RDT resistance.
Grounding the RDT pin programs the LM5105 to drive both
outputs with minimum deadtime.
20137530
LM5105 Enable: tsd
FIGURE 4.
STARTUP AND UVLO
Both top and bottom drivers include under-voltage lockout
(UVLO) protection circuitry which monitors the supply volt-
age (VDD) and bootstrap capacitor voltage (HB – HS) inde-
pendently. The UVLO circuit inhibits each driver until suffi-
cient supply voltage is available to turn-on the external
MOSFETs, and the UVLO hysteresis prevents chattering
during supply voltage transitions. When the supply voltage is
applied to the VDD pin of LM5105, the top and bottom gates
are held low until VDD exceeds the UVLO threshold, typically
about 6.9V. Any UVLO condition on the bootstrap capacitor
will disable only the high side output (HO).
20137531
LM5105 Dead-time: DT
FIGURE 5.
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8
POWER DISSIPATION CONSIDERATIONS
Operational Notes (Continued)
LAYOUT CONSIDERATIONS
The total IC power dissipation is the sum of the gate driver
losses and the bootstrap diode losses. The gate driver
losses are related to the switching frequency (f), output load
capacitance on LO and HO (CL), and supply voltage (VDD
and can be roughly calculated as:
The optimum performance of high and low side gate drivers
cannot be achieved without taking due considerations during
circuit board layout. Following points are emphasized.
)
2
1. A low ESR/ESL capacitor must be connected close to
the IC, and between VDD and VSS pins and between HB
and HS pins to support high peak currents being drawn
from VDD during turn-on of the external MOSFET.
PDGATES = 2 • f • CL • VDD
There are some additional losses in the gate drivers due to
the internal CMOS stages used to buffer the LO and HO
outputs. The following plot shows the measured gate driver
power dissipation versus frequency and load capacitance. At
higher frequencies and load capacitance values, the power
dissipation is dominated by the power losses driving the
output loads and agrees well with the above equation. This
plot can be used to approximate the power losses due to the
gate drivers.
2. To prevent large voltage transients at the drain of the top
MOSFET, a low ESR electrolytic capacitor must be con-
nected between MOSFET drain and ground (VSS).
3. In order to avoid large negative transients on the switch
node (HS) pin, the parasitic inductances in the source of
top MOSFET and in the drain of the bottom MOSFET
(synchronous rectifier) must be minimized.
Gate Driver Power Dissipation (LO + HO)
VCC = 12V, Neglecting Diode Losses
4. Grounding considerations:
a) The first priority in designing grounding connections is
to confine the high peak currents from charging and
discharging the MOSFET gate in a minimal physical
area. This will decrease the loop inductance and mini-
mize noise issues on the gate terminal of the MOSFET.
The MOSFETs should be placed as close as possible to
the gate driver.
b) The second high current path includes the bootstrap
capacitor, the bootstrap diode, the local ground refer-
enced bypass capacitor and low side MOSFET body
diode. The bootstrap capacitor is recharged on the
cycle-by-cycle basis through the bootstrap diode from
the ground referenced VDD bypass capacitor. The re-
charging occurs in a short time interval and involves high
peak current. Minimizing this loop length and area on the
circuit board is important to ensure reliable operation.
5. The resistor on the RDT pin must be placed very close to
the IC and seperated from high current paths to avoid
noise coupling to the time delay generator which could
disrupt timer operation.
20137505
The bootstrap diode power loss is the sum of the forward
bias power loss that occurs while charging the bootstrap
capacitor and the reverse bias power loss that occurs during
reverse recovery. Since each of these events happens once
per cycle, the diode power loss is proportional to frequency.
Larger capacitive loads require more current to recharge the
bootstrap capacitor resulting in more losses. Higher input
voltages (VIN) to the half bridge result in higher reverse
recovery losses. The following plot was generated based on
calculations and lab measurements of the diode recovery
time and current under several operating conditions. This
can be useful for approximating the diode power dissipation.
9
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The total IC power dissipation can be estimated from the
above plots by summing the gate drive losses with the
bootstrap diode losses for the intended application. Because
the diode losses can be significant, an external diode placed
in parallel with the internal bootstrap diode (refer to Figure 6)
and can be helpful in removing power from the IC. For this to
be effective, the external diode must be placed close to the
IC to minimize series inductance and have a significantly
lower forward voltage drop than the internal diode.
Operational Notes (Continued)
Diode Power Dissipation VIN = 80V
HS Transient Voltages Below Ground
The HS node will always be clamped by the body diode of
the lower external FET. In some situations, board resis-
tances and inductances can cause the HS node to tran-
siently swing several volts below ground. The HS node can
swing below ground provided:
1. HS must always be at a lower potential than HO. Pulling
HO more than -0.3V below HS can activate parasitic
transistors resulting in excessive current to flow from the
HB supply possibly resulting in damage to the IC. The
same relationship is true with LO and VSS. If necessary,
a Schottky diode can be placed externally between HO
and HS or LO and GND to protect the IC from this type
of transient. The diode must be placed as close to the IC
pins as possible in order to be effective.
20137506
Diode Power Dissipation VIN = 40V
2. HB to HS operating voltage should be 15V or less .
Hence, if the HS pin transient voltage is -5V, VDD should
be ideally limited to 10V to keep HB to HS below 15V.
3. A low ESR bypass capacitor between HB to HS as well
as VCC to VSS is essential for proper operation. The
capacitor should be located at the leads of the IC to
minimize series inductance. The peak currents from LO
and HO can be quite large. Any series inductances with
the bypass capacitor will cause voltage ringing at the
leads of the IC which must be avoided for reliable op-
eration.
20137507
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10
Operational Notes (Continued)
LM5105 Driving MOSFETs Connected in Half-Bridge Configuration
20137508
FIGURE 6.
11
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Physical Dimensions inches (millimeters) unless otherwise noted
Notes: Unless otherwise specified
1. Standard lead finish to be 200 microinches/5.00 micrometers minimum tin/lead (solder) on copper.
2. Pin 1 identification to have half of full circle option.
3. No JEDEC registration as of Feb. 2000.
LLP-10 Outline Drawing
NS Package Number SDC10A
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
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