LMK03002ISQX_技术文档

August 2007

LMK03002/LMK03002C

Precision Clock Conditioner with Integrated VCO

General Description

Features

The LMK03002/LMK03002C precision clock conditioners

combine the functions of jitter cleaning/reconditioning, multi-

plication, and distribution of a reference clock. The devices

integrate a Voltage Controlled Oscillator (VCO), a high per-

formance Integer-N Phase Locked Loop (PLL), a partially

integrated loop filter, and four LVPECL clock output distribu-

tion blocks.

Integrated VCO with very low phase noise floor

■

Integrated Integer-N PLL with outstanding normalized

phase noise contribution of -224 dBc/Hz

Clock generator performance (10 Hz - 20 MHz)

■

LMK03002C: 200 fs RMS jitter

—

Jitter cleaner performance grade (12 kHz to 20 MHz)

The VCO output is optionally accessible on the Fout port. In-

ternally, the VCO output goes through a VCO Divider to feed

the various clock distribution blocks.

LMK03002: 800 fs RMS jitter

LMK03002C: 400 fs RMS jitter

—

VCO frequency: 1566 to 1724 MHz

Clock output frequency range of 1 to 862 MHz

4 LVPECL clock outputs

■

Each clock distribution block includes a programmable di-

vider, a phase synchronization circuit, a programmable delay,

a clock output mux, and an LVPECL output buffer. This allows

multiple integer-related and phase-adjusted copies of the ref-

erence to be distributed to four system components.

Partially integrated loop filter

Dedicated divider and delay blocks on each clock output

Pin compatible family of clocking devices

3.15 to 3.45 V operation

The clock conditioners come in a 48-pin LLP package and are

footprint compatible with other clocking devices in the same

family.

Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)

Target Applications

Data Converter Clocking

■

Networking, SONET/SDH, DSLAM

Wireless Infrastructure

Medical

Test and Measurement

Military / Aerospace

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

300206

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Functional Block Diagram

30020601

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2

Connection Diagram

48-Pin LLP Package

30020602

Pin Descriptions

Pin #

1, 25

2

Pin Name

I/O

-

Description

GND

Fout

Ground

O

Internal VCO Frequency Output

3, 8, 13, 16, 19, 22, 26, Vcc1, Vcc2, Vcc3, Vcc4, Vcc5, Vcc6, Vcc7, Vcc8,

-

Power Supply

30, 31, 33, 37, 40, 43, 46

Vcc9, Vcc10, Vcc11, Vcc12, Vcc13, Vcc14

4

5

6

CLKuWire

DATAuWire

LEuWire

I

MICROWIRE Clock Input

MICROWIRE Data Input

MICROWIRE Latch Enable Input

7, 14, 15, 17, 18, 20, 21,

23, 24, 34, 35

NC

-

No Connection to these pins

9, 10

11

LDObyp1, LDObyp2

GOE

-

I

LDO Bypass

Global Output Enable

12

LD

O

I

Lock Detect and Test Output

Global Clock Output Synchronization

Oscillator Clock Input; Must be AC coupled

Charge Pump Output

27

SYNC*

28, 29

32

OSCin, OSCin*

CPout

I

O

I

36

Bias

Bias Bypass

38, 39

41, 42

44, 45

47, 48

DAP

CLKout0, CLKout0*

CLKout1, CLKout1*

CLKout2, CLKout2*

CLKout3, CLKout3*

DAP

O

-

LVPECL Clock Output 0

LVPECL Clock Output 1

LVPECL Clock Output 2

LVPECL Clock Output 3

Die Attach Pad is Ground

3

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Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors

for availability and specifications.

Parameter

Power Supply Voltage

Symbol

V_CC

V_IN

Ratings

-0.3 to 3.6

-0.3 to (V_CC+ 0.3)

-65 to 150

+260

Units

V

Input Voltage

V

T_STG

T_L

Storage Temperature Range

Lead Temperature (solder 4 s)

Junction Temperature

°C

T_J

125

Recommended Operating Conditions

Parameter

Ambient Temperature

Power Supply Voltage

Symbol

T_A

Min

-40

Typ

25

Max

85

Units

°C

V

V_CC

3.15

3.3

3.45

Note 1: "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability

and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in

the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the

device should not be operated beyond such conditions.

Note 2: This device is a high performance integrated circuit with ESD handling precautions. Handling of this device should only be done at ESD protected work

stations. The device is rated to a HBM-ESD of > 2 kV, a MM-ESD of > 200 V, and a CDM-ESD of > 1.2 kV.

Package Thermal Resistance

Package

θ_JA

θ_{J-PAD (Thermal Pad)}

48-Lead LLP (Note 3)

27.4° C/W

5.8° C/W

Note 3: Specification assumes 16 thermal vias connect the die attach pad to the embedded copper plane on the 4-layer JEDEC board. These vias play a key

role in improving the thermal performance of the LLP. It is recommended that the maximum number of vias be used in the board layout.

Electrical Characteristics (Note 4)

(3.15 V ≤ Vcc ≤ 3.45 V, -40 °C ≤ T_A≤ 85 °C, Differential Inputs/Outputs; except as specified. Typical values represent most likely

parametric norms at Vcc = 3.3 V, T_A= 25 °C, and at the Recommended Operation Conditions at the time of product characterization

and are not guaranteed).

Symbol

Parameter

Conditions

Current Consumption

Min

Typ

Max

Units

Entire device; CLKout0 & CLKout3

enabled in Bypass Mode

175

Power Supply Current

(Note 5)

I_CC

mA

Entire device; All Outputs Off (no

emitter resistors placed)

86

1

I_CCPD

Power Down Current

POWERDOWN = 1

Reference Oscillator

Reference Oscillator Input Frequency

Range for Square Wave

f_OSCinsquare

V_OSCinsquare

1

200

1.6

MHz

Vpp

AC coupled; Differential (V_OD

)

Square Wave Input Voltage for OSCin and

OSCin*

0.2

PLL

f_COMP

Phase Detector Frequency

40

MHz

µA

V_CPout= Vcc/2, PLL_CP_GAIN = 1x

V_CPout= Vcc/2, PLL_CP_GAIN = 4x

V_CPout= Vcc/2, PLL_CP_GAIN = 16x

V_CPout= Vcc/2, PLL_CP_GAIN = 32x

100

400

I_SRCECPout

Charge Pump Source Current

1600

3200

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Symbol

Parameter

Conditions

PLL (Continued)

Min

Typ

Max

Units

V_CPout= Vcc/2, PLL_CP_GAIN = 1x

V_CPout= Vcc/2, PLL_CP_GAIN = 4x

V_CPout= Vcc/2, PLL_CP_GAIN = 16x

V_CPout= Vcc/2, PLL_CP_GAIN = 32x

0.5 V < V_CPout< Vcc - 0.5 V

-100

-400

-1600

-3200

2

I_SINKCPout

Charge Pump Sink Current

μA

I_CPoutTRI

Charge Pump TRI-STATE^®Current

10

nA

%

V_CPout= Vcc / 2

T_A= 25°C

Magnitude of Charge Pump

Sink vs. Source Current Mismatch

I_CPout%MIS

3

4

Magnitude of Charge Pump

Current vs. Charge Pump Voltage

Variation

0.5 V < V_CPout< Vcc - 0.5 V

T_A= 25°C

I_CPoutVTUNE

%

Magnitude of Charge Pump Current vs.

Temperature Variation

I_CPoutTEMP

PN10kHz

PN1Hz

%

PLL_CP_GAIN = 1x

PLL_CP_GAIN = 32x

PLL_CP_GAIN = 1x

PLL_CP_GAIN = 32x

VCO

-117

-122

-219

-224

PLL 1/f Noise at 10 kHz Offset (Note 6)

Normalized to 1 GHz Output Frequency

dBc/Hz

Normalized Phase Noise Contribution

(Note 7)

f_Fout

VCO Tuning Range

LMK03002/LMK03002C

1566

1724

125

MHz

°C

After programming R15 for lock, no

changes to output configuration are

permitted to guarantee continuous

lock. (Note 8)

Allowable Temperature Drift for

Continuous Lock

|ΔT_CL

|

p_Fout

LMK03002/LMK03002C; T_A= 25 °C

2

dBm

Output Power to a 50 Ω load driven by Fout

Fine Tuning Sensitivity

(The lower sensitivity indicates the typical

sensitivity at the lower end of the tuning

range, the higher sensitivity at the higher

end of the tuning range)

K_Vtune

LMK03002/LMK03002C

11 to 15

MHz/V

LMK03002

12 kHz to 20 MHz bandwidth

800

400

J_RMSFout

Fout RMS Period Jitter

fs

LMK03002C

12 kHz to 20 MHz bandwidth

10 kHz Offset

-89

LMK03002C

100 kHz Offset

f_Fout= 1724 MHz

-113

-135

-155

-91

1 MHz Offset

(Note 9)

10 MHz Offset

10 kHz Offset

L(f)_Fout

Fout Single Side Band Phase Noise

dBc/Hz

LMK03002C

100 kHz Offset

f_Fout= 1566 MHz

-115

-137

-156

1 MHz Offset

(Note 9)

10 MHz Offset

5

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Symbol

Parameter

Conditions

Min

Typ

Max

Units

Clock Distribution Section (Note 10) - LVPECL Clock Outputs

CLKoutX_MUX

= Bypass

20

R_L= 100 Ω

Distribution Path =

800 MHz

Bandwidth =

12 kHz to 20 MHz

CLKoutX_MUX

= Divided

CLKoutX_DIV =

4

Jitter_ADD

Additive RMS Jitter (Note 10)

fs

75

Equal loading and identical clock

configuration

t_SKEW

CLKoutX to CLKoutY (Note 11)

Output High Voltage

-30

±3

30

ps

V

Termination = 50 Ω to Vcc - 2 V

Vcc -

0.98

V_OH

Termination = 50 Ω to Vcc - 2 V

CLKoutX output frequency = 200 MHz

Vcc -

1.8

V_OL

V_OD

Output Low Voltage

V

Differential Output Voltage

660

2.0

810

965

mV

Digital LVTTL Interfaces (Note 12)

V_IH

V_IL

I_IH

High-Level Input Voltage

Low-Level Input Voltage

High-Level Input Current

Low-Level Input Current

Vcc

0.8

5.0

V

V_IH= Vcc

V_IL= 0

-5.0

µA

I_IL

-40.0

Vcc -

0.4

V_OH

V_OL

I_OH= +500 µA

High-Level Output Voltage

Low-Level Output Voltage

V

I_OL= -500 µA

0.4

Digital MICROWIRE Interfaces (Note 13)

V_IH

V_IL

I_IH

High-Level Input Voltage

Low-Level Input Voltage

High-Level Input Current

Low-Level Input Current

1.6

Vcc

0.4

5.0

V

V_IH= Vcc

-5.0

µA

I_IL

V_IL= 0

MICROWIRE Timing

See Data Input Timing

t_CS

Data to Clock Set Up Time

Data to Clock Hold Time

Clock Pulse Width High

Clock Pulse Width Low

25

8

ns

t_CH

t_CWH

t_CWL

t_ES

25

Clock to Enable Set Up Time

Enable to Clock Set Up Time

Enable Pulse Width High

t_CES

t_EWH

Note 4: The Electrical Characteristics table lists guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified

or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.

Note 5: See 3.5 for more current consumption / power dissipation calculation information.

Note 6: A specification in modeling PLL in-band phase noise is the 1/f flicker noise, L_{PLL_flicker}(f), which is dominant close to the carrier. Flicker noise has a 10

dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = L_{PLL_flicker}(10 kHz) - 20log(Fout / 1 GHz), where L_{PLL_flicker}

(f) is the single side band phase noise of only the flicker noise's contribution to total noise, L(f). To measure L_{PLL_flicker}(f) it is important to be on the 10 dB/decade

slope close to the carrier. A high compare frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f). L_{PLL_flicker}(f)

can be masked by the reference oscillator performance if a low power or noisy source is used. The total PLL inband phase noise performance is the sum of

L_{PLL_flicker}(f) and L_{PLL_flat}(f).

Note 7: A specification in modeling PLL in-band phase noise is the Normalized Phase Noise Contribution, L_{PLL_flat}(f), of the PLL and is defined as PN1Hz =

L_{PLL_flat}(f) – 20log(N) – 10log(f_COMP). L_{PLL_flat}(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz Bandwidth and f_COMPis the phase

detector frequency of the synthesizer. L_{PLL_flat}(f) contributes to the total noise, L(f). To measure L_{PLL_flat}(f) the offset frequency, f, must be chosen sufficiently

smaller then the loop bandwidth of the PLL, and yet large enough to avoid a substantial noise contribution from the reference and flicker noise. L_{PLL_flat}(f) can be

masked by the reference oscillator performance if a low power or noisy source is used.

Note 8: Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction and stay in lock from the ambient temperature

and programmed state at which the device was when register R15 was programmed. The action of programming the R15 register, even to the same value,

activates a frequency calibration routine. This implies that the device will work over the entire frequency range, but if the temperature drifts more than the maximum

allowable drift for continuous lock, then it will be necessary to reprogram the R15 register to ensure that the device stays in lock. Regardless of what temperature

the device was initially programmed at, the ambient temperature can never drift outside the range of -40 °C ≤ T_A≤ 85 °C without violating specifications. For

this specification to be valid, the programmed state of the device must not change after R15 is programmed.

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Note 9: VCO phase noise is measured assuming the VCO is the dominant noise source due to a 75 Hz loop bandwidth. Over frequency, the phase noise typically

varies by 1 to 2 dB, with the worst case performance typically occurring at the highest frequency. Over temperature, the phase noise typically varies by 1 to 2 dB,

assuming the device is not reprogrammed. Reprogramming R15 will run the frequency calibration routine for optimum phase noise.

Note 10: The Clock Distribution Section includes all parts of the device except the PLL and VCO sections. Typical Additive Jitter specifications apply to the clock

distribution section only and is in RMS form addition to the jitter from the VCO.

Note 11: Specification is guaranteed by characterization and is not tested in production.

Note 12: Applies to GOE, LD, and SYNC*.

Note 13: Applies to CLKuWire, DATAuWire, and LEuWire.

Serial Data Timing Diagram

30020603

Data bits set on the DATAuWire signal are clocked into a shift register, MSB first, on each rising edge of the CLKuWire signal. On

the rising edge of the LEuWire signal, the data is sent from the shift register to the addressed register determined by the LSB bits.

After the programming is complete the CLKuWire, DATAuWire, and LEuWire signals should be returned to a low state.

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Charge Pump Current Specification Definitions

30020631

I1 = Charge Pump Sink Current at V_CPout= Vcc - ΔV

I2 = Charge Pump Sink Current at V_CPout= Vcc/2

I3 = Charge Pump Sink Current at V_CPout= ΔV

I4 = Charge Pump Source Current at V_CPout= Vcc - ΔV

I5 = Charge Pump Source Current at V_CPout= Vcc/2

I6 = Charge Pump Source Current at V_CPout= ΔV

ΔV = Voltage offset from the positive and negative supply rails. Defined to be 0.5 V for this device.

Charge Pump Output Current Magnitude Variation vs. Charge Pump Output Voltage

30020632

Charge Pump Sink Current vs. Charge Pump Output Source Current Mismatch

30020633

Charge Pump Output Current Magnitude Variation vs. Temperature

30020634

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1.5 CLKout DELAYS

1.0 Functional Description

Each individual clock output includes a delay adjustment.

Clock output delay registers (CLKoutX_DLY) support a 150

ps step size and range from 0 to 2250 ps of total delay.

The LMK03002/LMK03002C precision clock conditioners

combine the functions of jitter cleaning/reconditioning, multi-

plication, and distribution of a reference clock. The devices

integrate a Voltage Controlled Oscillator (VCO), a high per-

formance Integer-N Phase Locked Loop (PLL), a partially

integrated loop filter, and four LVPECL clock output distribu-

tion blocks.

1.6 LVPECL OUTPUTS

Each LVPECL output may be disabled individually by pro-

gramming the CLKoutX_EN bits. All the outputs may be dis-

abled simultaneously by pulling the GOE pin low or program-

ming EN_CLKout_Global to 0.

The devices include internal 3rd and 4th order poles to sim-

plify loop filter design and improve spurious performance. The

1st and 2nd order poles are off-chip to provide flexibility for

the design of various loop filter bandwidths.

1.7 GLOBAL CLOCK OUTPUT SYNCHRONIZATION

The SYNC* pin synchronizes the clock outputs. When the

SYNC* pin is held in a logic low state, the divided outputs are

also held in a logic low state. When the SYNC* pin goes high,

the divided clock outputs are activated and will transition to a

high state simultaneously. Clocks in the bypassed state are

not affected by SYNC* and are always synchronized with the

divided outputs.

The LMK03002/LMK03002C includes a 1.64 GHz VCO. The

VCO output is optionally accessible on the Fout port. Inter-

nally, the VCO output goes through an VCO Divider to feed

the various clock distribution blocks.

Each clock distribution block includes a programmable di-

vider, a phase synchronization circuit, a programmable delay,

a clock output mux, and an LVPECL output buffer. This allows

multiple integer-related and phase-adjusted copies of the ref-

erence to be distributed to four system components.

The SYNC* pin must be held low for greater than one clock

cycle of the output of the VCO Divider, also known as the

distribution path. Once this low event has been registered, the

outputs will not reflect the low state for four more cycles. Sim-

ilarly once the SYNC* pin becomes high, the outputs will not

simultaneously transition high until four more distribution path

clock cycles have passed. See the timing diagram below for

further detail. In the timing diagram below the clocks are pro-

grammed as CLKout0_MUX = Bypassed, CLKout1_MUX =

Divided, CLKout1_DIV = 2, CLKout2_MUX = Divided, and

CLKout2_DIV = 4.

The clock conditioners come in a 48-pin LLP package and are

footprint compatible with other clocking devices in the same

family.

1.1 BIAS PIN

To properly use the device, bypass Bias (pin 36) with a low

leakage 1 µF capacitor connected to Vcc. This is important

for low noise performance.

SYNC* Timing Diagram

1.2 LDO BYPASS

To properly use the device, bypass LDObyp1 (pin 9) with a

10 µF capacitor and LDObyp2 (pin 10) with a 0.1 µF capacitor.

1.3 OSCILLATOR INPUT PORT (OSCin, OSCin*)

The purpose of OSCin is to provide the PLL with a reference

signal. The OSCin port must be AC coupled, refer to the Sys-

tem Level Diagram in the Application Information section. The

OSCin port may be driven single endedly by AC grounding

OSCin* with a 0.1 µF capacitor.

1.4 LOW NOISE, FULLY INTEGRATED VCO

The LMK03002/LMK03002C devices contain a fully integrat-

ed VCO. In order for proper operation the VCO uses a fre-

quency calibration algorithm. The frequency calibration

algorithm is activated any time that the R15 register is pro-

grammed. Once R15 is programmed the temperature may not

drift more than the maximum allowable drift for continuous

lock, ΔT_CL, or else the VCO is not guaranteed to stay in lock.

30020604

The SYNC* pin provides an internal pull-up resistor as shown

on the functional block diagram. If the SYNC* pin is not ter-

minated externally the clock outputs will operate normally. If

the SYNC* function is not used, clock output synchronization

is not guaranteed.

For the frequency calibration algorithm to work properly OS-

Cin must be driven by a valid signal when R15 is programmed.

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1.8 CLKout OUTPUT STATES

2.0 General Programming

Information

The LMK03002/LMK03002C devices are programmed using

several 32-bit registers which control the device's operation.

The registers consist of a data field and an address field. The

last 4 register bits, ADDR[3:0] form the address field. The re-

maining 28 bits form the data field DATA[27:0].

Each clock output may be individually enabled with the

CLKoutX_EN bits. Each individual output enable control bit is

gated with the Global Output Enable input pin (GOE) and the

Global Output Enable bit (EN_CLKout_Global).

All clock outputs can be disabled simultaneously if the GOE

pin is pulled low by an external signal or EN_CLKout_Global

is set to 0.

During programming, LEuWire is low and serial data is

clocked in on the rising edge of CLKuWire (MSB first). When

LEuWire goes high, data is transferred to the register bank

selected by the address field. Only registers R0, R4 to R8,

R11, and R13 to R15 need to be programmed for proper de-

vice operation. After programming, CLKuWire, DATAuWire,

LEuWire should remain low to prevent spurious.

CLKoutX

_EN bit

EN_CLKout

_Global bit

GOE pin

Clock X

Output State

1

Don't care

0

1

0

Low

Off

Don't care

Off

High / No

Connect

1

Enabled

For the frequency calibration algorithm to work properly OS-

Cin must be driven by a valid signal when R15 is programmed.

Any changes to the PLL R divider or OSCin require R15 to be

programmed again to activate the frequency calibration rou-

tine.

When an LVPECL output is in the Off state, the outputs are

at a voltage of approximately 1 volt.

1.9 GLOBAL OUTPUT ENABLE AND LOCK DETECT

2.1 RECOMMENDED PROGRAMMING SEQUENCE

The GOE pin provides an internal pull-up resistor as shown

on the functional block diagram. If it is not terminated exter-

nally, the clock output states are determined by the Clock

The recommended programming sequence involves pro-

gramming R0 with the reset bit set (RESET = 1) to ensure the

device is in a default state. Registers are programmed in order

with R15 being the last register programmed. An example

programming sequence is shown below.

Output

Enable

bits

(CLKoutX_EN)

and

the

EN_CLKout_Global bit.

By programming the PLL_MUX register to Digital Lock Detect

Active High (See 2.6.2), the Lock Detect (LD) pin can be con-

nected to the GOE pin in which case all outputs are set low

automatically if the synthesizer is not locked.

•

Program R0 with the reset bit set (RESET = 1). This

ensures the device is in a default state.

•

Program R4 to R7 as necessary with desired clocks with

appropriate enable, mux, divider, and delay settings.

1.10 POWER ON RESET

•

Program R8.

Program R11 with DIV4 setting if necessary.

Program R13 with oscillator input frequency and internal

loop filter values.

When supply voltage to the device increases monotonically

from ground to Vcc, the power on reset circuit sets all registers

to their default values, see 2.3.1 for more information on de-

fault register values. Voltage should be applied to all Vcc pins

simultaneously.

•

Program R14 with Fout enable bit, global clock output bit,

power down setting, PLL mux setting, and PLL R divider.

Program R15 with PLL charge pump gain, VCO divider,

and PLL N divider. Also starts frequency calibration

routine.

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0

D I V 4

C L K o u t 0 _ E N C L K o u t 1 _ E N C L K o u t 2 _ E N C L K o u t 3 _ E N

R E S E T

R e g i s t e r

11

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P O W E R D O W N

E N _ C L K o u t _ G l o b a l

E N _ F o u t

R e g i s t e r

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2.3 REGISTERS R0, R4 to R7

forces all registers to their power on reset condition and there-

fore automatically clears this bit. If this bit is set, all other R0

bits are ignored and R0 needs to be programmed again if

used with its proper values and RESET = 0.

Registers R4 through R7 control the four clock outputs. Reg-

ister R3 controls CLKout0, Register R4 controls CLKout1, and

so on. There is one additional bit in register R0 called RESET.

The X in CLKoutX_MUX, CLKoutX_DIV, CLKoutX_DLY, and

CLKoutX_EN denote the actual clock output which may be

from 0 to 3.

2.3.1 RESET bit -- R0 only

This bit is only in register R0. The use of this bit is optional

and it should be set to '0' if not used. Setting this bit to a '1'

Default

Bit Value

Bit

Location

Bit Name

RESET

Bit State

Bit Description

Register

0

1

0

No reset, normal operation

Bypassed

Reset to power on defaults

CLKoutX mux mode

CLKoutX enable

R0

31

CLKoutX_MUX

CLKoutX_EN

CLKoutX_DIV

CLKoutX_DLY

DIV4

18:17

16

Disabled

R0 to R7

R11

Divide by 2

0 ps

CLKoutX clock divide

CLKoutX clock delay

Phase Detector Frequency

15:8

7:4

15

PDF ≤ 20 MHz

10 MHz OSCin

Low (~200 Ω)

OSCin_FREQ

VCO_R4_LF

VCO_R3_LF

VCO_C3_C4_LF

EN_Fout

10

0

OSCin Frequency in MHz

R4 internal loop filter values

R3 internal loop filter values

C3 and C4 internal loop filter values

Fout enable

21:14

13:11

10:8

7:4

R13

0

Low (~600 Ω)

C3 = 0 pF, C4 = 10 pF

Fout disabled

0

28

EN_CLKout_Global

POWERDOWN

PLL_MUX

1

Normal - CLKouts normal

Normal - Device active

Disabled

Global clock output enable

Device power down

27

0

R14

R15

26

0

Multiplexer control for LD pin

PLL R divide value

23:20

19:8

31:30

29:26

25:8

PLL_R

10

0

R divider = 10

100 uA

PLL_CP_GAIN

VCO_DIV

Charge pump current

VCO divide value

2

Divide by 2

PLL_N

760

N divider = 760

PLL N divide value

2.3.2 CLKoutX_MUX[1:0] -- Clock Output Multiplexers

SYNC* pin must be used to ensure that all edges of the clock

outputs are aligned (See 1.7). The Clock Output Dividers fol-

low the VCO Divider so the final clock divide for an output is

VCO Divider × Clock Output Divider. By adding the divider

block to the output path a fixed delay of approximately 100 ps

is incurred.

These bits control the Clock Output Multiplexer for each clock

output. Changing between the different modes changes the

blocks in the signal path and therefore incurs a delay relative

to the bypass mode. The different MUX modes and associ-

ated delays are listed below.

The actual Clock Output Divide value is twice the binary value

programmed as listed in the table below.

CLKoutX_MUX

[1:0]

Mode

Added Delay

Relative to

Bypass Mode

CLKoutX_DIV[7:0]

Clock Output

Divider value

0

1

Bypassed (default)

Divided

0 ps

0

.

0

.

0

.

0

.

0

.

0

1

.

0

1

0

.

0

1

0

1

0

1

.

Invalid

100 ps

2 (default)

400 ps

(In addition to the

programmed

delay)

4

6

2

3

Delayed

8

500 ps

(In addition to the

programmed

delay)

10

...

Divided and

Delayed

1

510

2.3.4 CLKoutX_DLY[3:0] -- Clock Output Delays

2.3.3 CLKoutX_DIV[7:0] -- Clock Output Dividers

These bits control the delay stages for each clock output. In

order for these delays to be active, the respective

CLKoutX_MUX (See 2.3.2) bit must be set to either "Delayed"

or "Divided and Delayed" mode. By adding the delay block to

These bits control the clock output divider value. In order for

these dividers to be active, the respective CLKoutX_MUX

(See 2.3.2) bit must be set to either "Divided" or "Divided and

Delayed" mode. After all the dividers are programed, the

13

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the output path a fixed delay of approximately 400 ps is in-

curred in addition to the delay shown in the table below.

to zero or if GOE pin is held low, all CLKoutX_EN bit states

will be ignored and all clock outputs will be disabled. See 1.8

for more information on CLKout states.

CLKoutX_DLY[3:0]

Delay (ps)

0 (default)

150

CLKoutX_EN bit

Conditions

CLKoutX State

0

1

0

1

EN_CLKout_Global Disabled (default)

bit = 1

GOE pin = High / No

Connect

Enabled

2

300

3

450

4

600

2.4 REGISTER R11

5

750

This register only has one bit and only needs to be pro-

grammed in the case that the phase detector frequency is

greater than 20 MHz and digital lock detect is used. Other-

wise, it is automatically defaulted to the correct values.

6

900

7

1050

1200

1350

1500

1650

1800

1950

2100

2250

8

9

2.4.1 DIV4 -- High Phase Detector Frequencies and Lock

Detect

10

11

12

13

14

15

This bit divides the frequency presented to the digital lock de-

tect circuitry by 4. It is necessary to get a reliable output from

the digital lock detect output in the case of a phase detector

frequency frequency greater than 20 MHz.

2.3.5 CLKoutX_EN bit -- Clock Output Enables

These bits control whether an individual clock output is en-

abled or not. If the EN_CLKout_Global bit (See 2.6.4) is set

DIV4

Digital Lock Detect Circuitry Mode

Not divided; Phase Detector Frequency ≤ 20 MHz (default)

Divided by 4; Phase Detector Frequency > 20 MHz

0

1

2.5 REGISTER R13

2.5.1 VCO_C3_C4_LF[3:0] -- Value for Internal Loop Filter

Capacitors C3 and C4

These bits control the capacitor values for C3 and C4 in the

internal loop filter.

VCO_C3_C4_LF[3:0]

Loop Filter Capacitors

C3 (pF)

C4 (pF)

10 (default)

60

0

0 (default)

1

0

2

50

10

3

0

110

4

50

110

5

100

0

110

6

160

7

50

160

8

9

100

150

10

60

10

110

11

60

12 to 15

Invalid

2.5.2 VCO_R3_LF[2:0] -- Value for Internal Loop Filter Resistor R3

These bits control the R3 resistor value in the internal loop filter. The recommended setting for VCO_R3_LF[2:0] = 0 for optimum

phase noise and jitter.

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14

VCO_R3_LF[2:0]

R3 Value (kΩ)

0

Low (~600 Ω) (default)

1

10

20

2

3

30

4

40

5 to 7

Invalid

2.5.3 VCO_R4_LF[2:0] -- Value for Internal Loop Filter Resistor R4

These bits control the R4 resistor value in the internal loop filter. The recommended setting for VCO_R4_LF[2:0] = 0 for optimum

phase noise and jitter.

VCO_R4_LF[2:0]

R4 Value (kΩ)

0

Low (~200 Ω) (default)

1

10

20

2

3

30

4

40

5 to 7

Invalid

15

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2.5.4 OSCin_FREQ[7:0] -- Oscillator Input Calibration

Adjustment

These bits are to be programmed to the OSCin frequency. If

the OSCin frequency is not an integral multiple of 1 MHz, then

round to the closest value.

OSCin_FREQ[7:0]

OSCin Frequency

1

1 MHz

2 MHz

2

...

10

...

10 MHz (default)

...

200

200 MHz

Invalid

201 to 255

2.6 REGISTER R14

2.6.1 PLL_R[11:0] -- R Divider Value

PLL_R[11:0]

PLL R Divide

Value

These bits program the PLL R Divider and are programmed

in binary fashion. Any changes to PLL_R require R15 to be

programmed again to active the frequency calibration routine.

0

.

0

.

0

.

0

.

0

.

0

.

0

.

0

.

0

.

0

.

1

.

0

.

2

...

10 (default)

...

PLL_R[11:0]

PLL R Divide

Value

0

.

0

.

0

.

0

.

0

.

0

.

0

.

0

.

1

.

0

.

1

.

0

.

0

1

Invalid

1

4095

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16

2.6.2 PLL_MUX[3:0] -- Multiplexer Control for LD Pin

PLL_MUX[3:0]

Output Type

LD Pin Function

These bits set the output mode of the LD pin. The table below

lists several different modes.

11

Push-Pull

R Divider Output/2

(50% Duty Cycle)

PLL_MUX[3:0]

Output Type

Hi-Z

LD Pin Function

Disabled (default)

Logic High

12 to 15

Invalid

0

1

2

3

2.6.3 POWERDOWN bit -- Device Power Down

Push-Pull

This bit can power down the device. Enabling this bit powers

down the entire device and all blocks, regardless of the state

of any of the other bits or pins.

Logic Low

Digital Lock Detect

(Active High)

POWERDOWN bit

Mode

4

5

6

7

Push-Pull

Digital Lock Detect

(Active Low)

0

1

Normal Operation (default)

Entire Device Powered Down

Analog Lock

Detect

2.6.4 EN_CLKout_Global bit -- Global Clock Output

Enable

Open Drain NMOS

Open Drain PMOS

Analog Lock

Detect

This bit overrides the individual CLKoutX_EN bits (See 2.3.5).

When this bit is set to 0, all clock outputs are disabled, re-

gardless of the state of any of the other bits or pins. See 1.8

for more information on CLKout states.

Analog Lock

Detect

8

9

Invalid

EN_CLKou

t_Global bit

Clock Outputs

Push-Pull

N Divider Output/2

(50% Duty Cycle)

0

1

All Off

10

Invalid

Normal Operation (default)

2.6.5 EN_Fout bit -- Fout port enable

This bit enables the Fout pin.

EN_Fout bit

Fout Pin Status

0

1

Disabled (default)

Enabled

17

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2.7 Register R15

contributes to the total N divide value, N_Total. N_Total= PLL N

Divider × VCO Divider. The VCO Divider can not be by-

passed. See 2.7.1 (PLL N Divider) for more information on

setting the VCO frequency.

Programming R15 also activates the frequency calibration

routine.

2.7.1 PLL_N[17:0] -- PLL N Divider

VCO_DIV[3:0]

VCO Divider

Value

These bits program the divide value for the PLL N Divider.

The PLL N Divider follows the VCO Divider and precedes the

PLL phase detector. Since the VCO Divider is also in the

feedback path from the VCO to the PLL Phase Detector, the

total N divide value, N_Total, is also influenced by the VCO Di-

vider value. N_Total= PLL N Divider × VCO Divider. The VCO

frequency is calculated as, f_VCO= f_OSCin× PLL N Divider ×

VCO Divider / PLL R Divider. Since the PLL N divider is a pure

binary counter there are no illegal divide values for PLL_N

[17:0] except for 0.

0

1

.

0

1

0

.

0

1

0

1

0

.

0

1

0

1

0

1

0

1

0

1

.

Invalid

2 (default)

3

4

5

6

7

PLL_N[17:0]

PLL N

Divider

Value

8

Invalid

...

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Invalid

1

Invalid

.

...

0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 0 0

760

2.7.3 PLL_CP_GAIN[1:0] -- PLL Charge Pump Gain

(default)

These bits set the charge pump gain of the PLL.

.

...

PLL_CP_GAIN[1:0]

Charge Pump Gain

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

262143

0

1

2

3

1x (default)

4x

2.7.2 VCO_DIV[3:0] -- VCO Divider

16x

32x

These bits program the divide value for the VCO Divider. The

VCO Divider follows the VCO output and precedes the clock

distribution blocks. Since the VCO Divider is in the feedback

path from the VCO to the PLL phase detector the VCO Divider

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18

distributed. The first and second pole of the loop filter are

external. The third and fourth poles are integrated.

3.0 Application Information

3.1 SYSTEM LEVEL DIAGRAM

The following shows the LMK300xx in a typical application. In

this setup the clock may be multiplied, reconditioned, and re-

30020670

FIGURE 1. Typical Application

3.2 BIAS PIN

3.3 LDO BYPASS

To properly use the device, bypass Bias (pin 36) with a low

leakage 1 µF capacitor connected to Vcc. This is important

for low noise performance.

To properly use the device, bypass LDObyp1 (pin 9) with a

10 µF capacitor and LDObyp2 (pin 10) with a 0.1 µF capacitor.

19

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3.4 LOOP FILTER

the loop filter is designed, it must be stable over the entire

frequency band, meaning that the changes in K_Vtunefrom the

low to high band specification will not make the loop filter un-

stable.

The internal charge pump is directly connected to the inte-

grated loop filter components. The first and second pole of the

loop filter are externally attached as shown in Figure 2. When

30020671

FIGURE 2. Loop Filter

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20

3.5 CURRENT CONSUMPTION / POWER DISSIPATION

CALCULATIONS

calculate estimated current consumption of the device. Un-

less otherwise noted Vcc = 3.3 V, T_A= 25 °C.

Due to the myriad of possible configurations the following ta-

ble serves to provide enough information to allow the user to

Table 3.5 - Block Current Consumption

Power

Current

Power

Dissipated in

LVPECL emitter

resistors (mW)

Block

Condition

Consumption at Dissipated in

3.3 V (mA)

device (mW)

Entire device,

core current

All outputs off; No LVPECL emitter resistors connected

86.0

283.8

-

Clock buffers

(internal)

The clock buffers are enabled anytime one of CLKout0

through CLKout3 are enabled

9

29.7

47.8

72

-

Fout buffer, EN_Fout = 1

14.5

40

LVPECL output, bypass mode (includes 120 Ω emitter

resistors)

60

Output buffers

LVPECL output, disabled mode (includes 120 Ω

emitter resistors)

17.4

0

38.3

0

19.1

-

LVPECL output, disabled mode. No emitter resistors

placed; open outputs

Divide enabled, divide = 2

5.3

8.5

5.8

9.9

175

17.5

28.0

19.1

32.7

457.5

-

Divide circuitry

per output

Divide enabled, divide > 2

-

Delay enabled, delay < 8

-

Delay circuitry

per output

Delay enabled, delay > 7

Entire device

CLKout0 & CLKout3 enabled in bypass mode

120

From Table 3.5 the current consumption can be calculated in

any configuration. For example, the current for the entire de-

vice with two LVPECL (CLKout0 and CLKout3) outputs in

bypass mode can be calculated by adding up the following

blocks: core current, clock buffers, and two LVPECL output

buffer currents. There will also be two LVPECL outputs draw-

ing emitter current, but some of the power from the current

draw is dissipated in the external 120 Ω resistors which

doesn't add to the power dissipation budget for the device. If

delays or divides are switched in, then the additional current

for these stages needs to be added as well.

& V_OLtypical specification. Therefore the power dissipated in

each emitter resistor is approximately (1.9 V)²/ 120 Ω = 30

mW. When the LVPECL output is disabled, the emitter resis-

tor voltage is ~1.07 V. Therefore the power dissipated in each

emitter resistor is approximately (1.07 V)²/ 120 Ω = 9.5 mW.

3.6 THERMAL MANAGEMENT

Power consumption of the LMK03002/LMK03002C devices

can be high enough to require attention to thermal manage-

ment. For reliability and performance reasons the die tem-

perature should be limited to a maximum of 125 °C. That is,

as an estimate, T_A(ambient temperature) plus device power

consumption times θ_JAshould not exceed 125 °C.

The package of the device has an exposed pad that provides

the primary heat removal path as well as excellent electrical

grounding to the printed circuit board. To maximize the re-

moval of heat from the package a thermal land pattern in-

cluding multiple vias to a ground plane must be incorporated

on the PCB within the footprint of the package. The exposed

pad must be soldered down to ensure adequate heat con-

duction out of the package. A recommended land and via

pattern is shown in Figure 3. More information on soldering

LLP packages can be obtained at www.national.com.

For power dissipated by the device, the total current entering

the device is multiplied by the voltage at the device minus the

power dissipated in any emitter resistors connected to any of

the LVPECL outputs. If no emitter resistors are connected to

the LVPECL outputs, this power will be 0 watts. For example,

in the case of two LVPECL (CLKout0 & CLKout3) outputs op-

erating at 3.3 volts, we calculate 3.3 V × (86 + 9 + 40 + 40)

mA = 3.3 V × 175 mA = 577.5 mW. Because two LVPECL

outputs (CLKout0 and CLKout3) have the emitter resistors

hooked up and the power dissipated by these resistors is 60

mW for each clock, the total device power dissipation is 533.9

mW - 120 mW = 457.5 mW.

When the LVPECL output is active, ~1.9 V is the average

voltage on each output as calculated from the LVPECL V_OH

21

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30020673

FIGURE 3. Recommended Land and Via Pattern

To minimize junction temperature it is recommended that a

possible), which could provide thermal insulation. The vias

shown in Figure 3 should connect these top and bottom cop-

per layers and to the ground layer. These vias act as “heat

pipes” to carry the thermal energy away from the device side

of the board to where it can be more effectively dissipated.

simple heat sink be built into the PCB (if the ground plane

layer is not exposed). This is done by including a copper area

of about 2 square inches on the opposite side of the PCB from

the device. This copper area may be plated or solder coated

to prevent corrosion but should not have conformal coating (if

www.national.com

22

Physical Dimensions inches (millimeters) unless otherwise noted

Leadless Leadframe Package (Bottom View)

48 Pin LLP (SQA48A) Package

Ordering Information

Order Number

Package

Marking

Packing

VCO Version

Performance

Grade

LVPECL

Outputs

LMK03002ISQ

LMK03002ISQX

LMK03002CISQ

LMK03002CISQX

K03002 I

K03002CI

250 Unit Tape and Reel

2500 Unit Tape and Reel

250 Unit Tape and Reel

2500 Unit Tape and Reel

1.64 GHz

800 fs

400 fs

4

23

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Notes

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型号：	LMK03002ISQX
厂家：	National Semiconductor
描述：	Precision Clock Conditioner with Integrated VCO 精密时钟调节器集成VCO 调节器时钟
文件：	总24页 (文件大小：477K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LMK03002ISQX [NSC]

相关型号：

LMK03002ISQX/NOPB

LMK03033

LMK03033CISQ

LMK03033CISQ/NOPB

LMK03033CISQE

LMK03033CISQE/NOPB

LMK03033CISQX

LMK03033CISQX/NOPB

LMK03033ISQ

LMK03033ISQ/NOPB

LMK03033ISQE/NOPB

LMK03033ISQX