LMP8358MTX [NSC]
Zero-Drift, Programmable Instrumentation Amplifier with Diagnostics; 零漂移，可编程仪表放大器与诊断
| 型号： | LMP8358MTX |
| 厂家： | 
National Semiconductor |
| 描述： | Zero-Drift, Programmable Instrumentation Amplifier with Diagnostics |
| 文件： | 总32页 (文件大小：966K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 5, 2010
LMP8358
Zero-Drift, Programmable Instrumentation Amplifier with
Diagnostics
General Description
Features
Typical Values unless otherwise noted, TA = 25°C
The LMP8358 is a precision programmable-gain instrumen-
tation amplifier in National's LMP® precision amplifier family.
Its gain can be programmed to 10, 20, 50, 100, 200, 500, or
1000 through an SPI-compatible serial interface or through a
parallel interface. Alternatively, its gain can be set to an arbi-
trary value using two external resistors. The LMP8358 uses
patented techniques to measure and continuously correct its
input offset voltage, eliminating offset drift over time and tem-
perature and the effect of 1/f noise. Its ground-sensing CMOS
input features a high CMRR and low input bias currents. It is
capable of sensing differential input voltages in a common-
mode range that extends from 100mV below the negative
supply to 1.4V below the positive supply, making it an ideal
solution for interfacing with ground-referenced sensors, sup-
ply-referenced sensor bridges, and any other application re-
quiring precision and long-term stability. Additionally, the
LMP8358 includes fault detection circuitry to detect open and
shorted inputs and deteriorating connections to the signal
source. Other features that make the LMP8358 a versatile
solution for many applications are its rail-to-rail output, low
input voltage noise and high gain-bandwidth product.
Supply voltage
Supply current
Max gain error
Max gain drift
Min CMRR
Max offset voltage
Max offset voltage drift
GBW (gain = 10)
Max non-linearity
Operating temperature range
Input fault detection
SPI or pin configurable modes
EMIRR at 1.8GHz
2.7V to 5.5V
■
■
■
■
■
■
■
■
■
■
■
■
■
■
1.8 mA
0.15%
16 ppm/°C
110 dB
10 µV
50 nV/°C
8 MHz
100 ppm
−40°C to 125°C
92 dB
14-Pin SOIC and 14-Pin TSSOP Package
Applications
Bridge sensor amplifier
■
■
■
■
Thermopile amplifier
Portable instrumentation
Medical instrumentation
Precision low-side current sensing
■
Typical Application
300454g1
LMP® is a registered trademark of National Semiconductor Corporation.
© 2010 National Semiconductor Corporation
300454
www.national.com
Storage Temperature Range
Junction Temperature (Note 4)
For soldering specifications:
see product folder at www.national.com and
www.national.com/ms/MS/MS-SOLDERING.pdf
−65°C to 150°C
150°C
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
ESD Tolerance (Note 2)
Human Body Model
Machine Model
Charge Device
2kV
200V
1kV
VS
Operating Ratings (Note 1)
Temperature Range
−40°C to 125°C
Supply Voltage (VS = V+ – V−)
2.7V to 5.5V
±100mV
VIN Differential (V+IN − V−IN
)
VIN Differential (V+IN − V−IN
)
Output Short Circuit Duration (Note 3)
Any pin relative to V−
+IN, −IN, OUT Pins
Package Thermal Resistance (θJA (Note 4)
14-Pin SOIC
14-Pin TSSOP
6V, −0.3V
V+ +0.3V, V− −0.3V
±10 mA
145°C/W
135°C/W
+IN, −IN Pins
3.3V Electrical Characteristics
Unless otherwise specified, all limits are guaranteed for TA = 25°C. V+ = 3.3V , V− = 0V, VREF = V+/2, VCM = V+/2, RL = 10 kΩ to
VREF, CL = 10 pF; Serial Control Register: G[2:0] = 110b (Gain = 1000x), COMP[2:0] = 000b, MUX[1:0] = 00b, POL, SHDN, FILT,
PIN = 0b, CUR[2:0] = 000b. Boldface limits apply at the temperature extremes.
Min
Typ
Max
Symbol
Parameter
Input Offset Voltage
Conditions
Units
(Note 6) (Note 5) (Note 6)
VOS
VCM = V+/2
VCM = 0V
1
1
10
15
µV
10
15
TCVOS Input Offset Voltage Temperature Drift VCM = V+/2
50
50
nV/°C
dB
(Note 8)
VCM = 0V
V− − 0.1V ≤ VCM ≤ V+ − 1.4V
CMRR Common Mode Rejection Ratio
110
105
139
CMVR Common Mode Voltage Range
VREFRR VREF Rejection Ratio
−0.1
1.9
V
CMRR ≥ 110 dB
V− + 0.1V ≤ VREFF ≤ V+ − 1.4V
110
105
145
138
dB
2.7V ≤ V+ ≤ 5.5V
PSRR
Power supply Rejection Ratio
112
105
dB
dB
EMIRR Electro Magnetic Interference
Rejection Ratio
+IN / −IN, VRF = 100 mVP, f = 900 MHz
+IN / −IN, VRF = 100 mVP, f = 1800 MHz
83
93
ZINDM
ZINCM
VINDM
IB
Differential Input Impedance
Common Mode Input Impedance
Differential Mode Input Voltage
Input Bias Current
50||1
50||1
MΩ ‖ pF
MΩ ‖ pF
mV
±100
0.006
1.2
2
nA
pA
IOS
en
Input Offset Current
0.1
27
31
28
27
28
28
27
27
112
Input Voltage Noise Density
Gain = 10, f = 1 kHz
Gain = 20, f = 1 kHz
Gain = 50, f = 1 kHz
Gain = 100, f = 1 kHz
Gain = 200, f = 1 kHz
Gain = 500, f = 1 kHz
Gain = 1000, f = 1 kHz
Gain = External, f = 1 kHz
nV/
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2
Min
Typ
Max
Symbol
Parameter
Input Voltage Noise
Conditions
Units
(Note 6) (Note 5) (Note 6)
en
Gain = 10, 0.1 Hz < f < 10 Hz
Gain = 20, 0.1 Hz < f < 10 Hz
Gain = 50, 0.1 Hz < f < 10 Hz
Gain = 100, 0.1 Hz < f < 10 Hz
Gain = 200, 0.1 Hz < f < 10 Hz
Gain = 500, 0.1 Hz < f < 10 Hz
Gain = 1000, 0.1 Hz < f < 10 Hz
Gain = External, 0.1 Hz < f < 10 Hz
Gain = 100, f = 1 kHz
0.9
0.6
0.6
0.7
0.6
0.6
0.6
0.6
0.5
µVPP
In
Input Current Noise Density
Gain Error
pA/
GE
Gain = 10, 20, 50, 100, 200, 500
VOUT = VREF + 1V and VOUT = VREF − 1V
0.03
0.1
0.15
%
%
GE
GE
Gain Error
Gain = 1000
0.03
0.15
0.25
VOUT = VREF + 1V and VOUT = VREF − 1V
Gain Error Contribution from Chip
Gain Error Temperature Coefficient
VOUT = VREF + 1V and VOUT = VREF − 1V
0.03
3
%
For all gain settings (internal and
external), VOUT = VREF + 1V and
VOUT = VREF − 1V
16
ppm/°C
NL
Non-Linearity
3.3
8
100
ppm
MHz
GBW
Gain Bandwidth
COMP[2:0] =000b, Gain > 10
COMP[2:0] = 001b, Gain > 30
COMP[2:0] = 010b, Gain > 200
COMP[2:0] = 011b, Gain > 300
COMP[2:0] = 1xxb, Gain > 1
Gain = 10, COMP[2:0] = 000b
Gain = 10, COMP[2:0] = 1xxb
Gain = 20, COMP[2:0] = 000b
Gain = 20, COMP[2:0] = 1xxb
Gain = 50, COMP[2:0] = 001b
Gain = 50, COMP[2:0] = 1xxb
Gain = 100, COMP[2:0] = 010b
Gain = 100, COMP[2:0] = 1xxb
Gain = 200, COMP[2:0] = 010b
Gain = 200, COMP[2:0] = 1xxb
Gain = 500, COMP[2:0] = 011b
Gain = 500, COMP[2:0] = 1xxb
Gain = 1000, COMP[2:0] = 011b
Gain = 1000, COMP[2:0] = 1xxb
24
80
240
0.8
900
70
BW
−3 dB Bandwidth
400
37
490
16
680
8
kHz
195
4
130
1.5
89
0.8
1.6
SR
Slew Rate
(Note 7)
COMP[2:0] = 000b, 10% to 90% of Step,
VOUT = 2 VPP
COMP[2:0] = 001b, 10% to 90% of Step,
VOUT = 2 VPP
3.8
6.5
9.3
0.17
4
COMP[2:0] = 010b, 10% to 90% of Step,
VOUT = 2 VPP
V/µs
COMP[2:0] = 011b, 10% to 90% of Step,
VOUT = 2 VPP
COMP[2:0] = 1xxb, 10% to 90% of Step,
VOUT = 2 VPP
ts
0.01% Settling Time
2 V Step, CL = 10 pF, COMP[2:0] = 011b
µs
3
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Min
Typ
Max
Symbol
Parameter
Conditions
RL = 2 kΩ to V+/2
Units
(Note 6) (Note 5) (Note 6)
VOUT
Output Voltage Swing High
32
40
RL = 10 kΩ to V+/2
RL > 1 MΩ to V+/2
RL = 2 kΩ to V+/2
RL = 10 kΩ to V+/2
RL > 1 MΩ to V+/2
VOUT tied to V+/2
VOUT tied to V+/2
12
17
mV from
top rail
7
12
Output Voltage Swing Low
28
38
mV from
bottom
rail
12
17
8
13
IOUT
Output Current Sourcing
Output Current Sinking
Supply Current
21
15
28
37
mA
32
25
IS
Fault detection off, VIN DIFF = 0V
Fault detection on, VIN DIFF = 0V
in Shutdown
1.8
1.9
0.014
85
2.1
2.2
1
mA
mA
µA
TSD_ON Turn-on time from Shutdown
µs
PSE
Prescaler Error (Offset + Gain Error)
Prescaler Gain Factor
VCM = V+/2
5
15
mV
V/V
0.02
10
ITEST
Fault Detection: Test Current
Setting 1 (CUR[2:0] = 001b), VCM < V+ −
nA
nA
µA
µA
µA
1.15V
Setting 2 (CUR[2:0] = 010b), VCM < V+ −
1.15V
Setting 3 (CUR[2:0] = 011b), VCM < V+
100
1
−
1.15V
Setting 4 (CUR[2:0] = 100b), VCM < V+
−
−
10
1.15V
Setting 5 (CUR[2:0] = 101b), VCM < V+
1.15V
100
5.0V Electrical Characteristics
Unless otherwise specified, all limits are guaranteed for TA = 25°C. V+ = 5.0V , V− = 0V, VREF = V+/2, VCM = V+/2, RL = 10 kΩ to
VREF, CL = 10 pF; Serial Control Register: G[2:0] = 110b (Gain = 1000x), COMP[2:0] = 000b, MUX[1:0] = 00b, POL, SHDN, FILT,
PIN = 0b, CUR[2:0] = 000b. Boldface limits apply at the temperature extremes.
Min
Typ
Max
Symbol
Parameter
Input Offset Voltage
Conditions
Units
(Note 6) (Note 5) (Note 6)
VOS
VCM = V+/2
VCM = 0V
0.9
0.9
10
15
µV
10
15
TCVOS Input Offset Voltage Temperature Drift VCM = V+/2
50
50
nV/°C
dB
(Note 8)
VCM = 0V
V− − 0.1V ≤ VCM ≤ V+ − 1.4V
V− + 0.1V ≤ VREFF ≤ V+ − 1.4V
CMRR ≥ 115 dB
CMRR Common Mode Rejection Ratio
116
105
142
150
VREFRR VREF Rejection Ratio
115
105
dB
V
CMVR Common Mode Voltage Range
−0.1
3.6
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4
Min
Typ
Max
Symbol
Parameter
Conditions
2.7V ≤ V+ ≤ 5.5V
Units
(Note 6) (Note 5) (Note 6)
PSRR
Power supply Rejection Ratio
112
105
138
dB
EMIRR Electro Magnetic Interference
Rejection Ratio
+IN / −IN, VRF = 100 mVP, f = 900 MHz
+IN / −IN, VRF = 100 mVP, f = 1800 MHz
83
93
dB
ZINDM
ZINCM
VINDM
IB
Differential Input Impedance
Common Mode Input Impedance
Differential Mode Input Voltage
Input Bias Current
50||1
50||1
MΩ ‖ pF
MΩ ‖ pF
mV
±100
0.006
1.2
nA
2
IOS
en
Input Offset Current
0.2
25
113
pA
Input Voltage Noise Density
Gain = 10, f = 1 kHz
Gain = 20, f = 1 kHz
28
Gain = 50, f = 1 kHz
26
Gain = 100, f = 1 kHz
25
nV/
Gain = 200, f = 1 kHz
28
Gain = 500, f = 1 kHz
26
Gain = 1000, f = 1 kHz
25
Gain = External, f = 1 kHz
Gain = 10, 0.1 Hz < f < 10 Hz
Gain = 20, 0.1 Hz < f < 10 Hz
Gain = 50, 0.1 Hz < f < 10 Hz
Gain = 100, 0.1 Hz < f < 10 Hz
Gain = 200, 0.1 Hz < f < 10 Hz
Gain = 500, 0.1 Hz < f < 10 Hz
Gain = 1000, 0.1 Hz < f < 10 Hz
Gain = External, 0.1 Hz < f < 10 Hz
Gain = 100, f = 1 kHz
25
en
Input Voltage Noise
0.7
0.7
0.5
0.6
0.6
0.5
0.6
0.6
0.5
µVPP
In
Input Current Noise Density
Gain Error
pA/
%
GE
Gain = 10, 20, 50, 100, 200, 500
VOUT = VREF + 1V and VOUT = VREF − 1V
0.03
0.1
0.15
GE
GE
Gain Error
Gain = 1000
VOUT = VREF + 1V and VOUT = VREF − 1V
0.03
0.15
0.25
%
Gain Error Contribution from chip
Gain Error Temperature Coefficient
VOUT = VREF + 1V and VOUT = VREF − 1V
0.03
3
%
For all gain settings (internal and
external), VOUT = VREF + 1V and
VOUT = VREF − 1V
16
ppm/°C
NL
Non-Linearity
3
8
100
ppm
MHz
GBW
Gain Bandwidth
COMP[2:0] = 000b, Gain > 10
COMP[2:0] = 001b, Gain > 100
COMP[2:0] = 010b, Gain > 200
COMP[2:0] = 011b, Gain > 500
24
80
240
0.8
COMP[2:0] = 1xxb,
Gain => 1
5
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Min
Typ
Max
Symbol
Parameter
−3 dB Bandwidth
Conditions
Units
(Note 6) (Note 5) (Note 6)
BW
Gain = 10, COMP[2:0] = 000b
Gain = 10, COMP[2:0] = 1xxb
Gain = 20, COMP[2:0] = 000b
Gain = 20, COMP[2:0] = 1xxb
Gain = 50, COMP[2:0] = 001b
Gain = 50, COMP[2:0] = 1xxb
Gain = 100, COMP[2:0] = 010b
Gain = 100, COMP[2:0] = 1xxb
Gain = 200, COMP[2:0] = 010b
Gain = 200, COMP[2:0] = 1xxb
Gain = 500, COMP[2:0] = 011b
Gain = 500, COMP[2:0] = 1xxb
Gain = 1000, COMP[2:0] = 011b
Gain = 1000, COMP[2:0] = 1xxb
930
74
385
37
460
16
640
8
kHz
195
4
130
1.5
89
0.8
1.7
SR
Slew Rate
(Note 7)
COMP[2:0] = 000b, 10% to 90% of Step,
VOUT = 2 VPP
COMP[2:0] = 001b, 10% to 90% of Step,
VOUT = 2 VPP
5.0
9.0
11.0
0.16
4
COMP[2:0] = 010b, 10% to 90% of Step,
VOUT = 2 VPP
V/µs
COMP[2:0] = 011b, 10% to 90% of Step,
VOUT = 2 VPP
COMP[2:0] = 1xxb, 10% to 90% of Step,
VOUT = 2 VPP
ts
0.01% Settling Time
2 V Step, CL = 10 pF, COMP[2:0] = 011b
µs
RL = 2 kΩ to V+/2
VOUT
Output Voltage Swing High
52
62
RL = 10 kΩ to V+/2
RL > 1 MΩ to V+/2
RL = 2 kΩ to V+/2
RL = 10 kΩ to V+/2
RL > 1 MΩ to V+/2
VOUT tied to V+/2
VOUT tied to V+/2
22
30
mV from
top rail
12
17
Output Voltage Swing Low
42
55
mV from
bottom
rail
16
22
12
17
IOUT
Output Current Sourcing
Output Current Sinking
Supply Current
23
16
31
41
mA
34
30
IS
Fault detection off, VIN DIFF = 0V
Fault detection on, VIN DIFF = 0V
in Shutdown
1.8
1.9
2.1
2.2
1
mA
mA
µA
0.006
85
TSD_ON Turn-on time from Shutdown
µs
PSE
Prescaler Error (Offset + Gain Error)
Prescaler Gain Factor
VCM = V+/2
5
8
mV
V/V
0.02
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Min
Typ
Max
Symbol
Parameter
Conditions
Units
(Note 6) (Note 5) (Note 6)
ITEST
Fault Detection: Test Current
Setting 1 (CUR[2:0] = 001b), VCM < V+ −
2.25V
10
nA
Setting 2 (CUR[2:0] = 010b), VCM < V+
−
100
1
nA
µA
µA
µA
2.25V
Setting 3 (CUR[2:0] = 011b), VCM < V+ −
2.25V
Setting 4 (CUR[2:0] = 100b), VCM < V+
−
10
2.25V
Setting 5 (CUR[2:0] = 101b), VCM < V+ −
2.25V
100
Electrical Characteristics (Serial Interface)
Unless otherwise specified, all limits guaranteed for TA = 25°C, V+ − V− ≥ 2.7V, V+ ≥ VHSER/VLPAR, V− ≤ VLSER/VHPAR, VD =
(VHSER/VLPAR) − (VLSER/VHPAR) ≥ 2.5V.
Min
(Note 6)
Typ
(Note 5)
Max
(Note 6)
Symbol
VIL
Parameter
Conditions
Units
Input Logic Low Threshold
Input Logic High Threshold
Output Logic Low Threshold
Output Logic High Threshold
Output Source Current, SDO
0.3 × VD
V
V
V
VIH
0.7 × VD
VOL
VOH
ISDO
ISDO = 2mA
ISDO = 2mA
0.2
VD − 0.2V
−2
VD = 3.3V or 5.0V,
CSB = 0V, VOH = V+ – 0.7V
mA
µA
Output Sink Current, SDO
VD = 3.3V or 5.0V,
2
CSB = 0V, VOL = 1.0V
IOZ
Output Tri-state Leakage Current, VD = 3.3V or 5.0V,
±1
SDO
CSB = VD = 3.3V or 5V
(Note 9)
t1
t2
t3
t4
t5
t6
t7
High Period, SCK
100
100
50
ns
ns
ns
ns
ns
ns
ns
Low Period, SCK
(Note 9)
Set Up Time, CSB to SCK
Set Up Time, SDI to SCK
Hold Time, SCK to SDI
Prop. Delay, SCK to SDO
(Note 9)
(Note 9)
30
(Note 9)
10
(Note 9)
60
Hold Time, SCK Transition to CSB (Note 9)
Rising Edge
50
50
t8
CSB Inactive
(Note 9)
(Note 9)
ns
ns
ns
ns
t9
Prop. Delay, CSB to SDO Active
50
50
t10
t11
Prop. Delay, CSB to SDO Inactive (Note 9)
Hold Time, SCK Transition to CSB (Note 9)
10
Falling Edge
tr/tf
Signal Rise and Fall Times
(Note 9)
1.5
5
ns
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but for which specific performance is not guaranteed. For guaranteed specifications and the test conditions, see Electrical Characteristics.
Note 2: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22–A115–A (ESD MM std. of JEDEC). Field-
Induced Charge-Device Model, applicable std. JESD22–C101–C (ESD FICDM std. of JEDEC).
Note 3: The short circuit test is a momentary test which applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated
ambient temperature can exceed the maximum allowable junction temperature of 150°C.
Note 4: The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
Note 5: Typical Values indicate the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will
also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material.
Note 6: All limits are guaranteed by testing or statistical analysis.
7
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Note 7: Slew rate is the average of the rising and falling slew rates.
Note 8: The offset voltage average drift is determined by dividing the value of VOS at the temperature extremes by the total temperature change.
Note 9: Load for these tests is shown in the Timing Diagram Test Circuit.
Connection Diagram
14-Pin SOIC/ 14-Pin TSSOP
30045402
Top View
Pin Descriptions
Pin Name
Communication Mode
Serial
Parallel
+IN
−IN
Positive Input
Negative Input
Reference Sense
Reference Force
Feedback
REFS
REFF
FB
OUT
Output
V+
Positive Supply
VHSER/VLPAR
V−
Set High
Set Low
Set High
Negative Supply
VLSER/VHPAR
CSB/SHDN
SCK/G2
SDI/G1
SDO/G0
Set Low
Chip Select
Shutdown (Active High)
Gain (MSB)
Gain
Serial Clock
Serial Data In
Serial Data Out
Gain (LSB)
Ordering Information
Package
Part Number
LMP8358MA
LMP8358MAX
LMP8358MT
LMP8358MTX
Package Marking
Transport Media
NSC Drawing
55 Units/Rail
2.5k Units Tape and Reel
94 Units/Rail
14-Pin SOIC
LMP8358MA
LMP8358MT
M14A
14-Pin TSSOP
MTC14
2.5k Units Tape and Reel
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8
Block Diagram
30045406
14-Pin SOIC/ 14-Pin TSSOP
9
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Timing Diagrams
30045403
SPI Timing Diagram
30045453
Timing Diagram Test Circuit
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10
Typical Performance Characteristics V+ = 3.3V and TA = 25°C unless otherwise noted.
Gain vs. Frequency for Various COMP Settings
Gain vs. Frequency for Various COMP Settings
300454c2
300454c3
Gain vs. Frequency for Various COMP Settings
Gain vs. Frequency for Various Cap Loads
300454c5
300454c4
Gain vs. Frequency for Various Cap Loads
Gain Error vs. Common Mode Voltage, VS = 5V
300454c6
300454f4
11
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Gain Error vs. Common Mode Voltage, VS = 3.3V
Gain Error Distribution, Gain = 10, VS = 3.3V
300454g4
300454f5
Gain Error Distribution, Gain = 100, VS = 3.3V
Gain Error Distribution, Gain = 1000, VS = 3.3V
300454g5
300454g6
VOS Distribution, VS = 3.3V
VOS Distribution, VS = 5.0V
300454g2
300454g3
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12
TCVOS Distribution, VS = 3.3V
TCVOS Distribution, VS = 5V
VOS vs. VCM, VS = 3.3V
VOS vs. VCM, VS = 5.0V
300454g7
300454g8
VOS vs. VCM, VS = 3.3V
300454e6
300454e5
VOS vs. VCM, VS = 5.0V
300454e7
300454e8
13
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VOS vs. VREF, VS = 3.3V
CMRR vs. Frequency
Voltage Noise vs. Time
CMRR vs. Frequency
300454d3
300454g9
PSRR vs. Frequency
300454d8
300454d9
Voltage Noise vs. Frequency
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14
Small Signal Step Response for Various COMP Settings
Small Signal Step Response for Various COMP Settings
300454d4
300454d5
Large Signal Step Response for Various COMP Settings
Large Signal Step Response for Various COMP Settings
300454d6
300454d7
Positive Overshoot vs. CLOAD
Supply Current vs. Supply Voltage
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300454e9
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Input Bias Current vs. VCM, VS = 3.3V
Input Bias Current vs. VCM, VS = 5.0V
300454f1
300454f0
THD+N vs. Frequency
THD+N vs. VOUT
300454e0
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ITEST1 vs. VCM
ITEST2 vs. VCM
300454g0
300454f9
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ITEST3 vs. VCM
ITEST4 vs. VCM
300454f8
300454f7
ITEST5 vs. VCM
Output Swing High vs. Supply Voltage
300454f2
300454f6
Output Swing Low vs. Supply Voltage
EMIRR IN+ vs. Frequency
300454f3
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17
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auto-zeroed the other stage provides the path between the
input pins and the output. The auto-zeroing decreases offset,
offset drift, and 1/f noise while the ping-pong architecture pro-
vides a continuous path between the input and the output. As
with all devices that use auto-zeroing, care must be taken with
the signal frequency used with the device. On-chip continu-
ous auto-zero correction circuitry eliminates the 1/f noise and
significantly reduces the offset voltage and offset voltage drift;
all of which are very low-frequency events. For slow-changing
sensor signals, below 2kHz, this correction is transparent.
Higher-frequency signals as well as fast changing edges will
show a settling and ramping time lasting about 1μs. Like all
auto-zeroing devices, if the input frequency is above the auto-
zero frequency, aliasing will occur. This can occur both at the
auto-zeroing frequency of about 12kHz and the ping-pong
frequency of about 50kHz. If needed, a low-pass filter should
be placed on the output of the LMP8358 to filter out this dis-
turbance.
Application Information
INTRODUCTION
The LMP8358 is a precision programmable gain instrumen-
tation amplifier. Its gain can be programmed to 10, 20, 50,
100, 200, 500 or 1000 through an SPI-compatible serial in-
terface or through a parallel interface. Alternatively, its gain
can be set to an arbitrary value using external resistors. Note
that at low gains the dynamic range is limited by the maximum
input differential voltage of ±100mV. The LMP8358 uses
patented techniques to measure and continuously correct its
input offset voltage, eliminating offset drift over time and tem-
perature, and the effect of 1/f noise. Its ground sensing CMOS
input features a high CMRR and low input bias currents. It is
capable of sensing differential input voltages in a common-
mode range that extends from 100 mV below the negative
supply to 1.4V below the positive supply, making it an ideal
solution for interfacing with ground-referenced sensors, sup-
ply-referenced sensor bridges, and any other application re-
quiring precision and long term stability. Additionally, the
LMP8358 includes fault detection circuitry, so open and short-
ed inputs can be detected, as well a deteriorating connection
to the signal source. Other features that make the LMP8358
a versatile solution for many applications are: its rail-to-rail
output, low input voltage noise and high gain-bandwidth prod-
uct.
COMMUNICATION WITH THE PART AND REGISTER
DESCRIPTION
The LMP8358 supports a serial and a parallel digital interface
mode as shown in Figure 1.
Parallel user mode Gain is set using G0, G1 and G2 pins.
The shutdown mode can be activated by
asserting SHDN. Fault detection fea-
tures are unavailable.
TRANSIENT RESPONSE TO FAST INPUTS
Serial user mode
The part is SPI-programmable through
SDI, SCK, SDO and CSB. All features
are available.
The LMP8358 is a current-feedback instrumentation amplifier
that consists of two auto-zeroed input stages. These two input
stages are operated in a ping-pong fashion: as one stage is
30045410
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300454a5
FIGURE 1. (A) Communication with LMP8358 in Parallel Mode (B) Communication with LMP8358 in Serial Mode
Communication Mode Selection
Table 1. Function of Digital IO Pins, Parallel Mode
The interface mode is determined by the two interface level
pins VLSER/VHPAR and VHSER/VLPAR.
Pin Name
Description
G0
Gain setting (LSB)
Gain setting
VLSER/VHPAR < VHSER/
VLPAR
Serial Interface. VLSER=
Logic low level, VHSER =
Logic high level.
G1
G2
Gain setting (MSB)
Shutdown (Active High)
Positive logic level
Negative logic level
VLSER/VHPAR > VHSER/
VLPAR
Parallel interface. VLPAR =
Logic low level, VHPAR =
Logic high level.
SHDN
VHPAR
VLPAR
The levels applied to the VLSER/VHPAR and VHSER/VL-
PAR pins should be between the V+ and V− levels as shown
in Figure 2.
Table 2. Pin Levels for Setting Gain, Parallel Mode
G2 G1 G0 Gain Setting
Bandwidth Compen-
sation
Setting
(Auto-
matically
Set)
0
0
0
10x (power-up
default)
930 kHz
000b
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
20x
385 kHz
460 kHz
640 kHz
195 kHz
130 kHz
89 kHz
000b
001b
010b
010b
011b
011b
1xxb
50x
100x
30045409
200x
FIGURE 2. Communication Mode Selection.
500x
1000x
User defined
PARALLEL CONTROL INTERFACE MODE
800 kHz
The LMP8358 is put into Parallel Mode by setting VLSER/
VHPAR > VHSER/VLPAR. The register in the LMP8358 does
not control the settings of the LMP8358 in this mode. Gain
and shutdown are set by placing a high or low logic level on
pins 11 (SHDN), 12 (G2), 13 (G1), and 14 (G0), as shown in
Table 1. Function of Digital IO Pins, Parallel Mode and Table
2. Pin Levels for Setting Gain, Parallel Mode. The logic high
and low levels are defined by the voltages on the VLSER/
VHPAR and VHSER/VLPAR pins. See the START UP AND
POWER ON RESET section for power on requirements when
using the parallel mode.
SERIAL CONTROL INTERFACE MODE
The LMP8358 is put into Serial Mode by setting VLSER/VH-
PAR < VHSER/VLPAR. In the Serial Mode the LMP8358 can
be programmed by using pins 11 – 14 as shown in Table 3.
Function of Digital IO Pins, Serial Mode and the SPI Timing
Diagram. The LMP8358 contains a 16 bit register which con-
trols the performance of the part. These bits can be changed
using the Serial Mode of communication. The register of the
LMP8358 is shown in Table 4. LMP8358 Register Descrip-
tion, Serial Mode. Immediately after power on the register
should be written with the value needed for the application.
See the START UP AND POWER ON RESET section.
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Table 3. Function of Digital IO Pins, Serial Mode
Bit No Name
Description
Pin Name
Description
11
12
13
14
15
PIN
Fault detection pin selection
Fault detection current setting (LSB)
Fault detection current setting
Fault detection current setting (MSB)
Unused, set to 0
SDO
Serial Data Out
Serial Data In
Serial Clock
CUR0
CUR1
CUR2
N/A
SDI
SCK
CSB
Chip Select
VLSER
VHSER
Negative Logic level
Positive Logic Level
Serial Control Interface Operation
The LMP8358 gain, bandwidth compensation, shutdown, in-
put options, and fault detection are controlled by an on board
programmable register. Data to be written into the control
register is first loaded into the LMP8358 via the serial inter-
face. The serial interface employs an 16-bit double-buffered
register for glitch-free transitions between settings. Data is
loaded through the serial data input, SDI. Data passing
through the shift register is output through the serial data out-
put, SDO. The serial clock, SCK controls the serial loading
process. All sixteen data bits are required to correctly program
the amplifier. The falling edge of CSB enables the shift reg-
ister to receive data. The SCK signal must be high during the
falling and rising edge of CSB. Each data bit is clocked into
the shift register on the rising edge of SCK. Data is transferred
from the shift register to the holding register on the rising edge
of CSB. Operation is shown in the SPI Timing Diagram.
Table 4. LMP8358 Register Description, Serial Mode
Bit No Name
Description
0
1
2
3
4
5
6
7
8
9
10
G0
G1
G2
Gain setting (LSB)
Gain setting
Gain setting (MSB)
COMP0 Frequency compensation setting (LSB)
COMP1 Frequency compensation setting
COMP2 Frequency compensation setting (MSB)
MUX0
MUX1
POL
Input multiplexer selection (LSB)
Input multiplexer selection (MSB)
Input polarity switch
SHDN
FILT
Shutdown Enable
The serial control pins can be connected in one of two ways
when two or more LMP8358s are used in an application.
Enable filtering using external cap
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Star Configuration
After the microcontroller writes, all registers will have the
same value. Using multiple CSB lines as shown in Figure 4
allows different values to be written into each register.
The configuration shown in Figure 3 can be used if each
LMP8358 will always have the same value in each register.
300454a3
FIGURE 3. Star Configuration for Writing the Same Value Into Each Register
300454a4
FIGURE 4. Star Configuration for Writing Different Values Into Each Register
Daisy Chain Configuration
tions are shown in Figure 5. In this configuration the SDO pin
of each LMP8358 is connected to the SDI pin of the following
LMP8358.
This configuration can be used to program the same or dif-
ferent values in the register of each LMP8358. The connec-
300454a5
FIGURE 5. Daisy Chain Configuration
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The following two examples show how the registers are writ-
ten in the Daisy Chain Configuration.
Tabel 5. If all three LMP8358s need a gain of 100 with a compensation level of 010. (0000 0000 0001 0011)
Register of LMP8358 #1 Register of LMP8358 #2 Register of LMP8358 #3 Notes
Power on
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
Default power on state
After first two bytes are 0000 0000 0001 0011
sent
The data in the register of
LMP8358 #1 is shifted
into the register of
LMP8358 #2, the data in
the register of LMP8358
#2 is shifted into the
After second two bytes 0000 0000 0001 0011
are sent
0000 0000 0001 0011
0000 0000 0001 0011
0000 0000 0000 0000
0000 0000 0001 0011
After third two bytes
are sent
0000 0000 0001 0011
register of LMP8358 #3.
Table 6. If LMP8358 #1 needs a gain of 20 (0000 0000 0000 0001), LMP8358 #2 needs a gain of 1000 with a compensation
level of 011 (0000 0000 0001 1110), and LMP8358 #3 needs a gain of 100 with a compenstation level of 010 (0000 0000 0001
0011).
Register of LMP8358 #1 Register of LMP8358 #2 Register of LMP8358 #3 Notes
Power on
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
Default power on state
After first two bytes are 0000 0000 0001 0011
sent
The data in the register of
LMP8358 #1 is shifted
into the register of
LMP8358 #2, the data in
the register of LMP8358
#2 is shifted into the
After second two bytes 0000 0000 0001 1110
are sent
0000 0000 0001 0011
0000 0000 0001 1110
0000 0000 0000 0000
0000 0000 0001 0011
After third two bytes
are sent
0000 0000 0000 0001
register of LMP8358 #3
LMP8358 SETTINGS
Gain (Serial, Parallel)
When G[2:0] = 111b in either serial or parallel mode switch
S1 is open and S2 is closed and the LMP8358 gain is set by
external resistors as shown in Figure 6. The gain is:
When the LMP8358 is in Parallel Mode the gain can be set
by applying a high or low level to pins 12 (G2), 13 (G1), and
14 (G0), as shown in Table 2. Pin Levels for Setting Gain,
Parallel Mode. The Frequency Compensation bits are auto-
matically set as shown in Table 2. Pin Levels for Setting Gain,
Parallel Mode to optimize the bandwidth. In Serial Mode the
gain is determined by setting G[2:0] as shown in Table 7. Gain
Setting (Register bits 2:0) and the bandwidth can be changed
using the Frequency Compensation bits in the register.
GAIN = 1 + (Z1/Z2)
When the gain is set by external resistors and COMP[2:0] =
1xxb, a capacitor can be used to implement a noise reduction
low pass filter. See the Filter and External Filter Capacitor
(Serial) section. R1and CFILTER are placed between the OUT
and FB pins. R2 is placed between the FB and REFS pins.
Table 7. Gain Setting (Register bits 2:0)
G2
0
G1
0
G0
0
Gain Setting
10x (power-up default)
0
0
1
20x
0
1
0
50x
0
1
1
100x
1
0
0
200x
1
0
1
500x
300454a6
1
1
0
1000x
User Defined
1
1
1
FIGURE 6. External Gain Set Resistors and Filter
Capacitor
When G[2:0] = 000b to 110b switch S1 is closed and switch
S2 is open as shown in the Block Diagram.
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Frequency Compensation (Serial)
at the selectable gain and compensation settings. Note that
for gains 10X and 20X, the recommended compensation set-
ting is 000b. For the gain setting 50X, compensation settings
may be 000b and 001b. Gain settings 100X and 200X may
use the three bandwidth compensation settings 000b, 001b,
and 010b. At gains of 500X and 1000X, all bandwidth com-
pensation ranges may be used. Note that for lower gains, it is
possible to under compensate the amplifier into instability.
The gain-bandwidth compensation is set to one of five levels
under program control. The amount of compensation can be
decreased to maximize the available bandwidth as the gain
of the amplifier is increased. The compensation level is se-
lected by setting bits COMP[2:0] of the control register with
000b, 001b, 010b, 011b, or 1xxb. Table 8. Frequency Com-
pensation (Register bits 5:3) shows the bandwidths achieved
Table 8. Frequency Compensation (Register bits 5:3)
Bandwidth
000
Gain\COMP [2:0]
001
010
011
1xx
10
930 kHz
385 kHz
160 kHz
80 kHz
38 kHz
16 kHz
8 kHz
n/a
n/a
n/a
74 kHz
37 kHz
16 kHz
8 kHz
20
n/a
n/a
n/a
50
460 kHz
225 kHz
95 kHz
40 kHz
22 kHz
n/a
n/a
100
200
500
1000
640 kHz
195 kHz
85 kHz
50 kHz
n/a
n/a
4 kHz
130 kHz
89 kHz
1.5 kHz
0.8 kHz
User Defined Gain
GBW Product
> 10x
8 MHz
> 30x
24 MHz
> 100x
80 MHz
> 300x
240 MHz
> 1x
0.8 MHz
(For external filter cap)
Input Multiplexer and Polarity Switch (Serial)
states shown in Table 9. Input Multiplexer and Polarity (Reg-
ister bits 8:6).
The Input Multiplexer Selection bits MUX[1:0] and Polarity bit
POL can be used to set the inputs of the LMP8358 to the
Table 9. Input Multiplexer and Polarity (Register bits 8:6)
MUX1
MUX0
Diff Input for POL = 0
Diff Input for POL = 1
0
0
0
1
1
0
1
1
Polarity Reversal
for example, to compensate for thermocouple voltages, resid-
ual offset of the LMP8358, or offsets of the sensor or ADC.
When MUX[1:0] = 00b and POL = 0b the LMP8358 has the
input of a normal instrumentation amplifier. The input for the
LMP8358 is defined as Gain × (V+IN − V−IN). When POL = 1b,
the input for the LMP8358 is defined as Gain × (V−IN – V+IN).
Polarity reversal can be used to do system level calibration,
Short Inputs
When MUX[1:0] = 01b and POL = 0b both inputs are con-
nected to the +IN pin of the LMP8358. The –IN pin is left
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floating. When MUX[1:0] = 01b and POL = 1b both inputs are
connected to the -IN pin of the LMP8358. The +IN pin is left
floating.
Table 13. RFILTER Value
RFILTER Value
18.5 kΩ
Gain
10
Compare Input to V-
20
112 kΩ
When MUX[1:0] = 10b or 11b one external input of the
LMP8358 is floating. The other external input is divided by 50
as shown in Table 9. Input Multiplexer and Polarity (Register
bits 8:6). The internal instrumentation amplifier input that is
not connected to the external pin is connected to V−. With a
scale factor of 1/50 this gives an overall gain of 0.2x, 0.4x, 1x,
2x, 4x, 10x, or 20x depending on what the gain is set to with
G[2:0] bits as shown in Table 10. Overall Gain using G[2:0],
MUX[1:0] and POL.
50
168 kΩ
100
200
500
1000
187 kΩ
1.12 MΩ
1.68 MΩ
1.87 MΩ
External Resistor R1
User-Defined Gain
Table 10. Overall Gain using G[2:0], MUX[1:0] and POL
The tolerance of the RFILTER value for the pre-defined gains
is about ±3%. If an external filter cap is not used FILT should
be set to 0b to prevent errors related to leakage currents on
the FB pin.
G[2:0]
MUX[1:0]
Overall System Gain
POL = 0b
POL = 1b
000b
001b
010b
011b
100b
101b
110b
10b or 11b
10b or 11b
10b or 11b
10b or 11b
10b or 11b
10b or 11b
10b or 11b
0.2
0.4
1
−0.2
−0.4
−1
Fault Detection Pin and Current Setting (Serial)
The LMP8358 has an internal current source that can be used
to detect faults in the overall system. See the FAULT DE-
TECTION METHODS Section. When PIN = 0b this current
source is connected to the +IN pin. When PIN = 1b the current
source is connected to the −IN pin.
2
−2
4
−4
10
20
−10
−20
Table 14. Pin Current Source (Register bit 11)
PIN
0
Current source is connected to
Shutdown Enable (Serial, Parallel)
+IN pin
−IN pin
When the SHDN bit of the LMP8358 register is set to 1b the
part is put into shutdown mode. It will use less than 1μA in this
state.
1
The Fault Detection Current bit, CUR[2:0] controls the amount
of current that sent to the input pin as shown in Table 15. Fault
Detection Current Source (Register bits 14:12).
Table 11. Shutdown (Register bit 9)
SHDN
Mode
Table 15. Fault Detection Current Source (Register bits
14:12)
0
1
Active mode
Shutdown mode
CUR2 CUR1 CUR0
Filter and External Filter Capacitor (Serial)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
disconnected and powered down *
The FILT bit controls the state of switch S2 shown in the Block
Diagram. When G[2:0] = 000b to 110b, switch S2 will be open
if FILT = 0b and S2 will be closed if FILT = 1b. When G[2:0]
= 111b switch S2 is always closed and does not depend on
the value in the FILT bit.
10 nA
100 nA
1 μA
10 µA
When FILT = 1b and COMP[2:0] = 1xxb the LMP8358 is unity-
gain stable and an external filter cap can be applied as shown
in Figure 6. The corner filter of the filter is:
100 µA
disconnected, but powered *
Do Not Use
F-3dB = 1/(2πRFILTERCFILTER
)
* Leaving the fault detection current source powered allows it
to switch between current levels faster, particularly when sup-
plying currents less than 1 µA.
RFILTER depends on the gain of the part and is shown inTable
13. RFILTER Value.
Table 12. Filter (Register bit 10)
FILT
Mode
0
1
No external filter cap used
External filter cap used
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24
FAULT DETECTION METHODS
Figure 7 which shows a bridge sensor connected through
some cabling to a supply and the LMP8358. The fault detec-
tion methods are described below.
Using the Multiplexer, Polarity, and Current features the end
user can detect faults in the system between the sensor and
the LMP8358. These examples will use the set up shown in
300454b5
FIGURE 7. Bridge Connected to the LMP8358 With No Problems
Common Mode Out of Range
mode voltage at the input pins, use the 1/50 feature by setting
MUX[1:0] to 10b to test the +IN pin or to 11b to test the −IN
pin, POL to 0b, and G[2:0] to 010b for a gain of 50 (0082x or
00C2x). This will give an overall gain of 1 and the output will
read 4V for either MUX setting.
Figure 8 shows an example of a degraded connection be-
tween the bottom of the bridge and ground. This fault is shown
by the 1.5 kΩ resistor placed between the bridge and ground.
This will raise the common mode at the inputs of the LMP8358
to 4V, which is out of the CMVR. To determine the common
300454b6
FIGURE 8. Degraded Connection Between the Bottom of the Bridge and Ground
25
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Open Input
of 50, and inject 100µA current by setting CUR[2:0] = 101b
(5082x or 58C2x). Since the input is open the input pin will be
pulled to V+. With an overall gain of 1 the output will read 5V
for open input.
Figure 9 shows an example of an open input fault. To sense
this type of fault use the 1/50 feature by setting MUX[1:0] to
10b to test the +IN pin or to 11b to test the −IN pin, POL to
0b, PIN to 1b to test the −IN pin, and G[2:0] to 010b for a gain
300454b7
FIGURE 9. Open Input
Input Shorted to V+ or V−
POL to 0b, and G[2:0] to 010b for a gain of 50 (0082x or
00C2x). This will give an overall gain of 1 and the output will
read either V+ or V− depending on whether the input pin is
shorted to V+ or V−.
Figure 10 shows an example of an input pin shorted to V+ or
V−. To sense this fault, use the 1/50 feature by setting MUX
[1:0] to 10b to test the +IN pin or to 11b to test the −IN pin,
300454b8
FIGURE 10. Input Shorted to V+ or V−
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26
Shorted Inputs
cause of the voltage drop across the internal ESD resistor,
which has a value between 60Ω to 90Ω. If the gain is set to
100× with an injected current of 100µA the output will be about
0.7V.
Figure 11 shows the inputs of the LMP8358 shorted. To detect
this fault set CUR[2:0] = 101b to inject a 100µA current and
set the gain to 10× (5000x). The LMP8358 is set up with nor-
mal differential inputs. The output will read about 0.07V be-
300454b9
FIGURE 11. Shorted Inputs
Degraded Input Line
to 010b for a gain of 50. This will give an overall gain of 1. Set
CUR[2:0] = 101b to inject a 100µA current and read the output
voltage (5082x). Next set MUX[1:0] to 11b and PIN to 1b to
test the −IN pin as shown in Figure 13 and read the output
(58C2x). If the voltages of these two measurements are dif-
ferent a degraded input fault exists.
Figure 12 shows an example of a degraded connection be-
tween the bridge and the +IN pin of the LMP8358. This fault
is shown by the 1 kΩ resistor placed between the bridge and
the LMP8358. To detect this fault use the 1/50 feature by set-
ting MUX[1:0] to 10b to test the +IN pin, POL to 0b, and G[2:0]
300454c0
FIGURE 12. Degraded Input Line, Step 1
300454c1
FIGURE 13. Degraded Input Line, Step 2
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Fault Detection Example
Matrix. If the circuit shown in Figure 7 is used the values
shown in column 2 of Table 16. Fault Detection Matrix would
show that the system is working correctly, the values in the
columns under the Possible Faults heading would show that
there is a potential problem and that operator attention is
needed.
Using the fault detection features of the LMP8358 an end
product, such as a scale, can periodically test that no damage
has occurred to the system. A routine can be written that
could, for example, run on start up, that will step through the
fault detection features shown above and compare the output
voltage to a table like that shown in Table 16. Fault Detection
Table 16. Fault Detection Matrix
No Faults
VOUT
Possible Faults
LMP8358
Register
VOUT
Possible Cause VOUT
Possible Cause
VOUT
Possible Cause
00 82x
2.5V
2.5V
VOUT < CMVR or
VOUT > CMVR
Input is out of
CMVR
V+
V+
+IN shorted to V+ 0V
−IN shorted to V+ 0V
+IN shorted to
GND
00 C2x
VOUT < CMVR or
VOUT > CMVR
Input is out of
CMVR
−IN shorted to
GND
50 00x
50 03x
50 82x
0.61V
4.97V
2.55V
V+
+IN Open
−IN
0.07V
0.7V
Inputs shorted
Inputs shorted
V+
2.65V*
Degraded +IN
line
58 C2x
50 82x
58 C2x
2.55V
2.55V
2.55V
2.55V*
2.55V*
2.65V*
Degraded +IN
line
Degraded −IN
line
Degraded −IN
line
* The values shown for a degraded input line will vary de-
pending on the resistance in the line. This table uses the value
in Figure 12 and Figure 13, 1kΩ.
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START UP AND POWER ON RESET
ration with the LMP7701 output connected to REFF, the
negative input of the op amp connected to REFS, and the
desired reference voltage connected to the positive input of
the op amp as shown in Figure 14.
During power on, 50µs after V+ − V− > 1V the LMP8358 resets
the internal register to 0000x. If the digital supplies and inputs
are undefined after the Power On Reset transients could oc-
cur which can cause erroneous data to be written over the
default values in the register. The following should be done to
prevent this from happening:
DIFFERENTIAL BRIDGE SENSOR
Non-amplified differential bridge sensors, which are used in
a variety of applications, typically have a very small differential
output signal. This small signal needs to be accurately am-
plified before it can be used by an ADC.
• Bring all supplies up at the same time. All power supplies,
analog and digital, should be brought up together within 40µs
so that the supplies are not undefined after the Power On
Reset at 50µs. This is easiest done by tying the VHSER/VL-
PAR and VLSER/VHPAR pins to the analog supplies. —
Parallel Mode
The high DC performance of the LMP8358 makes it a good
choice for use with a differential bridge sensor. This perfor-
mance includes low input offset voltage, low input offset volt-
age drift, and high CMRR. The on chip EMI rejection filters
available on the LMP8358 help remove the EMI interference
introduced to the signal as shown in Figure 14 and improves
the overall system performance.
• Immediately after power on, write to the register the value
needed for the application. (This is always recommended.) —
Serial Mode
LAYOUT
The circuit in Figure 14 shows a signal path solution for a typ-
ical bridge sensor using the LMP8358. The typical output
voltage of a resistive load cell is 2mV/V. If the bridge sensor
is using a 5V supply the maximum output voltage will be 2mV/
V × 5V = 10mV. The bridge voltage in this example is the
same as the LMP8358 and ADC161S626 supply voltage of
+5V. This 10mV signal must be accurately amplified by the
LMP8358 to best match the dynamic range of the ADC. This
is done by setting the gain of the LMP8358 to 200 which will
give an output from the LMP8358 of 2V. To use the complete
range of the ADC161S626 the VREF of the ADC should be set
to half of the input or 1V. This is done by the resistor divider
on the VREF pin of the ADC161S626. The negative input of
the ADC and the REFF and REFS pins of the LMP8358 can
be set to +2.5V to set the signal at the center of the supply. A
resistor divider supplies +2.5V to the positive input of an
LMP7701 set up in a buffer configuration. The LMP7701 acts
as a low impedance source for the REFF pin. The VIOand
VHSER/VLPAR pins should all be set to the same voltage as
the microcontroller, +3.3V in this example. The VLSER/VH-
PAR pin should be connected to ground. The resistor and
capacitor between the LMP8358 and the ADC161S626 serve
a dual purpose. The capacitor is a charge reservoir for the
sampling capacitor of the ADC. The resistor provides isolation
for the LMP8358 from the capacitive load. The values listed
in the ADC161S626 datasheet are 180Ω for the resistor and
the 470pF for the capacitor. These two components also form
a low pass filter of about 1.9MHz. If a filter is needed to at-
tenuate disturbance from the internal auto−zeroing at 12kHz
and the ping−pong frequency at 50kHz of the LMP8358 these
values could be changed to 7870Ω and 0.01µF which will
make a filter with a corner of about 2kHz.
The LMP8358 is a precision device that contains both analog
and digital sections as shown in the Block Diagram. The PCB
should be carefully designed to minimize the interaction be-
tween the analog and digital sections and to maximize the
performance of the part. This should include the following:
0.1µF ceramic capacitors should be placed as close as pos-
sible to each supply pin. If a digital supply pin is tied to an
analog pin only one 0.1µF capacitor is needed for both pins.
A larger 1µF or 10µF capacitor should be located near the part
for each supply.
Digital and analog traces should be kept away from each oth-
er. Analog and digital traces should not run next to each other,
if they do the digital signal can couple onto the analog line.
The LMP8358 pinout is set up to simplify layout by not having
analog, power, and digital pins mixed together. Pins 1 — 6
are the analog signals, pins 7 — 10 are the power pins, and
pins 11 — 14 are the digital signals.
Be aware of the signal and power return paths. The return
paths of the analog, digital, and power sections should not
cross each other and the return path should be underneath
the respective signal or power path. The best PCB layout is if
the bottom plane of the PCB is a solid plane.
The REFF and REFS pins are connected to the bottom side
of the gain resistors of the LMP8358 as shown in the Block
Diagram. Any impedance on these pins will change the spec-
ified gain. If the REFF and REFS pins are to be connected to
ground they should be tied directly to the ground plane and
not through thin traces that can add impedance. If the REFF
and REFS pins are to be connected to a voltage, the voltage
source must be low impedance. This can be done by adding
an op amp, such as the LMP7701, set up in a buffer configu-
29
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Physical Dimensions inches (millimeters) unless otherwise noted
14-Pin SOIC
NS Package Number M14A
14–Pin TSSOP
NS Package Number M14MT
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